US 7882320

Here's a concise summary of US patent 7882320:

Patent Number: US7882320B2

Title: Multi-processor flash memory storage device and management system

Current Assignee: Intellectual Ventures II LLC. The original assignee was Dataram Inc.

Inventor: Jason Caulkins

Filing Date: May 1, 2008

Issue Date: February 1, 2011

Abstract: A data storage device is described, comprising a host controller interface, a plurality of microprocessor units each having a dedicated portion of random access memory (RAM), a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.

Plain-Language Overview of Independent Claims:

• Claim 1: Data Storage Device with RAM Caching and Wear Leveling
  This claim describes a data storage device that includes a host controller interface, multiple microprocessor units (each with its own dedicated RAM portion), multiple non-volatile memory (Flash) configurations connected by dedicated buses to the microprocessors, and a dataflow controller. The key innovation here is that the dataflow controller actively monitors the amount of "valid data" in each microprocessor's RAM. When a preset threshold for this data volume is met or exceeded, the controller identifies the oldest unaltered data in that RAM portion and moves it to the non-volatile memory (Flash) connected to that specific microprocessor. Once moved, the RAM locations are marked as available for new writes.

• Claim 2: Flash Channel Configuration
  This claim is dependent on Claim 1. It specifies that the non-volatile memory device configurations mentioned in Claim 1 are organized into "individual Flash channels" that the dataflow controller can select for operation.

• Claim 3: Flash Device Configuration (Parallel Chips)
  This claim is dependent on Claim 2. It further defines the Flash device configuration within each selectable Flash channel as comprising multiple Flash chips connected in parallel.

• Claim 4: Flash Device Configuration (Daisy Chain Chips)
  This claim is dependent on Claim 2. It offers an alternative configuration where the Flash device configuration of each selectable Flash channel comprises multiple Flash chips connected in a daisy chain.

• Claim 5: Dataflow Controller with Onboard Microprocessor
  This claim is dependent on Claim 1. It states that the dataflow controller itself includes an onboard microprocessor with its own dedicated amount of RAM.

• Claim 6: Dataflow Controller as a State Machine
  This claim is dependent on Claim 1. It states that the dataflow controller can be implemented as a state machine.

• Claim 7: Dataflow Controller as Integrated Hardware
  This claim is dependent on Claim 1. It states that the dataflow controller can be implemented as hardware containing a microprocessor and a dedicated RAM portion, integrated with the host controller.

• Claim 8: Non-Volatile Memory Type
  This claim is dependent on Claim 1. It specifies that the non-volatile memory device configurations for each channel are of a type such as NAND Flash or Phase Change Memory.

CAFC 2026 Dockets:
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