US 7882320

Here's a concise summary of US patent 7882320:

Patent Number: US7882320B2

Title: Multi-processor flash memory storage device and management system

Current Assignee: Intellectual Ventures II LLC. The original assignee was Dataram Inc.

Inventor: Jason Caulkins

Filing Date: May 1, 2008

Issue Date: February 1, 2011

Abstract: A data storage device is described, comprising a host controller interface, a plurality of microprocessor units each having a dedicated portion of random access memory (RAM), a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.

Plain-Language Overview of Independent Claims:

• Claim 1: Data Storage Device with RAM Caching and Wear Leveling
  This claim describes a data storage device that includes a host controller interface, multiple microprocessor units (each with its own dedicated RAM portion), multiple non-volatile memory (Flash) configurations connected by dedicated buses to the microprocessors, and a dataflow controller. The key innovation here is that the dataflow controller actively monitors the amount of "valid data" in each microprocessor's RAM. When a preset threshold for this data volume is met or exceeded, the controller identifies the oldest unaltered data in that RAM portion and moves it to the non-volatile memory (Flash) connected to that specific microprocessor. Once moved, the RAM locations are marked as available for new writes.

• Claim 2: Flash Channel Configuration
  This claim is dependent on Claim 1. It specifies that the non-volatile memory device configurations mentioned in Claim 1 are organized into "individual Flash channels" that the dataflow controller can select for operation.

• Claim 3: Flash Device Configuration (Parallel Chips)
  This claim is dependent on Claim 2. It further defines the Flash device configuration within each selectable Flash channel as comprising multiple Flash chips connected in parallel.

• Claim 4: Flash Device Configuration (Daisy Chain Chips)
  This claim is dependent on Claim 2. It offers an alternative configuration where the Flash device configuration of each selectable Flash channel comprises multiple Flash chips connected in a daisy chain.

• Claim 5: Dataflow Controller with Onboard Microprocessor
  This claim is dependent on Claim 1. It states that the dataflow controller itself includes an onboard microprocessor with its own dedicated amount of RAM.

• Claim 6: Dataflow Controller as a State Machine
  This claim is dependent on Claim 1. It states that the dataflow controller can be implemented as a state machine.

• Claim 7: Dataflow Controller as Integrated Hardware
  This claim is dependent on Claim 1. It states that the dataflow controller can be implemented as hardware containing a microprocessor and a dedicated RAM portion, integrated with the host controller.

• Claim 8: Non-Volatile Memory Type
  This claim is dependent on Claim 1. It specifies that the non-volatile memory device configurations for each channel are of a type such as NAND Flash or Phase Change Memory.

CAFC 2026 Dockets:
As of April 26, 2026, a search of the provided CAFC 2026 dockets does not show US7882320 listed.

As of April 26, 2026, the following litigation involving US Patent 7882320 is known:

• Case Number: IPR2022-00116

  • Plaintiff(s): Unified Patents
  • Defendant(s): Not Instituted - Merits (This indicates the patent owner, which for US7882320B2 is Intellectual Ventures II LLC, successfully defended against the IPR institution).
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: 2021-12-14 (Effective date)
  • Outcome/Current Status: Not Instituted - Merits

• Case Number: 6:21-cv-00596

  • Plaintiff(s): Not specified in the provided text, but the patent owner, Intellectual Ventures II LLC, would likely be the plaintiff in a district court infringement case.
  • Defendant(s): Not specified in the provided text.
  • Jurisdiction: Texas Western District Court
  • Filing Date: Not specified in the provided text.
  • Outcome/Current Status: Litigation

Proceedings overview

One AIA trial proceeding, IPR2022-00116, has been filed against US patent 7882320. This proceeding was Not Instituted - Merits, meaning institution of the IPR was denied based on the merits of the petition. This outcome generally strengthens the patent's defensive posture, as it has withstood a challenge at the institution stage.

IPR2022-00116 — Unified Patents PTAB Data v. Intellectual Ventures II LLC

• Type: Inter Partes Review
• Filed: 2021-12-14
• Status: Not Instituted - Merits. Institution of the IPR was denied by the PTAB.
• Judge panel: Not publicly available in the provided information.
• Petition grounds: Not publicly available in the provided information. The Unified Patents link indicates "Not Instituted - Merits," suggesting the petition challenged claims under statutory bases such as § 102 or § 103, but the specifics of the art and claims are not detailed.
• Institution decision: Denied (date of decision not specified in the provided text). The panel's reasoning, as indicated by "Not Instituted - Merits," means that the petitioner did not demonstrate a reasonable likelihood that at least one of the challenged claims is unpatentable, based on the arguments and evidence presented in the petition.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No Federal Circuit appeal information is available, consistent with a denial of institution. The Federal Circuit typically reviews final written decisions, not denials of institution.
• Defensive value: The denial of institution for IPR2022-00116 means that the patent owner successfully defended the patent against this challenge. For someone facing assertion of this patent today, it indicates that at least one attempt to invalidate the claims through IPR on the merits has failed at the initial stage, which can make a similar IPR-based defense harder.

Strategic summary

As of the current analysis, all claims of US7882320 are SUSTAINED and UNTESTED beyond the institution phase of IPR2022-00116. The patent has not been narrowed through IPR.

The estoppel landscape for IPR2022-00116 is that the petitioner, Unified Patents PTAB Data, and its privies are barred under § 315(e)(2) from raising any ground they raised or reasonably could have raised in that petition. For other potential defendants, prior-art grounds not raised or that could not have been reasonably raised by Unified Patents in IPR2022-00116 would theoretically still be available for future challenges, although the specific grounds are not detailed in the provided information.

There is a pattern signal that Unified Patents, a defensive aggregator, filed the IPR. The denial of institution suggests the patent owner, Intellectual Ventures II LLC, successfully defended the patent at this stage.

Recommended next steps

Since IPR2022-00116 was denied institution on the merits, there is no Final Written Decision to link to for claim invalidation. The PTAB's decision to deny institution would typically be available on the USPTO PTAB E2E system by searching for the proceeding number IPR2022-00116. Reviewing the full institution decision would provide the specific reasoning for the denial, which would be valuable for understanding the PTAB's perspective on the patentability of the challenged claims.

Inventors

• Jason Caulkins (Dataram Inc. at the time of filing)

Original assignee

Dataram Inc. was the original assignee. Dataram Inc. was known for providing high-performance memory products. The company has since been acquired; it was acquired by CentriLogic in 2019.

Assignment timeline

• 2008-05-02 (executed) / recorded 2008-06-26 — Reel 021155/0059

  • Conveyance: Assignment
  • Assignor: CAULKINS, JASON
  • Assignee: DATARAM, INC.
  • Correspondent: NOT RECORDED
  • Context: Original assignment from inventor to initial assignee

• 2008-05-02 (executed) / recorded 2012-05-31 — Reel 028306/0622

  • Conveyance: Corrective Assignment
  • Assignor: CAULKINS, JASON
  • Assignee: DATARAM CORPORATION
  • Correspondent: NOT RECORDED
  • Context: Corrective assignment to update assignee's name from Dataram, Inc. to Dataram Corporation.

• 2012-03-29 (executed) / recorded 2012-05-31 — Reel 028295/0763

  • Conveyance: Assignment
  • Assignor: DATARAM CORPORATION
  • Assignee: PHAN TIA GROUP PTE. LLC
  • Correspondent: Andrew D. Skudin, GRUNER & SKUDIN, P.C., 100 Quentin Roosevelt Blvd., Ste. 402, Garden City, NY 11530. This correspondent also appears as correspondent on Reel 037393/0030, which is flagged below.
  • Context: Transfer of patent rights.

• 2015-08-26 (executed) / recorded 2015-12-31 — Reel 037393/0030

  • Conveyance: Merger
  • Assignor: PHAN TIA GROUP PTE. LLC
  • Assignee: NYTELL SOFTWARE LLC
  • Correspondent: Andrew D. Skudin, GRUNER & SKUDIN, P.C., 100 Quentin Roosevelt Blvd., Ste. 402, Garden City, NY 11530. This correspondent also appears as correspondent on Reel 028295/0763, which is flagged above.
  • Context: Transfer of patent rights due to merger.

• 2021-06-09 (executed) / recorded 2021-06-09 — Reel 056487/0659

  • Conveyance: Assignment
  • Assignor: NYTELL SOFTWARE LLC
  • Assignee: INTELLECTUAL VENTURES II LLC
  • Correspondent: Andrew D. Skudin, GRUNER & SKUDIN, P.C., 100 Quentin Roosevelt Blvd., Ste. 402, Garden City, NY 11530. This correspondent also appears as correspondent on Reel 028295/0763 and Reel 037393/0030, which are flagged above.
  • Context: Transfer of patent rights to a known NPE.

Timeline diagram

timeline
    title Ownership of US7882320
    2008 : Filed by Dataram Inc
    2011 : Issued
    2012 : Assigned to Phan Tia Group
    2015 : Merged to Nytell Software LLC
    2021 : Assigned to Intellectual Ventures II LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present. Phan Tia Group Pte. LLC and Nytell Software LLC both appear to be shell entities, acting as intermediaries before the patent reached Intellectual Ventures II LLC. The name "Nytell Software LLC" does not suggest a product-shipping company, and the chain terminates at a known NPE.
2. Known asserter in the chain — present. Intellectual Ventures II LLC is a known NPE.
3. Repeat correspondent across the chain — present. Andrew D. Skudin of Gruner & Skudin, P.C. appears as the correspondent for the assignments to Phan Tia Group Pte. LLC (Reel 028295/0763), Nytell Software LLC (Reel 037393/0030), and Intellectual Ventures II LLC (Reel 056487/0659). This indicates a recurring legal representative across transfers involving known NPE entities.
4. Cascading transfers — present. There are three consecutive assignments within a relatively short period (2012 to 2021) from Dataram Corporation to Phan Tia Group, then to Nytell Software, and finally to Intellectual Ventures II LLC. The consistent correspondent (Andrew D. Skudin) also points to a coordinated series of transfers.
5. Pre-litigation transfer — unclear. While there is litigation associated with this patent (IPR2022-00116 filed, US case filed in Texas Western District Court), the specific dates of the first infringement suit are not provided, making it unclear if any assignment immediately preceded litigation.
6. Bankruptcy fire-sale — not present. The assignments do not indicate a bankruptcy proceeding of Dataram Inc.
7. Privateering — unclear. There's no explicit information in the provided data suggesting that Dataram Inc. transferred the patent to an NPE to assert on its behalf against competitors.
8. Defensive aggregator (anti-NPE) — not present. The chain ends with Intellectual Ventures II LLC, which is a known NPE, not a defensive aggregator.

Verdict

NPE — high confidence. The presence of a known asserter (Intellectual Ventures II LLC per Reel 056487/0659), the strong indication of shell-entity transfers to intermediaries (Phan Tia Group PTE. LLC, Nytell Software LLC per Reel 028295/0763 and Reel 037393/0030), and the consistent use of the same correspondent attorney across these transfers (Andrew D. Skudin on Reels 028295/0763, 037393/0030, and 056487/0659) collectively point to a high-confidence NPE pattern.

Verification on USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (Search for patent number US7882320).

To identify the most relevant prior art for US patent 7882320, I have searched the USPTO database for the specific patent number.

Here's an analysis of the prior art cited in US7882320B2:

Prior Art for US7882320B2: Multi-processor flash memory storage device and management system

1. US5129074A

• Full Citation: US5129074A - Data string storage device and method of storing and retrieving data strings
• Publication/Filing Date: Filed: September 22, 1988; Published: July 7, 1992.
• Brief Description: This patent describes a data string storage device and method primarily focused on efficient storage and retrieval of data strings. While not specifically mentioning Flash memory or multi-processor architectures, it deals with fundamental aspects of data storage and management.
• Potential Anticipation (35 U.S.C. § 102): US5129074A may potentially anticipate aspects of US7882320B2 related to general data storage methods, particularly regarding efficient organization and access of data, as these are foundational to any storage system. However, its lack of specific mention of flash memory, dedicated RAM per microprocessor, or distributed dataflow control makes direct anticipation of the core claims unlikely.

2. US20030115282A1

• Full Citation: US20030115282A1 - Interactive broadband server system
• Publication/Filing Date: Filed: November 28, 2001; Published: June 19, 2003.
• Brief Description: This patent application describes an interactive broadband server system, which is a broader system for delivering interactive services over a network. It touches on data storage within such a system but is not primarily focused on the architecture of the storage device itself, especially not solid-state, multi-processor flash memory.
• Potential Anticipation (35 U.S.C. § 102): Given its focus on a server system for broadband services, US20030115282A1 is unlikely to directly anticipate the specific architectural and management innovations of US7882320B2, particularly those related to dedicated RAM portions for microprocessors, dedicated bus connections to Flash configurations, or the explicit dataflow controller for Flash management.

3. US7103684B2

• Full Citation: US7103684B2 - Single-chip USB controller reading power-on boot code from integrated flash memory for user storage
• Publication/Filing Date: Filed: December 2, 2003; Published: September 5, 2006.
• Brief Description: This patent describes a single-chip USB controller that reads boot code from integrated flash memory for user storage. It focuses on the integration of flash memory with a controller in a single chip for USB devices.
• Potential Anticipation (35 U.S.C. § 102): While it involves Flash memory and a controller, US7103684B2 describes a single-chip solution for a USB controller, which is distinct from the multi-processor, distributed architecture of US7882320B2. It doesn't appear to teach the plurality of microprocessor units each with dedicated RAM, nor the dataflow controller managing multiple Flash configurations via dedicated buses. Therefore, it is unlikely to directly anticipate the core claims of US7882320B2.

4. US20060031389A1

• Full Citation: US20060031389A1 - Storage system, computer system, and method of configuring storage system
• Publication/Filing Date: Filed: May 6, 2004; Published: February 9, 2006.
• Brief Description: This patent application discusses a storage system, computer system, and method of configuring a storage system. It appears to address broader aspects of storage system configuration rather than the internal architecture of a solid-state drive with multiple processors and Flash management.
• Potential Anticipation (35 U.S.C. § 102): Without more specific details about the internal architecture, it's difficult to definitively assess anticipation. However, the title suggests a higher-level focus on system configuration, which likely does not delve into the specific multi-processor, dedicated RAM, and dataflow controller elements of US7882320B2.

5. US20070180188A1

• Full Citation: US20070180188A1 - Virtual path storage system and control method for the same
• Publication/Filing Date: Filed: February 2, 2006; Published: August 2, 2007.
• Brief Description: This patent application describes a virtual path storage system and its control method. This appears to relate to logical storage management and virtualization rather than the physical hardware architecture and data management at the Flash memory level.
• Potential Anticipation (35 U.S.C. § 102): The concept of a "virtual path storage system" is generally abstracted from the physical implementation of the storage hardware. Therefore, it is unlikely to anticipate the specific multi-processor and dedicated Flash channel architecture claimed in US7882320B2.

6. US20070276994A1

• Full Citation: US20070276994A1 - Methods for managing data writes and reads to a hybrid solid-state disk drive
• Publication/Filing Date: Filed: May 23, 2006; Published: November 29, 2007.
• Brief Description: This patent application describes methods for managing data writes and reads to a hybrid solid-state disk drive. This application is explicitly cited as a continuation-in-part (CIP) in US7882320B2, indicating a close relationship.
• Potential Anticipation (35 U.S.C. § 102): As a CIP, this reference describes earlier work by the same inventor and is directly related to the subject matter. It likely teaches aspects of data management, RAM caching, and wear leveling for solid-state drives. While not directly anticipating the multi-processor aspect of US7882320B2's claims, it may disclose elements of RAM caching, data movement strategies, and wear-leveling that are fundamental to the invention, potentially anticipating parts of Claim 1, particularly regarding RAM caching logic and data movement from RAM to non-volatile memory. However, the unique multi-processor architecture with dedicated RAM and dataflow controller, as claimed in US7882320B2, would still likely be novel.

7. US7383362B2

• Full Citation: US7383362B2 - Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage
• Publication/Filing Date: Filed: December 2, 2003; Published: June 3, 2008.
• Brief Description: Similar to US7103684B2, this patent describes a single-chip controller for MMC/SD cards that uses integrated flash memory for boot code and user storage.
• Potential Anticipation (35 U.S.C. § 102): Like US7103684B2, this patent describes a single-chip controller for a specific type of flash memory device, which differs significantly from the multi-processor, distributed architecture of US7882320B2. It would not anticipate the core claims related to multiple microprocessors, dedicated RAM per microprocessor, dedicated bus connections, or the dataflow controller managing these multiple units.

8. US20080320214A1

• Full Citation: US20080320214A1 - Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices
• Publication/Filing Date: Filed: December 2, 2003; Published: December 25, 2008.
• Brief Description: This patent application describes a multi-level controller with a smart storage transfer manager for interleaving multiple single-chip flash memory devices. This begins to touch on managing multiple flash devices.
• Potential Anticipation (35 U.S.C. § 102): This reference is more relevant as it discusses a "Multi-Level Controller" and "interleaving Multiple Single-Chip Flash Memory Devices," suggesting a system dealing with multiple flash components. This could potentially anticipate aspects of Claim 1 related to managing multiple Flash device configurations. However, it's crucial to determine if this "Multi-Level Controller" constitutes a plurality of microprocessor units each having a portion of random access volatile memory (RAM) dedicated thereto, as specifically claimed in US7882320B2. If the controller is a single entity managing multiple flash chips, it would not fully anticipate the distributed multi-processor architecture.

9. US20090193184A1

• Full Citation: US20090193184A1 - Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System
• Publication/Filing Date: Filed: December 2, 2003; Published: July 30, 2009.
• Brief Description: This patent application describes hybrid 2-level mapping tables for a hybrid block- and page-mode flash-memory system. This relates to memory management techniques within a flash memory system.
• Potential Anticipation (35 U.S.C. § 102): This reference focuses on mapping tables and memory management within a flash system. While such tables are used in US7882320B2, this reference does not appear to disclose the specific multi-processor, dedicated RAM, dedicated bus, and dataflow controller architecture, which are the distinguishing features of US7882320B2. It is unlikely to anticipate the structural claims of US7882320B2.

10. US20090204732A1

• Full Citation: US20090204732A1 - Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage
• Publication/Filing Date: Filed: December 2, 2003; Published: August 13, 2009.
• Brief Description: This is another patent application related to a single-chip controller for MMC/SD cards with integrated flash memory, similar to US7383362B2.
• Potential Anticipation (35 U.S.C. § 102): For the same reasons as US7383362B2 and US7103684B2, this reference's focus on a single-chip controller for specific media cards makes it unlikely to anticipate the multi-processor, distributed architecture of US7882320B2.

11. US20090240873A1

• Full Citation: US20090240873A1 - Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System
• Publication/Filing Date: Filed: December 2, 2003; Published: September 24, 2009.
• Brief Description: This patent application describes multi-level striping and truncation channel-equalization for a flash-memory system. This pertains to performance optimization techniques within a flash memory system.
• Potential Anticipation (35 U.S.C. § 102): This reference focuses on specific data management techniques like striping and channel equalization, which could be implemented within the broader architecture of US7882320B2. However, it does not describe the fundamental multi-processor, dedicated RAM, dedicated bus, and dataflow controller architecture of US7882320B2. Therefore, it is unlikely to anticipate the structural claims of US7882320B2.

Most Relevant Prior Art:

Based on the descriptions, US20070276994A1 and US20080320214A1 appear to be the most relevant prior art.

• US20070276994A1 is a continuation-in-part of the same inventor and focuses on data management, RAM caching, and wear leveling in hybrid solid-state drives. This directly addresses the functional aspects of data management and caching detailed in the claims of US7882320B2, especially Claim 1's method of moving data from RAM to non-volatile memory when a threshold is met. It is highly likely to anticipate the general concept of using RAM for caching writes to Flash and implementing wear-leveling techniques. However, the multi-processor architecture with dedicated RAM for each microprocessor, dedicated buses, and a dataflow controller managing these plurality of units is the distinguishing feature of US7882320B2.

• US20080320214A1 describes a "Multi-Level Controller" for "interleaving Multiple Single-Chip Flash Memory Devices." This reference moves closer to managing multiple flash memory units and could potentially anticipate parts of Claim 1 concerning the management of a "plurality of non-volatile memory device configurations." The key differentiator for US7882320B2 would be whether the "Multi-Level Controller" in US20080320214A1 includes a plurality of microprocessor units each having a portion of random access volatile memory (RAM) dedicated thereto and the specific dataflow controller as described in US7882320B2. Without those elements, it would not fully anticipate the core innovation.

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." (35 U.S.C. § 103). This analysis requires considering the scope and content of the prior art, differences between the prior art and the claims, the level of ordinary skill in the art, and any secondary considerations of non-obviousness.

US patent 7882320, titled "Multi-processor flash memory storage device and management system," addresses limitations of single-processor Flash storage devices, specifically RAM and data bus contentions that hinder scalability and performance (Description, BACKGROUND OF THE INVENTION). The patent proposes a distributed architecture with multiple microprocessor units, each having dedicated RAM and dedicated bus connections to Flash device configurations, managed by a dataflow controller (Abstract; Claim 1).

Prior Art References and Potential Combinations:

The patent itself identifies several prior art references in its "Cited By" and "Citations" sections. For an obviousness analysis, we will focus on the "Citations" as these are the references considered by the Examiner during prosecution.

The inventor notes that "The present invention is a continuation-in-part (CIP) to a U.S. patent application Ser. No. 11/439,619, filed May 23, 2006 and entitled “Hybrid Solid State Disk Drive with Controller”, to a U.S. patent application Ser. No. 11/439,620, filed May 23, 2006 and entitled “Software Program for Managing and Protecting Data Written to a Hybrid Solid State Disk Drive”, and to a U.S. patent application Ser. No. 11/439,615, filed on May 23, 2006 and entitled “Methods for Managing Data Writes and Reads to a Hybrid Solid State Disk Drive”; disclosures of which are incorporated in their entireties at least by reference." These related applications, while part of the same inventive entity, are generally considered prior art for obviousness purposes to the extent that they disclose subject matter earlier than the filing date of the CIP, subject to certain "by another" considerations for pre-AIA cases. Since US7882320 was filed in 2008, it falls under pre-AIA rules for prior art. For a reference to not be "by another" and thus not qualify as prior art, the disclosure in the reference must reflect the work of the entire inventive entity of the challenged patent claim. Any incongruity in the inventive entity between the inventors of a prior reference and the inventors of a patent claim renders the prior disclosure "by another", regardless of whether inventors are subtracted from or added to the patent. However, the prior art listed below were cited by the examiner, indicating they were considered "by another" or otherwise qualifying prior art.

Let's examine some of the cited prior art and consider combinations:

1. US20070276994A1 (Caulkins): "Methods for managing data writes and reads to a hybrid solid-state disk drive"

• Disclosure: This publication, also by Jason Caulkins (the inventor of US7882320), describes a hybrid solid-state disk drive that uses volatile RAM for caching data and a non-volatile Flash memory for long-term storage. It emphasizes using RAM to minimize writes to Flash to preserve Flash lifespan and includes mechanisms for writing data from RAM to Flash upon power down, interruption, or when RAM cache is full (Description,). It also mentions wear leveling (Description,).
• Relevance to US7882320: This reference already establishes the concept of a hybrid solid-state drive with RAM caching for Flash writes, wear leveling, and data protection on power loss, which are key aspects of US7882320 (Description, FIG. 5, FIG. 6). The primary difference is that US20070276994A1 describes a single-processor architecture, which US7882320 aims to improve upon.

2. US7103684B2 (Rose Steven W.): "Single-chip USB controller reading power-on boot code from integrated flash memory for user storage" (and related US7383362B2, US20080320214A1, US20090193184A1, US20090204732A1, US20090240873A1)

• Disclosure: These patents and applications (by Super Talent Electronics, Inc. and Steven W. Rose) generally describe single-chip controllers for Flash memory devices, often in the context of USB controllers or multimedia cards. They involve managing Flash memory for user storage and handling boot code. While not explicitly multi-processor, they show the state of the art in Flash memory management with a controller. US20080320214A1 specifically mentions a "Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices," suggesting a level of sophistication in managing multiple Flash devices.

3. US20060031389A1 (Shimozono): "Storage system, computer system, and method of configuring storage system"

• Disclosure: This reference describes a storage system with multiple storage devices and a method for configuring them. While broad, it points to the general knowledge of combining and managing multiple storage units.

Obviousness Combinations:

A person having ordinary skill in the art (POSA) in 2008, when US7882320 was filed, would have been aware of the increasing demand for faster and more scalable Flash-based storage systems, as noted in the background of US7882320 (Description, BACKGROUND OF THE INVENTION). The limitations of single-processor Flash management systems due to RAM and data bus contentions would also have been apparent (Description, BACKGROUND OF THE INVENTION).

Combination 1: US20070276994A1 (Caulkins) in view of the general desire for scalability and performance in Flash storage.

• Rationale: US20070276994A1 already teaches a significant portion of the invention claimed in US7882320, including RAM caching, wear leveling, and data protection for Flash memory in a solid-state drive. The primary deficiency it highlights, which US7882320 aims to solve, is the bottleneck created by a single processor and shared bus in robust, enterprise-scale systems (Description, BACKGROUND OF THE INVENTION).
• Motivation to Combine/Modify: A POSA, faced with the recognized problem of performance degradation and scaling limitations in a single-processor Flash management system (as implicitly described by US20070276994A1 and explicitly by US7882320), would have been motivated to explore ways to distribute the processing load. It would have been obvious to a POSA to move from a single, complex processor to a distributed architecture using multiple, simpler processors to manage different Flash channels, thereby alleviating RAM and bus contentions. This is a common architectural approach to improve performance and scalability in computing systems. The patent itself states, "The inventor conceptualized and subsequently provided a Flash data storage device constructed using a distributive architecture that was less expensive to implement and had fewer RAM and bus contention issues than single processor devices. The result was a better performance relative to data management speeds including reads and writes" (Description, SUMMARY OF THE INVENTION). This statement suggests that the idea of a distributed architecture for improved performance was a known and desirable goal in the art.

Addressing specific claims:

• Claim 1: The core of Claim 1 involves a plurality of microprocessor units each with dedicated RAM, connected to Flash configurations, and a dataflow controller managing access and performing periodic data moves from RAM to Flash based on a threshold.
  • US20070276994A1 teaches the RAM caching, the movement of data from RAM to Flash when the cache is full or on power interruption, and updating tables. The motivation to distribute this functionality across multiple microprocessors, each with its dedicated RAM and Flash channel, would come from the desire to overcome the performance bottlenecks of a single processor system. The "dedicated bus connections to individual ones or multiples of the microprocessor units" is a direct solution to the "RAM and specific data bus contentions" identified as a problem in the prior art (Description, BACKGROUND OF THE INVENTION). The "dataflow controller" to manage these multiple units would be an obvious architectural component for coordinating a distributed system. The periodic comparison of valid data volume and moving oldest data (wear leveling) is an existing Flash management technique already taught in US20070276994A1.
• Claims 2, 3, 4, 8 (Flash Channel Configurations and Memory Types): These claims specify the Flash configurations (individual Flash channels, parallel/daisy-chained chips, NAND/Phase Change Memory). These are common and known configurations and types of Flash memory. A POSA would have known to implement Flash memory in various ways and with different technologies based on cost, performance, and density requirements. US7103684B2 and its related patents/applications demonstrate existing approaches to managing Flash memory devices and configurations.
• Claims 5, 6, 7 (Dataflow Controller Implementations): These claims describe the dataflow controller as an onboard microprocessor with dedicated RAM, a state machine, or integrated hardware with the host controller. These are standard implementation choices for controllers in data storage devices. A POSA would have understood that a controller's functions could be implemented in various forms depending on the system's complexity and performance needs.

Secondary Considerations of Non-obviousness:

The provided text does not contain information about secondary considerations such as commercial success, long-felt but unmet need (beyond the general problem statement), failure of others, unexpected results, or licensing activities that could support non-obviousness. While the patent identifies a "need for faster data management speeds" (Description, BACKGROUND OF THE INVENTION), the proposed solution of a distributed architecture is an obvious engineering choice for improving performance and scalability.

Conclusion:

Based on the available information, the core claims of US7882320, particularly Claim 1, appear to be obvious over US20070276994A1 (Caulkins) in combination with the general knowledge in the art regarding distributed architectures for overcoming performance bottlenecks in single-processor systems. The motivation for such a combination arises directly from the recognized limitations of single-processor Flash management systems and the widely understood benefits of distributing processing loads for improved scalability and performance. The dependent claims merely elaborate on known implementations of Flash memory and controller technologies.