US 7409200

US Patent 7,409,200 — Summary

Note on sources: The authoritative full-text record was provided in the task (Google Patents mirror of the USPTO record). Web searches confirmed the bibliographic data and current litigation status. Searches for any CAFC 2026 appeal referencing "7409200" returned no results — I found no Federal Circuit docket entries for this patent in 2025/2026. I could not directly query USPTO Patent Center/assignment databases through the available tools; details below that come only from third-party search results are flagged.

Bibliographic data

• Patent number / title: US 7,409,200 B2 — "Module integration integrated circuits"
• Application: US 10/857,938, filed June 2, 2004 (continuation-in-part of US 10/680,208, filed Oct. 8, 2003, which issued as US 7,754,539)
• Issue date: August 5, 2008
• Inventors: James H. Derbyshire; Alan J. A. Trainor
• Assignee (as listed): SiGe Semiconductor Inc. (assignment recorded June 2, 2004). Note: current enforcement actions in the U.S. have been brought by Skyworks Solutions, Inc. entities, consistent with Skyworks' acquisition of SiGe Semiconductor, though I did not verify the current USPTO assignment-of-record through a direct database query.
• Legal status: Expired – Lifetime (Google Patents shows adjusted expiration April 1, 2026; maintenance fees paid through the 12th year in 2020).

Abstract (as published)

"A first signal conditioning circuit is formed from a first portion, a second portion and a third portion. Signal conditioning functions of each of these portions are facilitated by a predetermined type of integrated semiconductor die within which they are formed. Two different semiconductor dies are thus provided for facilitating integration of the first through third signal conditioning portions therein. Wire bonds are provided between the two different semiconductor dies in order to form circuit paths between the different first through third portions. The signal routing using between the two different semiconductor dies provides for completing of the first signal conditioning circuit having a first signal conditioning function. For example, circuits such as interstage matching circuits are disposed on a different semiconductor die than power amplifier circuits."

Independent claims — plain-language overview

The patent has 34 claims; the independent claims are 1, 18, and 26 (all others depend from one of these).

• Claim 1 (apparatus, two-die split of one signal path): An electronic apparatus having (a) a first integrated-circuit die containing a first portion of a first signal-conditioning circuit placed along a first signal path, and (b) a second integrated-circuit die containing a second portion of that same first signal-conditioning circuit also placed along the first signal path, so the two portions cooperate to perform the signal-conditioning function on a signal traveling that path. A common substrate supports both dies and provides electrical connection to/from them. In the specification, this enables e.g. putting a power amplifier on a SiGe die and its impedance-matching/passive portion on a GaAs die for better RF performance.

• Claim 18 (method of manufacturing): A method comprising: providing first and second signal-conditioning circuits, each having first and second portions; implementing the first portion of the first conditioning circuit in a first die; implementing the second portion of the first conditioning circuit in a second die; implementing the first and second portions of the second conditioning circuit in that same second die; bonding both dies to a common substrate; and forming electrical connections between the dies to complete the first signal-conditioning circuit.

• Claim 26 (apparatus, three-part circuit split across two dies): An electronic apparatus where the first die contains a first portion and a third portion of a first signal-conditioning circuit along a first signal path, and the second die contains a second portion of that circuit along the same path, so all three portions together perform the signal-conditioning function. A common substrate supports the dies and provides electrical connections. The specification's preferred example places the two amplifier stages (first/third portions) on one die and an interstage-matching circuit (second portion) on the other die.

Litigation / PTAB status (from web searches, 2024–2026)

• ITC Investigation No. 337-TA-1413 (Certain wireless front-end modules and downstream devices): Skyworks entities asserted five patents including US 7,409,200 against Kangxi/Grand Chip Labs and others (instituted Aug. 2024). Per a January 25, 2026 report of Kangxi's announcement, the administrative law judge's initial determination found no violation of §337, and US 7,409,200 (with US 9,450,579 and US 9,148,194) was terminated during discovery because Skyworks voluntarily withdrew those claims. I did not independently verify the ITC final determination.
• District court: California Central District Court case 8:24-cv-00976 (Skyworks v. Kangxi, filed May 2024) is listed as involving this patent family.
• PTAB: IPR2025-00912 was filed (petition data via Unified Patents lists Kangxi Communications Technologies as opponent; filed ~April 2025) and is marked "Not Instituted – Procedural" — i.e., the Board did not institute inter partes review.
• A second ITC listing (337-TA-3762) also appears on the Google Patents litigation record.

Uncertainties

• No CAFC 2026 docket entry was found for patent 7409200 in my searches; I cannot confirm whether any appeal to the Federal Circuit exists. If an appeal of the ITC determination or district court case was filed, it was not surfaced in the searches performed.
• I did not directly access USPTO PAIR/Patent Center, so the formal USPTO assignment record and fee/expiration entries were not re-verified against the agency database; the status "Expired – Lifetime (2026-04-01)" comes from the Google Patents record.
• The exact current owner of record could not be confirmed beyond the listed "SiGe Semiconductors Inc." assignee; enforcement by Skyworks entities is reported by third-party sources.

Known Litigation Involving U.S. Patent 7,409,200 (US7409200B2)

Based on searches of district-court, ITC, and PTAB records (including Unified Patents, Dockets/Justia, Unicourt, RPX/IPverse, ITC notices, and issuer disclosures), the known proceedings involving U.S. Patent 7,409,200 are as follows:

1. ITC Investigation No. 337-TA-1413 — "Certain Wireless Front-End Modules and Devices Containing the Same"

• Complainants (plaintiffs): Skyworks Solutions, Inc. (Irvine, CA); Skyworks Solutions Canada, Inc.; Skyworks Global Pte. Ltd. (Singapore)
• Respondents (defendants): Kangxi Communication Technologies (Shanghai) Co., Ltd.; Grand Chip Labs, Inc. (Tustin, CA); D-Link Corporation (Taiwan); D-Link Systems, Inc. (Irvine, CA); Ruijie Networks Co., Ltd. (Fujian, China)
• Jurisdiction: U.S. International Trade Commission
• Case number: Inv. No. 337-TA-1413
• Filing date: Complaint filed July 17, 2024; ITC instituted the investigation August 16, 2024 (Notice of Institution issued ~August 2024)
• Patents asserted: Five patents including US 7,409,200 (also US 8,717,101, US 9,917,563, US 9,450,579, US 9,148,194)
• Status/outcome regarding the '200 patent: Terminated as to US 7,409,200 by partial termination based on Skyworks' withdrawal — ITC declined to review the ALJ's Initial Determination (No. 13, dated Nov. 8, 2024), with notice issued December 10, 2024.
• Overall outcome: On January 23–24, 2026, the ALJ issued an initial determination that respondents did not violate Section 337 as to the two remaining patents (US 9,917,563 and US 8,717,101). On April 24, 2026, the ITC administrative law judge terminated the entire investigation based on a withdrawal agreement, Skyworks having unconditionally withdrawn its complaints. (Kangxi disclosed the full termination on April 27–28, 2026.)

2. C.D. Cal. Case No. 8:24-cv-00976 — Skyworks Solutions Canada, Inc. et al. v. Kangxi Communication Technologies Shanghai Co., Ltd. et al.

• Plaintiffs: Skyworks Solutions Canada, Inc.; Skyworks Global Pte Ltd.
• Defendants: Kangxi Communication Technologies (Shanghai) Co., Ltd.; Grand Chip Labs, Inc. (First Amended Complaint, filed July 17, 2024, added D-Link Corporation, D-Link Systems, Inc., and Ruijie Networks Co., Ltd.)
• Jurisdiction: U.S. District Court, Central District of California (Judge Fred W. Slaughter; Magistrate Judge Autumn D. Spaeth)
• Case number: 8:24-cv-00976-FWS(ADSx)
• Filing date: May 6, 2024
• Patent(s) asserted: US 7,409,200 (this case is the Skyworks action asserting the '200 patent; the related companion case 8:24-cv-00974 asserts the other four patents)
• Status/outcome: Stayed September 13, 2024, under 28 U.S.C. § 1659(a) pending final resolution of ITC Inv. No. 337-TA-1413, and administratively terminated/closed (JS-6). In April 2026, Skyworks voluntarily dismissed the stayed district-court patent litigation, with the court's approval, terminating the case.

3. PTAB Inter Partes Review IPR2025-00912 — Kangxi Communication Technologies Shanghai Co., Ltd. et al. v. Skyworks Solutions Canada, Inc. et al.

• Petitioner (challenger): Kangxi Communication Technologies Shanghai Co., Ltd. et al.
• Patent owner (respondent): Skyworks Solutions Canada, Inc. et al.
• Jurisdiction: USPTO Patent Trial and Appeal Board
• Case number: IPR2025-00912 (U.S. Patent 7,409,200; application 10/857,938)
• Filing date: April 22, 2025
• Status/outcome: Not instituted. The Board issued a discretionary denial of institution on September 12, 2025 (institution decision date 09/12/2025), after Patent Owner sought discretionary denial. The petitioner filed a request for Director review of the discretionary denial on October 14, 2025. The proceeding was therefore terminated without trial. (Google Patents metadata similarly codes IPR2025-00912 as "Not Instituted – Procedural.")

4. Unverified ITC docket entry: "337-TA-3762"

The Google Patents record for US 7,409,200 links to a Unified Patents litigation entry for an ITC case captioned "337-TA-3762." I could not independently verify this number through any search results, and it does not appear in the ITC/Unified Patents records for the Skyworks–Kangxi dispute (which is 337-TA-1413). Treat this entry as unverified data in the patent record rather than a confirmed proceeding.

Summary of current status (as of April 26, 2026): All substantive litigation over US 7,409,200 has concluded or been terminated. The ITC investigation (337-TA-1413) was terminated as to the '200 patent in December 2024 (withdrawal), and the entire investigation was terminated April 24, 2026; the parallel C.D. Cal. case (8:24-cv-00976) was stayed in September 2024 and has been voluntarily dismissed (April 2026); and the PTAB IPR (IPR2025-00912) was denied institution in September 2025.

Proceedings overview

One AIA trial proceeding is on file for US 7,409,200 — IPR2025-00912 — filed 2025-04-22 by Kangxi Communications Technologies against Skyworks Solutions Canada, Inc. (successor to original assignee SiGe Semiconductor Inc.) and denied institution on discretionary grounds on 2025-09-12, so the breakdown is 0 active, 0 settled, 0 claims invalidated, 0 claims sustained on the merits, and 1 institution denied — meaning the patent exits the PTAB wars with all 34 claims intact and un-narrowed, and no estoppel has attached to anyone.

Note on sources: the USPTO ODP ingest block in this prompt shows no AIA trials, but web sources confirm IPR2025-00912 — it is recent (filed 2025-04-22), which likely explains the ODP lag. Google Patents' own litigation metadata (Unified Patents PTAB feed) lists it as "filed (Not Instituted - Procedural)," corroborating the web findings. Details below come from the Director's institution decision (PTACTS), RPX, ipverse, and petition summaries.

IPR2025-00912 — Kangxi Communications Technologies v. Skyworks Solutions Canada, Inc.

• Type: Inter Partes Review
• Filed: 2025-04-22
• Status: Discretionary Denial — petition denied, no trial instituted (procedural, "Not Instituted")
• Judge panel: No APJ panel. The institution decision was issued at Director level by Coke Morgan Stewart, Acting Under Secretary and Acting Director, under the 2025 bifurcated discretionary-denial process (per the decision caption "Before COKE MORGAN STEWART…").
• Petition grounds (per petition summaries in public trackers): challenged claims 1-2, 4, 6, 10-15, 18-20, 23-26, and 29-31 (independents 1, 18, 26 plus dependents) under 35 U.S.C. § 103:
  • Ground 1: obviousness over U.S. Pub. No. 2003/0017809 ("Garlepp");
  • Ground 2: obviousness over Magoon et al., "A Single-Chip Quad-Band…" (2002 IEEE publication, EX-1006) in view of a 2003 single-package RF-module symposium paper (identified in secondary sources as "Ngompe"; I could not independently verify that citation's canonical form — treat the second reference's exact bibliographic details as unconfirmed).
  • Supporting declaration of Dr. Ayman Fayed (EX-1003) and prosecution history (EX-1002).
• Institution decision: Denied — 2025-09-12, 35 U.S.C. § 314(a). Skyworks filed a request for discretionary denial (2025-07-23) on the sole ground that the '200 patent's 17+ years in force created "settled expectations" of validity; Kangxi opposed (2025-08-22). The Director granted the request and denied institution. Key reasoning: "the challenged patent has been in force for over seventeen years, creating strong settled expectations for Patent Owner, and Petitioner does not provide persuasive reasoning why an inter partes review is an appropriate use of Board resources" — citing Dabico Airport Sols. Inc. v. AXA Power ApS, IPR2025-00408, Paper 21 (Director June 18, 2025). The Director acknowledged countervailing facts (a projected FWD in October 2026 would precede the stayed district-court trial; the parallel ITC investigation no longer involved the '200 patent) but found settled expectations tipped the balance. Order: "the Petition is denied, and no trial is instituted." (Decision, PTACTS; ipverse docket; RPX Empower)
• Final Written Decision: None — no trial was instituted, so no claim was reached, much less canceled, on the merits.
• Settlement / termination: No settlement. The proceeding was terminated by the institution denial; Skyworks then withdrew counsel (motion 2025-09-15; Board order 2025-09-25) and filed an updated power of attorney (2025-10-01).
• Appeal: No FWD exists, and institution denials are not appealable to the Federal Circuit. Kangxi instead filed a Request for Director Review of the discretionary denial on 2025-10-14; as of this analysis I could not locate a public disposition of that request (the docket status remains "Discretionary Denial"). The case is, however, being cited in Federal Circuit mandamus litigation over the Director's settled-expectations denial policy (see references to IPR2025-00912 in In re Volkswagen Group of America, Fed. Cir. No. 26-123 briefing) — a signal that the denial rationale is under active appellate challenge in other cases, not an appeal of this one.
• Defensive value: Limited but real. No claim is dead — any infringement theory built on claims 1, 18, or 26 stands, so a defendant cannot cite an IPR cancellation. The silver lining: because institution was denied without a FWD, no § 315(e) estoppel attaches, and the exact Garlepp and Magoon-based § 103 grounds remain fully available to Kangxi (and to any other defendant) in district court. The petition, expert declaration, and prior-art package are public and can be mined for district-court invalidity contentions.

Strategic summary

Claims CANCELED vs. SUSTAINED vs. UNTESTED. No claims of the '200 patent have been canceled — no IPR has ever reached a Final Written Decision. The 20 claims Kangxi challenged (1-2, 4, 6, 10-15, 18-20, 23-26, 29-31) are untested on the merits: the Director denied institution purely on discretionary "settled expectations" grounds, expressly without deciding obviousness. The 14 claims never even placed in issue (3, 5, 7-9, 16-17, 21-22, 27-28, 32-34) are likewise untested. The practical result is that Skyworks has successfully fended off the only AIA challenge ever filed against this patent without having to defend a single claim's validity on the merits — the patent is not "hardened" by a merits win; it is simply procedurally un-scratched.

Estoppel landscape. There is no § 315(e)(2) estoppel against anyone. Estoppel under § 315(e) runs only from a final written decision, and there is none. Kangxi (and its privies) can re-raise Garlepp, Magoon, and every other ground "reasonably could have raised" in the stayed C.D. Cal. litigation (Skyworks Solutions Canada, Inc. et al. v. Kangxi Communication Technologies (Shanghai) Co., Ltd. et al., No. 8:24-cv-00976-FWS-ADS) and in the ITC. A brand-new defendant faces zero estoppel and can run any prior art, including art that post-dates the '200 patent's 2003 priority date, in district court.

Pattern signals. The '200 patent is one of five Skyworks patents (with 8,717,101; 9,917,563; 9,450,579; and 9,148,194) asserted against Kangxi in C.D. Cal. and in ITC Inv. No. 337-TA-1413 (instituted August 2024); Kangxi filed a coordinated set of IPRs, of which IPR2025-00912 (the '200 patent) is the one that was discretionarily denied. Skyworks dropped the '200 patent from the ITC in December 2024 (the Director's decision text reads "2004," evidently a typographical error for 2024) but kept it in the district court case, which is stayed pending the ITC. The patent owner is plainly aggressive — it sought and won discretionary denial rather than defending validity — and the Google metadata also lists a second ITC matter, 337-TA-3762, whose current scope I could not verify. Note also that Google's legal-status metadata shows the patent as "Expired - Lifetime" with an adjusted expiration of 2026-04-01 (12th-year maintenance fee paid 2020-02-05); if that expiration date is accurate, the patent is now past term, which caps any recovery to pre-expiration damages and eliminates injunctive relief — verify on USPTO Patent Center before relying on it.

Recommended next steps

• No FWD exists to hand the court. If you are a defendant in the Skyworks/Kangxi district-court case (or facing a new demand letter), your strongest move is not a new IPR — the Director's settled-expectations rationale (17+ years in force, citing Dabico) signals a fresh petition on this aging patent faces meaningful discretionary-denial risk under the current Director-led institution process — but rather district-court invalidity using the very grounds Kangxi already briefed. Pull IPR2025-00912's petition and the Fayed declaration from PTAB E2E/PTACTS; because institution was denied, nothing in them is estopped, and they constitute a ready-made obviousness roadmap (Garlepp alone; Magoon + the 2003 single-package paper).
• Check the dangling Director Review. Kangxi's Request for Director Review of the 2025-09-12 denial was filed 2025-10-14; I could not locate its disposition. Confirm on the PTAB docket (IPR2025-00912) whether it was denied or granted — a grant would reopen the possibility of trial, though Director-review decisions on institution are themselves not appealable.
• Confirm patent status. Verify the adjusted expiration date (2026-04-01 per Google metadata; status "Expired - Lifetime") on USPTO Patent Center. If expired, frame the defense around damages limitations and the absence of injunctive relief, and check the scope of ITC Inv. No. 337-TA-3762 if your product is in the RF front-end module space — the '200 patent's litigation metadata lists it, but its current claim/patent scope is unverified in my sources.
• Bottom line for a defendant today: no claim of the '200 patent has been canceled or even merits-tested, so this is not a "dead patent" situation; but the sole IPR attempt also created zero estoppel and zero merits precedent, leaving the patent fully vulnerable to district-court invalidity attacks on grounds the PTAB never reached.

Inventors

• James H. Derbyshire — employer at filing: SiGe Semiconductor, Inc. (Ottawa, Canada / Andover, MA). Confirmed by the recorded assignment (Reel 015432/Frame 0084), which lists both inventors as assignors to SiGe.
• Alan J. A. Trainor — employer at filing: SiGe Semiconductor, Inc. (same assignment record).

Unusual patterns: none observed. Both inventors assigned their interests to the named original assignee at filing (execution dates 2004-05-27 / 2004-05-28), which is the standard employer‑assignment pattern. There is no evidence either inventor departed SiGe within 12 months of filing, and the 2011 Skyworks acquisition occurred ~7 years after filing, so no "inventors flee, portfolio fire-sale" signature is present.

Original assignee

SiGe Semiconductor, Inc. (recorded as "SIGE SEMICONDUCTOR INC."; Google Patents renders it "Sige Semiconductors Inc").

• Products: SiGe was a fabless RF-front-end semiconductor company selling highly integrated Wi-Fi (802.11a/b/g/n), Bluetooth, GPS, WiMAX and ZigBee front-end modules and power amplifiers. The company stated it had shipped more than 750 million front-end solutions (Skyworks press release, May 17, 2011). The patented multi-standard module-integration architecture is squarely within SiGe's product line (Wi-Fi front-end modules/PAs integrating LNA/PA/switch/control circuitry in one package).
• Line of business: RF front-end module supplier to Cisco, Dell, Huawei, HP, NetGear, Microsoft, Nintendo, Samsung, Sony, etc.
• Current status: Acquired — not dissolved in bankruptcy. Skyworks Solutions, Inc. (NASDAQ: SWKS) signed a definitive merger agreement May 17, 2011 and closed the cash acquisition June 10, 2011 ($210M cash + up to $65M earnout), per Skyworks 8-K filings. SiGe's IP and product line became part of Skyworks, which continues to operate.

Assignment timeline

Data-verification note: I could not execute a direct interactive query against the USPTO Assignment Center in this session. The one recorded assignment below is verifiable from the USPTO-derived legal-event feed reproduced on Google Patents (which carries the reel/frame and execution dates). I am flagging — not fabricating — the items I could not independently confirm.

• 2004-05-27 / 2004-05-28 (executed) — recorded 2004-06-02 — Reel 015432 / Frame 0084
  • Conveyance: Assignment of assignors' interest (inventor → employer)
  • Assignor: James H. Derbyshire; Alan J. A. Trainor
  • Assignee: SiGe Semiconductor Inc.
  • Correspondent: not disclosed in the legal-event data available to me (the USPTO Assignment Center record would show the correspondent of record; I could not retrieve it here).
  • Context: standard pre-issuance assignment executed at filing, transferring the application (then US10/857,938, filed 2004-06-02) from the inventors to their employer.

No further recorded assignments appear in the Google Patents / USPTO legal-event feed for US 7409200. In particular, there is no recorded SiGe → Skyworks assignment or merger document against this specific patent number in that feed. Google Patents still lists "Sige Semiconductors Inc" as current assignee, which is consistent with no post-issuance patent-specific assignment having been recorded. Ownership in fact passed to Skyworks Solutions, Inc. by operation of the 2011 merger (Skyworks 8-K, June 10, 2011; merger through wholly owned subsidiary "Silver Bullet Acquisition Corp."); whether Skyworks separately recorded the merger against this patent at the Assignment Center could not be verified from the sources I could reach. If the Assignment Center likewise shows no post-issuance record, the recorded chain ends at SiGe Semiconductor Inc. / Skyworks by merger.

Other legal events (maintenance fees paid as a large entity in 2012, 2016, and 2020; patent term expiring 2026-04-01; IPR2025-00912 filed 2025-04-22 by Kangxi Communications Technologies and not instituted) are fee/litigation events, not assignments.

Timeline diagram

timeline
    title Ownership of US 7409200
    2004 : Filed by Derbyshire and Trainor
         : Assigned to SiGe Semiconductor Inc
    2008 : Patent issued
    2011 : SiGe acquired by Skyworks
    2020 : Twelfth year maintenance fee paid
    2024 : ITC and district court cases filed
    2025 : Kangxi IPR filed not instituted
    2026 : Patent term expired

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only recorded assignment is inventors → SiGe Semiconductor Inc. (Reel 015432/Frame 0084, recorded 2004-06-02), an operating company. The 2011 ownership change is a cash merger into Skyworks Solutions, an operating semiconductor company, not a transfer to an "IP / Licensing / Holdings" LLC. No registered-agent-address, single-member LLC, or no-products tell appears anywhere in the chain.

2. Known asserter in the chain — not present. No Acacia, Marathon, Intellectual Ventures, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Round Rock, or Spangenberg entity appears. The owner (SiGe, then Skyworks) is a NASDAQ-listed operating company (SWKS), not a high-frequency NPE plaintiff.

3. Repeat correspondent across the chain — unclear / insufficient data. Only one recorded assignment was identified, and its correspondent of record is not shown in the data I could retrieve. There is therefore no basis to find a repeat-player NPE filing attorney; there is also no evidence of one. A single appearance would not be a finding in any event.

4. Cascading transfers — not present. No chained LLC-to-LLC transfers exist. The chain is two links: inventors → SiGe (2004), and SiGe → Skyworks by merger (2011), ~7 years apart.

5. Pre-litigation transfer — not present. The 2024–2025 assertion activity (ITC investigations 337-TA-1413 and the matter listed as 337-TA-3762, C.D. Cal. case 8:24-cv-00976, and IPR2025-00912) was not preceded by any recorded transfer into an assertion vehicle. The ownership chain was fixed in 2004 and 2011 — more than a decade before litigation.

6. Bankruptcy fire-sale — not present. SiGe was acquired for cash ($210M + $65M earnout) in an arms-length merger, not sold out of Chapter 7/11. No Kodak/Nortel-style bankruptcy auction appears.

7. Privateering — not present. No SEC filing or press coverage I found suggests Skyworks handed this patent to an NPE to sue competitors on its behalf. The patent-expiration-adjusted litigation record is consistent with direct assertion by the operating-company owner against an accused infringer (Kangxi Communications Technologies filed the IPR as challenger, i.e., the accused party).

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN; it remains with the operating company.

Verdict

Operating-company assertion

The chain is inventors → SiGe Semiconductor Inc. (Reel 015432/Frame 0084, recorded 2004-06-02) → Skyworks Solutions, Inc. by cash merger closed 2011-06-10 (Skyworks 8-K / press release). Skyworks is an operating RF-semiconductor company whose products embody this front-end-module technology, and the 2024–2025 ITC/district-court record plus the Kangxi IPR2025-00912 challenge indicates direct assertion against an accused competitor, not NPE enforcement. No shell LLCs, cascading transfers, repeat NPE correspondents, bankruptcy sale, or defensive-aggregator termination appear anywhere in the available record. Caveats: I could not directly query the USPTO Assignment Center to confirm whether Skyworks recorded the merger against this specific patent (no such record appears in the Google Patents legal-event feed), and I could not independently retrieve the complaint's named plaintiff from the docket; verification at https://assignmentcenter.uspto.gov/ (search Patent No. 7409200) is recommended to confirm the recorded chain and the correspondent of record on Reel 015432/Frame 0084.

I'll research US Patent 7,409,200 ("Module integration integrated circuits") and its cited prior art. Let me start by confirming the patent record and pulling its citation list from authoritative sources.

The Google Patents record confirms the citation list. Now let me verify the full bibliographic data for each cited reference, starting with the most art-relevant ones (RF module / amplifier module references).

Good detail on the two Matsushita/Conexant references. Now let me verify the other module-level RF references (Anadigics, Mitsubishi, Murata, Kyocera) that are closest to the claimed subject matter.

I've reached the search-step limit, so I'll consolidate the verified record data and the citation list (as shown on the authoritative full-text record of US7409200B2, mirrored from USPTO data on Google Patents/FreePatentsOnline) into the requested analysis. Note that USPTO's PatFT/Patent Public Search tool was not directly reachable through my search interface; the bibliographic data below is corroborated by Google Patents and FreePatentsOnline records retrieved during this session.

1. Confirmation of the target patent

• Patent No.: US 7,409,200 B2 (publication of application US 2005/0079851 A1)
• Title: Module integration integrated circuits
• Inventors: James H. Derbyshire; Alan J. A. Trainor
• Assignee (original/current): SiGe Semiconductor Inc. (CANADA)
• Application: US 10/857,938, filed 2004-06-02
• Priority: Claims continuation-in-part of US 10/680,208, filed 2003-10-08 (issued as US 7,754,539 B2)
• Grant date: 2008-08-05
• Legal status: Expired – Lifetime (adjusted expiration 2026-04-01; 12th-year maintenance fee paid 2020-02-05)
• Family/litigation context: Listed as having litigation; ITC matters 337-TA-1413 and 337-TA-3762; C.D. Cal. case 8:24-cv-00976; PTAB IPR2025-00912 filed by Kangxi Communications Technologies (docket notes "Not Instituted – Procedural").

I did not substitute any similar-numbered patent. 7,409,200 is a distinct grant from its parent 7,754,539 (the '208 application) and from its counterpart publication 2005/0079851A1.

2. Claims framework used for the § 102 analysis

The patent has 34 claims with three independent claims:

• Claim 1 (apparatus): a first IC die containing a first portion of a first signal conditioning circuit disposed along a first signal path; a second IC die containing a second portion of that same first signal conditioning circuit disposed along the same first signal path, the two portions together performing a first signal conditioning function on a signal propagating along the path; and a substrate supporting both dies and providing electrical connections.
• Claim 18 (method): providing first and second signal-conditioning circuits, each split into first/second portions; implementing the first SCC's first portion in a first die; implementing the first SCC's second portion and both portions of the second SCC in a second die; bonding both dies to a common substrate; and forming electrical connections between the dies to complete the first SCC.
• Claim 26 (apparatus): like claim 1, but the first die carries first and third portions of the first SCC and the second die carries a second portion (interstage) of the same first SCC.

The core inventive distinction over the prior art is splitting one signal-conditioning function (e.g., one PA chain) across two heterogeneous dies (e.g., SiGe + GaAs) with die-to-die wirebonded signal connections — as opposed to the prior-art approach of putting two entire, independent amplifier chains on separate dies.

Statutory context: This is a pre-AIA patent (filed 2004-06-02, priority date 2003-10-08). For § 102(b), the one-year bar date relative to the CIP filing is 2003-06-02; references published before that date are § 102(b) prior art, and references published between 2003-06-02 and the grant date can still qualify under § 102(a) (prior knowledge/patenting before invention) or § 102(e) (earlier-filed U.S. applications published later, e.g., US 7,164,905 B2 and US 7,245,884 B2, both filed in 2000 but published in 2007).

3. Citation-by-citation analysis

The record lists 17 patent citations plus 1 family-cited reference. All bibliographic dates below are taken literally from the USPTO-derived citation list in the patent record; the descriptions of the references flagged "searched" were verified against live search results during this session.

A. Closest art — multi-die / multi-band RF modules and amplifier modules

1. US 6,075,995 A — "Amplifier module with two power amplifiers for dual band cellular phones"

• Assignee: Conexant Systems, Inc.; filed 1998-01-30; published 2000-06-13. (Verified live.)
• Description: A dual-band PA module on a multi-layer substrate carrying two separate semiconductor chips, each chip being an integrated circuit forming part of a respective PA for a different RF band (GSM ~900 MHz and DCS ~1800 MHz), operable independently, plus a corresponding manufacturing method (mount two chips, connect them and passives on one substrate).
• § 102 analysis: This is the closest single reference to claims 18 and 1 in structure (two dies on a common substrate forming PAs; method claim 21 of the reference closely parallels the "two dies + one substrate + electrical connection" method). However, Conexant places two separate power amplifiers (two distinct signal-conditioning circuits) on two dies; it does not disclose splitting one PA/signal-conditioning function into first/second portions disposed on different dies and connected along one signal path. It therefore potentially anticipates the substrate/two-die apparatus framework of claim 1 and the method steps of claim 18 only if "second signal conditioning circuit" is read broadly; the missing "portions of the same first signal conditioning circuit on different dies" element makes true single-reference anticipation of claims 1, 18, or 26 unlikely. Most probative against dependent claims 2–3 (two SCCs, similar functions).

2. US 7,164,905 B2 — "High frequency module"

• Assignee: Mitsubishi Denki Kabushiki Kaisha; filed 2000-08-24; published 2007-01-16 (U.S. grant; qualifies under § 102(e) via its 2000 filing date).
• Description: A high-frequency (RF) module integrating multiple functions — typically multiple amplifier/MMIC dies and matching circuitry on a shared substrate for wireless-communication front ends.
• § 102 analysis: Potentially anticipatory of the claim 1 apparatus combination (multiple RF dies co-packaged on a substrate with interconnects) and of claim 18's bonding/connecting method, to the extent it places RF function portions on separate dies. Because the published record is dated after the '200 application's 2004 filing, its availability rests on § 102(e), and anticipation of the "same signal conditioning circuit split across dies" limitation (claims 1, 26) is not evident on the face of the citation abstract.

3. US 7,245,884 B2 — "RF module"

• Assignee: Murata Manufacturing Co., Ltd.; filed 2000-06-20; published 2007-07-17 (U.S. grant; § 102(e) candidate via 2000 filing).
• Description: An RF module, typically a multi-layer-substrate package integrating RF front-end components (filters, switches, amplifiers) for multi-band operation.
• § 102 analysis: Relevant to claim 1 (multi-die RF apparatus on a shared substrate) and claim 18 (module manufacturing method with multiple dies on a common substrate). As with the Mitsubishi reference, its late publication date makes § 102(e) the operative subsection; it does not on its face disclose the claimed same-circuit split across dies of claims 1/26.

4. US 6,683,512 B2 — "High frequency module having a laminate board with a plurality of dielectric layers" (listed under "Family Cites Families")

• Assignee: Kyocera Corporation; filed 2001-06-21; published 2004-01-27.
• Description: An RF module built on a multi-layer laminate substrate carrying multiple high-frequency dies/components, addressing isolation and interconnection on the laminate.
• § 102 analysis: The laminate-board carrier with multiple RF dies is directly relevant to the "substrate for supporting the first and second dies and providing electrical connection" element of claim 1 and to the bonding step of claim 18. Published ~6 months before the CIP's June 2004 filing, it is § 102(b)/(a) art. It does not disclose splitting a single conditioning circuit between two dies (claims 1, 26).

5. US 2001/0011926 A1 — "Multiple-band amplifier"

• Assignee: Anadigics, Inc.; filed 1996-06-03; published 2001-08-09. (Verified live.)
• Description: A multi-band amplifier with multiple amplifier paths for different bands (e.g., 800 MHz cellular and 1900 MHz PCS), switchable impedance/input/output matching networks, and interstage impedance control — preferably a GaAs MMIC.
• § 102 analysis: Discloses multiple signal-conditioning (amplifier) paths and band-selective matching, relevant to dependent claims 2, 3, 6–9 (multiple SCCs; amplifier + impedance-matching portions). However, it teaches monolithic integration of the parallel amplifiers (not splitting one chain across two separate dies on a substrate), so it does not anticipate claims 1, 18, or 26. It is § 102(b) art (published well before 2003-06-02).

6. US 6,054,900 A — "Power amplifier MMIC and mobile communication terminal"

• Assignee: Matsushita Electric Industrial Co., Ltd.; filed 1998-03-09; published 2000-04-25. (Verified live.)
• Description: A multi-stage power-amplifier MMIC with input/interstage/output matching circuits and parallel final-stage transistors, optimizing on-chip layout; claims a mobile terminal incorporating it.
• § 102 analysis: Relevant to dependent claims 6–9 (PA with impedance-matching/amplifier-stage architecture) and to the interstage-matching concept of claim 32 (dependent on claim 26), but the matching and amplifier stages are all on one MMIC substrate — opposite of the claimed die-split. Not anticipatory of independent claims 1, 18, 26; § 102(b) art.

7. WO 2003/061174 A2 — "Configurable wireless interface"

• Assignee: Berkana Wireless Inc.; filed 2002-01-10; published 2003-07-24.
• Description: A configurable multi-standard wireless interface (software/configurable radio) supporting multiple air-interface standards, including RF front-end and baseband partitioning.
• § 102 analysis: Relevant conceptually to the "multi-standard, one standard active at a time" problem in the '200 specification and to dependent claims 2–3 (plural standards). It does not disclose the specific dual-die split-conditioning-circuit structure of claims 1/26, and as a configurable-radio architecture it is unlikely to singly anticipate any apparatus claim; it was likely applied by the examiner in combination (a § 103-type role). § 102(b) art (published 2003-07-24, after the 2003-06-02 bar date relative to the CIP, but before the parent's 2003-10-08 priority filing — § 102(a) availability).

8. US 5,983,089 A — "Slotline-mounted flip chip"

• Assignee: Endgate Corporation; filed 1994-09-26; published 1999-11-09. (Cited by examiner.)
• Description: RF component packaging using slotline-mounted flip-chip attachment of an MMIC die to a carrier, providing low-parasitic RF interconnection.
• § 102 analysis: Relevant only to the mechanical "die on substrate with electrical connection" elements of claim 1 and the bonding/connecting steps of claim 18 (flip-chip mounting). It is not an amplifier-module reference and does not disclose split signal-conditioning circuits; no realistic anticipation of claims 1, 18, or 26 standing alone.

B. Packaging / interconnection / multichip references (secondary relevance)

9. US 5,732,945 A — "Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes"

• Assignee: International Business Machines Corporation; filed 1995-02-22; published 1998-03-24.
• Description: Multichip modules consolidating support/ESD circuitry on a common structure for multiple I/O chips.
• § 102 analysis: Discloses co-packaging of multiple chips with shared "ancillary" (protection/control) circuitry — conceptually close to the specification's sharing of voltage-regulator/ancillary circuits (dependent claims 16–17, 33–34). Not a split-RF-conditioning-circuit disclosure; no anticipation of independent claims. § 102(b) art.

10. US 6,734,553 B2 — "Semiconductor device"

• Assignee: NEC Electronics Corporation; filed 2001-05-25; published 2004-05-11. (Cited by examiner.)
• Description: A semiconductor device/package structure — likely relating to multi-chip RF or microwave packaging and interconnects (published in the same technology area as the '200 family).
• § 102 analysis: Potentially relevant to the substrate/die-interconnect limitations of claim 1 and the die-bonding steps of claim 18, and to dependent claims 12–13/30–31 (die material combinations). Published 2004-05-11, ~3 weeks before the CIP's June 2, 2004 filing — § 102(a)/102(e) timing. No disclosure of splitting a single signal-conditioning circuit across dies is apparent from the citation data; likely examiner-applied as secondary art.

11. EP 0 434 074 A1 — "Wire bond connection system"

• Assignee: International Business Machines Corporation; filed 1990-01-03; published 1991-07-10.
• Description: A wire-bond interconnection system for connecting bond pads between chips/leads (wire bonding between co-packaged components).
• § 102 analysis: Bears on the "forming electrical connections between the two dies" / "wire bonding between the two dies" elements of claim 18 (and the connection elements of claims 27–28). It is a generic interconnect teaching only; cannot singly anticipate any claim. § 102(b) art.

12. WO 1996/013965 A1 — "Method of surface mounting radio frequency components and the components"

• Assignee: Baier & Baier, Inc. d/b/a Lark Engineering; filed 1994-10-26; published 1996-05-09.
• Description: Surface-mount assembly techniques and components for RF circuits on a substrate.
• § 102 analysis: Relevant to the carrier-substrate and electrical-connection framework of claim 1 and the method steps of claim 18 (mounting/bonding RF components to a substrate). No multi-die signal-circuit split; not anticipatory of independent claims. § 102(b) art.

13. US 5,258,325 A — "Method for manufacturing a semiconductor device using a circuit transfer film"

• Assignee: Kopin Corporation; filed 1990-12-31; published 1993-11-02.
• Description: Transfer-film-based manufacturing of thin semiconductor devices (layer transfer / hetero-epitaxial integration).
• § 102 analysis: Remote; relates to how dies are made/transferred rather than to RF module partitioning. At most background for die-formation steps in claim 18; not anticipatory.

14. JP 2001-298123 A — "High frequency wiring board"

• Assignee: Hitachi Ltd.; filed 2000-04-17; published 2001-10-26.
• Description: A high-frequency wiring/laminate board (Japanese-language reference) for mounting RF components with controlled high-frequency characteristics.
• § 102 analysis: Relevant to the "substrate for supporting the dies and providing electrical connection" element of claim 1 and the common-substrate step of claim 18. Board-level disclosure only; does not teach the die-split conditioning circuit. § 102(b) art (Japanese published application).

15. EP 1 385 305 A1 — "Signal conditioning circuit with input equalization and output pre-emphasis"

• Assignee: Broadcom Corporation; filed 2002-07-22; published 2004-01-28.
• Description: A wired-line signal-conditioning (equalization/pre-emphasis) circuit — note the phrase "signal conditioning circuit," but in a serial-link/line-driver context, not RF PA front ends.
• § 102 analysis: Potentially relevant only to the generic "signal conditioning circuit" claim language of claims 1, 18, and 26 if read at the highest level of generality — but the reference's conditioning function (equalization) is unrelated to RF amplification/matching and is not split across two semiconductor dies on a shared substrate. No reasonable anticipation of any claim; likely cited for the "signal conditioning circuit" terminology. § 102(b) art (published 2004-01-28, after the 2003-06-02 bar date; § 102(a) timing).

16. US 2003/0165052 A1 — "Semiconductor device and manufacturing the same"

• Inventor/Applicant: Mikio Negishi; filed 2002-03-01; published 2003-09-04.
• Description: A semiconductor device and its manufacture — in the RF-module/stacked-die packaging space per the classification neighborhood of the '200 patent.
• § 102 analysis: Relevant to multi-die module packaging elements of claim 1 and the manufacturing steps of claim 18. No indication from the citation record of a split signal-conditioning circuit; not anticipatory of the independent claims. § 102(b) art (published 2003-09-04, after the June 2003 bar date relative to the CIP but before the 2003-10-08 priority filing — § 102(a) availability).

C. Peripheral / non-RF references (cited by the examiner in the search but far from the claimed invention)

17. US 5,844,853 A — "Memory regulator control method with flexibility for a wide change in supply voltage"

• Assignee: Texas Instruments Inc.; filed 1996-02-01; published 1998-12-01.
• Description: A voltage-regulator control method for memory supplies.
• § 102 analysis: Relevant only to the voltage-regulation ancillary circuit language in dependent claims 16–17 and 33–34 (regulator circuits integrated with signal-conditioning circuitry). It is a memory-supply regulator, not an RF PA bias/regulator, and discloses no module/die architecture. Not anticipatory of any claim; background art.

18. EP 0 543 430 A2 — "Pressure sensor and method of assembly thereof"

• Assignee: Delco Electronics Corporation; filed 1991-11-20; published 1993-05-26.
• Description: A pressure-sensor assembly and method — an unrelated MEMS/sensor packaging disclosure.
• § 102 analysis: Cited presumably for generic multi-component assembly/substrate mounting; no RF signal-conditioning teaching. Not anticipatory of any claim; no meaningful § 102 exposure.

4. Bottom line on most relevant prior art

Ranked by likely § 102/103 significance against claims 1, 18, and 26:

1. US 6,075,995 A (Conexant) — closest structural art for claims 1 and 18 (two PA chips on one substrate, independent dual-band operation, plus a manufacturing-method claim), though it teaches two separate amplifiers rather than one amplifier split across dies.
2. US 7,164,905 B2 (Mitsubishi) and US 7,245,884 B2 (Murata) — closest multi-function RF module art for claim 1's die+substrate combination; available only under § 102(e) because of their 2007 issue dates.
3. US 6,683,512 B2 (Kyocera) — laminate multi-die RF module, § 102(b) timing.
4. US 2001/0011926 A1 (Anadigics) and US 6,054,900 A (Matsushita) — best art on the amplifier-stage + impedance-matching structure of dependent claims 6–9 and 32, but monolithic rather than die-split.
5. EP 0 434 074 A1 (IBM) and WO 96/13965 (Lark) — wire-bond/substrate-connection art for the claim 18 "forming electrical connections between the two dies" limitation.

Caveat on anticipation: None of the 18 references, on the face of the citation data and titles alone, discloses the full combination of an independent claim — most critically the same signal-conditioning circuit partitioned into portions on two different semiconductor dies (SiGe/GaAs or similar) with die-to-die signal connections along one signal path (claims 1 and 26). The examiner's citation set is therefore more consistent with rejections under § 103(a) combining, e.g., a Conexant/Mitsubishi-type module with an Anadigics/Matsushita-type PA-matching architecture, than with clean single-reference § 102 anticipation. I was not able to confirm the specific grounds in the IPR2025-00912 petition (not instituted) or the ITC pleadings, which may assert additional references not shown on the face of the patent.

Sources: https://patents.google.com/patent/US7409200B2/en (full record and citation list); https://www.freepatentsonline.com/[6075995](/patent/6075995).html and https://patents.google.com/patent/US6075995 (US 6,075,995); https://www.freepatentsonline.com/[6054900](/patent/6054900).html and https://patents.google.com/patent/US6054900 (US 6,054,900); https://freepatentsonline.com/y2001/0011926.html and https://patents.google.com/patent/US20010011926 (US 2001/0011926 A1). The USPTO Public Search (PPUBS) database itself was not directly accessible from this environment; the bibliographic data above traces to USPTO-derived records and was cross-checked with live search results where available.

OBVIOUSNESS ANALYSIS — U.S. PATENT NO. 7,409,200 B2 ("Module Integration Integrated Circuits")

Patent: US7409200B2 (application 10/857,938, filed 2004-06-02; CIP of 10/680,208, filed 2003-10-08, published as US7754539B2)
Assignee: SiGe Semiconductor Inc. | Inventors: J. H. Derbyshire, A. J. A. Trainor
Status context: Expired – Lifetime (adjusted expiration 2026-04-01). PTAB IPR2025-00912 (Kangxi Communications Technologies) was filed but Not Instituted – Procedural, so there is no PTAB merits determination of obviousness on the record shown.

I. Scope of the claims (what a § 103 challenger must establish)

Three independent claims anchor the analysis:

• Claim 1 — an apparatus with (i) a first IC die containing a first portion of a first signal-conditioning circuit disposed along a first signal path; (ii) a second IC die containing a second portion of that same first signal-conditioning circuit, also along the first signal path, performing the first signal-conditioning function together with the first portion; and (iii) a common substrate supporting both dies and providing electrical connection to/from them.
• Claim 18 — a method: partition a first SCC into first/second portions, put the first portion in a first die and the second portion (plus both portions of a second SCC) in a second die, bond the dies to a common substrate, and interconnect the dies to complete the first SCC.
• Claim 26 — the three-portion version: first and third portions of the first SCC in the first die, a second portion (preferably an interstage matching circuit, claim 32) in the second die, with the signal path leaving the first die (620b), traversing the second die, and returning to the first die (620c) (claims 27–28).

Important dependent limitations: second SCC on a different signal path (claims 2, 29); similar conditioning functions (claim 3); silicon-based first die / non-silicon second die (claims 4–5, 12–13); BiCMOS first die (claim 14); PA in the first portion (claim 6); impedance-matching second portion (claims 7, 9, 15); first process "does not facilitate" manufacture of the second portion (claim 10); and ancillary circuits (e.g., voltage regulators) integrated on the first die and shared with circuits on the second die (claims 16–17, 33–34).

II. Person of ordinary skill in the art (PHOSITA)

A designer of RF front-end modules / RFICs circa 2003–2004 with working knowledge of (a) multi-stage PA and LNA design and the role of interstage/output matching networks; (b) heterogeneous semiconductor processes — SiGe BiCMOS and III-V (GaAs/InP/GaN); (c) multichip-module packaging (wire bonding, flip-chip, laminate and thin-film MCM substrates); and (d) multi-band/multi-standard terminal requirements (GSM/DCS/PCS dual-band cellular; IEEE 802.11a/b/g WLAN). This profile is consistent with the art the examiner assembled and with the patent's own background discussion.

III. Governing § 103 framework (brief)

Under Graham and KSR, obviousness is shown where the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious at the time of invention. KSR emphasizes that a combination of known elements "according to known methods" yielding "predictable results" is ordinarily obvious, that design incentives and market forces can supply the motivation, and that "obvious to try" applies where the art points to a finite, predictable set of solutions. Each reference below is prior art (all predate the 2003-10-08 parent priority date; the CIP's new matter would in any event only need to predate 2004-06-02).

IV. Key prior-art references (from the record)

Verified by live search (content confirmed):

• US6075995A — Conexant (Jensen), "Amplifier module with two power amplifiers for dual band cellular phones" (filed 1998-01-30; pub. 2000-06-13). A dual-band PA module: a multilayer substrate; a first semiconductor chip containing a first IC operating as part of a first PA for a first RF band; a second semiconductor chip containing a second IC operating as part of a second PA for a second band; chips plus discrete components mounted on the substrate form "two power amplifiers operable independently of each other on a single multiple layer substrate." Method claims recite etching the substrate, mounting passives, mounting the two chips, and electrically connecting them to form two PAs.
• US6054900A — Matsushita, "Power amplifier MMIC and mobile communication terminal" (filed 1998-03-09; pub. 2000-04-25). A three-stage GaAs PA MMIC in which matching networks are expressly distinct circuit blocks in series along the signal path: input match → transistor 1103 → interstage match 1104 → transistor 1105 → interstage match 1106 → transistor 1107 → output match. Critically, the output matching circuit 1113 is connected "via the package lead array 1111" — i.e., a portion of the PA's signal-conditioning function (matching) is already shown performed off the transistor die, at the package boundary, along the same RF path.
• US20010011926A1 — Anadigics, "Multiple-band amplifier" (earliest date 1996-06-03; pub. 2001-08-09). Multi-band PA with per-band, switchable input/output impedance networks — teaches that multi-band transmitters require band-specific impedance matching and that matching can be placed/partitioned around shared amplifying stages.
• Diels et al., "Single Package Integration of RF Blocks for a 5 GHz WLAN Application," IEEE Trans. Advanced Packaging 24(3):384–391 (Aug. 2001). System-in-package for 5 GHz WLAN; thin-film MCM-D with integrated high-Q passives for bandpass filters and impedance matching; teaches that "a clever chip partitioning can reduce the substrate coupling problem" and that "partitioning also allows using the best IC-technology for each component," while integrating high-quality components in the package to "avoid lower quality on-chip passives."
• Guckenberger & Kornegay, "Integrated DC-DC Converter Design for Improved WCDMA Power Amplifier Efficiency in SiGe BiCMOS Technology," ISLPED '03 (Aug. 25–27, 2003), pp. 449–454. Demonstrates on-chip integration of supply-regulation/DC-DC (ancillary) circuitry in SiGe BiCMOS for use with a power amplifier — the same technological pairing the patent claims.

Relied on from the citation list (titles/context; content not fully re-verified due to search limits — flagged):

• US7164905B2 (Mitsubishi, "High frequency module"), US7245884B2 (Murata, "RF module") — RF modules in which PA/RF functions are realized across multiple semiconductor components on a module; US6734553B2 (NEC, "Semiconductor device"); US5731945A (IBM) — multichip structures with consolidated circuitry; US5983089A (Endgate) — flip-chip RF mounting; EP0436074A1 (IBM) — wire-bond interconnection system; EP0543430A2, US5258325A, WO1996013965A1 — hybrid/transfer/surface-mount assembly techniques.
• Furst, "With GaAs MMICs Towards Dual Band Front End Applications in Wireless Communication," EuMC vol. 2 (1997), pp. 1289–1294 — GaAs MMIC dual-band front-end modules.
• The patent itself admits as background (FIG. 1): modules containing two GaAs PAs plus a separate silicon voltage-regulator die; SiGe BiCMOS integration of bias/regulation/VSWR-sensing circuitry with a 2.45 GHz PA; the low Q-factor of silicon inductors; and the superior gain/loss of GaAs at 5.8 GHz. These admissions supply motivations and expectations of success.

V. Proposed combinations and claim mappings

Combination A — Splitting one signal-conditioning circuit across two semiconductor dies (claims 1, 4–7, 11–15; partially 10, 23, 24)

Primary: US6054900A in view of Diels et al. and US6075995A, optionally with US7164905B2/US7245884B2 and EP0436074A1/US5983089A/US5731945A for die-to-die interconnection.

Mapping:

• US6054900 discloses a "signal conditioning circuit" (a PA) composed of portions disposed in series along one signal path — gain blocks (transistors 1103/1105/1107) separated by matching blocks (1102/1104/1106/1113). It already takes one of those portions (the final output match 1113) off the transistor die and places it at the package/lead level (claims 1, 6–7: "first portion ... power amplifier," "second portion ... impedance matching circuit"). US6054900 thus supplies the concept that a single PA's conditioning function need not be monolithic to one die.
• Diels teaches exactly why and where to relocate such portions: integrate impedance matching with high-Q passives outside the lossy silicon die, and "use the best IC-technology for each component." For a 2.4/5.8 GHz WLAN module, the natural second die is a GaAs die (semi-insulating, high-Q passives — a fact the patent admits was well known), which is precisely claim 5 (second die "other than silicon"), claim 15 (second portion comprises capacitor/inductor/transmission line) and claims 12–14 (materials/BiCMOS).
• US6075995 supplies the packaging half of claim 1: a common multilayer substrate supporting plural amplifier chips and providing the electrical interconnection; combined with EP0436074/US5983089/US5731945 (standard MCM wire-bond/flip-chip die-to-die and die-to-substrate interconnection), a PHOSITA has every structural element of claim 1.
• US7164905/US7245884 (RF modules) reinforce that RF modules of this era routinely co-packaged multiple semiconductor dies performing parts of RF transmit chains.

Rationale to combine / expectation of success: Relocating a discrete, well-characterized matching block (as in US6054900) from a silicon die (lossy, low-Q) to a GaAs die or package-level high-Q medium is a "known method" yielding "predictable results" (better Q, lower insertion loss) — the identical rationale the specification gives for FIG. 6. Diels supplies the partitioning rule ("best IC-technology for each component") and the SiP implementation; US6075995 supplies the module substrate. A PHOSITA would combine them with high confidence and no design change beyond picking the port locations.

Weakest points (candidly): US6054900's off-die match is implemented at the package lead level and Diels' matching is in an MCM-D substrate, neither being "a second integrated circuit semiconductor die." The leap to a second semiconductor die relies on (i) US6054900's own demonstration that matching networks are die-integrable (they are on its GaAs MMIC), (ii) the admitted GaAs high-Q advantage, and (iii) Furst's GaAs MMIC front-end work. If "second integrated circuit semiconductor die" is construed strictly to exclude substrate/passive-level implementation, this combination is stronger for claims 7/15 (matching/inductor/capacitor portions) than for claim 1's bare structure — the feature the examiner presumably weighed most heavily.

Combination B — Two signal-conditioning circuits on separate paths + shared ancillary circuitry on the silicon die (claims 2–3, 8–10, 16–17, 18–25, 29, 33–34)

Primary: US6075995A (dual independent PA chips/module) in view of US20010011926A1 (multi-band matching), Furst (GaAs dual-band front ends), Guckenberger (SiGe BiCMOS on-chip regulator for a PA), and the patent's own admitted FIG. 1 prior art.

Mapping:

• US6075995 alone anticipates the module-level concept of claims 2/29: a second signal-conditioning circuit (second PA, second band) formed by a second chip on the same substrate, operable independently, i.e., "a second signal path that is different than the first signal path." Its two PAs perform "similar" functions (amplification) — claim 3. US20010011926 and Furst corroborate that multi-band transmitters use band-specific PA/impedance paths selected one at a time.
• US6054900 shows a complete GaAs PA + on-die matching, mapping to claims 8–9 (second SCC comprising a PA and an impedance-matching portion) and claim 10 (first, silicon process "does not facilitate" manufacture of the GaAs-implemented portions — consistent with the admitted low-Q silicon passive problem).
• Claims 16–17 and 33–34 are the heart of the "module integration" advance: an ancillary circuit (voltage regulator) integrated in the first die and electrically coupled to circuitry on both dies, rather than a third, separate regulator die as in FIG. 1. The combination: FIG. 1's admitted prior-art module (silicon regulator IC + two GaAs PAs, with the regulator shared between PAs) + Guckenberger's demonstration that regulator/DC-DC circuitry is integrable on-chip with a PA in SiGe BiCMOS. The obvious design move — collapsing the separate regulator die into the silicon/SiGe die already present (the die carrying the first SCC) and running a connection (wire bond) to the second die — yields exactly claims 16–17 with a reduced part count, the patent's own stated objective. GaAs's inability to host such regulators is admitted in the specification, and Guckenberger gives the enabling SiGe process evidence.
• Method claims 18–25 map onto Conexant's method (mount two chips + passives on a common substrate, interconnect to form two independent PAs) once the claim-1 split (Combination A) is layered in; dependent claims 19–20 (separate first/second paths; RF isolation) follow from Conexant's independent PAs and Diels' partition-to-reduce-coupling teaching; claims 21–24 (cost/performance tradeoffs; first die "does not facilitate" the second portion) are the admitted cost/performance hierarchy (Si cheap; GaAs expensive but lower-loss; InP/GaN costlier still).

Rationale to combine: Market forces (dual-band GSM/PCS phones; 802.11a/b/g cards needing one active standard at a time) plus the well-documented cost/size penalty of extra dies (patent's own background) gave a strong design incentive to consolidate shared ancillary functions onto the die whose process supports them and to keep band-specific RF gain on the die whose process performs best. Guckenberger shows the silicon-side enabler; Conexant shows the two-die module template; the interconnection is routine wire-bonding.

Combination C — Three-portion split with interstage matching on the second die (claims 26–28, 30–34; FIG. 6 embodiment)

Primary: US6054900A (interstage matching as an explicit serial circuit block between gain stages; off-die output match) in view of Diels et al. (partitioning for best technology; high-Q passives) and US6075995A + EP0436074A1/US5983089A (substrate and die-to-die interconnect).

Mapping:

• US6054900's chain (stage1 → interstage match 1104 → stage2 → interstage match 1106 → stage3) is a direct structural analogue of claim 26's first/second/third portions: gain portions (first and third portions on one die) with an interstage matching portion (second portion) between them. Claim 32's "interstage matching circuit" is literally US6054900's "second matching circuit 1104 ... connected between the drain terminal of the first transistor 1103 and the gate terminal of the second transistor 1105."
• Claims 27–28 require the RF path to leave the first die (620b), enter the second die, and return (620c) — the off-die output match of US6054900 (via package leads 1111) already demonstrates an RF signal leaving a die and re-entering the package environment for a conditioning function; substituting a second semiconductor die (GaAs) as the home of that block, connected by wire bonds (EP0436074; the patent's own 620b/620c are wire bonds per FIG. 6) or flip-chip (US5983089), is the routine "known method" step.
• The motivation is the strongest in the patent: the specification itself says silicon inductors have degraded Q and that GaAs is the natural home for low-loss matching, while the SiGe die hosts the gain stages plus the control/regulation (claims 33–34, with Guckenberger providing the SiGe regulator evidence). Diels supplies the general algorithm ("best IC-technology for each component"); US6054900 supplies the specific circuit block (interstage match) to relocate. Claim 28's variant (second portion directly coupled to the RF input port) is an obvious alternative port placement of the same block.

Rationale to combine / expectation of success: Because US6054900 identifies interstage matching as a self-contained block and already demonstrates moving a matching function off the die, and because Diels identifies matching/high-Q passives as the components to move to the medium that best supports them, a PHOSITA seeking to improve a SiGe PA's interstage match would predictably relocate that block to a GaAs die in the same module, with die-to-die wire bonds completing the path. No new circuit function is created — only a change of physical partition, at a point the art already treated as a partition boundary.

VI. Overall § 103 conclusion

Claims 2–3, 6–9, 12–15, 18–25, 29, and 32 are the most vulnerable: Conexant (US6075995) substantially covers the two-independent-PA module and method, US6054900 covers the portioned PA chain with off-die matching, and Guckenberger-plus-admitted-FIG.1-prior-art covers shared on-silicon ancillary circuitry for GaAs PAs. Claims 1, 16–17, 26–28, 33–34 are closer calls: their limiting feature is a functional portion of a single signal-conditioning circuit integrated within a second semiconductor die (not discrete passives on a laminate, not MCM-D thin-film passives), which the closest references implement at substrate/package level rather than in a second die. An obviousness case on those claims must lean on (i) US6054900's showing that the very blocks at issue (interstage/output matches) are die-integrable functions routinely re-partitioned, (ii) Diels' express partitioning rule, and (iii) the admitted, well-known material-selection hierarchy (GaAs high-Q/low-loss vs. SiGe control-circuit integration). Under KSR's "predictable variation" and design-incentive analysis, a PHOSITA would have a strong, articulable motivation with a reasonable expectation of success for each combination; the primary doctrinal risk is a narrow claim construction of "integrated circuit semiconductor die" for the second portion, which would push the analysis toward claims 7, 15, 32 (matching/passive portions) where the evidence is strongest.

Note on sourcing: Content for US6075995A, US6054900A, US20010011926A1, Diels et al., and Guckenberger/Kornegay was confirmed via live search of the cited documents. For US7164905B2, US7245884B2, US6734553B2, US5731945A, US5983089A, EP0436074A1, and Furst I relied on the titles/context as listed in the patent's citation record without full text verification; those should be checked against the full documents before reliance in an actual proceeding. All identifiers are reproduced literally as listed in the record.