US 9450579

Here's a concise summary of US Patent 9450579:

US Patent 9450579 Summary

• Title: Radio frequency devices having reduced intermodulation distortion
• Assignee: Skyworks Solutions Inc
• Inventors: Anuj Madan, Fikret Altunkilic, Guillaume Alexandre Blin
• Filing Date: 2015-08-22
• Issue Date (Publication Date): 2016-09-20
• Abstract: Radio-frequency (RF) devices are disclosed providing reduced intermodulation distortion. Disclosed RF and semiconductor devices can include a semiconductor substrate, a switch formed on the semiconductor substrate having a stack of field-effect transistors (FETs) connected in series, and a capacitor formed on the semiconductor substrate and connected in series with the switch, the capacitor configured to inhibit a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch.

Plain-Language Overview of Independent Claims:

• Claim 1 (Semiconductor Die): This claim describes a semiconductor die that acts as a core component of a radio-frequency (RF) switch. It includes:

  • A semiconductor substrate.
  • A first switch circuit on the substrate, connecting an antenna to a transmit node.
  • A second switch circuit on the substrate, connecting the antenna to a receive node.
  • A first capacitor on the substrate, placed in series between the first switch circuit and the antenna node.
  • A second capacitor on the substrate, placed in series between the second switch circuit and the antenna node.
  • A first shunt arm on the substrate, connected to the first switch circuit and the transmit node, which includes a third switch circuit connected to ground.
    The key innovation here is the inclusion of series capacitors (C1 and C2 in the specification, as seen in Figure 9) with the transmit and receive switch paths to the antenna, and the integration of these components, along with a shunt arm, on a single semiconductor die to improve intermodulation distortion (IMD) performance by inhibiting low-frequency blocker signals.

• Claim 7 (Method for Operating an RF Device): This claim outlines a method for operating an RF device that includes the components of Claim 1. The method involves:

  • Providing an RF device as described in Claim 1.
  • Controlling an RF switch within the device by turning the first switch circuit (transmit path) ON and the third switch circuit (transmit shunt) OFF.
  • Using the first capacitor to prevent a low-frequency blocker signal from mixing with a fundamental-frequency signal in the RF switch.
    This method emphasizes the functional benefit of the series capacitor in mitigating intermodulation distortion specifically from low-frequency blocker signals.

• Claim 13 (Wireless Device): This claim describes a wireless device incorporating the RF switch technology. The device includes:

  • A transceiver for processing RF signals.
  • An antenna communicating with the transceiver.
  • A switch module connected to the antenna and transceiver, which routes RF signals. This switch module comprises:
    • A first switch between the antenna and a transmit node.
    • A second switch between the antenna and a receive node.
    • A first capacitor in series with the first switch, between the first switch and the antenna.
    • A second capacitor in series with the second switch, between the second switch and the antenna.
    • A first shunt arm connected to the first switch and the transmit node, which includes a third switch connected to ground.
      This claim places the semiconductor die and its associated capacitors within the broader context of a functional wireless device, highlighting its utility in real-world applications.

Litigation Status:

As of April 26, 2026, the patent family for US9450579 has reported litigation. This includes:

• US cases filed in the California Central District Court and the International Trade Commission (multiple cases noted: 337-TA-1413, 337-TA-3762).
• A PTAB (Patent Trial and Appeal Board) case, IPR2024-01456, which was filed and is noted as "Settlement".
  The patent is currently listed as "Active," with an anticipated expiration date of 2033-07-06.

US Patent 9450579, titled "Radio frequency devices having reduced intermodulation distortion," has been involved in the following known litigation:

1. Skyworks Solutions, Inc. v. Kangxi Communication Technologies Shanghai Co., Ltd. et al.

   • Jurisdiction: U.S. District Court for the Central District of California
   • Case Number: 8:24-cv-00974
   • Filing Date: May 6, 2024
   • Plaintiff(s): Skyworks Solutions, Inc.
   • Defendant(s): Kangxi Communication Technologies Shanghai Co., Ltd., Grand Chip Labs, Inc., D-Link Systems Inc., Ruijie Networks Co., Ltd., D-Link Corp.
   • Outcome/Current Status: The case was closed on September 13, 2024, with an outcome of "Case Stayed," indicating that no substantive verdict on infringement or validity was entered. The litigation was reportedly suspended due to a related '337 investigation' at the International Trade Commission.

2. Certain Wireless Front-End Modules, Devices Containing the Same, and Components Thereof

   • Jurisdiction: International Trade Commission (ITC)
   • Case Number: 337-TA-1413
   • Filing Date: July 16, 2024 (also reported as July 17, 2024)
   • Plaintiff(s)/Complainant(s): Skyworks Solutions, Inc., Skyworks Solutions Canada, Inc., Skyworks Global Pte Ltd.
   • Defendant(s)/Respondent(s): Grand Chip Labs Inc., D-Link Systems Inc., Kangxi Communication Technologies (Shanghai) Co., Ltd.
   • Outcome/Current Status: On January 23, 2026, an Administrative Law Judge (ALJ) issued an Initial Determination ruling that Kangxi Communication Technologies (Shanghai) Co., Ltd. did not infringe on Skyworks' patent rights and found no violation of Section 337. The case is subsequently expected to proceed to administrative review and final ruling stages, and as of April 17, 2026, it is "Pending Before the Commission."

3. Kangxi Communication Technologies (Shanghai) Co., Ltd. v. Skyworks Solutions Inc.

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2024-01456
   • Filing Date: November 12, 2024
   • Plaintiff(s)/Petitioner(s): Kangxi Communication Technologies (Shanghai) Co., Ltd.
   • Defendant(s)/Patent Owner(s): Skyworks Solutions Inc.
   • Outcome/Current Status: The case reached a "Settlement."

Proceedings overview

There is one AIA trial proceeding on file for US patent 9450579. This proceeding was an Inter Partes Review (IPR) which was ultimately terminated due to settlement. This means the patent's claims were not adjudicated on the merits by the PTAB, leaving them untested by a final written decision.

IPR2024-01456 — Kangxi Communication Technologies (Shanghai) Co., Ltd. v. SKYWORKS SOLUTIONS, INC.

• Type: Inter Partes Review
• Filed: 2024-11-12
• Status: Terminated-Settled. The proceeding was concluded due to a settlement between the parties.
• Judge panel: Not publicly available from the provided data.
• Petition grounds: The petition challenged claims 1-6, 9-18 of U.S. Patent No. 9,450,579 as unpatentable under 35 U.S.C. § 103(a). The challenged claims were claims 1-6 and 9-18.
• Institution decision: The PTAB instituted review on claims 1-6 and 9-18 on May 13, 2025. The Board determined that Petitioner showed a reasonable likelihood of prevailing with respect to at least one challenged claim.
• Final Written Decision (if issued): Not issued, as the proceeding terminated due to settlement.
• Settlement / termination: The proceeding was terminated as settled on May 11, 2026. The terms of the settlement are confidential.
• Appeal: No appeal was filed with the Federal Circuit, as the proceeding was terminated by settlement before a Final Written Decision on the merits.
• Defensive value: This proceeding indicates that the PTAB found sufficient merit in Kangxi's challenge to institute review on claims 1-6 and 9-18. However, because the case settled, these claims were not ultimately invalidated by the PTAB. Any defendant facing assertion of these claims will need to assess the strength of the prior art raised in this IPR petition (which led to institution) to determine if a new IPR or other invalidity defense is warranted.

Strategic summary

All 18 claims of US9450579 remain UNTESTED by a Final Written Decision from the PTAB. While claims 1-6 and 9-18 were challenged in IPR2024-01456, and institution was granted for these claims, the proceeding settled before a merits determination. Consequently, no claims of the patent have been canceled or explicitly sustained by the PTAB.

The estoppel landscape for Kangxi Communication Technologies (Shanghai) Co., Ltd., and its privies, would likely bar them from raising the same or reasonably could have raised grounds against claims 1-6 and 9-18 in future PTAB proceedings, due to the settlement after institution. For other defendants, the prior art presented in IPR2024-01456 (which was deemed sufficient for institution) remains available for potential new challenges, provided they are not in privy with Kangxi. The specific prior art used for institution would need to be reviewed to understand which grounds are still available for other parties.

There is no pattern of multiple IPRs from the same petitioner on this patent, nor has the patent owner pursued PTAB appeals aggressively, as only one IPR has been filed, and it settled. Unified Patents has indicated its involvement as the petitioner.

Recommended next steps

• Review the institution decision for IPR2024-01456 to understand the PTAB's reasoning for instituting review on claims 1-6 and 9-18. The institution decision is a public record available on the USPTO PTAB E2E system (e.g., by searching for IPR2024-01456).
• Obtain and analyze the petition and the prior art cited in IPR2024-01456 to assess the strength of the invalidity arguments that led to institution. This information would be valuable for developing a defensive strategy.
• Given that the patent owner chose to settle after institution, it suggests a desire to avoid a full merits review, which could be a signal to potential defendants regarding the perceived weakness of the claims against the challenged art. Further investigation into the details of the instituted grounds is warranted.

Inventors

• Anuj Madan: Likely employed by Skyworks Solutions Inc. at the time of filing, as Skyworks Solutions Inc. is the original assignee.
• Fikret Altunkilic: Likely employed by Skyworks Solutions Inc. at the time of filing, as Skyworks Solutions Inc. is the original assignee.
• Guillaume Alexandre Blin: Likely employed by Skyworks Solutions Inc. at the time of filing, as Skyworks Solutions Inc. is the original assignee.

Original assignee

The original assignee is Skyworks Solutions Inc. They are a public American semiconductor company that develops, manufactures, and markets analog and mixed-signal semiconductor products and solutions. Their products include amplifiers, antenna tuners, attenuators, automotive tuners and digital radios, switches, and RF front-end modules, which are used in various applications like smartphones, automotive, and wireless infrastructure. Skyworks Solutions Inc. is currently operating and publicly traded on the Nasdaq Global Select Market under the ticker symbol SWKS. Recent SEC filings indicate ongoing business operations and financial reporting as of June 2026.

Assignment timeline

No assignments for US9450579 were found in the USPTO Assignment Center.

Timeline diagram

timeline
    title Ownership of US 9450579
    2012 : Priority date of original application
    2015 : Application filed by Skyworks Solutions Inc
    2016 : Patent issued to Skyworks Solutions Inc

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The patent was issued to Skyworks Solutions Inc., an operating company. No transfers to shell entities have been recorded.
2. Known asserter in the chain — Not present. Skyworks Solutions Inc. is not identified as a known NPE/asserter by RPX or Unified Patents.
3. Repeat correspondent across the chain — Not present. No assignments have been recorded for this patent, thus no correspondent chain exists to analyze.
4. Cascading transfers — Not present. No assignments have been recorded for this patent.
5. Pre-litigation transfer — Unclear. Without litigation data for this specific patent, it is not possible to determine if any assignments (were they to exist) occurred within 6 months of a lawsuit.
6. Bankruptcy fire-sale — Not present. Skyworks Solutions Inc. is an active, publicly traded company and has not filed for bankruptcy.
7. Privateering — Not present. No evidence of transfer to an NPE for assertion on behalf of Skyworks Solutions Inc.
8. Defensive aggregator (anti-NPE) — Not present. The patent is still held by the original operating company, Skyworks Solutions Inc.

Verdict

Insufficient data. There are no recorded assignments for US patent 9450579 in the USPTO Assignment Center. The patent remains with the original assignee, Skyworks Solutions Inc., a known operating company that manufactures and sells semiconductor products. Therefore, without any assignment records, it is not possible to identify any NPE/patent-troll patterns.

Verification Link: USPTO Assignment Center - US9450579 (Search by patent number 9450579)

To identify the most relevant prior art for US patent 9450579, I will examine the "Citations" and "Cited By" sections provided in the patent text. The "Citations" section typically lists prior art cited by the applicant or examiner during prosecution, while "Cited By" lists patents that have referenced US9450579. For this task, I will focus on the "Citations" as direct prior art that was considered during the examination of US9450579.

The authoritative patent text for US9450579 lists 40 "Citations" and 1 "Family Cites Families". I will extract information for each of these citations.

Here is an analysis of the most relevant prior art for US Patent 9450579, based on the provided patent text:

Prior Art Citations for US Patent 9450579:

1. US4255756A

• Full Citation: US4255756A - Substrate bias generator
• Publication Date: 1981-03-10
• Filing Date: 1979-01-05
• Brief Description: Discloses a substrate bias generator circuit. While not directly related to RF switches, the concept of biasing substrates could be a foundational element for some aspects of FET control.
• Potentially Anticipates: Potentially foundational to general FET operation and biasing, but unlikely to anticipate the specific capacitor configuration for IMD reduction in RF switches as claimed in US9450579.

2. US4999585A

• Full Citation: US4999585A - Circuit technique for cancelling non-linear capacitor-induced harmonic distortion
• Publication Date: 1991-03-12
• Filing Date: 1989-11-06
• Brief Description: Describes a circuit technique for canceling non-linear capacitor-induced harmonic distortion. This is highly relevant as US9450579 explicitly addresses intermodulation distortion (IMD) using capacitors.
• Potentially Anticipates: Claims 1, 7, and 13 to the extent that they relate to using a capacitor to mitigate distortion caused by non-linearity, particularly Claim 7's focus on "inhibiting a low-frequency blocker signal from mixing with a fundamental-frequency signal in the RF switch using the first capacitor."

3. US5382826A

• Full Citation: US5382826A - Stacked high voltage transistor unit
• Publication Date: 1995-01-17
• Filing Date: 1993-12-21
• Brief Description: Describes a stacked high voltage transistor unit. US9450579 mentions a "stack of field-effect transistors (FETs) connected in series" in its claims, particularly in relation to power handling capability.
• Potentially Anticipates: Claims 1, 7, and 13 regarding the use of stacked FETs in a switch circuit, specifically the "stack of field-effect transistors (FETs) connected in series."

4. US5644266A

• Full Citation: US5644266A - Dynamic threshold voltage scheme for low voltage CMOS inverter
• Publication Date: 1997-07-01
• Filing Date: 1995-11-13
• Brief Description: Focuses on a dynamic threshold voltage scheme for CMOS inverters. This relates to FET operation and control, which is part of the broader context of RF switches.
• Potentially Anticipates: General aspects of FET control and biasing.

5. US5748016A

• Full Citation: US5748016A - Driver circuit
• Publication Date: 1998-05-05
• Filing Date: 1995-03-22
• Brief Description: Discloses a driver circuit, which could be relevant to controlling the ON/OFF states of transistors in a switch.
• Potentially Anticipates: The general concept of a circuit for controlling switches, as mentioned in Claim 7 "controlling an RF switch".

6. US5753955A

• Full Citation: US5753955A - MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates
• Publication Date: 1998-05-19
• Filing Date: 1996-12-19
• Brief Description: Describes a MOS device with gate-to-body connection and current limiting for SOI substrates. This is highly relevant as US9450579 emphasizes SOI FETs and their biasing/coupling.
• Potentially Anticipates: Claims 2, 3, 8, 9, 14 which refer to an insulator layer and SOI technology, and implicitly the body biasing aspects of the FETs.

7. US5969564A

• Full Citation: US5969564A - Insulated-gate field effect transistor and method for driving thereof
• Publication Date: 1999-10-19
• Filing Date: 1997-02-07
• Brief Description: Covers an insulated-gate field effect transistor and its driving method. This is fundamental to FET-based switches.
• Potentially Anticipates: General aspects of FET design and driving mechanisms in the switch circuits of claims 1, 7, and 13.

8. US6281737B1

• Full Citation: US6281737B1 - Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor
• Publication Date: 2001-08-28
• Filing Date: 1998-11-20
• Brief Description: Addresses reducing parasitic bipolar current in SOI transistors. This is relevant to the performance and design of SOI FETs mentioned in US9450579.
• Potentially Anticipates: Claims 2, 3, 8, 9, 14 regarding SOI technology and its performance characteristics.

9. JP2005515657A

• Full Citation: JP2005515657A - Switch circuit and high-frequency signal switching method
• Publication Date: 2005-05-26
• Filing Date: 2001-10-10
• Brief Description: Discloses a switch circuit and a high-frequency signal switching method. This is broadly relevant to the core subject matter of US9450579.
• Potentially Anticipates: The general concept of an RF switch circuit and method of operation as described in Claims 1 and 7, but likely without the specific capacitor-based IMD reduction.

10. US20050195037A1

• Full Citation: US20050195037A1 - Absolute power detector
• Publication Date: 2005-09-08
• Filing Date: 2000-09-12
• Brief Description: Describes an absolute power detector. This is less directly related to the switching mechanism or IMD reduction, but could be part of an RF system that utilizes such switches.
• Potentially Anticipates: Less direct anticipation of the core claims of US9450579.

11. US20050239415A1

• Full Citation: US20050239415A1 - High-frequency switch circuit and high-frequency transmitting/receiving apparatus
• Publication Date: 2005-10-27
• Filing Date: 2004-04-27
• Brief Description: Discloses a high-frequency switch circuit and a high-frequency transmitting/receiving apparatus. This is highly relevant as it describes the type of device and application claimed in US9450579.
• Potentially Anticipates: Claims 1 and 13, regarding the overall RF switch circuit and its integration into a transmit/receive apparatus, but without necessarily the specific IMD reduction technique.

12. US6989706B2

• Full Citation: US6989706B2 - Method for application of gating signal in insulated double gate FET
• Publication Date: 2006-01-24
• Filing Date: 2003-03-27
• Brief Description: Describes a method for applying gating signals in insulated double gate FETs, which is relevant to FET control.
• Potentially Anticipates: General FET control mechanisms in the switch circuits of claims 1, 7, and 13.

13. US7095266B2

• Full Citation: US7095266B2 - Circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches
• Publication Date: 2006-08-22
• Filing Date: 2004-08-18
• Brief Description: Discloses a circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches. Insertion loss is a performance parameter discussed in US9450579.
• Potentially Anticipates: General performance improvements in RF switches, but not specifically the IMD reduction via series capacitors.

14. US7236044B2

• Full Citation: US7236044B2 - Apparatus and method for adjusting the substrate impedance of a MOS transistor
• Publication Date: 2007-06-26
• Filing Date: 2003-10-14
• Brief Description: Describes adjusting the substrate impedance of a MOS transistor. This is relevant to the body biasing and control of FETs, particularly in SOI contexts.
• Potentially Anticipates: Aspects of FET control, especially those related to substrate/body, mentioned in the detailed description of US9450579.

15. US7265604B2

• Full Citation: US7265604B2 - High-frequency switch circuit arrangement
• Publication Date: 2007-09-04
• Filing Date: 2004-11-26
• Brief Description: Discloses a high-frequency switch circuit arrangement. This is directly relevant to the core subject matter.
• Potentially Anticipates: Claims 1 and 13, regarding the general architecture of an RF switch circuit.

16. US7385436B2

• Full Citation: US7385436B2 - Fully depleted silicon on insulator semiconductor devices
• Publication Date: 2008-06-10
• Filing Date: 2005-07-11
• Brief Description: Focuses on fully depleted silicon-on-insulator (SOI) semiconductor devices. This is highly relevant given US9450579's emphasis on SOI FETs.
• Potentially Anticipates: Claims 2, 3, 8, 9, 14 concerning the use of SOI technology for the switch circuits.

17. US7619462B2

• Full Citation: US7619462B2 - Unpowered switch and bleeder circuit
• Publication Date: 2009-11-17
• Filing Date: 2005-02-09
• Brief Description: Describes an unpowered switch and a bleeder circuit. This could relate to the operation of FET switches, especially when in an OFF state.
• Potentially Anticipates: General aspects of switch design, particularly the OFF state characteristics.

18. US7659770B2

• Full Citation: US7659770B2 - High frequency switching circuit
• Publication Date: 2010-02-09
• Filing Date: 2007-04-17
• Brief Description: Discloses a high-frequency switching circuit, directly relevant to the field of US9450579.
• Potentially Anticipates: Claims 1 and 13, for the broader concept of an RF switching circuit.

19. US7659765B2

• Full Citation: US7659765B2 - Resistor circuit
• Publication Date: 2010-02-09
• Filing Date: 2005-06-07
• Brief Description: Describes a resistor circuit. Less directly relevant to the core claims of US9450579, which focus on FETs and capacitors for IMD.
• Potentially Anticipates: Unlikely to anticipate the specific IMD reduction method of US9450579.

20. US20100060377A1

• Full Citation: US20100060377A1 - Switch circuit and semiconductor device
• Publication Date: 2010-03-11
• Filing Date: 2007-08-16
• Brief Description: Discloses a switch circuit and semiconductor device.
• Potentially Anticipates: General switch circuits and semiconductor device implementation as in claims 1 and 13.

21. US7683433B2

• Full Citation: US7683433B2 - Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
• Publication Date: 2010-03-23
• Filing Date: 2004-07-07
• Brief Description: Focuses on improving drive-strength and leakage of deep submicron MOS transistors. This relates to the performance of FETs within a switch.
• Potentially Anticipates: General performance improvements of FETs within a switch, but not the specific IMD reduction.

22. US7848712B2

• Full Citation: US7848712B2 - CMOS RF switch for high-performance radio systems
• Publication Date: 2010-12-07
• Filing Date: 2007-05-03
• Brief Description: Discloses a CMOS RF switch for high-performance radio systems. This is highly relevant to the application space of US9450579.
• Potentially Anticipates: The general concept of an RF switch for high-performance systems (claims 1, 13) and the use of FETs, but likely not the specific capacitor configuration for IMD.

23. US20110025403A1

• Full Citation: US20110025403A1 - Switch with improved biasing
• Publication Date: 2011-02-03
• Filing Date: 2009-07-28
• Brief Description: Describes a switch with improved biasing. Biasing is a key aspect of FET switch control discussed in US9450579.
• Potentially Anticipates: The general concept of improved biasing for switches, particularly in relation to the methods of control mentioned in Claim 7.

24. US7885614B2

• Full Citation: US7885614B2 - Antenna switch with adaptive filter
• Publication Date: 2011-02-08
• Filing Date: 2003-07-22
• Brief Description: Discloses an antenna switch with an adaptive filter. This is highly relevant as US9450579 claims a switch connected to an antenna. While it uses an "adaptive filter", the core idea of connecting to an antenna and potentially filtering signals could be considered.
• Potentially Anticipates: The general architecture of a switch connected to an antenna (claims 1 and 13), though the adaptive filter mechanism differs from the series capacitor for IMD.

25. US7890063B2

• Full Citation: US7890063B2 - Systems, methods, and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using body switching in multistacking structure
• Publication Date: 2011-02-15
• Filing Date: 2006-10-03
• Brief Description: Describes CMOS antenna switches using body switching in a multistacking structure. This is very relevant due to the mention of stacked transistors and body control, both present in US9450579.
• Potentially Anticipates: Claims 1, 7, and 13 regarding stacked FETs and their control, particularly body biasing (as discussed in the detailed description of US9450579).

26. US7898297B2

• Full Citation: US7898297B2 - Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
• Publication Date: 2011-03-01
• Filing Date: 2005-01-04
• Brief Description: Covers dynamic threshold voltage control for MOS transistors. Similar to US5644266A, this is a general FET control technique.
• Potentially Anticipates: General aspects of FET control.

27. US7910993B2

• Full Citation: US7910993B2 - Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink
• Publication Date: 2011-03-22
• Filing Date: 2005-07-11
• Brief Description: Describes improving linearity of MOSFETs using an accumulated charge sink. Linearity and IMD are closely related, and this patent directly addresses improving linearity.
• Potentially Anticipates: Claims 1, 7, and 13 to the extent they aim for improved linearity and reduced IMD, as this patent aims for linearity improvement, though by a different mechanism (charge sink vs. series capacitor).

28. US7928794B2

• Full Citation: US7928794B2 - Method and apparatus for a dynamically self-bootstrapped switch
• Publication Date: 2011-04-19
• Filing Date: 2008-07-21
• Brief Description: Discloses a dynamically self-bootstrapped switch. Bootstrapping is a common technique for enhancing switch performance.
• Potentially Anticipates: General switch control techniques and performance enhancement, but not the specific IMD reduction method.

29. WO2011045442A2

• Full Citation: WO2011045442A2 - Switching system and method
• Publication Date: 2011-04-21
• Filing Date: 2009-10-16
• Brief Description: Discloses a switching system and method. Broadly relevant to the field of US9450579.
• Potentially Anticipates: The general concept of an RF switching system and method (claims 1 and 7).

30. US20110148501A1

• Full Citation: US20110148501A1 - Variable attenuator having stacked transistors
• Publication Date: 2011-06-23
• Filing Date: 2009-12-23
• Brief Description: Describes a variable attenuator with stacked transistors. This is relevant to the use of stacked FETs for signal manipulation.
• Potentially Anticipates: Claims 1, 7, and 13 regarding the use of stacked transistors in a circuit.

31. US20110260773A1

• Full Citation: US20110260773A1 - High power fet switch
• Publication Date: 2011-10-27
• Filing Date: 2010-04-27
• Brief Description: Discloses a high power FET switch. US9450579 discusses high power handling capability.
• Potentially Anticipates: Claims 1, 7, and 13 concerning the use of FETs in a high-power switch configuration.

32. US8441304B2

• Full Citation: US8441304B2 - High-frequency switch circuit
• Publication Date: 2013-05-14
• Filing Date: 2010-04-19
• Brief Description: Discloses a high-frequency switch circuit. Directly relevant to the core subject matter.
• Potentially Anticipates: Claims 1 and 13, for the general concept of an RF switch circuit.

33. US8461903B1

• Full Citation: US8461903B1 - SOI switch enhancement
• Publication Date: 2013-06-11
• Filing Date: 2009-09-11
• Brief Description: Focuses on SOI switch enhancement. This is highly relevant due to US9450579's emphasis on SOI technology.
• Potentially Anticipates: Claims 2, 3, 8, 9, 14 concerning SOI switch implementations and their enhancements.

34. US8514008B2

• Full Citation: US8514008B2 - RF isolation switch circuit
• Publication Date: 2013-08-20
• Filing Date: 2010-07-28
• Brief Description: Describes an RF isolation switch circuit. Isolation is a performance parameter discussed in US9450579.
• Potentially Anticipates: General performance improvements in RF switches, but not specifically the IMD reduction via series capacitors.

35. US20140002171A1

• Full Citation: US20140002171A1 - Body-contacted partially depleted silicon on insulator transistor
• Publication Date: 2014-01-02
• Filing Date: 2012-06-27
• Brief Description: Discloses a body-contacted partially depleted silicon-on-insulator transistor. This is highly relevant to the SOI FETs and their body control in US9450579.
• Potentially Anticipates: Claims 2, 3, 8, 9, 14 regarding SOI technology and body contact, as discussed in the detailed description.

36. US20140009214A1

• Full Citation: US20140009214A1 - Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches
• Publication Date: 2014-01-09
• Filing Date: 2012-07-07
• Brief Description: This patent application, filed on the same priority date (2012-07-07) as US9450579's underlying provisional application (US Provisional Application No. 61/669,045), also from Skyworks Solutions Inc., focuses on SOI-based RF switches. It likely shares significant overlapping technical disclosure with US9450579. It is critical to note that US9450579 states it is a divisional of US13/936,175, filed 2013-07-06, which claims priority to US Provisional Application No. 61/669,045, filed 2012-07-07. This means US20140009214A1 is a related application, likely a co-pending or family member.
• Potentially Anticipates: Given the shared priority date and assignee, this document is likely a family member or co-pending application, rather than prior art in the traditional sense of anticipating the invention. However, its content would be highly relevant for understanding the state of the art by the same inventors.

37. US20140009203A1

• Full Citation: US20140009203A1 - Switch linearization by non-linear compensation of a field-effect transistor
• Publication Date: 2014-01-09
• Filing Date: 2012-07-07
• Brief Description: This patent application, also from Skyworks Solutions Inc. and filed on the same priority date (2012-07-07) as US9450579's underlying provisional, describes switch linearization through non-linear compensation of FETs. This is directly related to improving IMD performance.
• Potentially Anticipates: Similar to US20140009214A1, this is likely a family member or co-pending application. Its technical content on linearity improvement is highly relevant to the IMD reduction goal of US9450579, and could potentially anticipate certain broad aspects of IMD improvement.

38. US20140009208A1

• Full Citation: US20140009208A1 - CMOS Switching Circuitry of a Transmitter Module
• Publication Date: 2014-01-09
• Filing Date: 2012-07-09
• Brief Description: Describes CMOS switching circuitry of a transmitter module. This is highly relevant to the transmit path of the RF device in US9450579.
• Potentially Anticipates: Claims 1 and 13 regarding the first switch circuit between an antenna node and a transmit node.

39. US8723260B1

• Full Citation: US8723260B1 - Semiconductor radio frequency switch with body contact
• Publication Date: 2014-05-13
• Filing Date: 2009-03-12
• Brief Description: Discloses a semiconductor RF switch with body contact. Body contact is a control mechanism for FETs described in US9450579.
• Potentially Anticipates: General aspects of FET control, particularly body contact, mentioned in the detailed description.

40. US8779840B2

• Full Citation: US8779840B2 - High frequency switch
• Publication Date: 2014-07-15
• Filing Date: 2010-12-20
• Brief Description: Discloses a high frequency switch. Directly relevant.
• Potentially Anticipates: Claims 1 and 13, for the general concept of an RF switch.

Family Cites Families:

US7049863B2

• Full Citation: US7049863B2 - Output driver circuit with reduced RF noise, reduced power consumption, and reduced load capacitance susceptibility
• Publication Date: 2006-05-23
• Filing Date: 2004-07-13
• Brief Description: Describes an output driver circuit with reduced RF noise, power consumption, and load capacitance susceptibility. While not a switch directly, elements of improved RF performance and power consumption are relevant to the benefits of SOI technology mentioned in US9450579.
• Potentially Anticipates: Less directly, but some general performance benefits (like reduced power consumption in SOI) could be considered.

Most Relevant Prior Art for US9450579:

Based on the analysis, the most relevant prior art references that potentially anticipate aspects of US9450579 under 35 U.S.C. § 102 are those that specifically address:

1. Intermodulation Distortion (IMD) or Linearity Improvement:

   • US4999585A ("Circuit technique for cancelling non-linear capacitor-induced harmonic distortion"): Directly addresses capacitor-induced distortion, which is central to US9450579's claims.
   • US7910993B2 ("Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink"): Addresses improving MOSFET linearity, a key goal of US9450579, even if the method differs.
   • US20140009203A1 ("Switch linearization by non-linear compensation of a field-effect transistor"): Very relevant as it addresses switch linearization and is from the same assignee with a shared priority date.

2. Stacked FETs in Switch Circuits:

   • US5382826A ("Stacked high voltage transistor unit"): Discloses stacked transistors.
   • US7890063B2 ("Systems, methods, and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using body switching in multistacking structure"): Explicitly mentions stacked structures in antenna switches.
   • US20110148501A1 ("Variable attenuator having stacked transistors"): Shows stacked transistors in a different application.

3. Silicon-on-Insulator (SOI) Technology for RF Switches:

   • US5753955A ("MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates"): Focuses on MOS devices on SOI with body connections.
   • US6281737B1 ("Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor"): Addresses performance improvements in SOI transistors.
   • US7385436B2 ("Fully depleted silicon on insulator semiconductor devices"): Discloses fully depleted SOI devices.
   • US8461903B1 ("SOI switch enhancement"): Directly addresses SOI switch enhancements.
   • US20140002171A1 ("Body-contacted partially depleted silicon on insulator transistor"): Relevant to SOI transistors and body control.
   • US20140009214A1 ("Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches"): Highly relevant given shared priority date and assignee.

4. Overall RF Switch Architecture and Components (Antenna, Transmit/Receive Paths, Shunt Arms):

   • US20050239415A1 ("High-frequency switch circuit and high-frequency transmitting/receiving apparatus"): Describes general high-frequency switch circuits in transmit/receive systems.
   • US7265604B2 ("High-frequency switch circuit arrangement"): Describes high-frequency switch circuit arrangements.
   • US7848712B2 ("CMOS RF switch for high-performance radio systems"): Discloses CMOS RF switches for high-performance systems.
   • US7885614B2 ("Antenna switch with adaptive filter"): Describes an antenna switch.
   • US20140009208A1 ("CMOS Switching Circuitry of a Transmitter Module"): Relevant to transmit path circuitry.

The key distinguishing feature of US9450579, as highlighted in its independent claims, is the specific inclusion and configuration of the series capacitors (first and second capacitors) between the switch circuits and the antenna node, explicitly for the purpose of "inhibiting a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch." Prior art that explicitly combines this specific capacitor placement with stacked FETs on an SOI substrate for this stated purpose would be the most challenging to overcome.

Obviousness Analysis of US Patent 9450579 Under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 9450579, titled "Radio frequency devices having reduced intermodulation distortion," under 35 U.S.C. § 103, based on the provided prior art. The effective filing date for this patent is August 22, 2015, with a priority date of July 7, 2012.

Person Having Ordinary Skill in the Art (PHOSITA)

A person having ordinary skill in the art (PHOSITA) in this field would be an electrical engineer or a semiconductor device designer with experience in radio-frequency (RF) circuit design, particularly in the context of wireless communication systems and integrated circuit fabrication. This PHOSITA would be familiar with transistor switches (especially FETs), intermodulation distortion (IMD) phenomena, and techniques for improving RF switch performance, including linearity, insertion loss, and power handling, as well as the use of passive components like capacitors for signal conditioning and filtering.

Core Inventive Concept of US9450579

The central inventive concept of US9450579, particularly as highlighted in its independent claims, involves an RF switch system that includes a switch having a stack of field-effect transistors (FETs) connected in series, and critically, a capacitor connected in series with the switch, specifically configured to inhibit a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch, thereby reducing intermodulation distortion (IMD). These components are preferably integrated on a semiconductor die and used within a wireless device.

Obviousness Analysis

Independent Claim 1: Semiconductor Die

Claim 1 Elements:

1. A semiconductor die comprising:
   • a semiconductor substrate;
   • a first switch circuit formed on the semiconductor substrate connected between an antenna node and a transmit node;
   • a second switch circuit formed on the semiconductor substrate and connected between the antenna node and a receive node;
   • a first capacitor formed on the semiconductor substrate and connected in series with the first switch circuit between the first switch circuit and the antenna node;
   • a second capacitor formed on the semiconductor substrate and connected in series with the second switch circuit between the second switch circuit and the antenna node; and
   • a first shunt arm formed on the semiconductor substrate and connected to the first switch circuit and the transmit node, the first shunt arm including a third switch circuit connected to ground.

Combination of Prior Art:
Claim 1 would have been obvious to a PHOSITA in view of US7890063B2 (Samsung Electro-Mechanics) in combination with general knowledge of RF circuit design concerning the use of series capacitors for filtering low-frequency signals and mitigating intermodulation distortion.

• US7890063B2 discloses "CMOS antenna switches using body switching in multistacking structure." The term "CMOS" inherently implies implementation on a semiconductor die with a semiconductor substrate. "Antenna switches" clearly teaches the presence of a first switch circuit connected between an antenna node and a transmit node and a second switch circuit connected between the antenna node and a receive node, as this is a fundamental function of an antenna switch. The "multistacking structure" teaches that these switches comprise field-effect transistors (FETs) connected in series. Furthermore, a "shunt arm" with a switch to ground is a conventional component in RF antenna switches, providing isolation for inactive paths (as illustrated in FIG. 3 and FIG. 4 of US9450579).

• General Knowledge of RF Circuit Design: It was well-known in the art that intermodulation distortion (IMD) is a significant issue in RF systems, particularly in multi-band, multi-mode wireless communication environments, and that low-frequency blocker signals contribute to this distortion (as acknowledged in US9450579 itself, stating that IMD can result from signals mixing and that "Long Term Evolution (LTE) systems can benefit significantly from RF switches having reduced IMDs"). It is a fundamental principle of RF circuit design that capacitors can be used as filters. Coupling capacitors are known to block DC components while allowing AC signals to pass, thereby preventing signal distortion and reducing interference. Capacitors are pivotal in filtering applications, including high-pass filters that block low-frequency noise while allowing higher-frequency signals to pass. The frequency response of FET switches is also known to be influenced by DC-blocking capacitors, and their careful selection is necessary to preserve switch performance, especially at low frequencies.

Motivation to Combine:
A PHOSITA, faced with the recognized problem of intermodulation distortion caused by low-frequency blocker signals in RF switches (such as the CMOS antenna switch described in US7890063B2), would have been motivated to employ known techniques to mitigate this issue. Knowing that series capacitors effectively act as high-pass filters to block unwanted low-frequency signals, the PHOSITA would have found it obvious to connect a first capacitor in series with the first switch circuit and a second capacitor in series with the second switch circuit in the antenna switch taught by US7890063B2. The purpose would be to inhibit low-frequency blocker signals from mixing with fundamental-frequency signals, thereby improving the overall IMD performance of the switch. Furthermore, integrating these capacitors on the same semiconductor die as the switch circuits, as claimed, would be a conventional design choice for miniaturization, reduced parasitic effects, and improved performance in modern integrated RF solutions. This is further supported by references like US20140009214A1 (Skyworks Solutions, Inc.), which teaches "silicon-on-insulator based radio-frequency switches," demonstrating the common practice of integrating RF switches on a semiconductor die using advanced technologies.

Independent Claim 7: Method for Operating a Radio-Frequency (RF) Device

Claim 7 Elements:

1. A method for operating a radio-frequency (RF) device, the method comprising:
   • providing an RF device including a first switch circuit connected between an antenna node and a transmit node, a second switch circuit connected between the antenna node and a receiver node, a first capacitor connected in series with the first switch circuity between the first switch circuit and the antenna node, a second capacitor connected in series with the second switch circuit between the second switch circuit and the antenna node, and a first shunt arm connected to the first switch circuit and the transmit node, the first shunt arm including a third switch circuit connected to ground;
   • controlling an RF switch of the RF device by placing the first switch circuit in an ON state and placing the third switch circuit in an OFF state; and
   • inhibiting a low-frequency blocker signal from mixing with a fundamental-frequency signal in the RF switch using the first capacitor.

Combination of Prior Art:
Claim 7 would have been obvious to a PHOSITA in view of the combined teaching for Claim 1 (i.e., US7890063B2 and general knowledge of RF circuit design concerning series capacitors for filtering low-frequency signals and mitigating IMD).

• Providing an RF device: This step is met by providing the device rendered obvious under Claim 1.
• Controlling an RF switch: The act of controlling an RF switch by placing a desired path (e.g., transmit path) in an "ON" state and a corresponding shunt path in an "OFF" state is a fundamental and well-understood operation for any SPDT RF switch, as commonly depicted in figures like FIG. 3 and FIG. 4 of US9450579.
• Inhibiting a low-frequency blocker signal: This functional step directly results from the structural arrangement of the series capacitor in the RF path, as taught by the combination for Claim 1. Given the known filtering properties of series capacitors to block low frequencies, a PHOSITA would inherently understand that operating the device with these capacitors in place would achieve the function of inhibiting low-frequency blocker signals.

Motivation to Combine:
The motivation for this method is inherent in the design of the device itself. Once the RF device including the series capacitors (as described in the obvious combination for Claim 1) is provided, the operational steps would be evident. A PHOSITA, aware of the IMD problem caused by low-frequency blockers and having incorporated series capacitors for this very purpose, would naturally operate the switch such that the capacitors perform their intended function of inhibiting these unwanted signals. The act of "controlling an RF switch" (turning ON/OFF specific paths) is a routine operation in RF systems. The additional step of "inhibiting a low-frequency blocker signal... using the first capacitor" is not a new method but rather the expected and intended function of the capacitor, which was deliberately placed there to address a known problem with a known solution.

Independent Claim 13: Wireless Device

Claim 13 Elements:

1. A wireless device comprising:
   • a transceiver configured to process RF signals;
   • an antenna in communication with the transceiver; and
   • a switch module interconnected to the antenna and the transceiver and configured to selectively route RF signals to and from the antenna, the switch module including a first switch connected between the antenna and a transmit node, a second switch connected between the antenna and a receive node, a first capacitor connected in series with the first switch between the first switch and the antenna, a second capacitor connected in series with the second switch between the second switch and the antenna, and a first shunt arm connected to the first switch and the transmit node, the first shunt arm including a third switch connected to ground.

Combination of Prior Art:
Claim 13 would have been obvious to a PHOSITA in view of the combined teachings for Claim 1 (US7890063B2 and general knowledge of RF circuit design concerning series capacitors for filtering low-frequency signals and mitigating IMD) in further combination with general knowledge of wireless device architecture.

• Wireless Device Components: Wireless devices universally include a transceiver to process RF signals and an antenna in communication with the transceiver, as shown in FIG. 14 of US9450579, which depicts a typical wireless device architecture.
• Switch Module: The core of the switch module described in Claim 13 is precisely the semiconductor die and switch arrangement described in Claim 1, which has been shown to be obvious from US7890063B2 and general knowledge.

Motivation to Combine:
A PHOSITA designing a wireless device (such as a cellular phone or smartphone) would routinely integrate an RF switch module to selectively route RF signals between the transceiver and the antenna (as depicted in FIG. 14 of US9450579). Knowing that IMD performance is critical for wireless devices, particularly those operating under standards like LTE and supporting simultaneous voice and data (SVLTE), and that low-frequency blockers contribute to IMD (as explicitly stated in US9450579), the PHOSITA would be motivated to select or design a switch module that incorporates IMD reduction features. Therefore, it would be an obvious design choice to incorporate the switch module rendered obvious under Claim 1 (i.e., the stacked FET switch with series capacitors for inhibiting low-frequency blockers) into a wireless device. This integration would lead to a predictable improvement in the overall IMD performance of the wireless device, addressing a known problem with known solutions.

Conclusion

Based on the analysis, the independent claims (Claims 1, 7, and 13) of US Patent 9450579 would likely have been obvious to a person having ordinary skill in the art at the time of the invention. The combination of established RF switch architectures using stacked FETs (e.g., US7890063B2) with the well-known application of series capacitors for filtering low-frequency signals to reduce distortion, integrated on a semiconductor die, addresses a recognized problem (IMD from low-frequency blockers) with predictable results. The method of operating such a device and its inclusion in a wireless device are direct and obvious extensions of the underlying switch technology and its known benefits.