US 9148194

Here is a concise summary of US patent 9148194:

US Patent 9148194: Radio-frequency switch system having improved intermodulation distortion performance

• Title: Radio-frequency switch system having improved intermodulation distortion performance
• Assignee: Skyworks Solutions Inc
• Inventors: Anuj Madan, Fikret Altunkilic, Guillaume Alexandre Blin
• Filing Date: July 6, 2013
• Issue Date: September 29, 2015
• Abstract: The patent discloses radio-frequency (RF) switch circuits designed for improved switching performance. An RF switch system includes a switch with a stack of field-effect transistors (FETs) connected in series between first and second nodes. A capacitor is connected in series with this switch, configured to prevent a low-frequency blocker signal from mixing with a fundamental-frequency signal within the switch.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes an RF switch system featuring two primary signal paths connected to an antenna node. A first switch circuit and a first series capacitor establish a path between the antenna node and a transmit node. A second switch circuit and a second series capacitor create a path between the antenna node and a receive node. The system also includes two shunt arms: a first shunt arm for the transmit path, containing a third switch circuit connected to ground, and a second shunt arm for the receive path, incorporating a fourth switch circuit connected to ground.
• Claim 4: Similar to Claim 1, this independent claim describes an RF switch system with a transmit path (first switch, first series capacitor) and a receive path (second switch, second series capacitor) both connected to an antenna node. It also includes a first shunt arm for the transmit path, which comprises a third switch circuit connected to ground and, notably, a third capacitor connected between this third switch circuit and the transmit node.
• Claim 5: This claim specifies a method for manufacturing a semiconductor die. The method involves providing a semiconductor substrate and forming on it the components of the RF switch system described in Claim 1. This includes forming the first and second switch circuits, the first and second series capacitors, and the first and second shunt arms (each with a switch circuit to ground) for the transmit and receive nodes, respectively.
• Claim 7: This claim details a radio-frequency (RF) switch module. The module includes a packaging substrate designed to house various components. Mounted on this substrate is a semiconductor die, which integrates a first switch circuit (for the transmit path) and a second switch circuit (for the receive path), both connected to an antenna node. Additionally, the module contains a first capacitor in series with the first switch, a second capacitor in series with the second switch, and two shunt arms (each with a switch circuit connected to ground) for the transmit and receive nodes.

Litigation Information:
The Google Patent data indicates that the patent family has litigation, including cases filed in the California Central District Court, the International Trade Commission, and a PTAB case (IPR2024-01457). However, a search of CAFC 2026 dockets for the specific patent number 9148194 did not return any scheduled cases for May or June 2026. This does not preclude the possibility of litigation in other forums or at other times in 2026 at the CAFC.

As a patent attorney, I've researched known litigation involving US patent 9148194. Here's what I found:

Known Litigation Involving US Patent 9148194:

• Case 1: US case filed in California Central District Court

  • Jurisdiction: California Central District Court
  • Case Number: 8:24-cv-00974
  • Status: Critical
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.
  • Filing Date: Not explicitly stated in the provided text, but the litigation is listed under events for the patent, implying it was filed at some point before the current date of April 26, 2026.
  • Outcome/Current Status: Active

• Case 2: PTAB case IPR2024-01457 filed (Settlement)

  • Jurisdiction: PTAB (Patent Trial and Appeal Board)
  • Case Number: IPR2024-01457
  • Status: Litigation (Settlement)
  • Plaintiff(s): Not explicitly stated in the provided text, but the petitioner is generally the party challenging the patent in an IPR.
  • Defendant(s): Not explicitly stated in the provided text.
  • Filing Date: Not explicitly stated in the provided text, but the case number IPR2024-01457 indicates it was filed in 2024.
  • Outcome/Current Status: Litigation (Settlement)

• Case 3: US case filed in International Trade Commission

  • Jurisdiction: International Trade Commission
  • Case Number: 337-TA-3762
  • Status: Litigation
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.
  • Filing Date: Not explicitly stated in the provided text.
  • Outcome/Current Status: Litigation

• Case 4: US case filed in International Trade Commission

  • Jurisdiction: International Trade Commission
  • Case Number: 337-TA-1413
  • Status: Litigation
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.
  • Filing Date: Not explicitly stated in the provided text.
  • Outcome/Current Status: Litigation

• Case 5: First worldwide family litigation filed

  • Jurisdiction: Not specified, but described as "First worldwide family litigation."
  • Case Number: Not explicitly stated in the provided text.
  • Status: Litigation
  • Plaintiff(s): Not explicitly stated in the provided text.
  • Defendant(s): Not explicitly stated in the provided text.
  • Filing Date: Not explicitly stated in the provided text.
  • Outcome/Current Status: Litigation

The information regarding plaintiffs, defendants, and specific filing dates for some of these cases is not explicitly detailed in the provided patent text from Google Patents. Access to PACER would typically provide more granular details for U.S. District Court and PTAB cases.

Proceedings overview

There is one AIA trial proceeding on file for US patent 9148194, IPR2024-01457, which was terminated due to a settlement. As this IPR was settled, no claims of the patent have been invalidated or sustained by a Final Written Decision. This means the claims remain untested by the PTAB.

IPR2024-01457 — Kangxi Communication Technologies (Shanghai) Co., Ltd. v. SKYWORKS SOLUTIONS, INC.

• Type: Inter Partes Review
• Filed: 2024-11-12
• Status: Terminated-Settled. The proceeding concluded due to a settlement agreement between the petitioner and the patent owner.
• Judge panel: Information not publicly available without accessing the case documents on PTAB-E2E.
• Petition grounds: Details regarding the specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) are not publicly available in the provided snippet or readily accessible through general search without deep dive into PTAB-E2E documents.
• Institution decision: Information not publicly available without accessing the case documents on PTAB-E2E. Given the "Terminated-Settled" status and the time elapsed between filing (2024-11-12) and termination (2026-05-11), it is plausible that the petition was instituted before settlement, but this cannot be confirmed without accessing official documents.
• Final Written Decision: Not issued, as the proceeding was terminated due to settlement.
• Settlement / termination: The proceeding was terminated on 2026-05-11 due to a settlement between Kangxi Communication Technologies (Shanghai) Co., Ltd. and Skyworks Solutions, Inc.. The specific terms of the settlement are confidential.
• Appeal: Not applicable, as no Final Written Decision was issued.
• Defensive value: Since the proceeding was terminated via settlement and no institution decision or Final Written Decision is publicly available, the claims of US9148194 have not been formally challenged and adjudicated by the PTAB in this IPR. Therefore, the patent's claims remain undiminished by this specific PTAB action, and a potential defendant is not directly impacted by claim cancellation. However, the petitioner and its privies may be estopped from raising the same or reasonably could have raised grounds in future proceedings against the patent.

Strategic summary

The patent US9148194 has been subjected to one IPR proceeding, IPR2024-01457. This IPR, filed by Kangxi Communication Technologies (Shanghai) Co., Ltd. against Skyworks Solutions, Inc., was ultimately terminated due to a settlement on 2026-05-11. As a result, no claims of US9148194 have been canceled or sustained by the PTAB. All claims of the patent are considered UNTESTED by a Final Written Decision at the PTAB. The patent has not been narrowed through this IPR.

Regarding the estoppel landscape, if the IPR was instituted and then settled, the petitioner, Kangxi Communication Technologies (Shanghai) Co., Ltd., and its privies would be statutorily estopped under § 315(e)(2) from asserting in future district court litigation or other USPTO proceedings any invalidity ground that they raised or reasonably could have raised in the IPR. For other potential defendants not in privity with Kangxi, prior art grounds remain available for challenging the patent's validity. The fact that the case settled prior to a Final Written Decision means there is no public record of the claims being challenged or confirmed, which could be an advantage for future challengers in that no PTAB-level determination has upheld the claims.

There are no clear pattern signals of aggressive PTAB appeals by the patent owner or multiple IPRs filed by the same petitioner for this specific patent family based on the provided information. However, the litigation information on the Google Patents page mentions "Unified Patents Litigation Data" for this IPR, suggesting that Unified Patents may have been involved in some capacity, potentially as a source of prior art or a facilitator, although Kangxi Communication Technologies (Shanghai) Co., Ltd. is listed as the petitioner.

Recommended next steps

For a potential defendant facing assertion of US9148194, the claims of the patent remain untested by a PTAB Final Written Decision. The settlement in IPR2024-01457 means there is no public FWD to reference for claim cancellations or interpretations. To understand the full scope of any potential estoppel against Kangxi Communication Technologies (Shanghai) Co., Ltd., it would be necessary to review the settlement agreement and the IPR petition itself to determine which claims and grounds were explicitly raised or could have reasonably been raised.

Since the case settled, there are no active proceedings with upcoming trial-stage milestones for IPR2024-01457. If considering an IPR-based defense, a new petition would need to be filed, and the grounds would need to be carefully crafted to avoid any potential estoppel issues if the defendant has a relationship with the previous petitioner. The absence of a prior PTAB merits decision on the patent's claims means the patent's validity could still be challenged via an IPR by a new petitioner, assuming the statutory and regulatory requirements are met.

PTAB case IPR2024-01457 filed (Settlement) litigation. https://portal.unifiedpatents.com/ptab/case/IPR2024-01457

Inventors

• Anuj Madan (Skyworks Solutions Inc)
• Fikret Altunkilic (Skyworks Solutions Inc)
• Guillaume Alexandre Blin (Skyworks Solutions Inc)

No unusual patterns of inventors departing the original assignee within 12 months of filing are determinable from the provided information.

Original assignee

The original assignee named on the issued patent US9148194B2 is Skyworks Solutions Inc.

Skyworks Solutions Inc. is a leading company in analog semiconductors, connecting people, places, and things worldwide. They ship products embodying the claims, specifically radio-frequency (RF) switches and related components for wireless devices. Their primary line of business is the design, development, manufacture, and marketing of proprietary semiconductor products, including RF components, for use in automotive, broadband, cellular infrastructure, connected home, industrial, medical, military, smartphone, tablet, and wearable applications.

Current Status: Skyworks Solutions Inc. is an actively operating public company.

Assignment timeline

• 2014-03-03 (executed) / recorded 2014-03-03 — Reel 031267/0002
  • Conveyance: Assignment
  • Assignor: MADAN, ANUJ; ALTUNKILIC, FIKRET; BLIN, GUILLAUME ALEXANDRE
  • Assignee: SKYWORKS SOLUTIONS, INC.
  • Correspondent: KEVIN J. MCKENNA, STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C., 1100 NEW YORK AVENUE, NW WASHINGTON, DC 20005.
  • Context: Assignors interest assigned to Skyworks Solutions, Inc.

The USPTO Assignment Center shows this as the only assignment record for US9148194.

Timeline diagram

timeline
    title Ownership of US 9148194
    2013 : Application filed by Skyworks Solutions
    2014 : Inventors assigned to Skyworks Solutions
    2015 : Patent issued to Skyworks Solutions

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The patent remains with the original operating company, Skyworks Solutions Inc.
2. Known asserter in the chain — not present. Skyworks Solutions Inc. is an operating company, not a known NPE.
3. Repeat correspondent across the chain — not present. Only one assignment is recorded, so no recurrence can be observed. The correspondent, KEVIN J. MCKENNA of STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C., is a recognized patent prosecution attorney.
4. Cascading transfers — not present. Only one assignment is recorded.
5. Pre-litigation transfer — unclear. While there is current litigation activity for this patent family (mentioned in Google Patents, e.g., "US case filed in California Central District Court" and "PTAB case IPR2024-01457 filed"), the single assignment predates these actions significantly. Further investigation into the specific filing dates of those litigations relative to the assignment date would be needed for a definitive "present" or "not present."
6. Bankruptcy fire-sale — not present. Skyworks Solutions Inc. is an active, operating company.
7. Privateering — not present. The patent remains with the original operating company.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator.

Verdict

Insufficient data (no records, or only the original assignment)

The USPTO Assignment Center only shows the initial assignment of the inventors' rights to the original assignee, Skyworks Solutions Inc., recorded on 2014-03-03 (Reel 031267/0002). There are no subsequent assignments recorded that would indicate a transfer to an NPE or a defensive aggregator.

For verification, see the USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

I will now identify the most relevant prior art for US Patent 9148194 based on the provided patent text, focusing on the "Patent Citations" section. For each identified reference, I will provide the full citation, publication/filing date, a brief description, and which claim(s) it potentially anticipates under 35 U.S.C. § 102.

The core invention of US9148194 relates to an RF switch system incorporating series capacitors to inhibit low-frequency blocker signals from mixing with fundamental-frequency signals in the switch, thereby improving intermodulation distortion (IMD) performance. This system can be implemented using FETs, particularly SOI FETs, and can be integrated on a semiconductor die or within a module.

Based on this understanding, prior art describing RF switches, FETs, SOI technology, linearity/IMD improvement techniques, and the use of capacitors in RF paths will be considered most relevant. Since I don't have access to the full text of the cited patents, the description will be inferred primarily from their titles.

Here are some of the most relevant patent citations, selected based on their titles' direct relevance to RF switches, FETs, SOI, and linearity/IMD, and the inclusion of capacitors:

1. US7885614B2

   • Full Citation: US7885614B2, Nxp B.V., "Antenna switch with adaptive filter"
   • Publication Date: 2011-02-08 (Priority Date: 2003-07-22)
   • Brief Description: This patent describes an antenna switch that includes an adaptive filter. The mention of an "antenna switch" and "filter" suggests a system for handling RF signals and potentially addressing unwanted signal components, which could be related to IMD.
   • Potential Anticipation: Claims 1, 4, 5, 7. This patent generally pertains to antenna switches, which form the basis of claims 1, 4, 5, and 7 of US9148194. While it does not explicitly mention "series capacitors to inhibit low-frequency blocker signals," the concept of an "adaptive filter" in an antenna switch could potentially cover means for managing unwanted signals, which might anticipate some aspects of the broader system claims. However, without further detail, it's unlikely to anticipate the specific purpose (IMD reduction by blocking low-frequency blockers) or implementation (series capacitors at specific nodes) of the capacitors in US9148194. It is marked with an asterisk indicating it was "Cited by examiner".

2. US8129787B2

   • Full Citation: US8129787B2, Peregrine Semiconductor Corporation, "Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink"
   • Publication Date: 2012-03-06 (Priority Date: 2005-07-11)
   • Brief Description: This patent directly addresses improving the linearity of MOSFETs, which are key components of RF switches, and the abstract of US9148194 explicitly focuses on "improved intermodulation distortion performance" (a measure of non-linearity). The use of an "accumulated charge sink" hints at specific circuit techniques to achieve this.
   • Potential Anticipation: Claims 1, 2, 4, 5, 7, 8. The broad objective of improving linearity, which directly relates to IMD performance (as stated in US9148194's description), means this patent potentially anticipates the underlying problem and a general solution for improving RF switch performance. Specifically, Claim 2 and Claim 8 of US9148194 state the purpose of the capacitors is to "inhibit a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch" for improved IMD. A general method for improving linearity of MOSFETs could be seen as broadly anticipating this goal. It is marked with an asterisk indicating it was "Cited by examiner".

3. US7848712B2

   • Full Citation: US7848712B2, Intel Corporation, "CMOS RF switch for high-performance radio systems"
   • Publication Date: 2010-12-07 (Priority Date: 2007-05-03)
   • Brief Description: This patent describes a CMOS RF switch, which is a common implementation for RF switches, particularly those using FETs as discussed in US9148194. The title's mention of "high-performance radio systems" suggests an interest in optimizing switch characteristics.
   • Potential Anticipation: Claims 1, 4, 5, 7. This patent broadly covers CMOS RF switches, which are fundamental to US9148194's system, method, and module claims. It could anticipate the general structure of a switch between an antenna and transmit/receive nodes. However, it does not explicitly mention the specific capacitor configuration for IMD reduction. It is marked with an asterisk indicating it was "Cited by examiner".

4. US20110260773A1

   • Full Citation: US20110260773A1, Rf Micro Devices, Inc., "High power fet switch"
   • Publication Date: 2011-10-27 (Priority Date: 2010-04-27)
   • Brief Description: This application describes a high-power FET switch. US9148194 also discusses FETs and the ability to handle high power by stacking FETs. High power applications often introduce challenges with linearity and IMD.
   • Potential Anticipation: Claims 1, 4, 5, 7. This patent is relevant for disclosing high-power FET switches, which are a type of switch circuit used in US9148194. It could anticipate the general switch architecture if it includes series FETs. It is marked with an asterisk indicating it was "Cited by examiner".

5. JP2005515657A

   • Full Citation: JP2005515657A, Peregrine Semiconductor Corporation, "Switch circuit and high-frequency signal switching method"
   • Publication Date: 2005-05-26 (Priority Date: 2001-10-10)
   • Brief Description: This Japanese patent application, also by Peregrine Semiconductor, generally describes a switch circuit and method for high-frequency signal switching. Peregrine Semiconductor is known for SOI technology and RF switches.
   • Potential Anticipation: Claims 1, 4, 5, 7. This broad disclosure of a "switch circuit and high-frequency signal switching method" could potentially anticipate the general concept of an RF switch system or method as described in US9148194. Without further details, it's hard to assess specific anticipation of the capacitor arrangement.

6. US20050239415A1

   • Full Citation: US20050239415A1, Yoshitomo Sagae, "High-frequency switch circuit and high-frequency transmitting/receiving apparatus"
   • Publication Date: 2005-10-27 (Priority Date: 2004-04-27)
   • Brief Description: This patent describes a high-frequency switch circuit and a transmitting/receiving apparatus. This is highly relevant as US9148194 focuses on RF switch systems for transmit/receive paths.
   • Potential Anticipation: Claims 1, 4, 5, 7. This document likely discloses general high-frequency switch circuits and their use in transmit/receive paths, which could cover the broader aspects of the switch system, method, and module claims in US9148194.

7. US7095266B2

   • Full Citation: US7095266B2, Fairchild Semiconductor Corporation, "Circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches"
   • Publication Date: 2006-08-22 (Priority Date: 2004-08-18)
   • Brief Description: This patent explicitly discusses improving performance parameters of MOSFET switches, specifically "lowering insertion loss and increasing bandwidth." While not directly mentioning IMD, improving overall switch performance is a common goal, and techniques could be related.
   • Potential Anticipation: Claims 1, 4, 5, 7. This patent is relevant for techniques to improve MOSFET switch performance, which is a broader goal also addressed by US9148194.

8. US7910993B2

   • Full Citation: US7910993B2, Peregrine Semiconductor Corporation, "Method and apparatus for use in improving linearity of MOSFET's using an accumulated charge sink"
   • Publication Date: 2011-03-22 (Priority Date: 2005-07-11)
   • Brief Description: This patent is another one from Peregrine Semiconductor, again focusing on "improving linearity of MOSFET's using an accumulated charge sink." Similar to US8129787B2, this directly addresses the linearity aspect that US9148194 aims to improve with respect to IMD.
   • Potential Anticipation: Claims 1, 2, 4, 5, 7, 8. Similar to US8129787B2, this patent aims at improving the linearity of MOSFETs, which is directly relevant to IMD performance.

Summary of Potential Anticipation:

• Claims 1, 4, 5, 7 (System, Method, Module claims for the basic switch architecture): Many general RF switch patents (e.g., US7848712B2, US20050239415A1, US20110260773A1, JP2005515657A) could potentially anticipate the fundamental arrangement of switch circuits between antenna, transmit, and receive nodes, and shunt arms connected to ground. The novelty in US9148194 for these claims lies in the addition of the series capacitors.
• Claims 2, 8 (Purpose of capacitors for IMD reduction): Patents specifically addressing linearity or IMD improvement in RF switches or MOSFETs (e.g., US8129787B2, US7910993B2) are highly relevant. While they may not disclose the exact series capacitor configuration of US9148194, they anticipate the problem of IMD and may disclose other methods for improving linearity that could challenge the novelty of the general concept of IMD improvement. The claim specifically ties the capacitor to "inhibiting a low-frequency blocker signal from mixing with a fundamental-frequency signal." Without full patent texts, it's difficult to confirm if any prior art explicitly teaches this specific function of series capacitors.
• Claim 3 (Capacitors in shunt arms): This is a more specific configuration. Without reviewing the full text of the cited patents, it's unlikely to pinpoint direct anticipation from titles alone.
• Claim 6 (Forming an insulator layer for SOI): Patents related to SOI FET fabrication and structure (e.g., US7385436B2 "Fully depleted silicon on insulator semiconductor devices", though not listed above as a most relevant citation for the overall invention, it is relevant for this specific detail) could anticipate this element.
• Claims 9, 10, 11 (Integration details for capacitors): These claims specify where the capacitors are located (same die, second die, off-die). General trends in semiconductor integration would suggest that implementing passive components like capacitors alongside active components (switches) on-die or in modules is common practice.

It is crucial to note that "potential anticipation" is a high-level assessment based on limited information (titles and brief descriptions). A definitive anticipation analysis would require a thorough review of the full text, drawings, and prosecution history of each cited patent, and a detailed comparison with all elements of each claim of US9148194. However, the listed patents represent the most direct challenges to the broad concepts of RF switch design and IMD improvement within the provided prior art.

To assess the obviousness of US patent 9148194 under 35 U.S.C. § 103, we will consider combinations of the cited prior art references that would render the claimed inventions apparent to a person having ordinary skill in the art (PHOSITA). The core of US9148194B2 involves an RF switch system with series capacitors connected to inhibit low-frequency blocker signals from mixing with fundamental-frequency signals, thereby improving intermodulation distortion (IMD) performance, often utilizing silicon-on-insulator (SOI) field-effect transistors (FETs).

A PHOSITA in the field of RF circuit design for wireless communication devices would possess knowledge of fundamental RF circuit principles, various switch architectures, performance parameters like insertion loss, isolation, power handling, and intermodulation distortion (IMD), and fabrication technologies such as CMOS and SOI. They would also be familiar with techniques to mitigate IMD and optimize switch performance.

Claim 1: A radio-frequency (RF) switch system comprising specific switch circuits, shunt arms, and series capacitors.

Combination of Prior Art References:

1. US7890063B2 (Samsung Electro-Mechanics): This patent discloses "Systems, methods, and apparatuses for complementary metal oxide semiconductor (CMOS) antenna switches using body switching in multistacking structure." The abstract of US7890063B2 states that it concerns a "CMOS antenna switch capable of reducing a size thereof and suppressing signal distortion." This reference teaches the basic architecture of an RF switch with multiple paths, including series and shunt switch circuits implemented with stacked FETs. For instance, FIG. 1 generally depicts a multi-throw RF switch, and FIG. 2 shows stacked FETs in such a switch. This would teach the "first switch circuit connected between an antenna node and a transmit node," the "second switch circuit connected between the antenna node and a receive node," the "first shunt arm including a third switch circuit connected to ground," and the "second shunt arm including a fourth switch circuit connected to ground."
2. KR101594517B1 (RF PIN-Diode Switch circuits for improving Isolation and Harmonics Distortion): This reference teaches "RF PIN-Diode Switch circuits for improving Isolation and Harmonics Distortion." It explicitly mentions that "a DC block (capacitor) is installed in the signal input unit 100 to prevent the DC current from passing through the signal input unit 100". Crucially, the abstract and detailed description link this DC block capacitor to "reducing the distortion (harmonics) generated in the RF pin diode switch".
3. "CMOS Switches Offer High Performance in Low Power, Wideband Applications" (February 2004 article): This article discusses the use of DC blocking capacitors. It notes that "GaAs switch manufacturers get around this issue [requiring negative control voltages] by adding DC blocking capacitors in series with the RF pins of the switch." This demonstrates that series DC blocking capacitors at the RF input of a switch are a known component choice.

Obviousness Analysis for Claim 1:
US7890063B2 clearly teaches the primary structure of an RF switch system with series and shunt arms using stacked FETs, and a general motivation to suppress signal distortion. The addition of "a first capacitor connected in series with the first switch circuit between the first switch circuit and the antenna node" and "a second capacitor connected in series with the second switch circuit between the second switch circuit and the antenna node" would be obvious in light of KR101594517B1 and general knowledge in RF circuit design. KR101594517B1 explicitly teaches placing a DC blocking capacitor at the input of an RF switch and explicitly attributes distortion reduction to its presence. A PHOSITA would recognize that a low-frequency blocker signal is a type of unwanted signal that can cause distortion, and that capacitors are inherently capable of blocking low frequencies. Therefore, applying a known component (series DC blocking capacitor) from KR101594517B1 to the known switch structure of US7890063B2 to achieve a known result (distortion reduction by blocking low-frequency signals) would be obvious. The article "CMOS Switches Offer High Performance in Low Power, Wideband Applications" further reinforces the common practice of using series DC blocking capacitors with RF switches.

Motivation to Combine:
A PHOSITA facing the challenge of improving IMD performance in an RF switch system (as described in US7890063B2) would naturally consider known techniques for managing unwanted signals and non-linearity. The problem of intermodulation distortion, particularly from low-frequency blocker signals, is well-documented in RF systems (as indicated in the background of US9148194B2, referencing LTE/SVLTE environments). Knowing that capacitors effectively block low-frequency signals, and that blocking such signals from active devices can prevent non-linear mixing, a PHOSITA would be motivated to integrate series DC blocking capacitors (as taught by KR101594517B1) into the switch paths of US7890063B2. The explicit connection of DC blocking capacitors to distortion reduction in KR101594517B1 provides a clear motivation for this combination to achieve improved IMD performance.

Claim 2: The switch system of claim 1 wherein at least one of the first and second capacitors is configured to inhibit a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch.

Obviousness Analysis for Claim 2:
As discussed for Claim 1, the function of inhibiting low-frequency blocker signals from mixing with fundamental-frequency signals is an inherent characteristic of DC blocking capacitors when placed in series. KR101594517B1 explicitly connects DC block capacitors to "reducing the distortion (harmonics)" in RF switches. Furthermore, "Switched-capacitor circuitry for front-end radio frequency signal processing" describes using "switches and capacitors to achieve high order front-end filtering of out-of-band (OB) blocking signals for software defined and cognitive radio applications," and states that "The high order front-end filtering allows for overall enhanced linearity during RF signal processing". This directly teaches using capacitors and switches for blocker rejection to improve linearity, which directly addresses the function of inhibiting mixing and improving IMD.

Motivation:
The motivation here is directly tied to improving linearity and reducing distortion, a well-known goal in RF design. A PHOSITA would understand that low-frequency blockers, if allowed to couple into the active region of FETs, can cause non-linear mixing and generate IMD. Using series capacitors to prevent these low-frequency signals from reaching the active devices is a predictable way to achieve the desired inhibition and improve IMD, as explicitly suggested by the prior art.

Claim 3: The switch system of claim 1 wherein the first shunt arm includes a third capacitor connected between the third switch circuit and the transmit node, and the second shunt arm includes a fourth capacitor connected between the fourth switch circuit and the receive node.

Obviousness Analysis for Claim 3:
Extending the use of series capacitors to the shunt arms for similar purposes (DC blocking, low-frequency blocker inhibition, IMD improvement) would be obvious to a PHOSITA. RF shunt arms are typically used for isolation, and ensuring proper DC biasing and RF performance in these arms, including managing unwanted low-frequency signals, is a standard design consideration. KR101594517B1, for instance, shows a DC block capacitor in the signal output path as well as the input path, indicating that such capacitors are not limited to antenna-facing series switches.

Motivation:
The motivation would be to apply the same principles of DC isolation and low-frequency blocker rejection to the shunt paths, thereby potentially improving overall switch performance, including isolation and IMD, especially when the shunt arms are active or exposed to various signals. This represents a predictable design optimization by a PHOSITA.

Claim 4: A radio-frequency (RF) switch system comprising specific switch circuits, shunt arms, and series capacitors (similar to Claim 1, but with C3 only in the Tx shunt arm).

Obviousness Analysis for Claim 4:
This claim is a subset of Claim 3, describing the inclusion of a third capacitor in the transmit shunt arm. The reasoning for its obviousness is the same as for Claim 3, being a predictable application of known capacitor functions in a known switch architecture to achieve known benefits.

Claim 5: A method for fabricating a semiconductor die including the components of Claim 1.

Combination of Prior Art References:

1. US7890063B2 (Samsung Electro-Mechanics): Teaches fabricating CMOS antenna switches with stacked transistors.
2. EP2387094A1 (Switch circuit and method of switching radio frequency signals): Explicitly describes an RF switch circuit fabricated in a "silicon-on-insulator (SOI) technology", including "switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a "stacked" or serial configuration".
3. "RF SOI & RF CMOS" (Tower Semiconductor): This platform explicitly lists "High density (4fF/μm2) and high voltage (>25V) MIM capacitors" as features available in RF SOI technology, indicating that integrated capacitors are common.

Obviousness Analysis for Claim 5:
The method of fabricating switch circuits and capacitors on a semiconductor die is well-known in the art. US7890063B2 and EP2387094A1 teach forming the FET-based switch circuits and shunt arms on a semiconductor substrate, with EP2387094A1 specifically mentioning SOI technology. The fabrication of integrated capacitors on a semiconductor die, particularly in SOI processes, is also well-established, as shown by the availability of high-density MIM capacitors in RF SOI platforms. Therefore, combining these known fabrication methods for individual components to form the integrated circuit as described in Claim 1 would be obvious.

Motivation:
A PHOSITA would be motivated to integrate these components (FET switches, shunt switches, and capacitors) onto a single semiconductor die using known fabrication techniques to achieve benefits such as reduced size, improved performance due to lower parasitics, and lower manufacturing costs, all of which are common goals in semiconductor manufacturing.

Claim 6: The method of claim 5 further comprising forming an insulator layer between the first switch circuit and the semiconductor substrate.

Obviousness Analysis for Claim 6:
This claim describes a specific aspect of SOI technology. EP2387094A1 explicitly states that the RF switch circuit is "fabricated in a silicon-on-insulator (SOI) technology". The description of US9148194B2 also extensively discusses SOI technology, noting that "SOI technology can include a semiconductor substrate having an embedded layer of electrically insulating material, such as a buried oxide layer beneath a silicon device layer" [cite: 9148194B2, Description, "Examples of FET Structures and Fabrication Process Technologies"]. This is a fundamental characteristic of SOI fabrication, widely known and utilized for its benefits in RF applications (e.g., reduced parasitic capacitance, improved isolation, enhanced linearity).

Motivation:
The motivation for a PHOSITA to include an insulator layer (i.e., use SOI technology) when fabricating RF switches is clearly established in the prior art and in the patent itself. SOI technology provides "reduced power consumption," "decreased parasitic capacitance," "reduced junction capacitance or use of high resistivity substrate, enabling reduced substrate related RF losses," and "Electrically isolated SOI transistors can facilitate stacking, contributing to decreased chip size" [cite: 9148194B2, Description, "Examples of FET Structures and Fabrication Process Technologies"]. "Optimized CMOS-SOI Process for High Performance RF Switches" also highlights the role of SOI substrate in switch linearity.

Claim 7: A radio-frequency (RF) switch module comprising a packaging substrate, a semiconductor die, and series capacitors.

Obviousness Analysis for Claim 7:
The concept of mounting semiconductor dies with RF switch circuits onto a packaging substrate in a module is conventional in the art of RF front-end module (FEM) design. The integration of capacitors, whether on-die or as separate components, within such modules is also common practice. "RF SOI & RF CMOS" from Tower Semiconductor advertises "Feature-rich platforms for high performance RF front-end module (FEM) products", implying integration of various components including switches and capacitors. US9148194B2 itself describes and depicts a packaged module (FIGS. 12A and 12B).

Motivation:
A PHOSITA would be motivated to package RF switch circuits and associated capacitors in a module to achieve a compact, easily integrated solution for wireless devices. This is a standard engineering practice to manage form factor, cost, and system integration.

Claims 8, 9, 10, 11 (related to the module of Claim 7):

• Claim 8 (Function of capacitors in module): Same reasoning as Claim 2; the function of the capacitors remains the same regardless of their packaging.
• Claim 9 (First capacitor part of same semiconductor die): As noted for Claim 5, high-density integrated capacitors are available in RF SOI processes. Integrating capacitors on the same die as the switch circuit is a common practice to minimize parasitics and chip area.
• Claim 10 (First capacitor part of a second die mounted on the packaging substrate): Modular integration using multiple dies on a single packaging substrate is a known approach to leverage different technologies or optimize yields for complex systems.
• Claim 11 (First capacitor disposed at a location outside of the semiconductor die): Using discrete (off-die) capacitors for DC blocking or filtering in RF circuits is a long-standing practice. The article "CMOS Switches Offer High Performance in Low Power, Wideband Applications" mentions that "GaAs switch manufacturers get around this issue by adding DC blocking capacitors in series with the RF pins of the switch," and notes that these may be off-chip components due to "additional printed circuit board area and manufacturing costs". This demonstrates the common consideration of external capacitors.

Overall Conclusion:
The claimed RF switch system, method of fabrication, and module would have been obvious to a PHOSITA in light of the cited prior art. The combination of established RF switch architectures using stacked FETs on SOI (e.g., US7890063B2, EP2387094A1) with the known application of series DC blocking capacitors for distortion reduction and blocker rejection (e.g., KR101594517B1, "Switched-capacitor circuitry for front-end radio frequency signal processing") addresses a known problem (IMD from low-frequency blockers) with predictable results. The various implementation details concerning integration on-die, off-die, or within a module are also conventional engineering choices based on known trade-offs.

Therefore, a PHOSITA, motivated to improve the intermodulation distortion performance of RF switch systems in multi-band/multi-mode environments, would have been led to combine these known elements in a predictable manner, rendering the claims of US9148194B2 obvious under 35 U.S.C. § 103.