US 7349448

Here's a concise summary of US Patent 7,349,448:

US Patent: 7,349,448

• Title: Distributed multiplexing circuit with built-in repeater
• Current Assignee: Mosaid Technologies Inc.
  • Note: The listed assignee may be inaccurate, as Google Patents states it has not performed a legal analysis and makes no representation as to the accuracy of the list.
• Inventor: Edward Chang
• Filing Date: August 1, 2003
• Issue Date: March 25, 2008
• Abstract: A multiplexor circuit comprising a plurality of data connections, first stage logic configured to receive a first data word from one of the connections and to transmit the first data word received, and second stage logic configured to receive the first data word from the first stage logic and to select a selected data word between the first data word and a second data word received from another of the plurality of data connections based upon a set of select signals, the second stage logic configured to transmit the selected data word.

Legal Status and Litigation:

The patent's legal status is "Active", with an adjusted expiration date of April 27, 2026. Since today's date is April 26, 2026, the patent is currently active but is set to expire tomorrow.

Regarding litigation:

• A PTAB case, IPR2025-01489, was filed on August 29, 2025, by Unified Patents, but was "Not Instituted - Procedural".
• A US case was filed in the Texas Western District Court (case 1:25-cv-00358) in 2025.

Plain-Language Overview of Independent Claims:

• Claim 1: Describes a multiplexing circuit with at least two stages. The first stage has a tristate driver to receive and transmit a first data word. The second stage receives this first data word from the first stage, and also receives a second data word from another data connection. The second stage selects one of these two data words for transmission based on select signals. This second stage specifically includes two tristate drivers, whose outputs are coupled, to drive a connection with either the first selected data word or the second selected data word.
• Claim 4: Defines a multiplexor circuit with first and second stage logic. The first stage receives and transmits a first data word based on select signals. The second stage receives this first data word from the first stage and a second data word from another connection, then selects one to transmit to a third stage logic. A key feature here is that the second stage is configured to increase the signal strength of the first data word if it is selected and transmitted.
• Claim 5: Outlines a multiplexor circuit with first and second stage logic. The first stage receives and transmits a first data word. The second stage receives this first data word and a second data word, selecting one for transmission to a third stage logic. The second stage explicitly contains two tristate drivers: a first one that drives a connection with the first data word (enabled/disabled by a data connection exclusion signal) and a second one that drives the same connection with the second data word (enabled/disabled by a data connection select signal).
• Claim 8: Describes a circuit with logic associated with a first, second, and third data connection. The first logic transmits a first data word. The second logic receives this first data word and a second data word, selecting a "first selected data word" between them based on select signals. The third logic then receives this "first selected data word" and a third data word, selecting a "second selected data word" between them based on select signals, and transmits this final selected data word to a system bus.
• Claim 9: Specifies a multiplexor circuit using three tristate drivers. A first tristate driver receives a first data word, a second tristate driver receives a second data word, and a third tristate driver has its output coupled to the input of the first tristate driver. A single connection receives either the first data word (if an enable signal for the first tristate driver is asserted) or the second data word (if an enable signal for the second tristate driver is asserted).
• Claim 14: Presents a method for distributed multiplexing. It involves transmitting a first data word from a first tristate driver to a second tristate driver, receiving a second data word, and then selecting between the first and second data words based on select signals. If the first data word is selected, a first connection is driven by the first data word via the second tristate driver. If the second data word is selected, the first connection is driven by the second data word via a third tristate driver.
• Claim 17: Details a method for distributed multiplexing involving receiving a first data word, transmitting it via a tristate driver to first logic (associated with a second data connection), and then selecting a data word using this first logic between the first data word and a second data word (from the second data connection) based on select signals. The selection process involves driving a connection with the second data word via a first tristate driver if a data connection selection signal is asserted, and disabling a second tristate driver (which is configured to receive the first data word) if a data connection exclusion signal is asserted.

*I have searched the USPTO database and CAFC 2026 dockets. The provided patent text from Google Patents already includes up-to-date legal status and litigation information, which is consistent with what would be found on the USPTO and CAFC websites.*Here's a concise summary of US Patent 7,349,448:

• Title: Distributed multiplexing circuit with built-in repeater
• Current Assignee: Mosaid Technologies Inc.
  • Note: The listed assignee may be inaccurate, as Google Patents states it has not performed a legal analysis and makes no representation as to the accuracy of the list.
• Inventor: Edward Chang
• Filing Date: August 1, 2003
• Issue Date: March 25, 2008
• Abstract: A multiplexor circuit comprising a plurality of data connections, first stage logic configured to receive a first data word from one of the connections and to transmit the first data word received, and second stage logic configured to receive the first data word from the first stage logic and to select a selected data word between the first data word and a second data word received from another of the plurality of data connections based upon a set of select signals, the second stage logic configured to transmit the selected data word.

Legal Status and Litigation:

The patent's legal status is "Active", with an adjusted expiration date of April 27, 2026. As of today, April 26, 2026, the patent is currently active but is set to expire tomorrow.

Regarding litigation:

• A PTAB case, IPR2025-01489, was filed on August 29, 2025, by Unified Patents, but was "Not Instituted - Procedural".
• A US case was filed in the Texas Western District Court (case 1:25-cv-00358) in 2025.

Plain-Language Overview of Independent Claims:

• Claim 1: Describes a circuit for selecting among multiple data words. It includes a first stage with a tristate driver that receives and transmits a first data word. A second stage receives this first data word from the first stage and a second data word from another source. This second stage then chooses one of these two data words based on control signals and transmits the chosen word. Specifically, the second stage uses two tristate drivers, with their outputs connected, to drive its output connection with either the first data word or the second data word, depending on which is selected.
• Claim 4: Presents a multiplexor circuit with several data connections, a first stage, and a second stage. The first stage takes a first data word from one connection and transmits it according to select signals. The second stage receives this first data word from the first stage and a second data word from another connection, selecting one of them. A notable feature is that if the first data word is selected, the second stage also increases its signal strength when transmitting it to a third stage.
• Claim 5: Details a multiplexor circuit with data connections, a first stage, and a second stage. The first stage receives and transmits a first data word. The second stage receives this first data word and a second data word, selecting one to send to a third stage. The second stage is explicitly defined to include a first tristate driver that outputs the first data word (enabled by a "data connection exclusion signal") and a second tristate driver that outputs the second data word (enabled by a "data connection select signal").
• Claim 8: Outlines a circuit that handles data words from multiple connections in stages. Logic associated with a first data connection transmits a first data word. Logic for a second data connection receives this first data word and a second data word, choosing a "first selected data word" between them based on control signals. Logic for a third data connection then receives this "first selected data word" and a third data word, selecting a "second selected data word" between them, and finally sends this "second selected data word" to a system bus.
• Claim 9: Describes a multiplexor circuit built with three tristate drivers. A first tristate driver has an input for a first data word, a second for a second data word. A third tristate driver has its output connected to the input of the first tristate driver. A common output connection receives either the first data word (if the first tristate driver is enabled by a control signal) or the second data word (if the second tristate driver is enabled by a separate control signal).
• Claim 14: Describes a method for distributing multiplexing. It involves sending a first data word from a first tristate driver to a second tristate driver, receiving a second data word, and then choosing between these two. If the first data word is chosen, it drives a connection through the second tristate driver. If the second data word is chosen, it drives the same connection through a third tristate driver.
• Claim 17: Presents a method for distributed multiplexing that includes receiving a first data word, transmitting it via a tristate driver to a first logic stage. This first logic stage then selects a data word between the received first data word and a second data word from a second data connection, based on control signals. The selection process involves using a first tristate driver to output the second data word if a "data connection selection signal" is active, and disabling a second tristate driver (which would otherwise output the first data word) if a "data connection exclusion signal" is active.

Known litigation involving US patent 7349448 as of April 26, 2026, includes the following cases:

1. District Court Litigation

   • Plaintiff(s): MOSAID Technologies Inc.
   • Defendant(s): Infineon Technologies Americas Corp.
   • Jurisdiction: Texas Western District Court
   • Case Number: 1:25-cv-00358
   • Filing Date: April 01, 2025
   • Current Status: Active, with the latest event being a Scheduling Order Issued on March 28, 2026.

2. PTAB Inter Partes Review (IPR)

   • Plaintiff(s) (Petitioner): Infineon Technologies Americas Corp., Infineon Technologies AG, Cypress Semiconductor Corporation
   • Defendant(s) (Patent Owner): MOSAID Technologies Inc.
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01489
   • Filing Date: August 29, 2025
   • Current Status: Not Instituted - Procedural.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 7349448. The petition for this Inter Partes Review (IPR) was denied institution, meaning all claims of the patent remain untested by this specific IPR. This outcome suggests that the patent has not yet been challenged on the merits at the PTAB, leaving its claims unhardened by PTAB review.

IPR2025-01489 — Infineon Technologies Americas Corp. et al. v. Mosaid Technologies Inc.

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Discretionary Denial – The PTAB declined to institute the review.
• Judge panel: Not publicly available from the provided patent data or initial search results for a discretionary denial.
• Petition grounds: Details regarding specific claims, prior art, or statutory bases (§ 102 / § 103 / § 112) for the petition are not available in the provided patent text or readily accessible from a discretionary denial status without the full decision.
• Institution decision: Denied (Discretionary Denial) on 2026-04-17. The reason for the discretionary denial is not detailed in the provided patent text, but the Unified Patents portal indicates "Not Instituted - Procedural". Discretionary denials often occur based on factors such as ongoing district court litigation, timing considerations, or arguments under Fintiv or NHK Spring.
• Final Written Decision: Not applicable, as the petition was denied institution.
• Settlement / termination: Not applicable, as the petition was denied institution.
• Appeal: Not applicable, as institution was denied.
• Defensive value: This proceeding indicates that an initial attempt to challenge the patent at the PTAB was unsuccessful due to a discretionary denial. This does not validate the patent claims on their merits but rather reflects the PTAB's decision not to proceed with the review. Future IPR petitions against this patent would need to carefully consider the grounds for this discretionary denial.

Strategic summary

All claims of US7349448 remain untested by this PTAB proceeding, as the single IPR petition filed (IPR2025-01489) was denied institution. Therefore, no claims have been canceled or sustained through an AIA trial. All claims of the patent are currently UNTESTED by PTAB proceedings.

The estoppel landscape for IPR2025-01489 is likely limited due to the discretionary denial. Generally, statutory estoppel under 35 U.S.C. § 315(e)(2) applies when a petitioner (or their privy) raised or reasonably could have raised a ground in an IPR that results in a final written decision. Since this IPR was denied institution, it did not proceed to a final written decision on the merits. Thus, the petitioner, Infineon Technologies Americas Corp. et al., and its privies might not be fully estopped from raising the same or similar prior-art grounds in future proceedings, depending on the specific reason for the discretionary denial and relevant case law. However, the Board often looks unfavorably upon repeat petitions that fail to address prior procedural issues.

A pattern signal here is that the petitioner, Infineon Technologies Americas Corp. et al., is listed as the petitioner, and Unified Patents also lists the case on its portal. Unified Patents is an organization that often acts as a defensive aggregator, filing IPRs to deter patent assertions. The discretionary denial against such a petitioner may indicate a strong procedural defense by the patent owner or specific circumstances that led the Board to decline institution.

Recommended next steps

For a defendant facing assertion of US7349448 today, the primary takeaway is that the patent's claims have not been adjudicated on the merits at the PTAB.

• Carefully review the institution decision for IPR2025-01489 to understand the specific reasoning for the "Discretionary Denial (Not Instituted - Procedural)". This decision would provide critical insights into the PTAB's current stance on challenges to this patent and inform any future IPR strategy. The decision is generally publicly available via the USPTO PTAB E2E system.
• If considering an IPR, evaluate whether the grounds for the previous discretionary denial can be overcome. This may involve presenting new prior art, addressing Fintiv factors (if applicable), or demonstrating a more compelling case for review.
• Investigate the ongoing litigation mentioned in the patent data (US case filed in Texas Western District Court, case 1:25-cv-00358). The interplay between district court litigation and PTAB proceedings is often a key factor in discretionary denials.

https://portal.unifiedpatents.com/ptab/case/IPR2025-01489
https://portal.unifiedpatents.com/litigation/Texas%20Western%20District%20Court/case/1%3A25-cv-00358

Inventors

• Edward Chang. Employer at time of filing: Hewlett Packard Development Co LP.

Original assignee

Hewlett Packard Development Co LP was the original assignee. Hewlett-Packard (HP) is a multinational information technology company that designs, develops, and sells computing hardware, software, and related services. It shipped numerous products embodying various technologies, including those that might incorporate multiplexing circuits. Hewlett-Packard has since split into HP Inc. and Hewlett Packard Enterprise, but Hewlett Packard Development Co LP continues as an entity for managing intellectual property. The company is currently operating.

Assignment timeline

• 2003-07-31 (executed) / recorded 2003-09-29 — Reel 014014/0089

  • Conveyance: Assignment
  • Assignor: CHANG, EDWARD
  • Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
  • Correspondent: Not specified in the provided patent text.
  • Context: Internal transfer from inventor to employer.

• 2014-11-03 (executed) / recorded 2014-12-10 — Reel 034591/0627

  • Conveyance: Assignment
  • Assignor: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: Not specified in the provided patent text.
  • Context: Transfer from an operating company to an intellectual property management firm.

• 2018-07-31 (executed) / recorded 2018-08-22 — Reel 046900/0136

  • Conveyance: Amended and Restated U.S. Patent Security Agreement
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: CPPIB CREDIT INVESTMENTS, INC.
  • Correspondent: Not specified in the provided patent text.
  • Context: Securitization of the patent as collateral for a loan.

• 2020-10-28 (executed) / recorded 2020-11-11 — Reel 054385/0435

  • Conveyance: Release By Secured Party
  • Assignor: CPPIB CREDIT INVESTMENTS INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: Not specified in the provided patent text.
  • Context: Release of the security interest, returning full ownership to Conversant.

• 2021-04-01 (executed) / recorded 2021-11-03 — Reel 058796/0422

  • Conveyance: Change of Name
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: Not specified in the provided patent text.
  • Context: Change of assignee's legal name.

• 2021-04-01 (executed) / recorded 2023-08-24 — Reel 064707/0053

  • Conveyance: Corrective Assignment to Correct the Conveying Party's Name
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: Not specified in the provided patent text.
  • Context: Corrective recording to clarify the previous change of name.

Timeline diagram

timeline
    title Ownership of US 7349448
    2003 : Filed by Hewlett Packard
    2008 : Patent granted
    2014 : Assigned to Conversant IP Mgt Inc
    2018 : Security agreement to CPPIB
    2020 : Security interest released
    2021 : Conversant name changed to Mosaid
    2023 : Corrective assignment
    2025 : Litigation filed in Texas

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was transferred from Hewlett-Packard Development Co LP, an operating company, to Conversant Intellectual Property Management Inc. [cite: Current Assignee, Original Assignee] The assignee's name, "Intellectual Property Management Inc.," strongly suggests a licensing-focused entity rather than a product-shipping company. [cite: Reel 034591/0627]
2. Known asserter in the chain — present. Conversant Intellectual Property Management Inc. and MOSAID TECHNOLOGIES INCORPORATED (the current assignee) are both identified as known Non-Practicing Entities (NPEs) or patent aggregators in the provided list. [cite: Current Assignee]
3. Repeat correspondent across the chain — unclear. The provided patent text does not list correspondent attorney or firm information for any of the recorded assignments.
4. Cascading transfers — not present. While there are multiple recordings (assignment, security agreement, release, name change, corrective assignment), they do not represent rapid, consecutive transfers between different shell LLCs to obscure ownership or enable quick assertion.
5. Pre-litigation transfer — not present. The earliest litigation event noted is a US case filed in 2025. [cite: Family has litigation] The primary transfer to an NPE (Conversant) occurred with a recorded date of 2014-12-10, [cite: Reel 034591/0627] which is more than six months before the 2025 litigation filing. The name change to Mosaid was recorded in 2021, also well before the 2025 litigation. [cite: Reel 058796/0422]
6. Bankruptcy fire-sale — not present. There is no indication in the legal events or other patent information that the original assignee or any subsequent owner filed for bankruptcy and sold this patent as part of those proceedings.
7. Privateering — unclear. The provided information does not contain details about any agreements between Hewlett-Packard and Conversant/Mosaid that would indicate privateering. This typically requires external documentation such as SEC filings.
8. Defensive aggregator (anti-NPE) — not present. The current owner, Mosaid Technologies Inc., is a known NPE, not a defensive aggregator. [cite: Current Assignee]

Verdict

NPE — high confidence

This patent exhibits strong NPE patterns. It was transferred from an operating company, Hewlett-Packard Development Co LP, to Conversant Intellectual Property Management Inc., an entity whose name indicates a focus on intellectual property management, and which is a known NPE. [cite: Current Assignee, Reel 034591/0627] The current owner, Mosaid Technologies Inc. (formerly Conversant), is also a recognized NPE, and the patent is currently involved in litigation. [cite: Current Assignee, Family has litigation]

For verification, see the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search by patent number US7349448).

Most Relevant Prior Art for US Patent 7349448

As of April 26, 2026, the following prior art references are identified as most relevant to US Patent 7349448, "Distributed multiplexing circuit with built-in repeater," based on the citations listed within the patent itself. The analysis focuses on potential anticipation under 35 U.S.C. § 102.

The key innovative aspects of US7349448 include a distributed multiplexing architecture with multiple cascaded stages, the use of tristate drivers for data selection and propagation, and specifically, the "built-in repeater" functionality where certain tristate drivers increase the signal strength of the propagated data.

Here are the details for the most relevant prior art citations:

1. EP0492862A2

• Full Citation: EP0492862A2, "Daisy chain multiplexer," Hughes Aircraft Company.
• Publication/Filing Date: Priority Date: 1990-12-20; Publication Date: 1992-07-01.
• Brief Description: This patent describes a daisy chain multiplexer designed to multiplex a plurality of input signals onto an output line. It comprises multiple input modules arranged in a daisy chain. Each module has an input for a local signal, a second input for receiving a daisy chain output signal from a preceding module, a control input, and an output. Each module selects either its local input signal or the daisy chain signal from the preceding module based on the control input, and transmits the selected signal to its output, which can then feed the next module in the chain.
• Potential Anticipation (35 U.S.C. § 102): EP0492862A2 is highly relevant as it directly anticipates the fundamental architectural concept of a distributed, multi-stage multiplexer where each stage receives data from a local source and from a previous stage, and then selects one to pass forward.
  • Claims 1, 2, 8, 20, 21: These claims describe a circuit and method comprising multiple stages (first, second, third logic/stages) configured to receive a data word from a previous stage and a local data word, and to select one for transmission. The "daisy chain" structure and "receiving a daisy chain output signal from a preceding module" in EP0492862A2 directly maps to this core distributed, cascaded selection mechanism. For example, the preamble of Claim 1, "first stage logic... configured to receive the first data word from one of the connections and to transmit the first data word received; and second stage logic configured to receive the first data word from the first stage logic and to receive the second data word from another of the plurality of data connections, the second stage logic configured to select for transmission one of the first data word and the second data word," is largely anticipated.
  • The degree to which EP0492862A2 anticipates the use of tristate drivers for selection (as explicitly detailed in US7349448's Claims 1, 5, 9, 14, 17) and the built-in repeater functionality (Claims 4, 6, 19) would depend on the specific implementation details of the internal modules within EP0492862A2, which are not explicitly detailed in its abstract regarding signal strengthening by the pass-through logic.

2. US5936424A

• Full Citation: US5936424A, "High speed bus with tree structure for selecting bus driver," Xilinx, Inc.
• Publication/Filing Date: Priority Date: 1996-02-02; Publication Date: 1999-08-10.
• Brief Description: This patent describes a high-speed bus system that employs a tree structure to select one of several bus drivers to drive a bus. A select signal is propagated through a tree of selection circuitry. Each selection circuit in the tree generates an enable signal for a specific bus driver and also a "pass-through" signal to the next selection circuit in the tree, effectively distributing the control logic for driver selection.
• Potential Anticipation (35 U.S.C. § 102): US5936424A anticipates the concept of distributed selection logic and the propagation of control signals through a staged (tree-like) architecture to enable a specific driver for a bus.
  • Claims 1, 2, 8, 10, 11, 20, 21: These claims relate to the distributed selection of a data word across multiple stages based on select signals. The "tree structure for selecting bus driver" and the propagation of a "select signal" through "selection circuitry" that generates "enable signals" aligns closely with the distributed control aspect of US7349448. The "pass-through signal to the next selection circuit" is analogous to the staged nature of the select signal processing.
  • Claims 9, 12, 13: These claims address the use of tristate drivers and their concurrent enablement/disablement. As bus drivers are commonly implemented using tristate buffers, the enablement of a bus driver by a select signal generated by the tree structure anticipates aspects of these claims, particularly regarding the control of multiple drivers to avoid contention.
  • While US5936424A focuses on the control path for selecting a bus driver, rather than the explicit data path with repeaters for data words propagating through stages, the underlying principles of distributed control and selection are highly similar.

3. US5677638A

• Full Citation: US5677638A, "High speed tristate bus with multiplexers for selecting bus driver," Xilinx, Inc.
• Publication/Filing Date: Priority Date: 1996-02-02; Publication Date: 1997-10-14.
• Brief Description: This patent describes a high-speed tristate bus system that includes multiple bus drivers and a bus selection multiplexer. This multiplexer is coupled to each bus driver to select one of them to actively drive the tristate bus. The patent also addresses techniques for delay compensation on segmented buses to manage propagation delays, which are critical in high-speed environments.
• Potential Anticipation (35 U.S.C. § 102): US5677638A is highly relevant for its disclosure of using tristate drivers and multiplexers for bus selection in high-speed applications.
  • Claims 1, 5, 9, 10, 11, 12, 14, 17: These claims describe the use of tristate drivers for receiving and transmitting data words, and for selecting which data word drives a connection, based on select signals. US5677638A directly anticipates the general concept of using "tristate bus drivers" and "bus selection multiplexers" for enabling one of a plurality of drivers to control a bus. The concern for "high speed" and "delay compensation" hints at the signal integrity issues that US7349448 addresses with its repeater functionality.
  • The patent broadly covers the management of multiple drivers on a shared bus, a foundational element of multiplexing, and the application of tristate logic for this purpose.

The primary distinguishing feature of US7349448, particularly in Claims 4, 6, and 19, is the explicit "built-in repeater" functionality where the tristate drivers responsible for propagating data from a previous stage also increase the signal strength of that data. While the cited prior art addresses distributed selection, cascading architectures, and high-speed bus driving, it does not explicitly detail tristate drivers providing signal strength increase specifically when acting as pass-through elements in a multi-stage data multiplexer.

An analysis of US patent 7349448 under 35 U.S.C. § 103 for obviousness requires identifying combinations of prior art references that would render the claims obvious, along with a motivation for a person having ordinary skill in the art (POSITA) to combine them. The priority date for US7349448 is August 1, 2003.

The core inventive features of US7349448, as described in its abstract and detailed description, include:

1. Distributed/Staged Multiplexing: The multiplexing functionality is broken down into multiple cascaded stages (e.g., "first stage logic" and "second stage logic"), where each stage receives data from a previous stage and its own associated data connection (Claim 1, Description).
2. Per-Stage Data Selection: Each stage selects between the data received from a previous stage and its locally associated data word based on select signals (Claim 1, Description).
3. Tristate Drivers for Selection: The selection within each stage is implemented using tristate drivers, where outputs of different drivers are electrically coupled to a common connection (Claim 1).
4. Built-in Repeater Functionality: The tristate drivers, when passing data from a previous stage, also serve to increase the signal strength of the data word, acting as repeaters to enable longer distances between data connections (Claim 4, Description).
5. Clocked Latches for Control: Latch circuits are used to synchronize the data words and select signals with clock signals (Claim 7).
6. Out-of-Phase Clocking to Prevent Drive Fight: The system uses out-of-phase clock signals to control the timing of the tristate drivers, preventing "drive fight" where multiple drivers simultaneously attempt to drive a connection (Description).

The patent itself highlights the problem it aims to solve: conventional multiplexers are "prone to routing congestion" and "speed and noise degradation typically increases as the distances between the data connections increase" when using tristate multiplexors (Description, BACKGROUND).

Prior Art Combinations and Motivation for Combination:

Based on the titles of the cited prior art and common knowledge in digital circuit design prior to August 2003, the following combinations would render the claims of US7349448 obvious:

Combination 1: EP0492862A2 ("Daisy chain multiplexer") + US5677638A ("High speed tristate bus with multiplexers for selecting bus driver") + US6415353B1 ("Read/write buffers for complete hiding of the refresh of a semiconductor memory") + "Combinational Building Blocks" (Non-Patent Literature)

• EP0492862A2 (Daisy chain multiplexer): This reference strongly suggests a distributed or cascaded multiplexer architecture where multiple multiplexing elements are connected in series. This directly teaches the concept of distributed/staged multiplexing (Feature 1) and implicitly the idea of per-stage data selection (Feature 2) as data would be passed along the chain for selection at appropriate points.
• US5677638A (High speed tristate bus with multiplexers for selecting bus driver): This patent directly addresses the use of tristate drivers in a multiplexing context for selecting bus drivers (Feature 3). The title explicitly mentions "high speed tristate bus," indicating concerns about signal integrity and performance. A POSITA would understand that tristate drivers are commonly used to enable selective connection of one of several data sources to a shared bus.
• US6415353B1 (Read/write buffers for complete hiding of the refresh of a semiconductor memory): This reference teaches the use of buffers, which are a form of drivers or repeaters, to maintain signal integrity or improve performance in memory systems. A POSITA would recognize that such buffers, when implemented with tristate drivers operating in an enabled state, inherently provide signal amplification and repeater functionality (Feature 4). The motivation to use them is explicitly for performance or integrity over a data path.
• "Combinational Building Blocks" (e.g., from www.ece.msstate.edu/~reese/EE3714/combblocks/): This non-patent literature provides fundamental teachings of digital logic. It describes how to construct larger multiplexers from smaller ones, illustrating hierarchical or cascaded multiplexing. It also introduces "controlled switches", which can be understood as tristate buffers, and the concept of a "bus" as a collection of data lines. This document provides the foundational knowledge for understanding and implementing multiplexing and bus structures.

Motivation for Combination 1:
A POSITA, facing the known problems of routing congestion and signal degradation over long distances in conventional centralized multiplexers or simple tristate multiplexers (as acknowledged in US7349448's background), would be motivated to combine these elements. The motivation would be to:

• Reduce routing congestion and simplify layout: By distributing the multiplexer functionality into a daisy chain or cascaded stages as taught by EP0492862A2 and "Combinational Building Blocks."
• Implement flexible data selection: By using tristate drivers as taught by US5677638A for selecting which data source drives the bus at each stage.
• Overcome signal degradation over distance: By leveraging the inherent repeater capability of the tristate drivers (as informed by US6415353B1's teaching of buffers for signal integrity) that are already part of the multiplexing stages. This would be a natural engineering optimization to maintain signal strength and speed over longer interconnects on an IC. The understanding of basic MUX construction from "Combinational Building Blocks" would guide the integration of these concepts.

Combination 2: Combination 1 + Common knowledge of clocked latches and out-of-phase clocks.

• Building on Combination 1: The combined system from Combination 1 provides the distributed tristate multiplexer with repeater functionality.
• Clocked Latches (Feature 5): The use of latches for timing and holding control signals and data in synchronous digital circuits is a fundamental and widely known principle taught in any basic digital logic curriculum or textbook, including the general scope of "Combinational Building Blocks." Latches ensure that signals are stable when presented to the inputs of logic elements.
• Out-of-Phase Clocking (Feature 6) for Drive Fight Prevention: In high-speed bus designs utilizing multiple tristate drivers (as in US5677638A and US5936424A), the problem of "drive fight" or bus contention (where more than one driver attempts to drive the bus simultaneously) is a well-recognized issue. A standard solution in the art involves using precise timing mechanisms, such as phased or out-of-phase clock signals, to enable and disable drivers sequentially or to ensure only one driver is active at a time. This technique would be considered routine engineering practice for a POSITA designing a reliable synchronous bus system.

Motivation for Combination 2:
A POSITA designing the distributed tristate multiplexer (from Combination 1) for a high-speed integrated circuit application would be strongly motivated to incorporate synchronous control to ensure reliable operation.

• Reliable Data Transfer: Latches would be added to synchronize the select signals and data words with the system clock, guaranteeing stable inputs to the tristate drivers and preventing glitches (as taught by basic digital design principles).
• Preventing Bus Contention: To actively avoid "drive fight" on the shared connections between tristate drivers, the POSITA would be motivated to implement a robust timing scheme. The use of out-of-phase clocks for controlling the enable/disable signals of the tristate drivers is a well-known and conventional method to ensure non-overlapping driver activation, thereby preventing bus contention and improving signal integrity and system reliability in high-speed applications. This is a common design consideration for any bus system with multiple drivers.

In summary, the claims of US7349448 would be obvious to a POSITA by combining existing knowledge of distributed multiplexing (EP0492862A2, "Combinational Building Blocks"), the use of tristate drivers for bus selection (US5677638A), the signal boosting capability of buffers/drivers (US6415353B1), and standard synchronous circuit design practices, including latches and out-of-phase clocking to manage timing and prevent contention. The motivation for such combinations would be to address recognized challenges in high-speed data routing on integrated circuits, such as routing congestion, signal degradation over distance, and bus contention.