Prior art

The current date is April 26, 2026.

US Patent 7245299B2, titled "Bicubic surface real-time tesselation unit," was published on July 17, 2007, from an application filed on December 9, 2003, with a priority date of May 12, 2003. Its legal status is "Expired - Lifetime," expiring on March 19, 2024.

The patent describes an improved graphics processing unit (GPU) architecture and method for rendering objects represented as bicubic surfaces in real-time. Key inventive aspects include a tessellate unit placed between the transform and lighting units in a GPU (Claim 1), simplifying 3D surface subdivision to only two orthogonal cubic curves (Claim 3, 20), terminating subdivision based on a flatness threshold measured in screen coordinates (SC) (Claim 3, 20), enabling automatic level of detail, and crack prevention methods (Claim 5, 23).

The most relevant prior art cited by US7245299 (from its "Citations" section) are analyzed below for their potential to anticipate claims under 35 U.S.C. § 102.

Analysis of Cited Prior Art for US7245299

1. US5125073A

• Full Citation: US5,125,073 A, titled "Method and apparatus for adaptive forward differencing in the rendering of curves and surfaces," assigned to Sun Microsystems, Inc.
• Publication/Filing Date: Priority Date: May 8, 1987; Publication Date: June 23, 1992.
• Brief Description: This patent describes a method for adaptively rendering curves and surfaces using forward differencing, where the step size is adjusted to maintain accuracy in generating points. US7245299's background section explicitly references a similar approach by Sun Corporation in the mid-80s, noting its drawbacks such as pixel overstrikes, gaps, and slowness due to pixel-by-pixel rendering rather than triangle-based rendering.
• Potential Anticipation (35 U.S.C. § 102): US5125073A addresses the general problem of rendering curves and surfaces. However, it likely does not anticipate the specific GPU architecture with a tessellate unit between transform and lighting units (Claim 1), the reduction of surface subdivision to only two cubic curves (Claim 3, 20), the use of screen coordinates (SC) for flatness threshold and automatic level of detail (Claim 3, 4, 20), or the specific crack prevention methods (Claim 5, 23) as detailed in US7245299. Its method of adaptive forward differencing is explicitly distinguished as an inferior approach in the background of US7245299.

2. US5377320A

• Full Citation: US5,377,320 A, titled "Method and apparatus for the rendering of trimmed nurb surfaces," assigned to Sun Microsystems, Inc.
• Publication/Filing Date: Priority Date: September 30, 1992; Publication Date: December 27, 1994.
• Brief Description: This patent describes a method for adaptively rendering trimmed NURBS surfaces. US7245299 also discusses extending its methods to NURBS surfaces.
• Potential Anticipation (35 U.S.C. § 102): While US5377320A is relevant to rendering NURBS surfaces, its abstract and available information do not explicitly disclose the specific architectural placement of the tessellation unit (Claim 1), the core optimization of subdividing only two orthogonal curves (Claim 3, 20), or the use of screen coordinates for the flatness threshold (Claim 3, 4, 20) as claimed in US7245299. Therefore, it is unlikely to anticipate these specific features.

3. US6057848A

• Full Citation: US6,057,848 A, titled "System for rendering high order rational surface patches," assigned to Lsi Logic Corporation.
• Publication/Filing Date: Priority Date: April 8, 1997; Publication Date: May 2, 2000.
• Brief Description: This patent describes a hardware system for rendering high-order rational surface patches, incorporating a patch flatness test unit and a subdivision unit to convert patches into simpler primitives. This is directly relevant to real-time tessellation.
• Potential Anticipation (35 U.S.C. § 102): US6057848A broadly anticipates a system for rendering rational surface patches using flatness tests and subdivision (related to Claim 1 and 11). However, it does not explicitly disclose the precise architectural placement of the tessellate unit between the transform and lighting units (Claim 1), the subdivision optimization of reducing to only two cubic curves (Claim 3, 20), or the crucial criterion of measuring the flatness threshold in screen coordinates (SC) for automatic level of detail (Claim 3, 4, 20).

4. US6211883B1

• Full Citation: US6,211,883 B1, titled "Patch-flatness test unit for high order rational surface patch rendering systems," assigned to Lsi Logic Corporation.
• Publication/Filing Date: Priority Date: April 8, 1997; Publication Date: April 3, 2001.
• Brief Description: This patent details a dedicated hardware unit for performing flatness tests on high-order rational surface patches within a rendering system. This is a specific implementation aspect of adaptive tessellation.
• Potential Anticipation (35 U.S.C. § 102): This patent anticipates the concept of a "flatness test unit" for surfaces, which is a component of US7245299's subdivision termination criteria (Claim 3, 4, 20, 21, 22). However, it does not specify that the flatness threshold is measured in screen coordinates (SC) or is part of a subdivision limited to only two orthogonal curves, which are key inventive steps of US7245299. If its flatness test is in world coordinates or without these specific optimizations, it would not anticipate claims 3, 4, 20, 21, and 22.

5. WO2000031690A1

• Full Citation: WO2000031690 A1, titled "Method and device for creating and modifying digital 3d models," assigned to Opticore Ab.
• Publication/Filing Date: Priority Date: November 20, 1998; Publication Date: June 2, 2000.
• Brief Description: This international patent application describes methods and devices for general creation and modification of 3D digital models.
• Potential Anticipation (35 U.S.C. § 102): Given the very broad title and lack of specific details in its abstract within US7245299, this reference is unlikely to anticipate the specific hardware architecture, subdivision methods, SC-based flatness criteria, or crack prevention techniques detailed in the claims of US7245299. It provides general art in 3D modeling.

6. US6597356B1

• Full Citation: US6,597,356 B1, titled "Integrated tessellator in a graphics processing unit," assigned to Nvidia Corporation.
• Publication/Filing Date: Priority Date: August 31, 2000; Publication Date: July 22, 2003.
• Brief Description: This patent describes an integrated tessellator within a GPU. US7245299's background explicitly discusses this patent (Moreton from Nvidia), stating that it "doesn't directly tesselate patches in real-time, but rather uses triangle meshes pre-tesselated off-line in conjunction with a proprietary stitching method that avoids cracking and popping at the seams between the triangle meshes representing surface patches. His tesselator unit outputs triangle databases to be rendered by the existing components of the 3D graphics hardware."
• Potential Anticipation (35 U.S.C. § 102): While US6597356B1 describes an "integrated tessellator in a GPU" (similar to the concept in Claim 1 and 11), US7245299 clearly distinguishes itself by claiming direct real-time tessellation of patches from control points, and specifically placing the tessellate unit between the transform unit and the lighting unit (Claim 1, 11). US6597356B1's approach of using pre-tessellated meshes for output suggests it does not anticipate US7245299's method of generating a new subdivision for each view based on SC parameters (Claim 3, 4, 20) or its specific crack prevention methods (Claim 5, 23).

7. US6624811B1

• Full Citation: US6,624,811 B1, titled "System, method and article of manufacture for decomposing surfaces using guard curves and reversed stitching," assigned to Nvidia Corporation.
• Publication/Filing Date: Priority Date: August 31, 2000; Publication Date: September 23, 2003.
• Brief Description: This patent describes techniques for decomposing surfaces and handling seams or cracks using "guard curves and reversed stitching." This is directly relevant to crack prevention in rendering.
• Potential Anticipation (35 U.S.C. § 102): This patent addresses the problem of cracks between decomposed surface patches, which is also addressed by US7245299 (Claim 5, 14, 19(a)(v), 23). However, US7245299 claims specific crack prevention methods, namely using a "common subdivision for all surfaces sharing a boundary" (either a reunion or finest subdivision) or a "zipper approach" where non-coincident vertices are copied. These specific methods are distinct from "guard curves and reversed stitching," thus it likely does not anticipate the specific methods claimed in US7245299.

8. US20030117405A1

• Full Citation: US2003/0117405 A1, titled "Systems and methods for performing memory management operations to provide displays of complex virtual environments," assigned to Hubrecht Alain Yves Nestor.
• Publication/Filing Date: Priority Date: December 21, 2001; Publication Date: June 26, 2003.
• Brief Description: This patent application focuses on memory management for rendering complex virtual environments.
• Potential Anticipation (35 U.S.C. § 102): This patent is primarily directed to memory management rather than the core technical innovations of real-time surface tessellation algorithms or GPU architecture. Therefore, it is highly unlikely to anticipate any of the specific claims of US7245299 related to GPU components (Claim 1), subdivision techniques (Claim 3, 20), SC-based flatness thresholds (Claim 3, 4, 20), or crack prevention (Claim 5, 23).

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Most Relevant Prior Art for US7245299

Based on the analysis, US6597356B1 (Integrated tessellator in a graphics processing unit by Nvidia) and US6624811B1 (Decomposing surfaces using guard curves and reversed stitching by Nvidia) are highly relevant because they address similar problems (tessellation in GPUs and crack prevention, respectively) and are explicitly discussed and distinguished in the background of US7245299.

Additionally, US6057848A and US6211883B1 (Lsi Logic Corporation) are highly relevant as they describe hardware for rendering high-order rational surface patches and flatness test units, which are foundational concepts built upon by US7245299.

It is also crucial to note that U.S. Pat. No. 6,563,501 (Bicubic Surface Rendering by Adrian Sfarti, the same applicant), while not listed in the "Citations" section but as a "Related Parent Application," is explicitly stated in US7245299's description as providing the underlying method for minimizing computations by subdividing only two orthogonal curves and using SC for flatness determination. US7245299 "utilizes the above method... in order to provide an improved architecture for the computer graphics pipeline hardware." Therefore, US6563501 anticipates many of the methodological claims (e.g., Claims 3, 4, 12, 13, 19(a)(ii-iv), 20, 21), with US7245299's primary novelty residing in its hardware implementation and architectural placement of these methods (Claim 1, 11).