Obviousness

US patent 7245299 describes a graphics processing unit (GPU) for rendering objects by tessellating bicubic surfaces in real-time. The invention includes a tessellate unit coupled between the transform and lighting units of a GPU, which performs real-time tessellation of rational and non-rational bicubic surfaces. Key features of the claimed invention include transmitting objects as control points of bicubic surfaces, simplifying subdivision to only two orthogonal curves, terminating subdivision based on a flatness threshold in screen coordinates (SC), achieving automatic level of detail, and incorporating crack prevention methods.

Under 35 U.S.C. § 103, an invention is considered obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains."

The primary combination of prior art references that would render the claims of US7245299 obvious is U.S. Pat. No. 6,597,356 (Moreton) in combination with U.S. Pat. No. 6,563,501 (Sfarti).

Detailed Analysis of Obviousness:

1. Prior Art References and Their Teachings:

• U.S. Pat. No. 6,597,356 ("Moreton"): This patent, titled "Integrated Tesselator in a Graphics Processing Unit," describes an architecture that includes a tessellator unit within a GPU. However, the '299 patent explicitly differentiates Moreton's approach, stating that it "doesn't directly tesselate patches in real-time, but rather uses triangle meshes pre-tesselated off-line in conjunction with a proprietary stitching method that avoids cracking and popping at the seams between the triangle meshes representing surface patches. His tesselator unit outputs triangle databases to be rendered by the existing components of the 3D graphics hardware." Thus, Moreton teaches the integration of a tessellator unit within a GPU architecture.

• U.S. Pat. No. 6,563,501 ("Sfarti '501"): This patent, titled "Bicubic Surface Rendering" and co-authored by the same applicant as US7245299, provides an improved method and system for rendering bicubic surfaces. The '299 patent explicitly states, "The present invention utilizes the above method for minimizing the number of computations required for the subdivision of bicubic surfaces into triangles in order to provide an improved architecture for the computer graphics pipeline hardware."
  Key teachings of Sfarti '501, as described in US7245299, include:

  • Transforming only the control points of the surface.
  • Selecting a pair of orthogonal boundary curves for processing.
  • Iteratively subdividing only these two orthogonal curves.
  • Terminating subdivision when curves satisfy a flatness threshold expressed in screen coordinates (SC), thereby minimizing computations.
  • Estimating curvature based on flatness in SC (pixels) rather than world coordinates (WC).
  • Enabling "automatic level of detail" by accommodating distance to the viewer.
  • Stating that "the entire rendering process can potentially be performed in real-time" due to reduced computations.

2. Motivation for Combining Moreton ('356) and Sfarti ('501):

A person having ordinary skill in the art (POSITA) would have been motivated to combine the teachings of Moreton ('356) and Sfarti ('501) for several reasons, primarily to address well-known problems in computer graphics rendering described in the background of US7245299:

• Addressing Performance and Bus Bandwidth Limitations: The background of US7245299 clearly outlines that conventional off-line tessellation on the CPU, followed by transmitting vast "triangle meshes" over the Accelerated Graphics Port (AGP) bus to the GPU, creates significant "demands for higher bus bandwidth." This bottleneck, coupled with physical constraints on bus frequency increases, indicated a need to shift processing away from transmitting large triangle databases. Transmitting "control points of the bicubic surfaces" instead of fully tessellated meshes significantly reduces bus traffic.
• Improving Level of Detail (LoD) and Visual Quality: The '299 patent also points out that off-line tessellation produces "fixed triangulation" that can be inefficient. Objects far away might have "excessively large number of very small triangles," while objects close to the viewer might have "very large" triangles, causing them to lose "smoothness appearance" and look "more like a polyhedron."
• Leveraging Existing Hardware Integration Concepts: Moreton ('356) already demonstrated the concept of an "integrated tesselator in a Graphics Processing Unit." While Moreton's approach still relied on pre-tessellated meshes, the idea of having a dedicated tessellation unit within the GPU was established. A POSITA would logically seek a more efficient tessellation method to implement within this hardware paradigm.
• Implementing a Proven Efficient Method: Sfarti '501 provided a highly efficient method for bicubic surface rendering that explicitly minimized computations by subdividing only two orthogonal curves and using SC for termination. Crucially, the '501 patent states this method "can potentially be performed in real-time" and produces "automatic level of detail."
• Achieving Real-Time Tessellation: The '299 patent states a need for "a system and method for performing tessellation in real-time." By combining the hardware placement suggested by Moreton (tessellator in GPU) with the efficient, real-time-enabling method from Sfarti '501, a POSITA would arrive at a solution that directly addresses this long-felt need. The background itself details previous unsuccessful attempts at real-time hardware tessellation (Sun Corporation's pixel-by-pixel, Nvidia's biquadric), further underscoring the motivation for a successful real-time triangle-generating tessellator.

3. Obviousness of the Claims of US7245299:

• Claim 1 (Graphics processing unit): This claim describes a GPU with a transform unit, lighting unit, renderer unit, and a tessellate unit coupled between the transform and lighting units for real-time tessellation of surfaces, receiving control points of bicubic surfaces.

  • Moreton teaches an "integrated tesselator in a Graphics Processing Unit." Sfarti '501 teaches an efficient method for real-time rendering of bicubic surfaces by operating on control points and outputting triangles. A POSITA, motivated to overcome bandwidth and LoD issues, would combine these by implementing the Sfarti '501 real-time tessellation method within Moreton's GPU-integrated tessellator. The placement of the tessellate unit between the transform (which transforms control points) and lighting units (which light the tessellated triangles) is a logical and predictable architectural design choice within the graphics pipeline.

• Claim 11 (System): This claim covers a system with a processor and such a GPU. The processor transmitting objects as control points to the GPU, which then transforms, tessellates, lights, and renders, directly addresses the bandwidth problem identified in the prior art, as the CPU no longer needs to send entire triangle meshes. This system architecture directly follows from the motivation to move tessellation to the GPU and use control points as input for the '501 method.

• Claim 19 & 20 (Real-time Methods for Tessellating and Rendering): These claims detail the specific method steps of real-time tessellation, including transforming control points, subdividing only two cubic curves, terminating subdivision based on screen coordinates (SC), achieving automatic level of detail, preventing cracks, and generating vertices, normals, and texture coordinates in real-time.

  • These method steps are explicitly taught and enabled by Sfarti '501, which US7245299 acknowledges it "utilizes." The '501 patent describes these steps as minimizing computations and enabling real-time rendering with automatic LoD. Therefore, if a POSITA is motivated to implement a real-time tessellation in hardware (as motivated by Moreton + Sfarti '501 combination), the specific efficient method steps to achieve this, as taught by Sfarti '501, would be obvious to apply. The '299 patent explicitly states that the "tessellate unit 9 executes the microcode described above in the Step 1 through Step 4, thereby affecting the real-time tessellation," where Steps 1-4 are the detailed method steps largely derived from the '501 patent.

In conclusion, the combination of Moreton's U.S. Pat. No. 6,597,356, which introduced an integrated tessellator into a GPU, and Sfarti's U.S. Pat. No. 6,563,501, which provided an efficient, real-time-enabling method for bicubic surface tessellation using screen coordinates and subdivision of only two orthogonal curves, would have rendered the claims of US7245299 obvious to a person of ordinary skill in the art. The motivation to combine these references stems from the clear and recognized problems in the prior art concerning bus bandwidth limitations and the need for adaptive real-time tessellation with automatic level of detail in graphics rendering.