US 7123077

I'll verify the patent's current status and check for any litigation/docket activity before summarizing.

Summary of US 7,123,077 B2

Identification

Abstract (as issued): A charge pump circuit has an input stage, an output stage and multiple boosting stages coupled between them. The boosting stages are driven by four phase clock signals. Each boosting stage has two branch charge pumps, wherein each branch charge pump at least has a main pass transistor, a pre-charge transistor, two substrate transistors and capacitors. The substrate transistors and the main pass transistor are operated in association with the four phase clock signals to keep a potential of the body of the main pass transistors at a low level thus mitigating the body effect.

Plain-language overview of the independent claim (claim 1)

Claim 1 is the only independent claim; all others (2–6) depend from it. Claim 1 recites a "four-phase charge pump circuit with reduced body effect" comprising:

1. Top-level architecture — an input stage; an output stage that outputs a boosted voltage; and multiple boosting stages coupled between the input and output stages and driven by four phase clock signals.
2. Each boosting stage has an upper branch charge pump and a lower branch charge pump, and each branch charge pump contains four element groups:
   • A main pass transistor — has a body, a gate, a source terminal designated as a "first node," and a drain terminal designated as a "second node." The first and second nodes connect respectively to a front boosting stage and a rear boosting stage, and the body potential is kept at a low level by the four phase clock signals.
   • A pre-charge transistor — its drain and source terminals are coupled to the gate of the main pass transistor and to the second node; its gate is coupled to the first node of the main pass transistor. (Note: the claim does not assign which of the pre-charge transistor's source/drain goes to which of those two points — only that both are coupled to them; the specification states separately that the body and source of the pre-charge transistor are connected together, which is claimed only dependently in claims 4–6.)
   • Two capacitors — coupled respectively to the gate terminal of the main pass transistor and to the first node.
   • Two substrate transistors — each has a body, gate, source and drain; their source terminals and bodies are tied together and connected to the body of the main pass transistor; their drain terminals connect respectively to the first node and the second node of the main pass transistor.
   • Distinguishing interconnection (the crux of the claim) — the gate of the substrate transistor whose drain connects to the first node is connected to the second node of the main pass transistor; and the gate of the other substrate transistor is connected to the second node of the main pass transistor of the other branch charge pump.

Dependent claims (brief)

• Claim 2 — circuit is a negative charge pump; main pass, pre-charge and substrate transistors are N-channel MOSFETs.
• Claim 3 — circuit is a positive charge pump; those transistors are P-channel MOSFETs.
• Claim 4 — (from claim 1) the body and source terminal of the pre-charge transistor are connected together.
• Claim 5 — (from claim 2) same body-to-source connection of the pre-charge transistor, in the N-channel/negative-pump case.
• Claim 6 — (from claim 3) same, in the P-channel/positive-pump case.

Technical thrust: the substrate ("back-gate") transistors form a bias-switching network that keeps the body of each main pass transistor at a low level, so the body-to-source voltage is driven to zero before the main pass transistor turns on — reducing body effect and avoiding the delay/inefficiency caused by an elevated threshold voltage during charge transfer.

Status and docket checks (with uncertainty flagged)

• U.S. status: The Google Patents record for US7123077B2 states "Expired – Lifetime," with an adjusted expiration of 2025-01-23. Maintenance-fee events of record show payments at years 4 (2010), 8 (2014), and 12 (2018, small entity). Note a source discrepancy: a third-party aggregation record (RPX/insight) still lists the patent as an "Active Grant." Given the patent's term (filed 2004-09-23; adjusted expiration 2025-01-23) and today's date (April 2026), the patent has expired; I would treat the "Active Grant" label as stale.
• USPTO database: I could not directly query USPTO Patent Center / Patent Public Search in this session; the authoritative full text and bibliographic data I used are the Google Patents mirror of the USPTO record (https://patents.google.com/patent/US7123077/en), which matches the record provided.
• CAFC 2026 dockets: A targeted search found no CAFC 2026 docket, appeal, or litigation involving patent number 7123077. I cannot rule out that activity exists in a database I could not reach, but there is no evidence in the retrieved results of any Federal Circuit proceeding. Uncertainty noted.
• Forward citations of note: eMemory's own US 7,576,593 B2 ("Two-phase charge pump circuit without body effect," 2009) and US 2016/0006349 A1 ("Four-phase charge pump circuit") cite/relate to this family, indicating this patent is part of an ongoing eMemory charge-pump portfolio. CN104767383B ("A kind of phase charge pump booster circuit of low pressure four") also cites it.

If you need a certified litigation/docket history, that should be confirmed against PACER and the USPTO Patent Center, which I was unable to query directly here.

I'll research litigation involving US patent 7123077 across patent litigation databases.

The first-pass results returned noise (note: one result concerned U.S. Patent 7,187,307 — a different patent). Let me run targeted searches.

Let me query litigation-specific databases directly.

Bottom line

I found no litigation involving U.S. Patent 7,123,077. Based on my searches, there are no district court suits, ITC Section 337 investigations, or PTAB proceedings that name U.S. Patent 7,123,077 in any publicly indexed source I could reach.

What I checked and what I found

Important disambiguation (do not conflate)

My searches surfaced a body of litigation involving a different patent whose number is visually similar. Under the strict rule against auto-correction, I flag these as distinct from U.S. 7,123,077:

• U.S. Patent 7,187,307 B1 ("'307 patent," a communications line-code/serial-link patent) is at issue in:

  • Universal Connectivity Technologies Inc. v. Dell Technologies Inc., et al., No. 1:23-cv-01506-RP (W.D. Tex.)
  • Universal Connectivity Technologies Inc. v. HP Inc., No. 4:24-cv-04097-YGR (N.D. Cal.)
  • Universal Connectivity Technologies Inc. v. Lenovo Group Limited, No. 2:23-cv-00449-JRG (E.D. Tex.)
  • A related Lenovo-U.S. declaratory judgment action, No. 1:24-cv-01126-RGA (D. Del.)
  • And IPR2024-01429 et al. (Petitioners' RPI's include Dell, HP, and Lenovo)

  This is U.S. 7,187,307 — not the charge-pump patent 7,123,077. These are different patents owned by different entities and are unrelated to the eMemory charge-pump invention.

Context on the '077 patent

U.S. 7,123,077 ("Four-phase charge pump circuit with reduced body effect," eMemory Technology Inc., filed 2004-09-23, priority TW093123153A of 2004-08-03, granted 2006-10-17, expired — adjusted expiration 2025-01-23) appears in the record only as a cited prior art reference in later patents (e.g., US7777557, US11508435 family documents), not as an asserted patent. Its Chinese/Taiwanese counterpart, TWI261407B, likewise shows no litigation in the records I retrieved.

Confidence and limitations

• Confidence: moderate-to-high that there is no U.S. litigation. The absence of any litigation entry on Google Patents and RPX, combined with the patent's expired status (adjusted expiration 2025-01-23) and its owner's history of licensing rather than litigating, is consistent with a no-litigation record.
• Caveat: I was unable to directly complete queries against the Unified Patents litigation caselist and PACER/CAFC dockets (my search session terminated before I could finish those targeted lookups, and PACER requires paid authenticated access). Those databases are the most authoritative for a negative/positive litigation confirmation. A definitive clearance statement should be run against them directly, and against any foreign (e.g., Taiwan, China, Korea) dockets if non-U.S. enforcement is in scope.
• Nothing in my results should be taken as an affirmative representation that no litigation exists; it is a statement that I could not identify any.

I'll start by verifying the structured data against live sources. The ODP block says no AIA trials — let me stress-test that with web searches before writing.

⚠️ Important flag: the first hit — IPR2024-01429 — is against U.S. Patent No. 7,187,307, not our 7,123,077. Those are different patents (that IPR is about encoding/decoding application data bits and applies Fintiv). I need to confirm no proceedings exist against 7,123,077 specifically.

No hits on 7,123,077 itself. Let me run two more targeted checks — the TW counterpart and the patent's title — to be sure.

Proceedings overview

Zero AIA trial proceedings are on file against US 7,123,077 — the USPTO Open Data Portal returns no IPR, PGR, or CBM for this patent (0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution-denied), so the bottom-line defensive posture is not "this patent has been hardened by surviving PTAB" and not "the troll's claims are already canceled" — it is that no one has ever petitioned the Board on this patent, its six claims remain exactly as issued, and the patent has now expired (adjusted expiration 2025-01-23), which is itself the controlling defensive fact.

Before writing anything, I checked two things: (1) the structured ODP block supplied with this task, and (2) live web search. The searches returned proceedings only against similarly numbered but different patents — see the confusion trap below. I found no petition, institution decision, FWD, or appeal directed at US 7,123,077.

⚠️ Confusion trap — do not cite these as proceedings on your patent. Web search for "7123077 IPR" surfaces several real AIA trials that are not against US 7,123,077. If opposing counsel or a docket search feeds you any of these, verify the patent number character-by-character:

• IPR2024-01429 — challenges U.S. Patent No. 7,187,307 (digits transposed vs. 7,123,077). A Patent Owner's Preliminary Response is on file arguing Fintiv/discretionary denial based on a parallel "LGL" district court case; the subject matter is encoding/decoding application data bits and control bits. Entirely unrelated to charge pumps.
• IPR2025-01452 and a companion petition — challenge U.S. Patent No. 7,777,557 (a booster/charge-pump patent, Panasonic "Booster circuit" lineage) on Meng/Park grounds. Not 7,123,077.
• Other petitions surfaced (e.g., referencing the '018 and '875 patents) are likewise different patents.

Because we are deep in "7,1x3,0xx" territory across the charge-pump art, the single most important operational rule for this file is: confirm the seven-digit number on the caption of any PTAB paper before relying on it.

Strategic summary

Claim status. US 7,123,077 has six claims: independent claim 1 (the four-phase, upper/lower-branch charge-pump architecture with main pass transistor, pre-charge transistor, two capacitors, and the cross-coupled substrate-transistor body-bias scheme), and dependent claims 2–6 (2 = negative pump/N-channel; 3 = positive pump/P-channel; 4–6 = body and source of the pre-charge transistor tied together, appended to claims 1, 2, and 3 respectively). None of claims 1–6 has been canceled, confirmed, or even construed by the PTAB. All six are untested at the Board — the AIA-trial axis is simply blank, which means any "the claims are already dead" pitch is unsupported.

Estoppel landscape. With no IPR/PGR/CBM petition ever filed against this patent, there is no § 315(e)(2) estoppel, no § 325(e)(2) estoppel, and no petitioner-privity chain to worry about. Nothing has been foreclosed. Every prior-art ground you might want to raise remains theoretically available — including the art cited on the face of the patent (US 4,935,644; US 5,717,278; US 5,644,534; US 5,767,735; US 5,767,733; US 6,037,622; US 6,457,438; US 6,875,218/6,878,981; and the 2005 published application US 2005/0151580 to Lin, "Four-phase dual pumping circuit") — though two of these (6,457,438 and 6,878,981, both Intel single/double-pump "triple well, no body effect") are the most on-point § 102/§ 103 candidates for the body-effect mitigation concept.

The decisive fact is the clock, not the Board. Per the front-page data, the patent's adjusted expiration is 2025-01-23 and its legal status is "Expired – Lifetime." Today is 2026-09-29. There is therefore no forward-looking infringement exposure: a defendant's ongoing conduct cannot infringe an expired patent, and a prospective IPR challenge would be pointless (not to mention that the Board has, since 2025, applied heightened discretionary-denial and "settled expectations"-type doctrines to older, dormant patents). The remaining exposure is purely backward-looking — past damages for conduct during the six years before any complaint (35 U.S.C. § 286), if suit was filed before expiration. That window, too, is now largely spent.

Pattern signals. None to report. No serial petitioner, no defensive aggregator (the search surfaced Unified Patents only in unrelated policy briefs, not as a petitioner here), no patent-owner appeal activity, no litigation-triggered IPR chain against this patent. This is consistent with the patent's age and the fact that charge-pump architectures of this 2004 vintage became commoditized.

Recommended next steps

1. Lead with expiration, not validity. For any defendant facing an assertion today: confirm the asserted claims and the on-sale/use dates against the 2025-01-23 adjusted-expiration date. Any alleged infringement after that date is legally impossible; only pre-expiration, within-lookback conduct is even nominally in play.
2. If the assertion is pre-expiration, run a § 285/§ 101-style sanity check on the demand. A demand letter that cites claims 1–6 for current (post-expiration) products is defective on its face — there is no PTAB cancellation to point to, but there is also no live patent to enforce.
3. Do not gate your defense on a pending IPR. There is no institution-decision deadline, no oral hearing, and no statutory one-year FWD due date to track, because there is no trial. Anyone telling you an IPR is "pending" against 7,123,077 is looking at IPR2024-01429 (U.S. 7,187,307) or the '557-patent IPRs — verify the number.
4. The absence is a signal. Well-asserted, valuable patents attract IPRs; this one attracted none across two decades. Combined with expiration, that is strong evidence the patent was never a significant commercial lever. If you must defend on the merits (past damages), the Intel triple-well no-body-effect references (US 6,457,438; US 6,878,981) and Lin's US 2005/0151580 four-phase dual-pump publication are the first art to develop.

Sources / verification note. I relied on the structured "PTAB proceedings on file" block (ODP: no AIA trials) plus Google Patents US7123077B2 for claims, cited art, and expiration status. PTAB papers are public at the USPTO PTAB E2E portal (https://ptacts.uspto.gov) and PTAB Decisions; no CAFC appeal or CourtListener docket exists for this patent because no Board decision was ever issued. I could not retrieve any IPR/PGR/CBM captioned with US 7,123,077, and I have not fabricated a proceeding number, panel, FWD, or docket to fill the gap.

I'll research the assignment chain and ownership history for US 7,123,077.

I have the primary source (Google Patents legal events) showing a single assignment. Let me verify against the USPTO Assignment Center and cross-reference ownership/litigation.

Assignment & Ownership Chain — US 7,123,077 B2

Method note / source limitation (read first): I was unable to reach assignmentcenter.uspto.gov or assignment.uspto.gov directly in this session (tool/step limit hit mid-research). The authoritative assignment data I did obtain comes from the USPTO-derived legal-events block on the Google Patents record for US7123077B2 (https://patents.google.com/patent/US7123077/en), which surfaces the recording reel/frame, date, and conveyancing parties but does not expose the correspondent of record. I flag every place that gap matters. Nothing below is fabricated; where a reel/frame or correspondent was not retrievable, I say so.

Inventors

Unusual-pattern check: The flagged red-flag pattern — all inventors departing the original assignee within 12 months of filing, preceding a portfolio fire-sale — is not present on the record I retrieved. The only tenure datapoint I can affirmatively verify (Chang) shows continued eMemory inventorship over a decade later. No inventor employment-exodus evidence surfaced. That said, I could not retrieve HR/departure records for Chiu, so his post-2004 status is unknown.

Discrepancy flag: the pre-generated "Patent summary" lists the earlier priority date correctly (TW 093123153A, 2004-08-03), and I found no contradiction between the previously generated sections and the full text on inventors. The earlier sections also state "today's date (April 2026)" while this session's operating date is 2026-09-29 — a minor internal inconsistency, immaterial to ownership but worth noting.

Original assignee

eMemory Technology Inc. (Hsinchu / Zhubei, Taiwan; TWSE-listed via Taipei Exchange, ticker 3529). Named assignee on the face of the patent and sole assignee of the invention per reel 015825/0601.

• Primary line of business: pure-play logic non-volatile memory (Logic NVM) silicon IP — OTP/MTP/Flash/PUF technologies (NeoBit, NeoFuse, NeoMTP, NeoEE, NeoFlash, NeoPUF). It licenses IP to foundries, IDMs and fabless houses and collects royalties from wafer production; it is not a chip manufacturer.
• Does it ship a product embodying the claims? Not directly — eMemory does not sell chips. Its charge-pump IP is embodied in its customers' silicon. This is its actual revenue model, not a shell arrangement: ~70% of revenue is wafer-production royalty, cumulative design licenses exceeded 8,000, over 7,000 IP-based wafers shipped, and it holds e.g. the TSMC Best IP Partner Award continuously since 2010. Revenue ~US$112M (Forbes), 316–330+ employees (~70% R&D).
• Current status: Operating. Founded 2000, IPO 2011, headquarters Zhubei, Taiwan; subsidiary PUFsecurity (est. 2019). No bankruptcy, no dissolution, no acquisition of eMemory itself was found. This is a live, profitable operating company — the opposite of a wound-down assignor.

Assignment timeline

The Assignment Center counterpart on Google Patents shows exactly one recorded conveyance for US 10/947,677 → US 7,123,077. No post-issuance transfers, no security agreements, no mergers, no name changes are of record.

• 2004-09-20 (executed) / recorded 2004-09-23 — Reel 015825 / Frame 0601
  • Conveyance: Assignment (full — "ASSIGNMENT OF ASSIGNORS INTEREST")
  • Assignor: CHIU, LIANG-HSIANG; CHANG, WU-CHANG (the two named inventors)
  • Assignee: EMEMORY TECHNOLOGY INC. (Taiwan)
  • Correspondent: Not exposed in the retrieved record. The Google Patents legal-events mirror for reel 015825/0601 lists only REEL/FRAME and the assignment-of-interest description; it does not publish the attorney/agent of record, and I could not pull the underlying Patent Assignment Search page to obtain it. This field is a gap, not a negative finding. Because this single instrument is an inventor→company assignment — the ordinary filing-day instrument that every operating company executes — a correspondent here would be, at most, evidence of eMemory's outside IP counsel, not an NPE-shell indicator.
  • Context: Initial inventor-to-company assignment (standard pre-issuance title perfection). Not a fire-sale, reorg, securitization, or transfer-to-asserter.

Corroborating non-assignment legal events (from the same record):

• 2004-09-23 — application filed by eMemory Technology Inc.
• 2006-10-17 — patent granted / issued.
• 2010-04-02 — maintenance fee, year 4.
• 2014-04-02 — maintenance fee, year 8.
• 2018-03-20 — maintenance fee, year 12 (small entity).
• 2025-01-23 — adjusted expiration; status "Expired – Lifetime."

There are no later recorded assignments after 2004-09-23. Per the task's own rule, that absence is itself the finding: the original assignee still owned the patent at expiry.

Contradiction check vs prior sections: This is consistent with the previously generated "Patent summary" and "Litigation summary," which likewise identified eMemory as the sole assignee and the patent as expired — but note the prior summary cited "RPX Insight" as listing the patent "Active Grant." That is a stale third-party label; the primary source's "Expired – Lifetime / 2025-01-23" governs.

Timeline diagram

timeline
    title Ownership of US 7123077
    2004 : TW priority filed 2004-08-03
         : Inventors assign to eMemory 2004-09-20
         : US application filed 2004-09-23
    2006 : US 7123077 issues 2006-10-17
    2010 : Maintenance fee year 4 paid
    2014 : Maintenance fee year 8 paid
    2018 : Maintenance fee year 12 paid
    2025 : Patent expires 2025-01-23

NPE / troll-pattern signals

Verdict

Insufficient data — because the only recorded event is the original inventor→company assignment (reel 015825/0601, executed 2004-09-20, recorded 2004-09-23); there are no post-issuance transfers to analyze.

Substantively, this is not an NPE chain in any respect. The sole recorded assignee is eMemory Technology Inc., a genuine listed operating company that funds the patent via real IP-licensing royalties, paid maintenance fees through year 12 (2018), and explicitly let the patent expire on 2025-01-23 rather than assert it. Every one of the eight NPE/privateering signals is absent or untestable; none is present. The absence of any post-2004 assignment of record affirmatively indicates the original assignee held title to expiry.

Verification link (USPTO Assignment Center): https://assignmentcenter.uspto.gov/ — search patent number 7123077 (legacy interface: https://assignment.uspto.gov/patent/index.html). The authoritative reel to pull is 015825/0601; retrieving that image is the only way to confirm the correspondent of record, which the Google Patents mirror does not expose and which I could not obtain in this session.

Caveats (stated, not hedged): (a) I did not independently complete a live USPTO Assignment Center / PEDS pull; my reel/frame data is the USPTO-derived Google Patents legal-events block. (b) The correspondent of record is unknown to me — do not treat its omission as evidence of anything. (c) Foreign (TW/CN/KR) ownership of the sibling TWI261407B was outside the scope of records I could reach.

I'll run targeted searches — first to confirm the USPTO record for 7,123,077 itself, then to pull details on each of its 13 cited references.

I have solid data on several references. Let me pull details on the remaining cited references.

Prior-Art Analysis — U.S. Patent No. 7,123,077 B2

Note on scope: I treated "7123077" literally as U.S. Patent No. 7,123,077 B2 ("Four-phase charge pump circuit with reduced body effect," eMemory Technology Inc.). I did not return results for visually similar numbers such as U.S. 7,187,307 (the communications line-code patent that dominated earlier litigation searches) — that is a different patent and is excluded here. The authoritative record used is the Google Patents mirror of the USPTO record: https://patents.google.com/patent/[US7123077](/patent/US7123077)/en

Method / limitation: I retrieved and verified the full front-matter citation list (13 references) from the patent record, and I obtained full text for the four most technically salient references. Four of my follow-up lookups were cut off by a session step limit, so for the remaining references I rely on the citation metadata in the patent record plus general technical knowledge — those entries are flagged [metadata only]. I did not fabricate claim mappings for references I could not read in full.

1. The 13 references cited on the face of US 7,123,077

Note: reference #13 is the pre-grant publication of US 6,952,129 B2 ("Four-phase dual pumping circuit," Lin et al., eMemory Technology Inc., granted 2005-10-04). The two identifiers are the same disclosure. Its assignee is the same as the patent under review.

All of these were before the patent's earliest priority (2004-08-03) as of their filing dates, so they are available at minimum as pre-AIA §102(a)/(e) art; most are §102(b) art because they published/issued more than one year before the priority date.

2. The §102 test, applied to claim 1

Claim 1 is the sole independent claim; claims 2–6 depend from it (2 and 3 directly; 4–6 via 1/2/3). Consequence for anticipation: because every dependent claim incorporates all of claim 1, no dependent claim can be anticipated unless claim 1 itself is anticipated by that same reference. So the anticipation question reduces to whether any single reference discloses all of the following, in the "upper branch + lower branch" architecture:

• (A) input stage + output stage + multiple boosting stages driven by four phase clock signals;
• (B) each stage = an upper branch charge pump and a lower branch charge pump;
• (C) per branch, a main pass transistor (body, gate, source = "first node," drain = "second node," nodes to front/rear stages; body held low by the four clocks);
• (D) per branch, a pre-charge transistor whose drain and source couple to the gate of the main transistor and to the second node, and whose gate couples to the first node;
• (E) per branch, two capacitors coupled to the main transistor's gate and to the first node;
• (F) per branch, two substrate transistors, sources and bodies tied together and to the main transistor's body, drains to the first and second nodes respectively;
• (G) the distinguishing cross-connection: the gate of the substrate transistor whose drain connects to the first node is connected to the second node of the main transistor, and the gate of the other substrate transistor is connected to the second node of the main pass transistor of the other branch charge pump.

Bottom line up front: No reference on the §102 citation list discloses all of (A)–(G) in one disclosure. There is therefore no clean single-reference anticipation of claim 1 (and thus of claims 2–6) on the face of the references the examiner cited. The references are strongest as §103 obviousness material and as partial disclosures, which is consistent with the patent having issued over them.

3. Reference-by-reference analysis

Tier 1 — Most relevant: US 2005/0151580 A1 / US 6,952,129 B2 (Lin et al., eMemory)

• Full citation: US 2005/0151580 A1 (pub. 2005-07-14); granted as US 6,952,129 B2 (Oct. 4, 2005). App. 10/707,786, filed 2004-01-12. Inventors Hong-chin Lin, Ming-Chih Hsieh, Jain-Hao Lu, Chien-Hung Ho. Assignee: eMemory Technology Inc. Sources: https://patents.google.com/patent/US20050151580 and https://patents.justia.com/patent/[6952129](/patent/6952129)
• Description: A four-phase dual pumping circuit. Each stage has a first pumping unit and a second pumping unit that are "mirror and identical" (i.e., the two-branch architecture of element (B)); the circuit is controlled by four-phase clocks (element (A)). Each pumping unit contains a main pass transistor (element (C)), a "boosting transistor" that pre-charges the current stage with drain→gate of main pass transistor, source→drain (second node) of main pass transistor, and gate→source (first node) of the main pass transistor (this maps onto element (D)), two "small charge storing devices" coupled to the gate nodes and two "large charge storing devices" coupled to the drain nodes (capacitors, element (E)), and a substrate transistor used to bias the body and "eliminate body effects." Critically, "[t]he substrate transistor of either pump circuit is controlled by a high voltage signal sent from the other pump circuit" — i.e., the cross-branch gate control that corresponds to the second half of element (G). The same patent discloses NMOSFETs for negative pumping and PMOSFETs for positive pumping (mirroring claims 2 and 3).
• §102 assessment: This is the closest prior art and the same assignee's own earlier work. It clearly anticipates/renders obvious the architecture of (A), (B), (C), (D), and the cross-branch gate-control concept in (G). However, on the record I retrieved it discloses one substrate transistor per pumping unit, whereas claim 1 requires two per branch (element (F)) plus the specific gate-to-own-second-node connection for the first substrate transistor (element (G), first clause). It also locates the large storage capacitor at the drain/second node rather than at the first node (element (E) nuance). Because claim 1 requires the full (A)–(G) combination, US 6,952,129 does not, standing alone, anticipate claim 1 — but it is the primary §103 reference (the differences would be a two-substrate-transistor bias network and node assignment, which are exactly what US 6,878,981/US 6,452,438 teach).
• Claims it could be argued against: claim 1 (as the lead §103 reference), and derivatively claims 2 and 3, since it expressly discloses the NMOS/negative and PMOS/positive variants and the cross-branch substrate-transistor control.

Tier 2 — Strong secondary: the "well/substrate-bias transistor pair" references

US 6,878,981 B2 (Eshel, Tower Semiconductor)

• Full citation: US 6,878,981 B2, "Triple-well charge pump stage with no threshold voltage back-bias effect," Noam Eshel, Tower Semiconductor Ltd., filed 2003-03-20, granted 2005-04-12. Source: https://patents.google.com/patent/[US6878981B2](/patent/US6878981B2)/en
• Description: A single charge-pump stage with four n-channel transistors and two capacitors: (i) a first n-channel transistor = main pass device, source→input terminal, drain→output terminal; (ii) a second n-channel transistor = pre-charge device, source→input, drain→gate of the first transistor, gate→output; (iii) a third n-channel transistor, source→input, gate→output, drain→p-well; (iv) a fourth n-channel transistor, source→output, gate→input, drain→p-well. The third and fourth transistors keep the p-well at the lower of the two node voltages, driving V_SB to zero to eliminate the body effect. Stages are series-cascaded and driven by CLK1–CLK4.
• §102 assessment: Eshel discloses, in a single stage, elements (C)-like, (D)-like, (E) (two capacitors), and (F)-like (a pair of well-bias transistors whose drains tie together to the body and which bias it to eliminate body effect). But:
  • it is a single-branch serial stage, not the upper/lower branch architecture of element (B);
  • the well-bias transistor source/drain orientation is reversed relative to claim 1's element (F) (sources to input/output, drains to the p-well);
  • there is no cross-branch gate connection (element (G)); the fourth transistor's gate is tied to its own input node, not to another branch's second node.
    So Eshel does not anticipate claim 1. It is nonetheless highly probative §103 art for the "two substrate-bias transistors driving V_SB→0" limitation, which is the heart of the patent's stated advantage (and is cross-citable against the "reduced body effect" framing).
• Claims it could be argued against: none for a clean §102 anticipation of claim 1 as issued; §103 against claim 1 (and claims 2/4/5 for the N-channel/negative case and the pre-charge body-to-source link).

US 6,452,438 B1 (Li, Intel)

• Full citation: US 6,452,438 B1, "Triple well no body effect negative charge pump," Li (inventor); Intel Corporation; filed 2000-12-28, granted 2002-09-17. Sources: https://patentimages.storage.googleapis.com/0b/c8/6d/87e5732ca47361/US6452438.pdf ; https://www.freepatentsonline.com/[7342438](/patent/7342438).html (related continuation US 7,342,438, Bo Li/Ahmed Muneer)
• Description: A four-stage triple-well NMOS negative charge pump with four clock signals (CLOCK1–CLOCK4). Each pump cell/claim recites a switching device, a storage capacitor coupled to the source, a boot capacitor coupled to the gate, a pull-up/pull-down/control arrangement, and, notably, a pair of N-type well-biasing devices (e.g., 314/316) whose drains are tied to the substrate terminals of the stage's N-type devices. Gate connections: one bias device's gate is coupled to the source of the switching transistor; the other's gate is coupled to the drain. The well-biasing devices "alternately switch the potential on the substrates between the low voltage potential at the drain and that at the source," which "eliminate[s] body effect."
• §102 assessment: Li discloses two substrate/well-bias transistors per stage tied to the body (element (F)-like) and the source/drain node sensing that grounds the body-effect mitigation. But it is a single serial chain of stages (no upper/lower branch, element (B)), the bias-device source/drain orientation is inverted from claim 1's element (F), the gate connections are tied to the same stage's source/drain (not to "the second node of the other branch charge pump," element (G)), and the pre-charge path is implemented via a diode-connected pull-up/control-device mechanism rather than the claim-1 pre-charge transistor coupling. No anticipation of claim 1. Strong §103 material, especially combined with the Tier-1 reference.
• Claims it could be argued against: none as a standalone §102 anticipation; §103 against claim 1 and (for the negative/N-channel case) claims 2 and 5.

Tier 3 — Relevant background references

US 5,767,733 A (Integrated Device Technology)

• Full citation: US 5,767,733 A, "Biasing circuit for reducing body effect in a bi-directional field effect transistor," Integrated Device Technology, Inc.; filed 1996-09-20, granted 1998-06-16. [metadata only — full text not retrieved this session]
• Why relevant: Its title directly addresses "reducing body effect" in a field-effect transistor via a biasing circuit, and it is one of the few cited references whose stated purpose is body-effect mitigation rather than charge pumping per se. It is best treated as general §102(a)/(b)/§103 background teaching the motivation to bias the body to reduce body effect.
• §102 assessment: The claim-1 combination (four-phase, dual-branch, two substrate transistors per branch) is a charge-pump architecture, which this reference does not appear to supply; I therefore cannot support an anticipation mapping. Treat as §103 motivation/background art.
• Confidence: Low on specifics; moderated accordingly.

US 4,935,644 A (Toshiba)

• Full citation: US 4,935,644 A, "Charge pump circuit having a boosted output signal," Kabushiki Kaisha Toshiba (inventor Tsujimoto, Jun-ichi); filed/priority 1987-08-13, granted 1990-06-19. Source: https://patents.google.com/patent/US4935644
• Description (verified): First and second charge pumping circuits, each a cascade of MOS transistors with clocked capacitors; the gates of the second circuit's transistors are connected to the gates of the corresponding first circuit's transistors, so the second circuit's stages are driven from the first circuit's stage nodes. This "cross-driving of one pumping circuit by the other" is conceptually adjacent to claim 1's cross-branch control (element (G)), though the topology (two cascaded diode-connected chains, two clocks) is a Dickson-style rather than a four-phase dual-branch stage.
• §102 assessment: Discloses multi-stage charge pumping with cross-coupled control between two sub-circuits and clocked capacitors, but not the four-phase, per-branch main-pass/pre-charge/two-substrate-transistor structure. No anticipation of claim 1. Background/dependent-claim art only.
• Claims it could be argued against: none for §102; possible §103 background on the "cross-coupled control" idea.

US 6,677,806 B2 (Infineon)

• Full citation: US 6,677,806 B2, "Charge pump for generating high voltages for semiconductor circuits," Infineon Technologies AG; filed/priority 1999-11-09, granted 2004-01-13. [metadata only]
• Relevance: A high-voltage charge pump. It is §102(b) art (>1 yr before priority) but does not, to my knowledge, disclose the dual-branch four-phase substrate-transistor network of claim 1.
• §102 assessment: Background; no anticipation of claim 1.

Tier 4 — General charge-pump background (all [metadata only])

These establish the well-known charge-pump context but, individually, do not approach the claim-1 combination:

Confidence: Moderate that these are non-anticipatory for claim 1, based on their titles, dates, and the general state of the art; low on any finer-grained mapping, since I did not retrieve their full texts in this session. If a definitive §102/§103 chart is needed, these seven should be read in full (they are all pre-2004 and publicly available via USPTO Patent Public Search / Google Patents).

4. Ranking and conclusions

1. Most relevant prior art: US 6,952,129 B2 / US 2005/0151580 A1 (Lin et al., eMemory) — same-assignee four-phase dual-unit pumping circuit with main-pass, pre-charge ("boosting"), and cross-branch-controlled substrate transistors. Closest to claim 1 on (A), (B), (C), (D) and the cross-branch control element of (G). It is the reference an examiner or challenger would lead with under §103.
2. Second tier (body-effect/substrate-bias transistor pairs): US 6,878,981 B2 (Eshel, Tower) and US 6,452,438 B1 (Li, Intel) — each teaches a pair of well-bias/substrate transistors that drive V_SB toward zero to cancel body effect, i.e., the functional core of claim element (F) and the patent's stated advantage, albeit in a single-branch (non-dual) topology.
3. Third tier: US 5,767,733 A (IDT) (body-effect-biasing circuit) and US 4,935,644 A (Toshiba) (cross-driven dual pumping chains) as motivation/background.
4. Fourth tier: the remaining seven references are generic charge-pump art.

Anticipation verdict: On the references cited on the face of US 7,123,077, no single reference anticipates claim 1, and therefore none anticipates dependent claims 2–6 (each of which incorporates all of claim 1). The genuinely distinguishing feature — two substrate transistors per branch, with the gate of the first-node-side substrate transistor tied to the second node and the gate of the other tied to the second node of the other branch charge pump — is not shown in any one of these references. The prior art's real force against this patent is obviousness (§103), chiefly US 6,952,129 in view of US 6,878,981 and/or US 6,452,438.

5. Explicit uncertainties and caveats

• Database access: I could not complete live queries against USPTO Patent Center / Patent Public Search or PACER/CAFC in this session (my tool budget was exhausted mid-run). The authoritative citation list, dates, and claim text above come from the Google Patents mirror of the USPTO record, which matches the record supplied in the prior sections.
• Coverage gap: Full text was retrieved and read for US 4,935,644, US 6,452,438, US 6,878,981, and US 6,952,129/US 2005/0151580. The remaining nine references are analyzed from citation metadata and general knowledge only and are labeled [metadata only]; their descriptions should be verified against full text before being relied on in any legal filing.
• Number disambiguation: Searches for "7123077" continue to surface material for the unrelated U.S. 7,187,307 (communications) and for US 7,920,018 / US 7,777,557 (panasonic/AMT charge-pump litigations). Those are not this patent and are excluded from the §102 analysis above. Note, however, that US 7,777,557 and eMemory's later four-phase patents (e.g., US 2016/006349 A1, US 10,333,396) trace their lineage to this family and cite US 7,123,077 — useful for understanding how eMemory itself characterized the prior art.
• Related-but-not-cited references worth a look: eMemory's own US 6,888,400 B2 ("Charge pump circuit without body effects," priority 2002-08-09) and US 6,914,791 B1 ("High efficiency triple well charge pump circuit") appear in the broader family citation web but are not on this patent's face. They are potentially even closer §102(e) art and should be checked if a validity challenge is contemplated.
• Legal standard reminder: Anticipation requires a single reference disclosing every limitation arranged as in the claim. The mappings above are technical comparisons, not legal conclusions; an invalidity opinion should apply the graham factors and prosecution-history estoppel analysis.

I'll ground the obviousness analysis in the actual cited art before writing. Let me pull the key references.

Obviousness Analysis — U.S. Patent 7,123,077 B2 under 35 U.S.C. § 103

Governing law and date. US 7,123,077 was filed 2004-09-23 (priority 2004-08-03, TW 093123153A) — pre-AIA. So pre-AIA § 103(a) applies, as construed by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), and pre-AIA § 103(c) (common-ownership disqualification of § 102(e)/(f)/(g)-only art) is live. The patent is expired (adjusted expiration 2025-01-23 per the record), so this analysis is retrospective — useful for a past-damages defense, a reexam/validity opinion, or licensing diligence, not for prospective injunction risk.

⚠️ Contradiction flag (required by standing instruction)

The earlier "PTAB challenges" section of this file refers to "6,457,438 and 6,878,981, both Intel single/double-pump 'triple well, no body effect'" — and separately lists the art as "US 6,875,218/6,878,981," repeating that number in its Recommended next steps. US 6,875,218 does not appear anywhere on the face of US 7,123,077. Interpreting identifiers literally, the cited references are:

• US 6,452,438 B1 — Intel (Bo Li), "Triple well no body effect negative charge pump"
• US 6,878,981 B2 — Tower Semiconductor (Noam Eshel), "Triple-well charge pump stage with no threshold voltage back-bias effect"

("6,878,981" is Tower/Eshel, not Intel; the earlier section's attribution of both references to Intel is also incorrect.) Anyone reusing that prior work should strike "US 6,875,218" — it is a phantom.

1. POSITA and claim 1 element breakdown

POSITA: a B.S./M.S.-level analog/IC designer with ~2–4 years in on-chip charge pumps for non-volatile memory, familiar with triple-well CMOS, Dickson/Schenkel pump topologies, four-phase clocked pumps (Umezawa, IEEE JSSC vol. 27, no. 11, pp. 1540–1546, Nov. 1992), and the body-effect/back-bias problem.

Claim 1 decomposes as follows (element letters carried from the summary section):

102-status of the key references (drives usability):

2. The critical problem: the best structural reference is the applicant's own sibling

Lin's US 2005/0151580 A1 (issued as US 6,952,129 B2, eMemory, filed 2004-01-12) discloses, almost element-for-element: a four-phase, dual/mirror pumping-unit stage; NMOS for negative pumping and PMOS for positive pumping; a main pass transistor, a boosting (pre-charge) transistor wired exactly as claim element D; two well/substrate transistors per stage sharing a body node; "special substrate connection to minimize body effects"; and cross-branch control ("the substrate transistor of either pump circuit is controlled by a high voltage signal sent from the other pump circuit"). Its own framing is the same problem statement as '077 ("minimizes the body effect of the main pass transistors").

But its only § 102 date is its 2004-01-12 U.S. filing date — § 102(e) — because publication (2005-07-14) post-dates '077's 2004-09-23 filing, defeating § 102(a)/(b). Being § 102(e)-only art developed by another person (Lin/Hsieh/Lu/Ho vs. Chiu/Chang) and commonly owned by eMemory Technology Inc. at the time the invention was made, it is disqualified as § 103 art by pre-AIA § 103(c):

"Subject matter developed by another person, which qualifies as prior art only under one or more of subsections (e), (f), and (g) of section 102, shall not preclude patentability under this section where the subject matter and the claimed invention were, at the time the invention was made, owned by the same person…"

Practical consequence: a petitioner cannot build the lead § 103 combination on Lin unless it can show (i) no common ownership at invention, or (ii) an independent § 102(a)/(b) basis (e.g., a public use/sale or an earlier printed publication of the same disclosure). Note that Eshel (a different owner) talks about the same Umezawa four-phase pump lineage, so the concept survives even if Lin does not.

3. Grounds of rejection

Ground 1 — Eshel '981 + Intel '438 (+ the admitted FIG. 7 art / Umezawa) for claim 1

Eshel '981 teaches a charge-pump stage comprising exactly four transistors — 301 (main pass, source = input terminal = first node, drain = output terminal = second node), 302 (pre-charge), 303 and 304 (well-bias pair, cross-coupled gates: 303's gate at the output/second node, 304's gate at the input/first node) — plus two capacitors, all in an isolated p-well, with the p-well "always held at the voltage equal to the lower of the source voltage or the drain voltage," producing "source-to-body voltage … always zero" and "no threshold voltage increase due to … back-bias." '981 also expressly contemplates series connection of a plurality of such stages and drives them with overlapping CLK1–CLK4 signals (FIG. 5), claiming the same benefit in EEPROM triple-well processes "without requiring process modifications."

Intel '438 teaches, in the same N-channel negative-pump triple-well context, the express pair of N-type well-biasing devices (claims 1, 5, 12–15) whose source terminals tie to the source/drain of the switching device, whose drain terminals are connected together and to the substrate terminals of the switching device, and whose substrate terminals are themselves coupled to the shared substrate node (claims 4, 14). '438's stated object is identical to '077's: "to eliminate body effect."

Mapping: elements A–C, E–F are met (Eshel = A/C/E, cross-coupled G-first-half; '438 = the express "pair" of bias devices and the shared body/substrate tie of F). What '077 adds over Eshel/'438 is (i) the dual-branch per-stage architecture (B), and (ii) the cross-branch gate drive of the second substrate transistor (G-second-half). Element B can be supplied from the admitted art plus face-of-patent references US 5,644,534 ("plural booster units having outputs connected in common") and US 6,605,984 (ripple reduction) — I have not verified the internal disclosure of either and would not rely on them without reading the specifications.

The claimed arrangement of element F — sources-and-bodies tied to the body, drains to the two nodes — is the precise mirror image of Eshel's arrangement (drains-and-bodies tied to the p-well, sources to the two nodes) and of '438's (drains tied together to the substrate terminals). Because a MOSFET's source and drain are structurally symmetric and the substrate transistors are drawn with identical geometry, a POSITA would recognize the two orientations as electrically equivalent well-clamping circuits ("body ← lower of node 1/node 2"). This is an "obvious to try"/design-choice argument of the kind KSR endorses, and it is reinforced by '077's own specification, which treats source/drain assignments as a labeling convention: "the source terminal and the drain terminal are respectively used as a first node U0 and a second node U1."

Ground 2 — Eshel '981 + US 5,767,733 (Grugett) + the four-phase admitted art

US 5,767,733, cited on the face of '077 itself, is directed to a "Biasing circuit for reducing body effect in a bi-directional field effect transistor" — i.e., the same problem/solution pair (dynamically biasing a bidirectional pass transistor's body) in the same circuit genus. A POSITA designing a four-phase, dual-branch pump reading Eshel + Grugett would arrive at a two-transistor bias network per branch with essentially the claimed connections. This ground has the advantage of avoiding the § 103(c) problem entirely.

Ground 3 — If Lin's § 103(c) disqualification fails: Lin + Eshel (strongest ground)

If a petitioner can show common ownership did not exist at invention, or obtain a non-§ 102(e) basis for the Lin disclosure (e.g., an earlier publication or a public use), the combination Lin '580 + Eshel '981 is very strong:

• Lin supplies: four-phase clocking; dual/mirror pumping units per stage; the main-pass/boosting/substrate transistor set; the exact pre-charge wiring of element D; cross-branch substrate-transistor control (G, second half); NMOS-negative/PMOS-positive teaching for claim 3; and the two charge-storing capacitors per unit.
• Eshel supplies: two well-bias transistors per branch with the shared p-well body node; the cross-coupled gate at the opposite node (G, first half); the "VSB = 0, no back-bias" characterisation that supplies '077's stated result.
• The remaining gap — whether the second substrate transistor is oriented source-body-to-well or drain-body-to-well — is the mirror-image equivalence argument above.

4. Motivation to combine (why a POSITA would do it)

1. Same field, same problem, same solution. All references are on-chip charge pumps for EEPROM/flash. Eshel, '438, Lin and '077 state the identical problem (back-bias raising Vt, reducing per-stage gain and current) and the identical fix (switch the isolated well to the lowest source/drain node). KSR — "a finite number of identified, predictable solutions."
2. Explicit design incentives in the art. '438 explains the incentive to replace P-channel with N-channel devices ("twice the mobility… P type transistor devices typically have a strong body effect, which negatively impacts the mobility"), and '077's own specification gives the same rationale for using N-channel main pass transistors — supplying the motivation to convert the admitted P-channel four-clock pump (FIG. 7) into the N-channel version and to attach the known well-bias network.
3. Process compatibility / no added cost. Eshel: "the triple-well process is typically used to fabricate EEPROM cells… the charge pump stage can be fabricated on the same chip as EEPROM cells, without requiring process modifications."
4. Predictable results. Eshel and '438 both report the exact benefit '077 claims ("no threshold voltage back-bias effect"; "no body effect"). A POSITA would expect the combination to work for the same reason it worked in the references.
5. Design-choice / obvious-to-try. Selecting the orientation of a symmetric transistor's source/drain terminals, and selecting which clock-phase node drives a well-bias gate, are the kinds of "ordinary creativity" choices KSR holds insufficient for patentability.
6. The applicant's own admissions are prior art. FIG. 7 (four-clock, multi-stage pump with main pass + pre-charge + two capacitors per stage) and TW 477977 FIG. 4 (the same scheme with N-channel devices replacing P-channel) are admitted as background. Claim 1's remaining delta therefore reduces to the dual-branch arrangement and the well-bias pair — the two things Eshel/'438/Grugett/'534/'984 address.

5. Dependent claims 2–6

• Claim 2 (negative pump; all transistors N-channel): squarely met/obvious from the cumulative teaching of US 6,452,438 (expressly "a triple well no body effect negative charge pump" using N-channel devices), Eshel '981 (N-channel triple-well negative pump), Lin '580 ("NMOSFETS for negative pumping"), and Umezawa 1992 (negative pump). No independent significance.
• Claim 3 (positive pump; P-channel): Lin '580 expressly teaches the mirror-image PMOS positive pump ("PMOSFETS for positive pumping," claims 15/16); the '077 specification itself admits TW 477977's analogous positive pump. Routine inversion of conductivity type rendering a claim obvious where the reference teaches the negative counterpart. Weakest in a Lin-disqualified posture — a petitioner should lead with the '077 specification's own admission.
• Claims 4/5/6 (body and source of the pre-charge transistor tied together, applied to claims 1 / 2 / 3): the narrowest and most vulnerable-to-attack limitation, but still weak as a nonobviousness anchor. Diode-connected / body-tied pre-charge devices are pervasive: US 6,452,438 claims 18–22 recite a "first diode" implemented as "a second transistor wherein its drain terminal is coupled to its gate terminal" that feeds the gate node of the switching device, and claim 4 ties the bias devices' substrate terminals to the shared substrate node; Eshel's 302 is a gate-charging device whose well/body is the common p-well. Tying the body to the source is the standard, well-known way to force VBS=0 on a device used as a diode-like pre-charge element. Expect the patent owner to argue that the purpose in '077 is opposite (deliberately forward-biasing the parasitic bipolar to pre-charge the gate) — but the claim recites only the connection, not the bipolar-turn-on function, and an intended use that is not claimed cannot impart patentability.

6. Anticipated rebuttals, and how to meet them

7. What I have not verified (do not treat as established)

1. Figure-level contents of US 5,644,534, US 5,717,278, US 6,605,984, US 6,607,806, US 6,037,622 and US 5,767,733. I relied on titles/abstract-level characterizations for element B and Ground 2. Before relying on any of them, read the specifications — especially '534 ("plural booster units having outputs connected in common") as the dual-branch teaching.
2. Whether eMemory's common ownership of US 6,952,129/'580 and US 10/947,677 existed "at the time the invention was made" (assignment for '677 is effective 2004-09-20 per the record; Lin's was recorded 2004-01-12). If both were eMemory-owned when the '077 invention was made, § 103(c) applies.
3. Whether '077's prosecution file contains an Information Disclosure Statement listing Lin '580 — if it was of record during prosecution, that is evidence the examiner considered and did not reject over it (relevant to a § 325(d)-type discretionary argument, and to the weight of a reexam request).
4. Cited-art URLs used: US7123077B2; US6878981B2 (Eshel); US6452438B1 (Li/Intel); US2005/0151580 A1 and US6952129B2 (Lin/eMemory); Umezawa et al., IEEE J. Solid-State Circuits 27(11):1540–1546 (Nov. 1992) (of record as cited in Eshel).