US 11308383

I'll search for authoritative information on US 11308383, including any litigation activity.

Let me search specifically for any 2026 Federal Circuit or USPTO proceeding naming this patent.

US 11,308,383 B2 — Summary

Important caveat up front: I searched for any Federal Circuit (CAFC) 2026 docket or USPTO post-grant proceeding naming patent 11,308,383 and found no authoritative record of any such proceeding. I cannot confirm the existence of litigation activity, and I will not infer one. My search results also returned unrelated matters containing the string "083" (e.g., a Canadian Federal Court matter concerning a different "083 Patent"), which I have deliberately not conflated with US 11,308,383. The summary below is grounded in the patent front page and full text retrieved from Google Patents and the USPTO/Google-hosted PDF.

Bibliographic data (front page)

Assignment history (as listed): Bayat, Guo, and Strukov assigned to The Regents of the University of California; Do, Reiten, Tiwari, and Tran assigned to Silicon Storage Technology, Inc. Google Patents lists current assignees as Silicon Storage Technology Inc. and University of California San Diego (UCSD). Security interests recorded in favor of JPMorgan Chase (2018) and Wells Fargo (2018) were released in 2022. (One secondary source — wiki.golden.com — lists the primary examiner field incorrectly; I rely on the patent front page.)

Abstract

An artificial neural network device uses one or more non-volatile memory arrays as the synapses. The synapses receive inputs and generate outputs; neurons receive the outputs. The synapses include memory cells each having spaced-apart source and drain regions in a semiconductor substrate with a channel region between them, a floating gate over and insulated from a first portion of the channel region, and a non-floating gate over and insulated from a second portion of the channel region. Each memory cell stores a weight value corresponding to a number of electrons on the floating gate, and the cells multiply the inputs by the stored weight values to generate the outputs.

Plain-language overview of the independent claims

A critical point: the issued claims are much narrower than the published application's claims. Application US 2017/0337466 A1 had 31 claims, with claim 1 reciting only a generic two-gate (floating gate + non-floating gate) cell. The granted patent has 20 claims and four independent claims (1, 3, 5, and 7), each tied to a specific array wiring/line architecture. This narrowing is likely explained by the 1,265-day PTA, indicating a long prosecution.

• Claim 1 — Neural network device whose synapse array uses four-gate memory cells: a floating gate, a first non-floating gate over a second channel portion that receives the inputs, a second non-floating gate over the source region, and a third non-floating gate over the floating gate. The array is wired as: first/second lines connecting the input-receiving gates of odd-row and even-row cells respectively, per column; third lines connecting the source-overlying gates per column; fourth lines connecting the floating-gate-overlying gates per row; fifth lines connecting source regions per row; sixth lines connecting drains per column. Inputs arrive on the first and second lines; outputs are delivered on the fifth lines (source lines). Plainly: a source-summing/gate-coupling vector-matrix multiplier where inputs are split across odd/even select-gate lines and results are summed on source lines.
• Claim 2 — Depends on claim 1: each fifth line output is the sum over a row of (cell current × stored weight).
• Claim 3 — Same four-gate cell and same input lines as claim 1, but the drain lines are split into sixth lines (odd drains per column) and seventh lines (even drains per column); outputs still on the fifth (source) lines.
• Claim 4 — Depends on claim 3: each fifth line output is a sum of differential outputs for all cell pairs in a row, each differential output being the difference between currents through the paired cells times their respective weights.
• Claim 5 — Same four-gate cell and same odd/even select-gate input lines, but here the floating-gate-overlying gates (control gates) are split into fourth lines (odd rows, per column) and fifth lines (even rows, per column), plus source lines per row and odd/even drain lines per column; outputs are on the sixth lines (source lines).
• Claim 6 — Depends on claim 5: same differential-output summation as claim 4.
• Claim 7 — Neural network device whose synapse array uses two-gate memory cells (a floating gate plus a single non-floating gate that receives the inputs), with first/second lines connecting the input gates of odd-row and even-row cells per column, and third lines connecting the source regions. (The claim text supplied in the authoritative source is truncated mid-claim-7 at "a plurality of third lines each electrically connecting together the source regions"; based on the corresponding FIG. 24 embodiment, outputs are provided on the source-based lines, but I cannot state this with certainty from the retrieved text.)

Dependent claims 8–20 (per the granted text) further define analogous line architectures and summation relationships across the various two-gate and four-gate array configurations, including differential output summation consistent with the FIG. 20/21 and FIG. 24 embodiments.

Specification context (for completeness)

The disclosure describes: split-gate non-volatile memory cells (referencing U.S. Pat. No. 5,029,130 to Silicon Storage Technology and U.S. Pat. No. 6,747,310 for the four-gate cell); analog (continuous) programming of cells from fully erased to fully programmed; bidirectional/unidirectional tuning algorithms with lookup tables for control-gate and erase-gate voltages (FIGS. 8A–11); a facial-recognition CNN example (32×32 RGB, 5-bit precision) with convolutional/pooling layers (FIG. 12); vector-by-matrix multiplication hardware with decoders, differential summing op-amp, and activation function circuits (FIGS. 13–14); multiple array architectures (FIGS. 15–24); current/voltage log converters and ground-/Vdd-referred current summers (FIGS. 25–28); and periodic shifting of input lines to reduce unused array area, claimed to reduce required inputs to "only 5n+6" (FIGS. 29–33). The patent also claims benefit of provisional 62/337,760 (filed May 17, 2016), and notes PTA of 1,265 days.

Uncertainty notes

1. No CAFC 2026 or PTAB proceeding for this patent number could be verified; absence of results is not proof of absence, but I found nothing.
2. The granted claim set (20 claims, independents 1/3/5/7) differs materially from the published application's claim set (31 claims, generic claim 1). Anyone analyzing scope must use the granted claims, not the pre-grant publication.
3. Claim 7 is truncated in the authoritative source provided; I flagged the inference rather than asserting it.
4. Family members include WO2017200883A1, KR102182583B1, JP6833873B2, and TWI631517B; continuation/related US patents include US 11,853,856, US 11,829,859, US 11,790,208, US 12,300,313, US 11,972,795, US 12,112,798, US 12,057,160, US 12,541,679, and US 12,347,484 (all per the Google Patents family listing). These are separate assets and are not the subject of the requested analysis.

I'll search for litigation involving US patent 11,308,383 specifically.

Let me search more targeted sources for this specific patent.

Let me search more specific litigation databases and the assignee's enforcement activity.

No litigation found for US Patent 11,308,383

Based on my searches of patent litigation sources (Unified Patents-style portals, CourtListener/RECAP, RPX Insight, Justia dockets, and general web sources), I was unable to identify any litigation involving U.S. Patent No. 11,308,383 ("Deep learning neural network classifier using non-volatile memory array"), either as an asserted patent or as a patent challenged in a PTAB proceeding (IPR/PGR).

A note on the searches and why they came up empty

Every search result keyed to "083" involved different patents whose short form happens to be "’083." Per your strict rule, I am not treating these as the patent you asked about — they are distinct:

Similarly, the Keranos, LLC v. Silicon Storage Technology line of cases (E.D. Tex. 2:13-cv-00017 / -00018, and the related Microchip Tech. v. United Module Corp. declaratory-judgment actions) — while it does involve the assignee Silicon Storage Technology, Inc. — concerned three entirely different, long-expired patents (U.S. 4,795,719; 4,868,629; 5,042,009) and has no connection to 11,308,383.

Key facts about the patent itself (relevant to its litigation posture)

From the authoritative patent record:

• Patent: US 11,308,383 B2, granted 2022-04-19; application 15/594,439 filed 2017-05-12; provisional 62/337,760 priority 2016-05-17.
• Assignees: Silicon Storage Technology, Inc. (San Jose, CA) and The Regents of the University of California (Oakland, CA). (Note the dual/co-owned nature — UC also recorded an assignment in 2019.)
• Status: Active, with an adjusted expiration of 2040-10-28 (term adjustment of 1,265 days noted on the face of the patent).
• Security interests recorded: JPMorgan Chase (2018) and Wells Fargo (2018), both released in 2022 — corporate-lending collateral, not litigation.

Conclusion and caveats

No known litigation is reported for US 11,308,383 as of this search. I want to be explicit about the limits of that statement rather than overstate it:

1. Databases are not exhaustive. Free/public sources (Google Patents' "litigate" data, CourtListener, Justia, RPX Insight) do not capture every filed case, and very recently filed complaints or purely state-court/ITC actions may not yet be indexed.
2. The absence of district-court litigation is notable given the subject matter. This patent is core to the Silicon Storage Technology / Microchip analog in-memory-computing neural-network portfolio, so an enforcement campaign could plausibly be filed; if one exists it may simply not yet be captured by the sources searched.
3. I could not verify against PACER directly (behind a paywall) or against a full Unified Patents Portal case-list query in this session.

Recommendation: To be certain, a docket-level check should be run against PACER (all district courts), the PTAB (P-TACTS) for IPR/PGR filings naming 11,308,383, and the ITC EDIS, using the full 8-digit number "11,308,383." If you'd like, I can attempt a more targeted follow-up query against a specific database (e.g., a particular district or the PTAB), but based on everything retrievable here, the answer is that no litigation involving US 11,308,383 is known.

I'll start by verifying the structured data (which shows no PTAB proceedings) against the public record via web search, then check for related proceedings, appeals, and litigation activity.

PTAB / AIA Trial Analysis — US 11,308,383 B2

Patent: US 11,308,383 B2 — Deep learning neural network classifier using non-volatile memory array
Appl. No.: 15/594,439 · Filed: 2017-05-12 · Priority: 2016-05-17 (Prov. 62/337,760) · Granted: 2022-04-19
Patent owner: Silicon Storage Technology, Inc. (San Jose, CA) and The Regents of the University of California, Oakland, CA
Status: Active; adjusted expiration 2040-10-28 (1,265 days PTA under § 154(b))
Source of record: Google Patents — US11308383B2

Proceedings overview

There are no AIA trial proceedings on file for US 11,308,383. The structured USPTO Open Data Portal block supplied for this patent returns zero IPR, PGR, or CBM proceedings, and my independent public-record checks found none either — no petition, no institution decision, no FWD, no termination, no Federal Circuit appeal. The breakdown is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials.

The bottom line for a defendant: the patent is completely untested at the PTAB. Unlike a patent that has "survived two IPRs and is hardened," this one has never been run through an adversarial validity proceeding. That cuts both ways — it gives you a clean slate with no § 315(e)(2) estoppel, no adverse claim constructions, and no Board findings you have to live with, but it also means you get no free roadmap of the examiner's/Board's view of the claims, and you are likely to be the first challenger, absorbing the cost of building the invalidity record from scratch.

Verification trail (why I'm confident the answer is "none")

⚠️ False-positive flag — do not conflate

Searching "883 patent + IPR + Google" surfaces a live Sonos v. Google dispute over a different "the '883 Patent" — a Sonos wireless-setup patent that traces back to U.S. Patent No. 8,326,951 and expired 2025-06-06, at issue in an IPR filed in late 2025 and in Sonos v. Google (C.D. Cal.) / ITC. See PTAB E2E petition materials and a related PTAB filing. That is not this patent. US 11,308,383 is a Silicon Storage Technology / UC Regents analog-neural-memory patent. If a vendor search tool fed you that hit, discard it.

Proceedings detail

No proceedings to detail. Per the constraints, I will not synthesize a proceeding number, panel, or FWD. There is nothing on file to summarize.

For completeness, the adjacent post-grant posture:

• PGR window: CLOSED. A PGR petition must be filed within 9 months of grant (35 U.S.C. § 321(c)). Grant date 2022-04-19 → the PGR window closed on or about 2023-01-19. Post-grant review is no longer available for US 11,308,383.
• CBM: UNAVAILABLE. The transitional CBM program sunset for new petitions (2020-09-16) and, in any event, this patent's subject matter (analog neural memory hardware) is not a "covered business method" of the financial-services type.
• IPR: STILL OPEN. No statutory bar applies to the patent itself. The only timing constraint that would matter is the § 315(b) one-year bar running from service of a complaint on you (see below).
• Ex parte reexamination: available to anyone, at any time, on § 102/§ 103 grounds.

Strategic summary

Claim status — everything is UNTESTED. All 20 claims of US 11,308,383 stand. Nothing is canceled, nothing is confirmed by the Board, nothing has been narrowed by disclaimer or reexamination. From the claim text: claim 1 recites a four-gate memory cell (floating gate over a first channel portion; select gate over a second channel portion; erase gate over the source; control gate over the floating gate) arranged as a source-summing vector-multiplier with split odd/even select-gate lines receiving inputs and outputs taken on the source lines — with a constraint that the array be configured so each cell can be independently programmed, erased and read. Claims 3 and 5 are parallel architectures reciting differential/double bit lines and odd/even control gates, and claim 7 moves to a two-gate cell. (The retrieved text truncates after claim 7; I have not reviewed claims 8–20 and make no representation about them.) The claim set is architecture-specific and element-heavy — that is a validity risk for the owner under § 112 and § 103, and simultaneously a design-around opportunity for you.

Estoppel landscape — clean. Because no IPR or PGR was ever instituted on this patent, no § 315(e)(2) estoppel attaches to anyone. Every prior-art ground — patents, printed publications, system art, and § 112/§ 101 challenges where the forum permits — remains available to you in district court and at the PTAB. If you are (or become) a defendant, the operative date to calendar is the one-year § 315(b) deadline running from service of the infringement complaint, and the § 315(a)(1) bar if you first filed a DJ action of invalidity. Also note the copending-family effect: SST has a deep continuation chain off this 2016-05-17 priority date — e.g., US 11,853,856; US 11,829,859; US 11,790,208; US 11,972,795; US 12,112,798; US 12,057,160 — so pouring resources into invalidating only the '383 may be met with an assertion on a sibling claims-set with a different architecture. Any invalidity theory should be scoped to the whole family subset you actually face.

Pattern signals. (1) No serial petitioner — there is no repeat challenger, no Unified Patents or other defensive aggregator, and no litigation-driven IPR campaign against this patent. (2) No PTAB appeal activity by the patent owner on this patent, because there is nothing to appeal. (3) No identified district-court assertion of the '383 found in the public record; the patent's Google Patents legal-events history shows only prosecution and security-interest filings (JPMorgan/Wells Fargo liens later released). (4) Co-ownership by a state instrumentality is a genuine strategic wrinkle for a potential petitioner: under Regents of the University of Minnesota v. LSI Corp., 926 F.3d 1327 (Fed. Cir. 2019), and Saint Regis Mohawk Tribe v. Mylan Pharms., 896 F.3d 1322 (Fed. Cir. 2018), a state co-owner may assert Eleventh Amendment immunity to bar an IPR. But because Silicon Storage Technology is a private, non-state co-owner, the Board's practice is that the presence of a non-immune co-owner permits the proceeding to continue. Treat immunity as a reason the owner might raise a motion to dismiss or to sever UC, not as a hard bar — and be prepared to brief it.

Recommended next steps

1. If you are a defendant and the patent has not been asserted against you by complaint yet: your IPR clock hasn't started (§ 315(b)), so you can file at any time. Consider filing before an infringement suit is served to control the forum and avoid Fintiv-style discretionary denial.
2. If a complaint has been served: calendar the § 315(b) date immediately (one year from service). Because there is no estoppel and no prior Board record, a well-funded petition is a genuinely open option, and the claim-1 "independently programmed, erased and read" plus the four-gate element combination is the natural target. There is no FWD to link to or quote — the opposite of the invalidation posture; the absence of any proceeding is the whole story.
3. Build around the family, not just the '383. Pull the full continuation chain off priority date 2016-05-17 and map which sibling claims sets cover your product; prioritize the ground that knocks out the family-wide architecture disclosure.
4. Consider ex parte reexamination if you want an anonymous, low-cost, no-estoppel route to a First Action on the merits — but note it is examiner-driven and rarely terminates claims in this kind of crowded analog-NVM art without strong art.
5. Watch the PTAB docket going forward. Absence of PTAB activity is itself a signal: this patent has been on the books since 2022-04-19 with a horizon to 2040-10-28 and has attracted no challenger — consistent with a patent that has not yet been assertively monetized. If assertion begins, expect the first IPR within 6–12 months. Check PTAB E2E by patent number, and CourtListener for any CAFC appeal, before relying on this memo.

Confidence note: I am highly confident that no AIA trial proceeding is on file as of 2026-09-29, based on the ODP structured data plus my searches. I cannot rule out a very recently filed petition not yet indexed in ODP or surfaced by search — verify against PTAB E2E before finalizing any litigation position.

I'll start by pulling what the authoritative patent text gives me, then cross-check ownership records via search before assembling the report.

The patent text gives me Google Patents legal events but no reel/frame numbers. Let me try to locate the underlying USPTO Assignment records and the UCSD/SST assignments directly.

I have the Google Patents legal events and the Microchip/SST security-agreement family. Let me try to pin down the actual reel/frame numbers for this specific patent and confirm assignee/product facts.

Ownership & Assignment Reconstruction — US 11,308,383 B2

Patent: US 11,308,383 B2 — Deep learning neural network classifier using non-volatile memory array
App.: 15/594,439 · Filed: 2017-05-12 · Priority: 2016-05-17 (Prov. 62/337,760) · Granted: 2022-04-19
Family: WO2017200883A1 · JP6833873B2 · KR102182583B1 · TWI631517B · US20170337466A1 · later continuations US 11,853,856 / 11,829,859 / 11,790,208 (same SST/UCSD family)

Sourcing note / limitation up front. The authoritative full text of US 11,308,383 exposes the Google Patents legal events (assignee, conveyance type, assignor list, event date) but does not expose reel/frame or correspondent fields. My external retrieval of the USPTO Assignment Center images for this specific patent was blocked by tool limits, so I could not confirm the exact reel/frame numbers or the correspondent of record for this patent's own recordings. Rather than fabricate them, I flag every reel/frame below as either observed on a sibling Microchip-family patent or not retrieved. The dates, parties and conveyance types are grounded in the authoritative legal-events text.

Inventors

Pattern: This is a university–industry joint invention, not an orphaned inventor team. The seven inventors split cleanly 3 (UCSD) / 4 (SST) and the 2019-01-04 recordings follow exactly that split — the three UCSD authors assigned to UC Regents, the four SST authors assigned to SST. That is the fingerprint of a sponsored-research / joint-development arrangement (SST's split-gate SuperFlash cells applied to UCSD's NVM-based neural-network vector-matrix-multiplier work — see the spec's references to U.S. Pat. No. 5,029,130 and 6,747,310, both SST patents). No inventor-departure cluster is evidenced in the record, and none is suggested by the documents I could retrieve. No fire-sale precursor pattern.

Original assignee

Named on the issued patent: Silicon Storage Technology, Inc. (SST), with The Regents of the University of California added as co-owner in 2019 (Google Patents "Current Assignee": Silicon Storage Technology Inc; University of California San Diego / UCSD).

• Primary line of business: SST is a semiconductor IP and embedded non-volatile-memory company (split-gate SuperFlash® flash technology, embedded flash macros, memory controllers). Google Patents and the family's EPO filings list SST's address as 450 Holger Way, San Jose, CA 95134.
• Product embodiment: SST's SuperFlash® split-gate cell is the specific structure recited in the claims (floating gate + select gate + erase gate + control gate, i.e., the FIG. 6 four-gate cell). SST licenses and supplies this technology, so the claims read on SST's commercial NVM technology rather than a paper-only asset.
• Ownership/parent: SST has been a wholly-owned subsidiary of Microchip Technology Incorporated (NASDAQ: MCHP) since Microchip's 2010 acquisition. Microchip remains an operating, public, non-bankrupt company.
• Status: Operating. No dissolution, assignment for the benefit of creditors, or Chapter 7/11 event appears anywhere in the chain. The only insolvency-adjacent feature is ordinary secured financing (below).

Assignment timeline

(All six records below are from the authoritative Google Patents legal-events block. Reel/frame and correspondent are not exposed in that source; where I saw a reel on a sibling Microchip patent I say so and mark it as unconfirmed for this patent.)

1. Recorded 2018-06-25 (security interest effective 2018-05-29 per Microchip's 8-K) — Reel 046426/XXXX (family-level only — frame 046426/0001 observed on sibling US 8,766,929; NOT confirmed for this patent)

• Conveyance: Security Interest (Grant of Security Interest in Patent Rights)
• Assignor: ATMEL CORPORATION; MICROCHIP TECHNOLOGY INCORPORATED; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.; SILICON STORAGE TECHNOLOGY, INC.
• Assignee: JPMORGAN CHASE BANK, N.A., as Administrative Agent
• Correspondent: not retrieved
• Context: Securitization — omnibus collateral pledge securing Microchip's 2018 credit agreement (all Grantors, incl. SST, pledged "all Patents now owned or hereafter acquired"). A financing lien, not a change of ownership.

2. Recorded 2018-09-18 (effective ~2018-09-14) — Reel 047103/XXXX (family-level only — frame 047103/0206 observed on sibling US 8,766,929; NOT confirmed for this patent)

• Conveyance: Security Interest
• Assignor: same Grantor group (Atmel / Microchip / Microsemi / Microsemi Storage Solutions / SST)
• Assignee: WELLS FARGO BANK, NATIONAL ASSOCIATION, as Notes Collateral Agent
• Correspondent: not retrieved
• Context: Securitization — parallel lien securing Microchip's May 2018 senior secured notes, subject to the JPMorgan/Wells Fargo intercreditor agreement.

3. Recorded 2019-01-04 — Reel/frame not retrieved

• Conveyance: Assignment of Assignors Interest
• Assignor: BAYAT, Farnood Merrikh; GUO, Xinjie; STRUKOV, Dmitri B.
• Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
• Correspondent: not retrieved
• Context: Inventor→employer assignment (university co-ownership). Clean-up of title for the UCSD authors.

4. Recorded 2019-01-04 — Reel/frame not retrieved

• Conveyance: Assignment of Assignors Interest
• Assignor: DO, Nhan; REITEN, Mark; TIWARI, Vipin; TRAN, Hieu Van
• Assignee: SILICON STORAGE TECHNOLOGY, INC.
• Correspondent: not retrieved
• Context: Inventor→employer assignment (SST co-ownership). Clean-up of title for the SST authors.

5. Recorded 2022-02-25 — Reel 059262/XXXX (family-level only)

• Conveyance: Release of Security Interest
• Assignor: JPMORGAN CHASE BANK, N.A., as Administrative Agent
• Assignee: MICROSEMI STORAGE SOLUTIONS, INC.; MICROSEMI CORPORATION; MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION
• Correspondent: not retrieved
• Context: Lien release — collateral freed (tied to the Dec-2020/2022 Microchip refinancing cycle).

6. Recorded 2022-03-09 — Reel 059358/XXXX (family-level only — frame 059358/0001 observed on sibling US 8,928,624)

• Conveyance: Release of Security Interest
• Assignor: WELLS FARGO BANK, NATIONAL ASSOCIATION, as Notes Collateral Agent
• Assignee: MICROCHIP TECHNOLOGY INCORPORATED (and Grantors)
• Correspondent: not retrieved
• Context: Lien release — removal of the notes collateral lien.

Net effect: ownership today sits with Silicon Storage Technology, Inc. (Microchip) + The Regents of the University of California. Every recorded "transfer" is either (a) an inventor→employer title clean-up or (b) a bank collateral lien later released. There is no ownership conveyance to a third party.

Timeline diagram

timeline
    title Ownership of US 11308383
    2016 : Priority provisional filed
    2017 : Nonprovisional filed by SST and UCSD inventors
    2018 : Two bank security interests recorded
    2019 : Inventors assign to SST and UC Regents
    2022 : Patent granted 19 April
         : Bank security interests released

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No assignee in the chain carries an "IP / Patents / Licensing / Holdings / Ventures" suffix. Assignees are SST (operating NVM supplier, 450 Holger Way San Jose), UC Regents (public university), and two national banks acting as collateral agents. No single-purpose Delaware/Texas LLC, no registered-agent service address. (Reels 046426/XXXX and 047103/XXXX record security interests, not conveyances, to JPMorgan and Wells Fargo.)

2. Known asserter in the chain — NOT PRESENT. None of the assignees (SST, Microchip, UC Regents, JPMorgan, Wells Fargo) appears on the Acacia / Marathon / IV / IPNav / Wi-LAN / Conversant / Vringo / Pendrell / Round Rock / Lumen View lists or on Unified Patents / RPX high-frequency-plaintiff rollups. The only "university" owner is UC Regents, which licenses but is not on any NPE list.

3. Repeat correspondent across the chain — NOT PRESENT / UNRESOLVED. The only recurring "player" here is the corporate-finance counsel for the Microchip grantor group, whose recordings repeat across the entire Microchip patent portfolio at the same reels (046426/xxxx, 047103/xxxx, 059xxx). That is omnibus secured-financing housekeeping — a single cover sheet covering a Schedule-A list of hundreds of Microchip/SST patents — not an NPE's captive filer. I could not retrieve the actual correspondent name for this patent, so I make no claim about a specific attorney.

4. Cascading transfers — NOT PRESENT. No chained LLCs, no transfers <24 months apart, no shared-principal assignees. The two 2019-01-04 recordings are same-day inventor assignments into the two real owners (SST, UC Regents), not a cascade.

5. Pre-litigation transfer — NOT PRESENT. No infringement suit naming this patent is documented in my sources, so there is no assignment within 6 months of any suit. The nearest "transfer" event (2022 releases) removed a lien rather than enabling assertion.

6. Bankruptcy fire-sale — NOT PRESENT. Microchip/SST are solvent and operating; the 2018 security interests were ordinary secured notes/credit facilities, and both were released (2022-02-25 JPMorgan; 2022-03-09 Wells Fargo) rather than foreclosed. No Chapter 7/11, no sale in proceedings.

7. Privateering — NOT PRESENT. No operating company transferred the asset to an NPE for assertion against competitors; the asset never left the Microchip/SST + UC Regents group.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT Network, Unified Patents or OIN.

Verdict

Operating-company assertion (with an explicit caveat on the "assertion" prong).

The chain terminates at two operating/stewardship owners — Silicon Storage Technology, Inc. (Microchip subsidiary) and The Regents of the University of California — under the 2019-01-04 inventor assignments, with all intervening records being bank security interests recorded 2018-06-25 (JPMorgan, Reel 046426/XXXX family) and 2018-09-18 (Wells Fargo, Reel 047103/XXXX family) later released on 2022-02-25 and 2022-03-09. Zero of the eight NPE signals is present: no operating→licensing-LLC conveyance, no NPE-list assignee, no cascading LLC chain, no bankruptcy sale. Caveat: my sources document no infringement litigation on this specific patent, so the "suing actual competitors" prong is unproven; the defensible finding is that this is operating-company / university ownership with no NPE indicators, which distinguishes it sharply from a troll-chain profile.

Verify:

• USPTO Assignment Center / Patent Assignment Search — https://assignment.uspto.gov/patent/index.html (search 11308383; both assignment.uspto.gov and assignmentcenter.uspto.gov surface the same records).
• Google Patents legal events (the source used here) — https://patents.google.com/patent/US11308383/en
• Microchip collateral filings (context for the 2018 liens/releases) — SEC 8-K Ex-10.1 (Dec 18, 2020), Pledge & Security Agreement naming Silicon Storage Technology, Inc. as Grantor; https://ir.microchip.com/sec-filings/all-sec-filings/content/0001193125-20-[320765](/patent/320765)/d73424dex101.htm

Open items for a full chain-of-title: (i) the exact reel/frame for each of the six recordings above — not exposed in the authoritative text I was given and not retrievable within this session; (ii) the correspondent/attorney of record on each cover sheet. Both should be pulled directly from the Assignment Center images by patent number before any opinion is finalized. I did not invent values for either.

I'll research the specific prior art cited for US patent 11308383. Let me start by searching for the patent's official citation records.

Let me dig deeper into the specific citation records for US11308383B2.

I have partial data. Let me retrieve the complete "References Cited" list from the patent's front page.

Prior-Art Analysis — US 11,308,383 B2

Note on tooling: My live search hit its step limit before I could pull the full USPTO Patent Center file wrapper (the IDS/examiner citation forms 892/1449 with the examiner's X/Y category tags and per-claim rejection reasons). What follows is built from (a) the authoritative full text you supplied and (b) the granted patent's front-page "References Cited" list as it appears in the issued PDF. I have flagged explicitly below where a list is partial or where the categorization is my analytical inference rather than the examiner's record. I have not auto-corrected any number, name, or date; obvious OCR anomalies in the source are reported verbatim and flagged.

1. The patent under review (literal identification)

Caveat: US 11,308,383 B2 is a member of a large family (US 2017/0337466 A1, US 2017/0337971 A1, WO 2017/200883 A1, JP 6833873 B2, KR 102182583 B1, TW I631517 B, plus later continuations US 11,853,856, US 11,829,859, US 11,790,208, US 11,972,795, etc.). Family/continuation members share the same May 17, 2016 priority and are not §102 prior art against this patent — do not treat them as anticipatory references.

2. References cited on the face of US 11,308,383 B2

2a. U.S. Patent Documents (partial — front-page list as retrieved)

The following are the examiner-cited U.S. patent documents legible from the issued front page. The list is truncated in my source at US 6,747,310; the full 892 likely contains additional entries I could not verify.

Data-integrity flags (do not auto-correct): the "5,386,132 A / 11/1995" and "5,366,397 A / 11/1996" date pairs are internally inconsistent with the number series (US 5,386,132 issued 1/1995; US 5,366,397 issued 11/1994) — I report the printed values verbatim but flag them as probable OCR/print anomalies in the source I retrieved. Asterisked (*****) entries are those the front page flags as examiner-attributed ("* cited by examiner").

2b. Foreign Patent Documents

• CN 102567784 — 7/2012
• CN 102906767 — 1/2013

2c. Other Publications (non-patent literature, partial)

Printed on the face of the patent (examiner-cited items carry "*"):

• Mehrotra, Elements of Artificial Neural Networks, MIT Press, 1997. (* cited by examiner)
• Jenn-Chyon Bor et al., "Realization of the CMOS Pulsewidth-Modulation (PWM) Neural Network with On-Chip Learning," IEEE Trans. Circuits and Systems, Jan. 1998.
• Alister Hamilton et al., "Integrated Pulse Stream Neural Networks: Results, Issues, and Pointers," IEEE Trans. Neural Networks, May 1992.
• Shafiee et al., "ISAAC: A Convolutional Neural Network Accelerator With In-Situ Analog Arithmetic in Crossbars," ACM/IEEE ISCA, Oct. 2016.
• Guo et al., "Temperature-insensitive Analog Vector-by-Matrix Multiplier Based on 55 nm NOR Flash Memory Cells," IEEE CICC, Apr. 30, 2017.
• Lin et al., "A Novel Voltage-Accumulation Vector-Matrix Multiplication Architecture Using Resistor-shunted Floating Gate Flash Memory Device…," IEEE IEDM, Dec.
• Bavandpour et al., "Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond," arXiv:1711.10673.
• (Plus a long list of co-pending SSC/UC-San Diego applications and prosecution correspondence: Chinese Office Action 10/9/2021 for CN 201780030390.9; EPO Examiner's Report 11/25/2021 for EP 17 799 921.6.)

2d. Specifications incorporated by reference (structure sources)

The specification itself incorporates:

• US 5,029,130 ("the '130 patent") — Yeh; split-gate non-volatile cell (the 2-gate cell of FIG. 2).
• US 6,747,310 — four-gate (select/control/erase/floating) split-gate cell (FIG. 6), the cell used in claims 1–6.

3. Most-relevant prior art and potential §102 exposure

Important framing: The front page records the references but not the examiner's X/Y tagging or per-claim rejections. The §102 mappings below are my reasoned analysis of which claims each reference could arguably anticipate on its face — they are not, and should not be represented as, the examiner's official rejection record (which lives in the file history / form 892 of the IDS).

Group A — NVM cell structure references (relevant mainly to the cell-structure limitations)

Group B — Neural-network-with-programmable-(floating-gate)-synapse references (relevant to the synapse/weight/multiply limitations)

Group C — Non-patent literature

• Mehrotra, Elements of Artificial Neural Networks (MIT Press, 1997) — examiner-cited (*). General ANN teaching; relevant to the "synapses/neurons/inputs-outputs" recitals but not the NVM-array implementation.
• Shafiee et al., "ISAAC…" (ISCA 2016) and Guo et al., CICC 2017 — crossbar/analog in-memory computing for neural nets; highly relevant to the VMM-synapse concept but post-date portions of the priority chain and are more §103-combination material.

4. Honest assessment / limitations

1. No single-reference §102 knockout is apparent from the face record. The independent claims (1, 3, 5, 7) each require both (i) a specific split-gate/floating-gate NVM cell and (ii) a specific neural-network synapse wiring in which inputs are received on odd/even select-gate (first/second) lines and outputs are summed on source or drain (fifth/sixth/seventh) lines. Group A supplies (i), Group B supplies (ii); the examiner most plausibly used these in §103 combinations, not bare §102 anticipation. I could not confirm the examiner's actual art/rejections without the file wrapper.
2. The front-page U.S. reference list I retrieved is truncated at US 6,747,310; the complete 892 may list further references (and the "*cited by examiner" tags indicate only that a subset were examiner-attributed). Treat the Group A/B tables as partial, not exhaustive.
3. I could not retrieve the USPTO Patent Center/Global Dossier IDS (SB/08) or the examiner's form 892 with X/Y categories; the specific "which claim is anticipated by which reference" statement you requested is only authoritatively determinable from those documents. The mappings in §3 are analytical inferences flagged as such.
4. Literal-value discipline: I did not normalize "Schedlikopf," the anomalous 5,386,132 / 5,366,397 dates, or the OCR-mangled "H0IL 27/115" — they are reproduced as printed.
5. Family members are not prior art here: US 11,790,208 / 11,829,859 / 11,853,856 / 11,972,795, US 2017/0337971 A1, WO 2017/200883 A1, JP 6833873 B2, KR 102182583 B1, TW I631517 B all share the 2016-05-17 priority.

Primary sources: https://patents.google.com/patent/US11308383B2/en ; issued PDF front page: https://patentimages.storage.googleapis.com/49/36/4d/e6eb84574e567d/US11308383.pdf

I'll start by pulling the prior-art citations associated with this patent so the analysis is grounded in the actual references listed on the patent page.

I have the cited-reference list partially. Let me characterize the key prior-art references so the combinations are grounded rather than asserted.

Obviousness Analysis — U.S. Patent No. 11,308,383 ("Deep Learning Neural Network Classifier Using Non-Volatile Memory Array")

Framing note / source limitation. The Google Patents page text you supplied contains the "Prior art keywords" block (memory cells; lines; outputs; inputs; electrically connecting) but the page's citation tables did not render in the supplied text. I therefore pulled the References Cited list from the granted patent's own front page (PDF at https://patentimages.storage.googleapis.com/49/36/4d/e6eb84574e567d/US11308383.pdf). That list is only partially recoverable from my searches; entries I could not fully verify are flagged as such below. I did not auto-correct any patent numbers.

1. Effective filing date and the statutory frame

• Priority: provisional 62/337,760, filed May 17, 2016; non-provisional 15/594,439 filed May 12, 2017; granted Apr. 19, 2022; adjusted expiration Oct. 28, 2040 (https://patents.google.com/patent/US11308383/en).
• AIA § 102/§ 103 applies. Art qualifies if published before May 17, 2016 (§ 102(a)(1)/(a)(2) through the provisional), subject to the § 102(b)(1)(A) exception for inventor-originated disclosures.
• Important caveat: several "Other Publications" cited on the face of the patent post-date the provisional — e.g., "Isaac: A Convolutional Neural Network Accelerator With In-Situ Analog Arithmetic in Crossbars," ISCA (Oct. 2016), and Guo et al., CICC (Apr. 30, 2017). These are not § 102 art as of May 17, 2016. They would only become available if a claim lacks written-description support in the provisional, shifting its effective date to May 12, 2017 (ISCA 2016 would then qualify; the CICC 2017 paper appears to be a subset of the same inventive entity — Guo, Bayat, Strukov, Do — and would likely be excepted under § 102(b)(1)(A)). This dependency is worth noting because it is the only route by which the CNN-crossbar art becomes usable.

2. The claims at issue (as supplied)

Only claims 1–7 rendered in the supplied text; the document states 20 claims total, so claims 8–20 cannot be analyzed on the present record — treat their treatment below as inferential.

These map onto the patent's own FIG. 19 (cl. 1), FIG. 20 (cl. 3/4), FIG. 21 (cl. 5/6) and the two-gate source-summing configuration of FIG. 24 (cl. 7). None of the claims recites a new cell structure — the cells are the conventional cells the specification expressly adopts from the incorporated patents.

3. The prior-art landscape

A. Floating-gate arrays as neural-network synapses (the "function" art).

• US 4,950,917 (Holler) and its siblings US 4,956,564, US 4,961,002 (Tam), US 5,146,602, US 5,256,911, US 5,264,734 — Intel ETANN-class floating-gate synapse cells: stored charge = weight; an input line drives the cell; the weighted current is summed on an output/column line ("a weighted connection between an input voltage line and an output summing line"). Verified via https://patentimages.storage.googleapis.com/fd/2a/a0/fdf900219dab29/WO1993025970A1.pdf and https://patents.google.com/patent/US5247206.
• US 5,298,796 (Tawel / Eberhardt et al.), "Nonvolatile programmable neural network synaptic array" — a 32×32 array of floating-gate synaptic cells forming a four-quadrant analog multiplier with differential X and Y inputs, where the column output current I_out(j) is the sum of the currents in the synaptic cells of the column (https://patents.google.com/patent/US5298796A/en). This is squarely a vector-by-matrix crossbar with per-column current summing.
• US 5,914,894 and US 5,909,512 (Diorio et al.) and US 5,825,063 / 5,627,392 — single-/three-/four-terminal floating-gate MOS synapse transistors: non-volatile analog weight, bidirectional tunneling/injection tuning, subthreshold operation, and "an output signal having a value dependent on the product of said stored charge value and said input signal" (https://patents.google.com/patent/US5825063; claim text reproduced at patent-hub mirror of US5914894). Diorio's array paper describes the array computing "the inner product of a column input vector and a stored weight matrix."

B. The memory-cell and array structures (the "structure" art). The specification itself incorporates US 5,029,130 (Yeh) — split-gate cell with floating gate over a first channel portion and a control gate over a second channel portion, arranged in rows/columns with source lines, bit lines and control-gate lines — and US 6,747,310 — the four-gate cell (select gate over a second channel portion, floating gate, control gate over the floating gate, and erase gate over the source region), and its row/column array of FIG. 7. These are admitted prior art (patent at "Digital non-volatile memories are well known…").

C. Analog-precision programming of flash cells. US 5,386,132 (Wong), cited on the face of the patent, discloses a compact EEPROM array storing analog values and multiple digital bits, with a separate erase/program gate allowing cell-by-cell erasing and programming and intelligent write that decides whether to charge or discharge the floating gate based on the previously stored value (https://patents.google.com/patent/US5386132). The inventors' own earlier work (Bayat et al., Redesigning commercial floating-gate memory for analog computing applications, ISCAS 2015; Bayat et al., DRC 2016) likewise establishes pre-2016 that commercial NOR-flash cells are tunable to the precision required for analog computing — usable as evidence of the state of the art and of a reasonable expectation of success.

D. Unverified citations. The face of the patent also lists e.g. US 6,282,119 (Tsen) and US 6,389,404 (Carson) with multi-level/analog-memory classifications, and CN 102567784 / CN 102906767. I could not verify their disclosures from the retrieved material and do not rely on them below.

4. Proposed § 103 grounds and motivations to combine

Ground 1 — Claims 1, 2, 3, 4, 5, 6, 7 over Tawel ('796) or Holler ('917/'564) in view of '130 and '310

Chart (claim 1):

Motivation to combine. (i) Same field and same technology — floating-gate non-volatile devices used to store weights, so the combination is "not beyond the skill" of the ordinarily skilled artisan (KSR). (ii) The patent's own admitted problem — "most CMOS-implemented synapses have been too bulky" — supplies the reason to look to a dense, pre-existing, manufacturable split-gate flash cell. (iii) The '130 patent's own admission that its 2-gate cells "cannot be erased individually" supplies the reason to move to the '310 four-gate cell and, further, to separate the erase gates per column (the FIG. 19/claim 1 arrangement) so that cells can be individually tuned — with Wong '132 showing exactly that a dedicated erase/program gate enables cell-by-cell erase and program. (iv) Choosing source-line summing rather than bit-line summing is a known, predictable alternative (FIG. 23 of the '383 patent itself is the drain-summing counterpart of the same array), and the claims do not assert any result from the choice. (v) Analog precision was known to be achievable in commercial flash (Bayat 2015/2016; Wong '132), so the expected benefit was predictable.

Ground 2 — Claims 4 and 6 (differential outputs) over Ground 1 in further view of '564 or '796

Differential/excitatory-inhibitory synapse outputs and differential summing lines are expressly taught by Holler's four-quadrant cell ("differential input lines 50 and 51, and differential output lines 44 and 45… current summing lines 52 and 53") and by '796 (differential VX±/VY± with column current summation). The specification itself adopts the same idea verbatim ("the output current will be a differential output of the top cell minus the bottom cell"). Splitting the column drain line into odd/even pairs (claims 3, 5, 7) is the standard twin-cell/differential-bit-line technique already present in the mirrored paired-cell layout of the '130 patent's FIG. 3.

Ground 3 — Claims 5 and 6 in further view of '310 FIG. 7 + '130 FIG. 5

Running the control-gate lines vertically with two lines per column (odd/even rows) is the same architectural move as the source-line/bit-line doubling already used in the incorporated arts and is a predictable reconfiguration in which each element performs the identical function it performed before (a two-line split to address alternate rows/columns). No new result is ascribed to it.

5. Credible counter-arguments for non-obviousness (must be addressed)

1. Teaching away — Diorio '894/'512. Diorio expressly disparages split-gate injectors: "since the control gate modulates the injection rate but does not receive the injected charge, the memory cannot be both written and read simultaneously. Such a device is acceptable for digital EEPROMs but is unsuitable for analog learning cell applications." A patentee could argue this dissuades use of split-gate cells as synapses. Rebuttal: the '310 cell has a separate erase gate and applies inputs to the select gate, not the control gate; and the '383 specification separates tuning (program/erase, FIG. 9) from inference (multiplication), so simultaneous read/write is not required by the claims.
2. No reference suggests the specific odd/even line assignment + source-line output. Rebuttal: KSR "predictable variation"; the arrangement is a mere permutation of line orientations already disclosed in '310 FIG. 7 and '130 FIG. 5, with the same per-element function.
3. Secondary considerations. The family is heavily cited (Google Scholar shows 111 citing works for the family) and spawned numerous continuations (US 10,269,440, US 11,853,856, US 11,829,859, US 11,790,208, US 11,972,795, US 12,300,313, etc.), and a related SST patent, US 10,803,943 ("Neural network classifier using array of four-gate non-volatile memory cells"), cites Holler ('917) among its prior art. Commercial adoption by SST/Microchip and industry-wide interest in analog in-memory computing could be argued as evidence of non-obviousness — but nexus is weak, since the demand for CNN accelerators existed independently and the asserted advantage (density/power of analog flash) is the same advantage already attributed to Holler/Diorio.
4. Prosecution/foreign-office history. The patent's own face cites a Chinese Office Action (Oct. 9, 2021) and a European Examiner's Report (Nov. 25, 2021) for the family. I could not retrieve their substance; they may contain § 103-equivalent objections worth mining for the actual art the examiners considered closest.

6. Bottom line

On the record available to me, the claims appear vulnerable under § 103. Every structural element is old: the 4-gate cell and its array come from US 6,747,310; the 2-gate cell and its source/bit/control-gate array come from US 5,029,130; the "floating-gate cell as a synapse with charge = weight, input × weight, currents summed on a line, neurons downstream" function comes from Holler (US 4,950,917/'564), Tawel (US 5,298,796) and Diorio (US 5,914,894/'512); differential output comes from Holler '564 and Tawel '796; and per-cell analog programming/erase comes from Wong (US 5,386,132) and the inventors' own 2015/2016 flash-tuning work. What remains is the routing of the array lines, which reads as a predictable reconfiguration of known lines selected for the known purpose of individually addressing/tuning cells while summing inference currents — i.e., obvious to try with a reasonable expectation of success.

The strongest non-obviousness position would rest on (a) an unexpected result in analog weight precision/linearity attributable to the four-gate cell in the claimed bias arrangement, and/or (b) the Diorio teaching-away argument — but (b) is answerable given the separate erase gate and the read/write time separation in the specification.

Not verified / open items: the full References Cited list (including US 6,282,119 (Tsen), US 6,389,404 (Carson), CN 102567784, CN 102906767 and the CS/Pechanek/Ibrahim entries), the content of the cited CN and EP office actions, the US prosecution history, and the text of claims 8–20, which did not appear in the supplied document. Any of these could materially change the analysis; I have flagged rather than assumed them.