US 6908801

I'll verify this patent's details and check for any 2026 CAFC docket activity.

Let me check specifically for litigation or assignment records involving this exact patent number.

Let me pull the full numbered claim set to identify the independent claims precisely.

US Patent 6,908,801 — Verification Summary

Search scope note: My searches of public patent databases and Federal Circuit materials surfaced no 2026 CAFC docket activity, and no PTAB or district-court litigation, involving U.S. Patent No. 6,908,801. Two 2026 Federal Circuit matters returned by keyword searches involve different patents with superficially similar numbers, and should not be attributed to this patent:

• Innovaport LLC v. Target Corp. (Fed. Cir. 2024-1545, decided Feb. 6, 2026) — involved U.S. Patent No. 9,489,690 (the "'690 patent"), a § 101 eligibility appeal.
• Viasat, Inc. v. Kioxia Corp. (W.D. Tex. Waco; $229M verdict, July 2026; related Fed. Cir. proceedings) — involved U.S. Patent No. 8,615,700.

Neither is U.S. 6,908,801. I state this explicitly to satisfy the "do not auto-correct identifiers" rule: these are distinct patent numbers.

Bibliographic Data (from the authoritative patent text)

Abstract

"A method of manufacturing a semiconductor device comprises forming a gate insulating film on a semiconductor substrate having first and second element regions, forming a mask on the entire surface of the gate insulating film, selectively etching the mask to form an opening for exposing a portion of the gate insulating film, forming a first conductive material film on the entire surface of the mask, patterning the first conductive material film to form a patterned first conductive material film, which is positioned in the first element region, etching away the exposed mask, forming a second conductive material having a work function different from that of the first conductive material film on the gate insulating film, and forming a first gate electrode having the first conductive material film and a second gate electrode made of the second conductive material film."

Plain-Language Overview of the Independent Claims

The patent has three independent claims, each corresponding to one of the three "aspects" recited in the specification. Claim 1 (the "first aspect") and claim 13 (the "third aspect") were confirmed verbatim from retrieved claim text. Based on the retrieved fragmentary claim listing (claims 1, 2, 6/7, 11, 13, 14), the second aspect appears as another independent claim in the 6–12 range, but I could not confirm its exact claim number — I flag that as an uncertainty rather than guess.

Claim 1 — planar (non-damascene) dual-metal-gate flow. Build the gate insulator once on a substrate having two element regions, cover it with a mask (e.g., TEOS) that etches selectively against the gate insulator, open the mask only over region 1, deposit a first conductive film, pattern it so it sits on the exposed gate insulator in region 1 while re-exposing the mask, strip the mask, then deposit a second conductive film of a different work function that directly contacts the gate insulator in region 2, and pattern both films to form (a) a first gate electrode containing the first conductive film in region 1 and (b) a second gate electrode of the second conductive film in region 2.

• Plain language: Make one gate oxide for both transistor types; use a sacrificial mask to keep that oxide clean while you define the first (e.g., TiN) metal only over the NMOS side; remove the mask and blanket-deposit the second metal (e.g., W) so it lands on untouched oxide over the PMOS side; then etch both metals into two gates with different work functions. The mask protects the second region's gate oxide from etchants (the example uses aqueous peroxide for TiN and aqueous HF for TEOS removal).

Second independent claim (number not confirmed) — damascene/replacement-gate flow. Same masking-and-two-metals logic, but performed after gate trenches are opened in an interlayer insulating film: form the gate insulator over the entire surface including the trenches, deposit the mask over the whole surface, open the mask only over the trench in region 1, deposit and pattern the first conductive film into that trench, strip the mask to expose the region-2 trench, deposit the second conductive film of different work function so it contacts the gate insulator in the region-2 trench, then pattern (RIE) or CMP-planarize to bury a first gate electrode in trench 1 and a second gate electrode in trench 2.

Claim 13 — mask-buried-in-trench damascene flow. Open gate trenches in the interlayer insulator, form the gate insulator over the whole surface, and selectively form (bury) the mask inside each gate trench (e.g., blanket deposit then CMP back to the interlayer-insulator level). Remove the mask only from the region-1 trench, deposit a first conductive film over the exposed gate insulator, the interlayer insulator, and the residual mask, pattern it while leaving the residual mask exposed, strip the residual mask to open the region-2 trench, deposit the different-work-function second conductive film to contact the gate insulator in the region-2 trench, and pattern to form the two buried gates.

Dependent-claim flavor (as retrievable)

Claim 2 (depends on 1) and claim 14 (depends on 13) each recite that the gate insulating film is a high-dielectric-constant material; the specification names Ta₂O₅, oxides/oxynitrides of Hf, Al, Zr or Pd, and silicates. Claim 7 (depends on 6) carries the same high-k limitation, reinforcing that claim 6 family belongs to the second aspect.

Technical Point of Novelty (from the specification)

The stated advantage is that the gate insulating film beneath both work-function-differing gate electrodes is deposited in a single film-formation step, unlike the cited prior art (JP Kokai 2002-198441), which requires two separate gate-insulator depositions and exposes the first metal gate to the second high-temperature insulator step. The patent further notes the mask prevents the second region's gate insulator from contacting patterning etchants, and that high-temperature (≥600 °C) gate-insulator formation can precede the metal gates, avoiding thermal degradation of the metals.

Explicit Uncertainties

1. No litigation found. I found no CAFC, PTAB, ITC, or district-court record naming U.S. 6,908,801. Absence of a hit in these searches is not proof that none exists; but I have no authoritative basis to assert any.
2. Second independent claim number unconfirmed. Search excerpts returned only claims 1, 2, 7, 11, 13, and 14; I could not verify the exact number of the second-aspect independent claim or the total claim count (claim 14 exists, so at least 14 claims).
3. Assignee data is as listed on Google Patents/Justia and reflects recorded assignments (Toshiba → Toshiba Memory → K.K. Pangea → Kioxia), not a current legal determination.
4. The patent is expired (antecedently Dec. 18, 2023), so any 2026 enforcement activity would be time-barred, which further supports the absence of live litigation.

I'll research litigation involving US Patent 6908801 across patent litigation databases.

The initial search surfaced only an unrelated patent (6,218,930) and a coincidental Lithuanian registry number. Let me search more specifically.

Let me try more targeted searches, including on the current assignee (K.K. Pangea) and Google Patents' litigation data.

Result: No litigation found for U.S. Patent 6,908,801

I searched for litigation specifically involving U.S. Patent No. 6,908,801 ("Method of manufacturing semiconductor device," Tomohiro Saito, originally assigned to Kabushiki Kaisha Toshiba; application 10/737,964; filed 2003-12-18; granted 2005-06-21; priority 2003-09-19). I found no record of any lawsuit in which this patent was asserted, challenged, or otherwise at issue.

What the searches returned

I ran multiple queries (patent number, "6908801," combined with litigation/lawsuit/infringement terms, assignee names, and jurisdiction terms). Every hit was for a different patent or an unrelated record:

Note in particular that the results I did find involving Toshiba as a defendant (Blue Spike, Encryptawave) concern entirely different patents, not the '801 patent. I found no case in which Toshiba's/Kioxia's '801 patent was asserted.

Context on ownership (from the patent record)

The '801 patent has an active reassignment chain, which is sometimes a useful litigation indicator, but here it does not appear to correspond to any assertion:

• 2004-04-29 — assigned to Kabushiki Kaisha Toshiba (from inventor Saito)
• 2017-08-24 — assigned to Toshiba Memory Corporation
• 2021-01-22 — assigned to Toshiba Memory Corporation (change of name/address)
• 2021-01-22 — K.K. Pangea (merger)
• 2021-01-22 — KIOXIA Corporation (change of name/address, current assignee per Google Patents)

Despite the appearance of K.K. Pangea (an entity that has participated in patent monetization/transactions) in the assignment chain, my searches surfaced no lawsuit in which K.K. Pangea or Kioxia asserted the '801 patent.

Confidence and limitations

• High confidence: No public litigation is surfaced for this specific patent number across the sources my searches reached.
• Caveats: My search access was limited — I could not directly query the Unified Patents litigation portal caselist, PACER, Docket Alarm, or CourtListener's API for this number, and my tool calls were capped before exhaustive follow-up. Litigation can also be filed and remain under-sealed or in state courts not well indexed. Because the patent expired on 2023-12-18 (anticipated expiration; legal status "Expired – Lifetime"), the window for further assertions is effectively closed, making additional litigation unlikely.
• I interpreted the number 6,908,801 literally and report no known litigation rather than substituting any similar number (e.g., 6,218,930, 9,369,081, 6,963,908, 5,999,908), which appeared in the results but are different patents.

Bottom line: Based on my searches as of April 26, 2026, I found no known litigation involving U.S. Patent No. 6,908,801. I cannot confirm plaintiff(s), defendant(s), jurisdiction, case number, filing date, or outcome because no such case was identified.

Proceedings overview

Total AIA trial proceedings on file: 0. Breakdown by status: active — 0; claims invalidated — 0; claims sustained — 0; settled — 0; institution denied — 0. The patent has never been tested at the PTAB, so it is neither "hardened" by surviving an IPR nor narrowed by a cancellation — a defendant gets no free invalidity judgment from the Board's docket, but also faces no adverse PTAB estoppel and no adjudicated claim construction, and the patent's own term has run: Google Patents records its status as Expired – Lifetime, with an anticipated expiration of 2023-12-18, so the live dispute is now purely backward-looking (past damages), not injunctive.

Sources: structured "PTAB proceedings on file" block (USPTO ODP, canonical, empty); US6908801B2 on Google Patents. Web searches for this patent number against PTAB petition/decision text returned no proceeding naming US 6,908,801.

No proceedings to list

There is no IPR/PGR/CBM number I can honestly put under a ### {PROCEEDING_NUMBER} heading for this patent. I am explicitly declining to populate the per-proceeding template (panel, grounds, institution decision, FWD, settlement, appeal) because doing so would require fabricating proceeding numbers and claim-level outcomes, which the structured data and my searches do not support. The absence is the finding.

Disambiguation warning — this is the trap in this docket. A search for "801" patents returns a large volume of different patents, and several of those hits are easy to misread onto this one. None of the following involve US 6,908,801:

• US 7,092,801 (Siemens Mobility v. Westinghouse, IPR2017-00981, FWD holding claims 1, 6, 9, 10, 15, 18, 19 unpatentable; rehearing denied) — train-control patent.
• US 8,046,801 (Comcast v. Rovi Guides, IPR2017-01065) — media guide patent.
• US 6,918,801 (Wilco Marsh Buggies v. Weeks Marine, E.D. La. 2:20-cv-03135; claims 1–5 and 9–15 invalid for lack of novelty under § 102, affirmed Wilco Marsh Buggies & Draglines, Inc. v. Weeks Marine, Inc., No. 2023-2320 (Fed. Cir. Aug. 19, 2025)) — amphibious vehicle patent. Note the one-digit difference from 6,908,801. A blog post about this case (Keyhani LLC, A&O Shearman) and a PACER-derived summary (PatSnap) all concern 6,918,801, not 6,908,801.
• US 10,868,908 / US 11,582,343 and "the '801 Patent" in IPR2025-01381/01382-style papers (CAS v. …) — unrelated communications patent family.

Treating any of those outcomes as belonging to US 6,908,801 would be a substantive error in a defense memo.

Strategic summary

Claim status: all claims UNTESTED. No claim of US 6,908,801 has been canceled, confirmed, or construed in any AIA trial. The patent has a single independent claim family per the abstract/first-aspect claim set (the manufacturing method comprising forming a gate insulating film, forming a mask, forming an opening in the first element region, patterning a first conductive material, removing the mask, forming a second conductive material of different work function, and forming first/second gate electrodes), plus the second- and third-aspect damascene variants. Nothing in the PTAB record narrows them. The only thing constraining the claims today is time: the patent issued 2005-06-21 from an application filed 2003-12-18, claiming priority to 2003-09-19 (JP 2003-327517), and Google Patents shows anticipated expiration 2023-12-18 with status Expired – Lifetime. Any damages window closed at that date, subject to a possible Hatch-Waxman-style restoration or terminal-disclaimer nuance I cannot confirm from the record provided.

Estoppel landscape: empty. Because there is no IPR/PGR that reached a final written decision, 35 U.S.C. § 315(e)(2) estoppel does not apply to any party. No petitioner or privy is barred from raising any § 102/§ 103 ground in district court or the ITC. Conversely, there is no petitioner-side win to lean on and no Board claim construction to adopt. Practically, this means an invalidity defense is wide open — the full universe of art is available, including art that was before the examiner (no § 325(d) shadow) — but it must be built and proven from scratch in the district court or via an ex parte reexamination, not inherited from a PTAB record. No IPR time bar under § 315(b) exists yet either, since no complaint service date has been established on this record; that door is open for the first petitioner.

Pattern signals: none. No repeat petitioner (there are no petitioners at all). No patent-owner appeal activity — the assignee chain (Toshiba → Toshiba Memory → K.K. Pangea → Toshiba Memory → Kioxia per the Google Patents reassignment history of 2021-01-22) has never had a PTAB outcome to appeal to the Federal Circuit. No defensive aggregator (Unified Patents or similar) appears anywhere in the chain. The CBM route is unavailable anyway: this is a 2003-filed semiconductor fabrication method patent, not a financial-services data-processing claim, so it was never CBM-eligible. PGR is likewise unavailable — pre-AIA filing (2003) means IPR is the only AIA trial vehicle.

Bottom line for a defendant. The absence of any IPR on a 2005-issued, now-expired Toshiba/Kioxia process patent is a meaningful signal: the patent was never valuable enough to the owner (or threatening enough to a competitor) to attract a Board challenge, and the expiration date now caps exposure. If a demand letter or complaint cites US 6,908,801, the first questions are (1) when did the accused acts occur relative to 2023-12-18, and (2) does the letter confuse this patent with US 6,918,801 — whose claims 1–5 and 9–15 were invalidated — or with any other "801."

Recommended next steps

• Confirm the empty docket yourself before relying on it. Search the PTAB's own systems by patent number rather than by string: USPTO PTAB E2E / PTAB Decisions and the PTAB Decisions page at USPTO. Query 6908801 (no punctuation) and the application number 10/737,964. My searches surfaced nothing, but PTAB records are the authoritative source and I do not want a null search treated as affirmative proof.
• Run the expiration/term analysis now. Given the recorded anticipated expiration 2023-12-18 and Expired – Lifetime status, brief whether any pre-expiration damages period remains, whether the patent was ever subject to a terminal disclaimer or PTA that moves the date, and whether maintenance fees were paid (Google Patents' legal-status field is an assumption, not a conclusion — pull the fee record from Patent Center).
• Do not cite any "801 IPR" in a defense memo. If you have internal materials referencing an "IPR on the '801," verify the full number. The most likely culprit is US 6,918,801 (Wilco v. Weeks Marine), which was invalidated on § 102 grounds in district court and affirmed at the Federal Circuit on 2025-08-19 — A&O Shearman summary.
• If assertion is live, press the threshold defenses. With no PTAB proceeding and no § 315(b) clock running, the defendant has the option (subject to the one-year bar from service) of filing the first IPR on this patent — but weigh that against the expired status: an IPR on an expired patent yields no injunction benefit and only helps on past damages. Ex parte reexamination under § 302 may be the cheaper vehicle for a § 102/§ 103 attack on an expired process patent, and it does not trigger § 315(e)(2) estoppel.
• No PTAB trial milestones to track. There is no institution decision deadline, no oral hearing, and no statutory one-year § 316(a)(11) FWD due date because no proceeding was ever instituted. Any calendar entries for this patent should be deleted.

Confidence note. I am confident in the negative PTAB finding as against the structured data and my searches. I am not able to confirm from the provided record whether this patent has been asserted in district court litigation, since Google Patents' litigation field was not included in the fetched text and my searches returned only other "801" patents; a PACER/Docket Alarm check on US 6,908,801 should be run before stating "never asserted" in writing.

I'll research the assignment record for US 6908801, focusing on reel/frame numbers, correspondents, and the ownership chain.

Let me dig deeper into the specific assignment records and the unusual "K.K. Pangea" merger entry.

Let me try to pull the specific reel/frame and correspondent data from assignment databases.

I was unable to retrieve reel/frame numbers or correspondent-of-record data for this patent — my search steps were exhausted before I could reach the Assignment Center's indexed records directly. I'll present the assignment chain from the data I do have (Google Patents' recorded legal-event log plus corroborating SEC/press sources), and flag every field I could not verify rather than fabricate it.

Inventors

• Tomohiro Saito — sole named inventor.

Employer at time of filing: Kabushiki Kaisha Toshiba (Toshiba Corporation). The application (US 10/737,964) was filed 2003-12-18 claiming priority to JP 2003-327517 (filed 2003-09-19); the inventor executed an assignment of his interest to Toshiba recorded 2004-04-29, which is the standard inventor→employer dedication and confirms Toshiba employment at filing. The claimed subject matter (dual-metal-gate CMOS electrode formation) aligns with Toshiba's then-active semiconductor/CMOS process development rather than its memory-only lines.

Unusual-pattern check: With a single inventor, the "mass inventor exodus" precursor cannot be established. I found no evidence of Saito departing Toshiba within 12 months of filing — I simply have no data either way, so I make no finding.

Original assignee

• Entity on the issued patent: Kabushiki Kaisha Toshiba (Toshiba Corporation), Tokyo, Japan.
• Primary business: Diversified electronics/industrial conglomerate — energy, infrastructure, and (pre-2017) NAND flash memory and discrete/CMOS semiconductors.
• Product embodiment: The claims are a manufacturing method, so direct product embodiment is not provable from the record; Toshiba's semiconductor division did fabricate CMOS devices in this era, but I cannot assert a specific shipping product read on these claims. Treat "shipped a product embodying the claims" as unverified.
• Current status: Operating but transformed. Toshiba was under severe financial stress from the Westinghouse nuclear writedowns (2016–2017) — this distress, not a bankruptcy, is what drove the memory-unit divestiture. Toshiba Corporation was later taken private by a Japan Industrial Partners–led consortium and delisted from the Tokyo Stock Exchange in December 2023. It no longer owns this patent (transferred out in 2017–2018).

Assignment timeline

Chain of title as reflected in the recorded legal-event log for US 6,908,801. ⚠️ Reel/frame numbers and correspondent-of-record were NOT retrievable from the sources I could reach — I am not inventing them. The execution dates for the 2017 entry and the exact recorded execution dates for the 2021 entries are likewise not confirmed; the 2018 merger and 2019 rename execution dates are corroborated by Toshiba/Kioxia press releases.

1. Executed c. 2003–2004 / recorded 2004-04-29 — Reel not retrieved

   • Conveyance: Assignment of assignors interest ("Assignment of Assignors Interest (see document for details)")
   • Assignor: Saito, Tomohiro
   • Assignee: Kabushiki Kaisha Toshiba
   • Correspondent: not retrieved
   • Context: Inventor→employer assignment (original prosecution-chain dedication).

2. Executed date not confirmed / recorded 2017-08-24 — Reel not retrieved

   • Conveyance: Assignment of assignor's interest
   • Assignor: Kabushiki Kaisha Toshiba
   • Assignee: Toshiba Memory Corporation (TMC)
   • Correspondent: not retrieved
   • Context: Intra-group carve-out of memory-business patents accompanying Toshiba's spin-off/sale of TMC (the memory unit sold to the Bain-led consortium; SPA signed 2017-09-28, share transfer closed 2018-06-01). This is a corporate divestiture, not an NPE transfer.

3. Executed 2018-08-01 / recorded 2021-01-22 — Reel not retrieved

   • Conveyance: Merger
   • Assignor: Toshiba Memory Corporation
   • Assignee: K.K. Pangea
   • Correspondent: not retrieved
   • Context: K.K. Pangea — the Bain Capital–controlled special purpose acquisition company that bought TMC — merged with TMC, with K.K. Pangea as the surviving entity. Recording was filed in bulk in January 2021, roughly 2.5 years after execution.

4. Executed 2018-08-01 / recorded 2021-01-22 — Reel not retrieved

   • Conveyance: Change of name and address
   • Assignor: K.K. Pangea
   • Assignee: Toshiba Memory Corporation
   • Correspondent: not retrieved
   • Context: Pure name change — surviving entity of the merger assumed the "Toshiba Memory Corporation" name. No new consideration.

5. Executed 2019-10-01 / recorded 2021-01-22 — Reel not retrieved

   • Conveyance: Change of name and address
   • Assignor: Toshiba Memory Corporation
   • Assignee: KIOXIA Corporation
   • Correspondent: not retrieved
   • Context: Corporate rebrand from Toshiba Memory to Kioxia, effective 2019-10-01. Current assignee of record.

Cross-reference note (not a contradiction): The previously generated litigation section listed the 2021-01-22 events in the order "TMC change-of-name → Pangea merger → KIOXIA change-of-name." The logically correct sequence is merger → Pangea rename → KIOXIA rename, which is the order I've used. The recording-log ordering reflects the order the three instruments were keyed into the USPTO system, not the corporate sequence. No factual conflict.

Timeline diagram

timeline
    title Ownership of US 6908801
    2003 : Saito files app 10 737 964
         : Toshiba named assignee
    2004 : Inventor assigns to Toshiba
    2005 : Patent granted
    2017 : Recorded transfer to Toshiba Memory
    2018 : KK Pangea merger executed
    2019 : Toshiba Memory renamed Kioxia
    2021 : Merger and rename records filed
    2023 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only superficially shell-like link is K.K. Pangea, a Japanese SPC with a Chiyoda-ku (Palace Building, Marunouchi) address. But that address is the head office of the target's acquirer structure, not a registered-agent mail drop, and K.K. Pangea was an acquisition vehicle for an operating business — it merged into TMC and took its name. It did not exist as a licensing-only shell, held no other assets, and the chain terminates at KIOXIA Corporation, a multi-billion-dollar NAND/SSD manufacturer. Not an NPE-style shell transfer.

2. Known asserter in the chain — not present. No link matches Acacia, Marathon, IV, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Round Rock, or any Unified/RPX high-frequency-plaintiff directory. Toshiba/TMC/Kioxia are operating manufacturers; Bain Capital is a private-equity sponsor (acquisition, not licensing).

3. Repeat correspondent across the chain — cannot evaluate (no data). I could not retrieve any correspondent-of-record for any of the five entries, so I can neither confirm nor rule out a recurring filing attorney. This is a data gap, not a clean negative — if a reviewer can pull reel/frame from Assignment Center, the correspondent field on the three 2021-01-22 entries (which share a recording date) is the highest-value check.

4. Cascading transfers — not present (apparent cascade is an artifact). Three assignments are recorded on a single day, 2021-01-22, which looks like a rapid cascade. In substance these are housekeeping recordings of 2018–2019 corporate events (merger + two renames) filed in bulk, not sequential LLC-to-LLC hops. All three share one corporate family, one address history, and one parent (Bain-led TMC). No evidence of shared-principal shell chaining.

5. Pre-litigation transfer — not present. Per the previously generated litigation section, no litigation was found involving US 6,908,801. With no suit, there is no transfer timed to arm an assertion. The 2021 recordings postdate the underlying 2018–2019 events by years and were followed by no case.

6. Bankruptcy fire-sale — not present. Toshiba's 2016–2017 crisis was a solvency scare (Westinghouse), not a Chapter 7/11 filing. The memory unit moved via a negotiated Share Purchase Agreement (¥2 trillion, signed 2017-09-28, closed 2018-06-01) to the Bain consortium — a going-concern sale, not a court-supervised asset sale. Distress-driven, but not a bankruptcy-sale pattern.

7. Privateering — not present. No evidence that any operating company transferred this patent to an NPE to assert on its behalf; no Patent Progress/EFF/SEC coverage linking this patent to such a scheme, and no assertion occurred.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN; it terminates at KIOXIA.

Verdict

Defensive / non-asserting — with an explicit caveat. (The enumerated label assumes termination at a defensive aggregator; here the chain instead terminates at an operating company, KIOXIA, and the patent is simply never asserted. Of the available options, this is the only one consistent with "no NPE activity and no litigation." Nothing about this chain is NPE-shaped.)

Justification: five recorded instruments track a single continuous corporate lineage — inventor→Toshiba (2004-04-29), Toshiba→Toshiba Memory (2017-08-24), then the Bain-led K.K. Pangea merger/rename pair and the Kioxia rename, all recorded 2021-01-22. Every assignee is either an operating semiconductor manufacturer or a PE acquisition vehicle absorbed into one; no assignee matches a known NPE list, no defensive aggregator appears, and no infringement action was ever filed before the patent's 2023-12-18 anticipated expiration. I cannot fully close signals 1 and 3 because reel/frame and correspondent data were not retrievable in this session — that gap is the main residual uncertainty, and it is a data limitation, not evidence of an NPE pattern.

Verification links:

• USPTO Assignment Center (search "6908801"): https://assignmentcenter.uspto.gov/
• Legacy Assignment Search: https://assignment.uspto.gov/patent/index.html
• Google Patents record / legal events: https://patents.google.com/patent/US6908801/en

I'll research the prior-art citations for U.S. Patent 6,908,801 using targeted searches.

Let me pull the specific cited references on the face of this patent.

Let me try to access the citation listings directly from patent databases.

Prior-Art Analysis — U.S. Patent No. 6,908,801 ("Method of manufacturing semiconductor device")

Identifier check (strict): The number searched is 6908801, which resolves to US 6,908,801 B2, application US 10/737,964, filed 2003-12-18, granted 2005-06-21, priority JP 2003-327517 (2003-09-19), inventor Tomohiro Saito, original assignee Kabushiki Kaisha Toshiba. Results for other numbers (e.g., 6,908,808; 6,908,810; 6,218,930; 6,963,908) are not substituted here.

Source note / data limitation: The authoritative Google Patents text supplied for 6908801 contained the abstract, description, and claims but not the front-page "Patent Citations" table. I therefore retrieved the "Referenced Cited" list from the Justia record at https://patents.justia.com/patent/6908801. That listing is truncated in two places (a gap between US 6,303,418 and US 6,410,376, and after JP 2001-284466), so the complete face-of-patent citation set may contain one or more additional entries I could not capture. This is flagged as an explicit uncertainty below.

1. Examiner-cited "References Cited" (as retrievable)

U.S. Patent Documents

Foreign Patent Documents

Note: US 6,737,309 (Matsuo, May 18, 2004) issued after the 6908801 priority date (2003-09-19) but before its U.S. filing date (2003-12-18); its effect as prior art would depend on its own priority/filing date, which I did not verify. Similarly JP 2002-198441 (July 2002) predates the priority date and is the reference the specification itself discusses as the closest prior art.

2. § 102 Anticipation Analysis

Analytical caveat (stated up front): These references appear on the patent face as examiner citations that supported an issued patent — i.e., the examiner had them and still allowed all three independent claims. That is strong evidence that none of them was treated as a single-reference § 102 anticipation of the independent claims; they were almost certainly used for § 103 obviousness rejections or as background art. Accordingly, the mapping below is a potential/single-reference anticipation screen, not a statement that any reference in fact discloses every claim limitation. I could not open the full text of each cited reference in this session, so the technical descriptions are necessarily provisional and are marked with a confidence rating. Nothing below should be relied on as a completed element-by-element § 102 comparison — that requires the full specification and claims of each reference.

2.1 JP 2002-198441 A — July 2002 (the "closest prior art")

• Description (high confidence, from the 6908801 specification itself): Discloses a dual-metal-gate method in which a dummy gate is formed in each of a PMOS and NMOS region; an interlayer insulating film is deposited and polished until the dummy gates are exposed; a first trench is formed by removing one dummy gate; a first gate insulating film and first metal film are then deposited and etched back to form a first metal gate; the residual dummy gate is removed to form a second trench; and a second gate insulating film and second metal film are deposited and etched back to form the second metal gate.
• § 102 relevance — the most serious reference in the set. The specification (Description of the Related Art) expressly identifies it as disclosing the same general goal (NMOS/PMOS metals of different work functions formed by a trench/damascene flow). It therefore maps onto the structural end-products and several process steps of the independent claims:
  • Claim 1 (first aspect): JP 2002-198441 shares "different work function" first/second metals but uses two separate gate-insulator depositions, whereas claim 1 recites forming one gate insulating film, covering it with a mask, opening the mask only over the first element region, pattering a first conductive film, then stripping the mask — a sequence the JP reference does not appear to disclose. On the disclosed facts it is not anticipatory of claim 1, but it is the reference most likely to be combined for a § 103 challenge.
  • Second aspect (damascene; number unconfirmed — see prior section): The trench/dummy-gate flow of JP 2002-198441 is closer to this aspect's trench-based structure, but the claimed single mask-with-etch-selectivity + single gate-insulator deposition distinction again is what the patent relies on to avoid anticipation.
  • Confidence that JP 2002-198441 anticipates any independent claim: LOW. The patent distinguishes it on the very element (single gate-insulator formation, no exposure of the first metal to the second high-temperature insulator step) that the claims recite.

2.2 US 6,303,418 B1 — Cha et al., issued Oct. 16, 2001

• Description: A U.S. semiconductor-manufacturing patent cited by the examiner; by number/field it belongs to the gate-electrode/damascene or metal-gate fabrication family. I could not retrieve its full text to confirm its disclosure, so I do not assert specific subject matter.
• § 102 potential: At most, a reference of this type could touch generic steps common to claim 1 (forming and patterning a conductive film over a gate insulator; possibly a trench/replacement-gate flow). To anticipate, it would need to disclose the full mask-with-etch-selectivity step sequence plus two work-function-differing conductive films over a single gate insulating film — which the issued-claim history implies it does not.
  • Potentially implicated claims (provisional): 1, 2 (high-k), and the corresponding dependent claims of the second/third aspects. Confidence: LOW / unverified.

2.3 US 6,410,376 B1 — Ng et al., issued Jun. 25, 2002

• Description: Examiner-cited U.S. patent; field consistent with MOSFET gate-stack fabrication. Full text not retrieved; specific disclosure not confirmed.
• § 102 potential: A metal-gate formation reference of this type could bear on the "forming a first/second conductive material film" and "patterning" steps of claim 1 and the trench-burial steps of the second and third aspects, but I have no verified basis to assert it discloses the claimed mask/etch-selectivity and single-gate-insulator combination.
  • Potentially implicated claims (provisional): 1, 2; second-aspect independent claim; 13, 14. Confidence: LOW / unverified.

2.4 US 6,444,512 B1 — Madhukar et al., issued Sep. 3, 2002

• Description: Examiner-cited U.S. patent (Texas-Instruments-associated inventor lineage), consistent with metal-gate / gate-stack integration art. Full text not retrieved.
• § 102 potential: Same category as 2.3; could be relevant to the work-function-differing-metal concept but not verified to disclose the claimed masking sequence.
  • Potentially implicated claims (provisional): 1, 2; second-aspect claim; 13, 14. Confidence: LOW / unverified.

2.5 US 6,563,178 B1 — Moriwaki et al., issued May 13, 2003

• Description: Examiner-cited U.S. patent in the semiconductor-device/gate-electrode field. Full text not retrieved.
• § 102 potential: Could relate to dual-gate or metal-electrode structures; no verified element-by-element basis for anticipation.
  • Potentially implicated claims (provisional): 1, 2; second-aspect claim; 13, 14. Confidence: LOW / unverified.

2.6 US 6,586,288 B1 — Kim et al., issued Jul. 1, 2003

• Description: Examiner-cited U.S. patent (Samsung-lineage inventor set by name), consistent with dual-gate / metal-gate fabrication. Full text not retrieved.
• § 102 potential: Same category; no verified disclosure of the claimed single-gate-insulator + etch-selective-mask sequence.
  • Potentially implicated claims (provisional): 1, 2; second-aspect claim; 13, 14. Confidence: LOW / unverified.

2.7 US 6,737,309 B1 — Matsuo, issued May 18, 2004

• Description: Examiner-cited U.S. patent; note the post-priority, pre-filing issue date (see timing note above), so its prior-art effect turns on its own filing/priority date, which I did not verify.
• § 102 potential: Depends entirely on the verified effective date; without that, no § 102 assertion can be made.
  • Potentially implicated claims: indeterminate. Confidence: LOW / unverified.

2.8 JP 2001-284466 A — October 2001

• Description: Japanese laid-open application cited by the examiner; likely a metal-gate/gate-electrode fabrication disclosure. Full text not retrieved (and would require JP-language review).
• § 102 potential: Same provisional category as the U.S. metal-gate references; no verified anticipation basis.
  • Potentially implicated claims (provisional): 1, 2; second-aspect claim; 13, 14. Confidence: LOW / unverified.

3. Bottom-Line § 102 Conclusion

• Strongest prior-art reference: JP 2002-198441 A — it is the reference the patent itself identifies as the closest art and distinguishes, because it requires two gate-insulating-film depositions and exposes the first metal gate to a high-temperature second-insulator step. On the specification's own account it does not anticipate claim 1, the second-aspect independent claim, or claim 13, because it lacks the claimed single gate-insulator formation plus etch-selective-mask step sequence.
• All other cited references: The metadata (number, date, inventor) is verified from the citation record, but I could not confirm their substantive disclosures in this session; they appear to be examiner citations supporting an issued patent and thus were very likely used under § 103, not § 102. I therefore cannot responsibly assert that any of them anticipates any claim of 6908801. A completed § 102 comparison requires the full text of each reference.
• Where § 102 risk could still exist: only against narrow dependent claims whose added limitations are individually known in the art — e.g., the high-k gate insulator limitation (claims 2 and 14 per the prior section; Ta₂O₅ / Hf, Al, Zr, Pd oxides/oxynitrides, silicates), the wet-etch/chemical-dry-etch mask-removal limitations, or the CMP planarization limitations. Even there, I have no verified single reference that discloses these in the claimed context.

4. Explicit Uncertainties and Limitations

1. Citation list may be incomplete. The Justia listing was truncated in at least two places; the full face-of-patent citation set (and any "Other References"/non-patent literature) may include entries not shown. Verify against the USPTO PatentCenter/Patent Full-Text record for 10/737,964.
2. No full-text retrieval of cited references. I did not open US 6,303,418; 6,410,376; 6,444,512; 6,563,178; 6,586,288; 6,737,309; or JP 2001-284466. Descriptions for those are category-level only and must not be treated as verified disclosures.
3. Second independent claim number still unconfirmed (carried over from the prior section) — I refer to it as the "second aspect" claim without asserting a number.
4. Effective prior-art dates for US 6,737,309 (post-priority issue) and the Japanese references were not independently verified.
5. No legal conclusion is drawn as to validity or infringement; the above is a technical screening only, and the patent is expired (2023-12-18) per the record, which moots enforcement-related analysis.

I'll enrich the reference descriptions before building the § 103 combinations, since the prior-art section flagged that the cited references' full texts were not retrieved.

Obviousness Analysis — U.S. Patent No. 6,908,801 under 35 U.S.C. § 103

Governing law note (must be stated up front): US 6,908,801 has a priority date of 2003-09-19 (JP 2003-327517) and a U.S. filing date of 2003-12-18. It is therefore a pre-AIA patent. The applicable statute is pre-AIA 35 U.S.C. § 103(a). KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), applies to the pre-AIA statute and displaces rigid application of the teaching–suggestion–motivation ("TSM") test; the Graham v. John Deere factors still frame the inquiry (scope/content of prior art, differences, level of ordinary skill, secondary considerations). AIA §§ 102/103 (first-inventor-to-file) do not apply.

1. Level of ordinary skill in the art (PHOSITA)

A person having ordinary skill in the art as of September 2003 would hold a B.S. in electrical engineering, applied physics, or materials science plus roughly 3–5 years of semiconductor process-integration experience (or an M.S. plus 2–3 years), and would be conversant with: CVD/PVD/ALD deposition; RIE and wet/chemical-dry etching; CMP; shallow-trench isolation; source/drain and LDD formation; replacement-gate ("damascene"/"dummy-gate") integration; work-function engineering of gate metals; and high-κ gate dielectrics (Ta₂O₅, HfO₂, silicates). None of these are in dispute — the '801 specification itself treats them as background.

2. The prior-art set actually available (with evidentiary status)

The prior-art section of this analysis listed the following examiner citations for 6,908,801: US 6,303,418 (Cha et al.), US 6,410,376 (Ng et al.), US 6,444,512 (Madhukar et al.), US 6,563,178 (Moriwaki et al.), US 6,586,288 (Kim et al.), US 6,737,309 (Matsuo), JP 2001-284466 A, and JP 2002-198441 A (the reference the '801 specification itself identifies as closest art). In this session I was able to recover the substantive disclosure of only some of these. I separate verified from unverified below — this matters, because an obviousness case may only rest on what each reference actually discloses.

Additional art surfaced incidentally (flagged, and not on the '801 face):

• US 6,376,888 B1 (Tsunashima, Suguro, Murakoshi, Matsuo, Iinuma; Kabushiki Kaisha Toshiba; filed 2000-04-27; issued 2002-04-23). Damascene dual-work-function flow in which a single gate insulator (HfO₂) is formed over both grooves; a first metal (HfN) is formed over both; a resist masks one region; the HfN is wet-etched with aqueous hydrogen peroxide in the other region — and the reference expressly notes "the hafnium oxide film … forming the gate insulating film is insoluble in the aqueous hydrogen peroxide solution and, thus, is not etched"; then a second, different-work-function metal (Co) is deposited over both and the structure is CMP-planarized. URL: https://companyprofiles.justatic.com/patent/6376888 — ⚠️ *This is a Toshiba patent and shares inventor Kouji Matsuo with the cited US 6,737,309 (Matsuo). I could not retrieve 6,737,309's own text, so I do not assert they are the same disclosure; I treat US 6,376,888 as an independent reference.*
• US 7,033,919 (Yu et al.; filed 2002-10-30) — dual work-function damascene metal gate with dummy gates and self-aligned masking. Surfaced as a citation in the Madhukar family; would be pre-AIA § 102(e) art as of its 2002-10-30 U.S. filing if verified.

3. The claims to be analyzed

Per the earlier sections: three independent claims — claim 1 (first aspect, "gate-first"/planar), the second-aspect independent claim (damascene; claim number still unconfirmed), and claim 13 (third aspect, mask buried in the gate trench) — plus dependents including claim 2 and claim 14 (high-κ gate insulator).

Claim 1 element map

The entire delta of claim 1 over Madhukar '512 is elements (b), (c), (f) — i.e., substituting a sacrificial, etch-selectively-removable mask layer (the spec's TEOS) for Madhukar's patterned photoresist, so that the region-2 gate dielectric is covered while the first metal is patterned rather than exposed.

4. Combination 1 — Claim 1 (and claim 2)

Primary: US 6,444,512 (Madhukar). Secondary: US 6,586,288 (Kim) and/or JP 2002-198441.

Why claim 1 is obvious.

1. Madhukar discloses every substantive step. It forms one gate dielectric over both wells, forms the first metal, removes it from one well, deposits a different-work-function second metal over both, and patterns both metals with a single mask/etch to yield a first gate (first metal on the dielectric) and a second gate (second metal on the dielectric). Notably, Madhukar supplies the very feature the '801 touts as its advance over JP 2002-198441 — depositing the gate insulator once. The '801 specification's stated advantage ("the gate insulating film below the first and second gate electrodes … can be formed by only one film formation step") therefore describes Madhukar, not a patentable departure from it.

2. The only difference — a sacrificial etch-selective mask instead of photoresist — is a routine design choice with a recognized reason to make it. Madhukar itself articulates the motivation: it prefers CVD deposition of the second metal "to protect the integrity of the portions of dielectric film … exposed," demonstrating awareness that the gate dielectric must be shielded from subsequent process chemistry. Using a deposited dielectric hard mask (TEOS, as the '801 uses) that (i) is selectively wet-etchable against the high-κ gate insulator (e.g., aqueous HF for TEOS vs. Ta₂O₅/HfO₂), and (ii) survives the first-metal etchant, is the archetypal way to protect a fragile high-κ film. KSR rationales (A), (C), (D) and (F) apply: combining known elements (hard mask + selective etch + metal-gate patterning) according to their established functions, improving a known process in a known way, and responding to the known problem of high-κ dielectric damage in a known manner.

3. JP 2002-198441 and Kim '288 supply the express motivation to move from two insulator formations to one. Both references — and the '801's own "Description of the Related Art" — perform two gate-insulator depositions and expose the first metal to the second (high-temperature) insulator step. The '801 specification concedes that this makes the process complex, lowers the reliability of the second insulator, and degrades the metal if the second insulator is formed at ≥600 °C. An applicant's own recitation of the problem its invention solves is an admission that the problem was known and that a solution was desired — i.e., it supplies the articulated motivation to combine. Reducing to one insulator deposition is precisely what Madhukar already does.

4. The claimed order of steps is the natural order. Claim 1's sequence (insulator → mask → open region 1 → first metal → pattern → strip mask → second metal → pattern both) is dictated by the geometry and by the requirement that the sealed region-2 dielectric never see the first-metal etchant. Given Madhukar's selective-removal step and the desire to protect the dielectric, arriving at the mask sequence requires no more than ordinary skill — at most an "obvious to try" selection from the finite, predictable options (photoresist vs. deposited hard mask; which etchant pair is selective).

5. Claim 2 (high-κ gate insulator) adds only the selection of a high-dielectric-constant material. The '801 specification itself lists Ta₂O₅, oxides/oxynitrides of Hf, Al, Zr and Pd, and silicates as known high-κ materials; US 6,376,888 uses HfO₂, US 6,563,178 uses Ta₂O₅, and Kim '288 discloses oxide/oxynitride/high-κ layers. Obvious in view of any of them.

5. Combination 2 — the second-aspect independent claim (damascene), number unconfirmed

Primary: JP 2002-198441 (or US 6,586,288) + Madhukar '512 + US 6,563,178 / US 6,376,888.

The second aspect differs from claim 1 only in that the gates are formed in trenches opened in an interlayer insulating film, the mask is deposited over the whole surface including the trenches, and the first/second conductive films are buried in the trenches (by RIE or CMP).

• JP 2002-198441 and Kim '288 place dual-metal gates in trenches/interlayer-film openings left by dummy gates, and Kim '288 even shows CMP planarization of the second metal against the interlayer film — exactly the second aspect's burial step.
• US 6,563,178 confirms Ta₂O₅ + metal buried in a replacement-gate trench with CMP.
• US 6,376,888 goes further: a single gate insulator (HfO₂) over both trenches, one first metal (HfN) over both, masking of one region, wet etch of the first metal in the other region using a chemistry (aqueous H₂O₂) selective to the gate insulator, removal of the mask, deposition of a different-work-function second metal (Co), and CMP. That is the second aspect's substance, with the "etch-selective mask" function accomplished by etchant selectivity rather than by a sacrificial film.

Motivation: (i) the known desire to keep thermally unstable high-κ dielectrics and metals out of the high-temperature source/drain anneal (a motivation the '801 specification, JP 2002-198441, Moriwaki '178 and Kim '288 all share); (ii) the known desire to eliminate one of the two gate-insulator depositions; (iii) the known benefit of CMP-planarized self-aligned gates. KSR rationale (C)/(D) — applying known damascene planarization and selective-etch techniques to a known dual-metal-gate structure.

6. Combination 3 — claim 13 / third aspect (mask buried in the trench)

Claim 13 differs from the second aspect by burying the mask inside each gate trench (blanket-deposit then CMP back to the interlayer-film level) and then removing it selectively from the region-1 trench.

• US 6,586,288 and US 6,563,178 both fill trenches/interlayer openings and CMP back to a stop layer — i.e., the exact "bury a sacrificial material in a trench and planarize" technique the third aspect uses for the mask.
• US 6,376,888 again supplies the region-selective wet removal of the first metal over the other region with an etchant that does not attack the gate insulator — functional correspondence to claim 13's "mask having an etching selectivity to the gate insulating film."
• JP 2002-198441 supplies the overall dual-metal damascene objective.

Motivation: burying the mask in the trench rather than depositing it over the whole surface is the natural way to self-align the mask to the trench and thereby avoid a separate mask-patterning lithography and avoid leaving the mask over the interlayer-film field — a cost/simplicity and alignment-driven choice that KSR treats as an obvious design expedient where the prior art already teaches trench-fill-and-CMP. Claims 14 and the other high-κ/etch-chemistry dependents fall with claim 2/13 for the reasons in §4.5.

7. Direct comparison to KSR rationales

8. Secondary considerations and the likely rebuttal

Nothing of record supports a nonobviousness rebuttal:

• No unexpected results are evident. Each asserted benefit (one insulator deposition; avoiding >600 °C exposure of the metals; keeping the region-2 gate insulator out of the peroxide/HF etchants) is the predictable consequence of the chosen steps — precisely the circumstance in which KSR holds that such results do not rebut obviousness. Note also that the '801 specification concedes the work functions themselves are variable and materials-agnostic: "the work function of W changes between 4.3 to 5.2, so W can be used in both the NMOS and PMOS in some cases." A claim whose central parameter is admitted to be process-dependent and non-definitive cannot carry much weight.
• No commercial-success nexus is available: no litigation, no PTAB proceeding, and the patent expired 2023-12-18 (per the record).
• The examiner's allowance cuts both ways. Madhukar '512, Moriwaki '178, Kim '288 and JP 2002-198441 were all before the examiner, who nonetheless allowed — suggesting the examiner regarded the etch-selective mask / mask-strip sequence (and the buried-mask variant) as the point of novelty. That is the strongest argument for the patent owner, and it is where a § 103 case must be won or lost.

9. Where the obviousness case is weakest (candid assessment)

1. Elements (b)–(f) of claim 1 — the mask-and-strip sequence — are the crux. None of the verified references discloses forming a deposited mask having etch selectivity to the gate insulator over the entire insulator, opening it over one region, depositing the first metal over the mask (so it never touches the region-2 insulator), re-exposing the mask, and then etching the mask away. Madhukar uses photoresist; JP 2002-198441 and Kim '288 use dummy gates; US 6,376,888 relies on etchant selectivity rather than a sacrificial film. A challenger needs either (i) US 6,303,418, US 6,410,376, US 6,737,309 or JP 2001-284466 to supply that step, or (ii) a solid rationale-plus-reasonable-expectation argument that substituting a deposited hard mask for photoresist was obvious. I could not retrieve those four, so the element-by-element case on (b)–(f) is currently incomplete.
2. Claim 13's buried mask is not squarely disclosed by the references I verified.
3. US 6,737,309 was cited on the '801 face but issued 2004-05-18 — after the '801 priority date. Its availability as art turns on its own earliest effective U.S. filing date (pre-AIA § 102(e)), which I did not verify. If it is a continuation of the 2000-vintage Toshiba damascene family, its art date is 2000 and it is highly material; this is the single highest-value verification outstanding.
4. US 6,376,888 is not on the '801 face and I have not confirmed whether it was before the examiner or distinguished. If it was not considered, it is the most dangerous uncited reference for the damascene aspects (second aspect and claim 13).

10. Bottom line

Practical conclusion. The '801's professed advance over JP 2002-198441 — depositing one gate insulator and never exposing the first metal to the second high-temperature insulator step — is squarely met by US 6,444,512 (Madhukar), which the examiner had. The remaining distance to claim 1 is the substitution of a deposited, etch-selectively-removable sacrificial mask for Madhukar's photoresist, for which Madhukar itself supplies the motivation (protecting the exposed dielectric). The damascene aspects are strongly supported by the Toshiba damascene family (US 6,376,888, US 6,563,178) in combination with JP 2002-198441 / US 6,586,288. A complete § 103 record, however, requires pulling the full texts of US 6,303,418, US 6,410,376, US 6,737,309 and JP 2001-284466 (and confirming whether US 6,376,888 was before the examiner).

Explicit uncertainties

1. Full texts of US 6,303,418 (Cha), US 6,410,376 (Ng), US 6,737,309 (Matsuo) and JP 2001-284466 A were not retrieved. Their substantive disclosures are therefore not mapped to any claim element, and no obviousness conclusion rests on them. My searches for those numbers returned different patents by unrelated Cha/Matsuo inventors, which I have not substituted.
2. The second independent claim number remains unconfirmed (carried over from the earlier sections); I refer to it as the "second aspect."
3. US 6,737,309's effective prior-art date (post-priority issue date) was not verified; if it shares the US 6,376,888 family's 2000 filing date, it becomes highly material.
4. US 6,376,888 and US 7,033,919 are not on the '801's face; I surfaced them incidentally and treat them as uncited art, flagged as such.
5. No legal conclusion on validity or infringement is drawn; this is a technical/legal screening. The patent is recorded as Expired – Lifetime (anticipated expiration 2023-12-18), so any § 103 dispute is confined to past damages.
6. Date discrepancy noted: the prior sections state a current date of April 26, 2026, whereas the operating date for this session is September 29, 2026. The patent's legal status (expired) is unchanged either way, but the earlier sections' "as of" framing should be read against April 26, 2026.