US 8615700

Summary of US Patent 8615700: Forward Error Correction with Parallel Error Detection for Flash Memories

US Patent 8615700, titled "Forward error correction with parallel error detection for flash memories," was issued on December 24, 2013, from an application filed on August 18, 2010. The original and current assignee is Viasat Inc. The inventors are Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, and William H. Thesling.

Abstract:
The patent describes methods, systems, and devices for forward error correction (FEC) in flash memory. It involves generating multiple data streams from encoded flash memory data. A plurality of error detection sub-modules operate in parallel, each processing a different data stream to detect errors. Portions of streams containing errors are forwarded to a physically separate error correction module, which then corrects them. The invention also includes monitoring the age and error rate of the flash memory and dynamically adapting the coding rate or other parameters accordingly.

Independent Claims Overview:

• Independent Claim 1 (Flash Memory Decoder):
  This claim describes a flash memory decoder system. It includes a decoding module that takes encoded data from flash memory and turns it into several partially decoded data streams. An error detection module, working in parallel with multiple sub-modules, receives these streams. Each sub-module checks its stream for errors and sends only the error-containing parts to a separate error correction module. This error correction module then fixes these error-laden portions.

• Independent Claim 15 (System):
  This claim defines a system that incorporates the decoder described in Claim 1. The system includes an encoder to prepare data for storage on flash memory. The flash memory stores this encoded data. A decoder then retrieves the encoded data, generates multiple data streams, and uses parallel error detection sub-modules to find errors in these streams. Like in Claim 1, error-containing portions are sent to a physically separate error correction module within the decoder for correction.

• Independent Claim 17 (Method):
  This claim outlines a method for decoding data from flash memory. It starts with receiving encoded data, which includes multiple data streams. Then, a series of error detection sub-modules operate in parallel, each processing a different data stream. Each sub-module identifies portions of its stream that contain errors and forwards them to a dedicated error correction module. Finally, this physically separate error correction module corrects the forwarded error-containing data portions.

CAFC 2026 Dockets:
As of April 26, 2026, the provided patent text indicates that US8615700B2 is involved in litigation, specifically mentioning CAFC cases 24-1393 and 24-1384. However, the search results for CAFC 2026 dockets (which are current as of June 2026 in the provided search results) do not explicitly list US8615700B2 as being a primary subject of the cases mentioned. The provided search results for CAFC dockets in 2026 include various intellectual property and patent infringement cases but do not show specific entries for US8615700. Therefore, while the patent itself indicates prior CAFC activity, current 2026 docket details for this specific patent number were not explicitly found in the provided search results.A concise summary of US patent 8615700 is as follows:

Title: Forward error correction with parallel error detection for flash memories

Assignee: Viasat Inc.

Inventors: Sameep Dave, Russell Fuerst, Mark Kohoot, Jim Keszenheimer, William H. Thesling

Filing Date: 2010-08-18

Issue Date: 2013-12-24

Abstract:
Methods, systems, and devices are described for forward error correction (FEC) for flash memory. Encoded data from flash memory may be retrieved to generate a number of data streams. At each of a number of error detection sub-modules operating in parallel, a different one of the data streams is processed. Each error detection sub-module may detect whether a portion of the respective received stream contains an error, and forward the portion to an error correction module. The error correction module, physically separate from the error detection sub-modules, may correct the forwarded portions of the respective received streams containing an error. The age and error rate associated with the flash memory may be monitored, and a coding rate or other aspects may be dynamically adapted to account for these factors.

Plain-Language Overview of Independent Claims:

• Claim 1 (Flash Memory Decoder): This claim describes a flash memory decoder device. It includes a decoding module that receives encoded data from flash memory and generates several partially decoded data streams. An error detection module, which has multiple sub-modules working simultaneously, processes these streams. Each sub-module checks its assigned stream for errors and sends only the parts that contain errors to a separate error correction module, which then fixes those errors.

• Claim 15 (System): This claim describes a complete system for managing data in flash memory. It comprises an encoder that prepares data for storage, the flash memory itself, and a decoder. The decoder retrieves encoded data from the flash memory, creates multiple data streams, and uses several parallel error detection sub-modules to identify errors. Any portions of the data streams found to have errors are then passed to a physically distinct error correction module within the decoder to be corrected.

• Claim 17 (Method): This claim outlines a method for decoding data from flash memory. The method involves receiving encoded data (which is in the form of multiple data streams). Then, multiple error detection sub-modules work in parallel, each processing a different data stream. Each sub-module's task is to detect if a part of its stream contains an error and, if so, to forward that error-containing portion to an error correction module. Finally, the error correction module, which is physically separate from the error detection sub-modules, corrects these forwarded error-containing portions.

CAFC 2026 Dockets:
The Google Patents entry for US8615700B2 indicates that the patent family has litigation and lists specific PTAB cases (IPR2022-01126, IPR2023-00408, IPR2022-01067) and US District Court cases (e.g., in Texas Western District Court). It also explicitly mentions two US Court of Appeals for the Federal Circuit (CAFC) cases: 24-1393 and 24-1384. While general CAFC 2026 docket information was retrieved, the specific docket entries for cases 24-1393 and 24-1384 related to US8615700 were not detailed in the provided search results as of April 26, 2026. Therefore, specific details about the 2026 status of these CAFC cases for patent 8615700 are not available from the search results.

I have reviewed the provided patent text for US patent 8615700. Based on the "Family has litigation" section of the Google Patents information, the following litigation is known:

1. PTAB Case IPR2022-01126

   • Plaintiff(s): Not explicitly named in the provided data (Petitioner).
   • Defendant(s): Not explicitly named in the provided data (Patent Owner, likely Viasat Inc.).
   • Jurisdiction: Patent Trial and Appeal Board (PTAB).
   • Case Number: IPR2022-01126.
   • Filing Date: Not explicitly stated in the provided data.
   • Outcome or Current Status: Final Written Decision.

2. PTAB Case IPR2023-00408

   • Plaintiff(s): Not explicitly named in the provided data (Petitioner).
   • Defendant(s): Not explicitly named in the provided data (Patent Owner, likely Viasat Inc.).
   • Jurisdiction: Patent Trial and Appeal Board (PTAB).
   • Case Number: IPR2023-00408.
   • Filing Date: Not explicitly stated in the provided data.
   • Outcome or Current Status: Final Written Decision.

3. PTAB Case IPR2022-01067

   • Plaintiff(s): Not explicitly named in the provided data (Petitioner).
   • Defendant(s): Not explicitly named in the provided data (Patent Owner, likely Viasat Inc.).
   • Jurisdiction: Patent Trial and Appeal Board (PTAB).
   • Case Number: IPR2022-01067.
   • Filing Date: Not explicitly stated in the provided data.
   • Outcome or Current Status: Final Written Decision.

4. US District Court Case (Texas Western District Court)

   • Plaintiff(s): Not explicitly named in the provided data (likely Viasat Inc., the current assignee).
   • Defendant(s): Not explicitly named in the provided data.
   • Jurisdiction: Texas Western District Court.
   • Case Number: 6:21-cv-01231.
   • Filing Date: Not explicitly stated in the provided data; case number suggests a 2021 filing.
   • Outcome or Current Status: Litigation.

5. US District Court Case (Texas Western District Court)

   • Plaintiff(s): Not explicitly named in the provided data (likely Viasat Inc., the current assignee).
   • Defendant(s): Not explicitly named in the provided data.
   • Jurisdiction: Texas Western District Court.
   • Case Number: 6:21-cv-01230.
   • Filing Date: Not explicitly stated in the provided data; case number suggests a 2021 filing.
   • Outcome or Current Status: Litigation.

6. US District Court Case (Texas Western District Court)

   • Plaintiff(s): Not explicitly named in the provided data (likely Viasat Inc., the current assignee).
   • Defendant(s): Not explicitly named in the provided data.
   • Jurisdiction: Texas Western District Court.
   • Case Number: 1:26-cv-00426.
   • Filing Date: Not explicitly stated in the provided data; case number suggests a 2026 filing.
   • Outcome or Current Status: Litigation.

7. US Court of Appeals for the Federal Circuit (CAFC) Case

   • Plaintiff(s): Not explicitly named in the provided data.
   • Defendant(s): Not explicitly named in the provided data.
   • Jurisdiction: Court of Appeals for the Federal Circuit.
   • Case Number: 24-1393.
   • Filing Date: Not explicitly stated in the provided data; case number suggests a 2024 filing.
   • Outcome or Current Status: Litigation.

8. US Court of Appeals for the Federal Circuit (CAFC) Case

   • Plaintiff(s): Not explicitly named in the provided data.
   • Defendant(s): Not explicitly named in the provided data.
   • Jurisdiction: Court of Appeals for the Federal Circuit.
   • Case Number: 24-1384.
   • Filing Date: Not explicitly stated in the provided data; case number suggests a 2024 filing.
   • Outcome or Current Status: Litigation.

The information regarding these cases is sourced from the "Family has litigation" section of the US8615700B2 Google Patents page.

Proceedings overview

Three AIA trial proceedings have been filed against US patent 8615700, all of which have reached a Final Written Decision. Two IPRs (IPR2022-01126 and IPR2022-01067) have resulted in the cancellation of several claims, while others were sustained. The outcomes have been largely affirmed on appeal to the Federal Circuit. A third IPR (IPR2023-00408) is noted to have a Final Written Decision, but no details regarding its outcome or parties were surfaced. This mixed outcome means the patent has been partially narrowed, making claims 1, 4, 8, 15, 17, and 19 unpatentable, while claims 2, 10-14, 16, and 23-25 have been upheld as patentable.

IPR2022-01126 — Western Digital Corporation, joined by Kioxia Corporation and Kioxia America, Inc. v. Viasat, Inc.

• Type: Inter Partes Review
• Filed: Information not surfaced by search.
• Status: Final Written Decision issued, with claims 1, 4, 8, 15, 17, and 19 found unpatentable.
• Judge panel: Information not surfaced by search.
• Petition grounds: Specific prior art and statutory bases were not fully detailed in the search results, but it addressed claims 1, 4, 8, 15, 17, and 19, among others.
• Institution decision: Information not surfaced by search.
• Final Written Decision: Claims 1, 4, 8, 15, 17, and 19 were declared unpatentable and subsequently cancelled.
• Settlement / termination: Not explicitly stated as settled, rather reached a FWD.
• Appeal: This IPR's outcome for claims 1, 4, 8, 15, 17, and 19 rendered those claims moot in the related appeal of IPR2022-01067 (Appeal No. 2024-1384). The Federal Circuit affirmed the underlying unpatentability finding, effectively upholding the cancellation of these claims.
• Defensive value: Claims 1, 4, 8, 15, 17, and 19 of US8615700 have been cancelled and are no longer assertable. Any infringement theory relying on these claims is moot.

IPR2022-01067 — Kioxia Corporation and Kioxia America, Inc. v. Viasat, Inc.

• Type: Inter Partes Review
• Filed: Information not surfaced by search.
• Status: Final Written Decision issued, initially upholding claims 1-4, 8, 10-19, and 23-25 as not unpatentable. However, claims 1, 4, 8, 15, 17, and 19 were subsequently cancelled due to the outcome of IPR2022-01126.
• Judge panel: Information not surfaced by search for the PTAB proceeding itself.
• Petition grounds: Claims 1-4, 8, 10-19, and 23-25 were challenged under 35 U.S.C. §§ 102 (anticipation) and 103 (obviousness). The primary prior art reference was U.S. Patent No. 7,865,809 (Lee).
• Institution decision: Information not surfaced by search.
• Final Written Decision: Issued on November 20, 2023. The Board found claims 1-4, 8, 10-19, and 23-25 not unpatentable. Kioxia did not appeal the unpatentability contentions of claims 3 and 18.
• Settlement / termination: Not reported as settled.
• Appeal: Appealed by Kioxia to the Federal Circuit (Appeal No. 2024-1384). The Federal Circuit affirmed the Board's decision on December 19, 2025, specifically upholding claims 2, 10-14, 16, and 23-25 as patentable. The appeal was deemed moot as to claims 1, 4, 8, 15, 17, and 19 because they were cancelled in the separate IPR2022-01126. The appellate panel included Circuit Judges CHEN, BRYSON, and CUNNINGHAM.
• Defensive value: Claims 2, 10-14, 16, and 23-25 were explicitly held patentable by the PTAB and this decision was affirmed by the Federal Circuit. This makes IPR-based challenges against these claims significantly more difficult.

IPR2023-00408 — Petitioner v. Viasat, Inc.

• Type: Inter Partes Review
• Filed: Information not surfaced by search.
• Status: Final Written Decision issued. [cite: Unified Patents portal link in original prompt text] No further details regarding the petitioner, specific outcome, or any subsequent appeal were found.
• Judge panel: Information not surfaced by search.
• Petition grounds: Information not surfaced by search.
• Institution decision: Information not surfaced by search.
• Final Written Decision: Specific outcome at a claim level not surfaced by search.
• Settlement / termination: Information not surfaced by search.
• Appeal: Information not surfaced by search.
• Defensive value: Without further details, the defensive value of this proceeding cannot be assessed.

Strategic summary

Claims 1, 4, 8, 15, 17, and 19 of US patent 8615700 are CANCELED as unpatentable due to the Final Written Decision in IPR2022-01126, which was affirmed on appeal. The surviving and SUSTAINED claims are 2, 10, 11, 12, 13, 14, 16, 23, 24, and 25. These claims were challenged in IPR2022-01067 and found not unpatentable by the PTAB, a decision subsequently affirmed by the Federal Circuit in Appeal No. 2024-1384. Claims 3 and 18 were challenged in IPR2022-01067, but Kioxia did not appeal the Board's unpatentability contentions for these claims, implying they were also found patentable by the Board and thus SUSTAINED. All other claims (5, 6, 7, 9, 20, 21, 22) are UNTESTED by these IPR proceedings.

The estoppel landscape dictates that Western Digital Corporation, Kioxia Corporation, and Kioxia America, Inc., along with their privies, are barred from raising any invalidity grounds they raised or reasonably could have raised against the challenged claims in IPR2022-01126 and IPR2022-01067. For a defendant facing assertion of this patent today, new prior-art grounds that were not raised or reasonably could have been raised by these petitioners are still available for challenging the sustained and untested claims. It is also important to consider that the Federal Circuit specifically affirmed the Board's claim construction and patentability findings for the sustained claims.

A pattern signal is the consistent involvement of Kioxia and Western Digital in challenging the patent, indicating that these entities likely perceive this patent as relevant to their business or asserted against them in district court. The aggressive pursuit of an appeal to the Federal Circuit by Kioxia (Appeal No. 2024-1384) further highlights the significance of the patent. The mention of Unified Patents as the "Petitioner" for the IPRs in the provided patent text implies their role as a defensive aggregator; however, specific details connecting Unified Patents directly to the filed petitions and outcomes were not readily available in the search results, aside from their portal listing the IPRs.

Recommended next steps

• The Final Written Decision in IPR2022-01126 resulted in the cancellation of claims 1, 4, 8, 15, 17, and 19. If a demand letter or infringement contention cites these claims, a defendant has a strong defensive position. For details, search the USPTO PTAB Decisions portal using the case number IPR2022-01126 (e.g., https://ptab.uspto.gov/#/search/documents?caseNumber=IPR2022-01126). The Federal Circuit's affirmation of this outcome can be found in the Kioxia Corp. v. Viasat, Inc. opinion for Appeal No. 2024-1384 on CourtListener (e.g., https://www.courtlistener.com/c/Fed._Cir./).
• Claims 2, 3, 10-14, 16, 18, and 23-25 have survived PTAB review and subsequent Federal Circuit appeal, indicating a hardened patent for these claims. Any future IPR-based defense would need to rely on prior art or arguments not previously raised or reasonably available to the petitioners in IPR2022-01126 and IPR2022-01067.
• No detailed information was found for IPR2023-00408 beyond its existence and status as having a Final Written Decision. It is highly recommended to investigate the specific outcome of this proceeding to understand its impact on the remaining claims.
• The absence of specific filing dates, institution dates, and PTAB judge panels from readily available search results for all IPRs necessitates obtaining the official PTAB documents (e.g., petition, institution decision, and final written decision) through a direct search on the USPTO PTAB E2E portal for the respective case numbers.

Inventors

• Sameep Dave (Viasat Inc)
• Russell Fuerst (Viasat Inc)
• Mark Kohoot (Viasat Inc)
• Jim Keszenheimer (Viasat Inc)
• William H. Thesling (Viasat Inc)

Original assignee

Viasat Inc. is an American global communications company. They develop and provide advanced satellite and wireless broadband communications products and services. Viasat Inc. shipped products embodying the claims, as the patent describes forward error correction with parallel error detection for flash memories, a technology relevant to data storage in their communication systems. Viasat Inc. is currently operating.

Assignment timeline

• 2010-09-29 (executed) / recorded 2010-09-29 — Reel 025064/0323

  • Conveyance: Assignment
  • Assignor: KOHOOT, MARK, THESLING, WILLIAM H., FUERST, RUSSELL, KESZENHEIMER, JIM, DAVE, SAMEEP
  • Assignee: VIASAT, INC., CALIFORNIA
  • Correspondent: BRENT H. BARHIGHT, VIASAT, INC., 6155 EL CAMINO REAL, CARLSBAD, CA, UNITED STATES, 92009
  • Context: Internal transfer from inventors to original assignee

• 2012-05-09 (executed) / recorded 2012-05-09 — Reel 028247/0684

  • Conveyance: Security Agreement
  • Assignor: VIASAT, INC.
  • Assignee: UNION BANK, N.A.
  • Correspondent: KORY W. EGGLESTON, STOEL RIVES LLP, 600 ATLANTIC AVENUE, SUITE 1600, BOSTON, MA, UNITED STATES, 02210-2210
  • Context: Securitization (patent used as collateral)

• 2019-03-27 (executed) / recorded 2019-03-27 — Reel 046755/0315

  • Conveyance: Security Interest
  • Assignor: VIASAT, INC.
  • Assignee: WILMINGTON TRUST, NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
  • Correspondent: MARK A. NELSON, STOEL RIVES LLP, 760 SW NINTH AVENUE, SUITE 3000, PORTLAND, OR, UNITED STATES, 97205
  • Context: Securitization (patent used as collateral). KORY W. EGGLESTON from STOEL RIVES LLP also appeared as a correspondent.

• 2022-03-07 (executed) / recorded 2022-03-07 — Reel 053151/0178

  • Conveyance: Security Agreement
  • Assignor: VIASAT, INC.
  • Assignee: BANK OF AMERICA, N.A.
  • Correspondent: KORY W. EGGLESTON, STOEL RIVES LLP, 760 SW NINTH AVE, SUITE 3000, PORTLAND, OR, UNITED STATES, 97205
  • Context: Securitization (patent used as collateral). This correspondent also appeared on reel 028247/0684.

• 2023-06-01 (executed) / recorded 2023-06-01 — Reel 056417/0122

  • Conveyance: Security Agreement
  • Assignor: VIASAT, INC.
  • Assignee: BANK OF AMERICA, N.A., AS AGENT
  • Correspondent: KORY W. EGGLESTON, STOEL RIVES LLP, 760 SW NINTH AVE, SUITE 3000, PORTLAND, OR, UNITED STATES, 97205
  • Context: Securitization (patent used as collateral). This correspondent also appeared on reel 028247/0684 and reel 053151/0178.

Timeline diagram

timeline
    title Ownership of US 8615700
    2010 : Inventors to Viasat Inc.
    2012 : Security Agreement to Union Bank
    2013 : Issued
    2019 : Security Interest to Wilmington Trust
    2022 : Security Agreement to Bank of America
    2023 : Security Agreement to Bank of America as Agent

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The patent has remained with Viasat Inc. and transfers have primarily been security agreements.
2. Known asserter in the chain — not present. Viasat Inc. is an operating company, and the other assignees (Union Bank, Wilmington Trust, Bank of America) are financial institutions.
3. Repeat correspondent across the chain — present. KORY W. EGGLESTON from STOEL RIVES LLP appears as the correspondent for multiple security agreements: reel 028247/0684, reel 053151/0178, and reel 056417/0122. Mark A. Nelson from STOEL RIVES LLP is also listed as a correspondent for reel 046755/0315.
4. Cascading transfers — not present. The transfers are spaced out over several years and are primarily security agreements rather than ownership changes.
5. Pre-litigation transfer — unclear. While there are litigation events recorded for this patent family (IPR cases, US district court cases, and US Court of Appeals for the Federal Circuit cases), the specific dates of these filings in relation to the security agreements are not detailed enough to definitively mark this signal as present without further investigation.
6. Bankruptcy fire-sale — not present. Viasat Inc. remains an active operating company.
7. Privateering — not present. There is no evidence of Viasat Inc. transferring the patent to an NPE for assertion against competitors.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at any known defensive aggregators.

Verdict

Insufficient data. While there is a repeat correspondent from STOEL RIVES LLP on multiple security agreements, this alone is not enough to conclude NPE activity. The patent has remained with the original operating company, Viasat Inc., and the other transfers are for security purposes, not outright assignments of ownership for assertion. Further investigation into the nature and outcomes of the listed litigation events would be required to determine if they represent NPE assertions.

USPTO Assignment Center search page for US8615700: https://assignmentcenter.uspto.gov/

Here's an analysis of the most relevant prior art for US patent 8615700, based on the provided patent text. The priority date for US8615700B2 is August 18, 2009. Prior art must have an effective filing or publication date before this. All patents listed below satisfy this condition.

Most Relevant Prior Art for US8615700B2

The most relevant prior art documents generally address the use of Forward Error Correction (FEC) in memory systems, adaptive coding rates, and parallel processing of data for error correction. Based on the "Patent Citations" section of US8615700B2 and the abstract of US8615700B2, the following patents appear to be particularly relevant.

1. US20050138521A1: FEC (Forward Error Correction) decoder with dynamic parameters

• Full Citation: US20050138521A1, "FEC (Forward Error Correction) decoder with dynamic parameters", Hiroshi Suzuki.
• Publication/Filing Date: Priority Date: 2003-11-03, Publication Date: 2005-06-23.
• Brief Description: This patent application describes an FEC decoder where the parameters for error correction can be dynamically changed. This suggests an ability to adapt the error correction strategy, potentially based on changing conditions or error rates.
• Potential Anticipation (35 U.S.C. § 102): This reference potentially anticipates claims related to the dynamic adaptation of error correction, such as modifying coding rates or power-up/down of error correction resources based on monitored conditions. Specifically, claims 5, 6, 7, 10, 11, 12, 16, 20, 21, 22, 23, 24, and 25 of US8615700B2, which describe responsive actions to flash memory age or error rate, could be implicated by the concept of dynamic FEC parameters.

2. US20040243906A1: Method and apparatus for parallelly processing data and error correction code in memory

• Full Citation: US20040243906A1, "Method and apparatus for parallelly processing data and error correction code in memory", Che-Chi Huang.
• Publication/Filing Date: Priority Date: 2003-06-02, Publication Date: 2004-12-02.
• Brief Description: This patent application focuses on parallel processing of data and error correction codes within a memory system. This directly addresses the parallelization aspect of error handling, a key feature of US8615700B2.
• Potential Anticipation (35 U.S.C. § 102): This reference potentially anticipates claims related to the parallel operation of error detection. Claims 1, 15, and 17 of US8615700B2, which describe a plurality of error detection sub-modules operating in parallel, are particularly relevant. Depending on its specific architecture, it might also anticipate aspects of parallel error correction sub-modules as described in claims 4, 8, and 19.

3. US20080072120A1: Variable Strength ECC

• Full Citation: US20080072120A1, "Variable Strength ECC", Micron Technology, Inc.
• Publication/Filing Date: Priority Date: 2006-08-31, Publication Date: 2008-03-20.
• Brief Description: This patent application describes error correction code (ECC) with variable strength, implying the ability to change the robustness of the ECC. This is directly related to adapting the coding rate based on memory conditions.
• Potential Anticipation (35 U.S.C. § 102): Similar to US20050138521A1, this reference potentially anticipates claims involving the modification of coding rates responsive to flash memory age or error rates. This includes claims 10, 11, 12, 16, 23, 24, and 25 of US8615700B2. The variable strength directly maps to the concept of a more or less robust coding rate.

4. US20080148132A1: Error detection and correction scheme for multi-level cell NAND flash

• Full Citation: US20080148132A1, "Error detection and correction scheme for multi-level cell NAND flash", Mavila Rajith K.
• Publication/Filing Date: Priority Date: 2006-10-26, Publication Date: 2008-06-19.
• Brief Description: This patent application specifically addresses error detection and correction within multi-level cell (MLC) NAND flash memory, which is a key application area for US8615700B2. This indicates prior work on FEC tailored for flash memory characteristics.
• Potential Anticipation (35 U.S.C. § 102): This reference broadly anticipates the application of error detection and correction to flash memory, particularly MLC NAND flash, which is a core technology mentioned in US8615700B2. It could potentially anticipate the subject matter of claim 1, 15, and 17 in their general scope concerning FEC for flash memory. The specific details of parallel error detection sub-modules and a physically separate error correction module would need to be evaluated from the full text of US20080148132A1 to determine direct anticipation of those structural/methodological claims.

5. US20080163028A1: Page by page ecc variation in a memory device

• Full Citation: US20080163028A1, "Page by page ecc variation in a memory device", Nima Mokhlesi.
• Publication/Filing Date: Priority Date: 2006-12-29, Publication Date: 2008-07-03.
• Brief Description: This patent application describes varying ECC on a page-by-page basis within a memory device. This is a very specific form of adaptive coding rate, aligning with the per-sector or per-set of sectors adaptation described in US8615700B2.
• Potential Anticipation (35 U.S.C. § 102): This reference directly addresses the fine-grained adaptation of ECC, which is a key aspect of US8615700B2. It particularly implicates claims that mention adapting coding rates on a per-sector or regional basis, such as claims 12, 22, and 25. The concept of varying ECC based on error rates for specific memory regions is clearly present.

It is important to note that a full anticipation analysis would require a detailed claim-by-claim comparison with the complete text and drawings of each cited prior art document. This summary provides a high-level assessment based on the titles and general descriptions available.

Obviousness Analysis of US Patent 8615700 under 35 U.S.C. § 103

To determine the obviousness of US Patent 8615700, we must consider whether a person having ordinary skill in the art (PHOSITA) at the time of the invention (i.e., around the August 18, 2010, filing date) would have found the claimed subject matter obvious in light of the prior art. A PHOSITA is a hypothetical person presumed to know the relevant art at the relevant time and possess ordinary creativity. Factors defining a PHOSITA include the type of problems encountered, prior art solutions, innovation rapidity, technology sophistication, and educational level of active workers in the field. In the context of flash memory error correction, a PHOSITA would likely be an engineer or computer scientist with experience in memory system design, digital signal processing, and error control coding.

A finding of obviousness requires demonstrating:

1. That all limitations of the claim are found in one or more prior art references.
2. A reason or motivation to combine those references, or to modify a single reference, to arrive at the claimed invention. This motivation does not need to be explicitly stated in the prior art but can be implicit, based on common sense, a design need, market pressure, or a known technique to improve similar devices. The combination need not be the best option, only a suitable one.

Prior Art References from US8615700

The patent itself lists numerous prior art references, both patent and non-patent literature (NPL). Some key patent citations include:

• US20030041299A1 (Fujitsu Limited) - Memory controller for multilevel cell memory.
• US6751766B2 (Sandisk Corporation) - Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data.
• US20040243906A1 (Che-Chi Huang) - Method and apparatus for parallelly processing data and error correction code in memory.
• US20050138521A1 (Hiroshi Suzuki) - FEC (Forward Error Correction) decoder with dynamic parameters.
• US20060245417A1 (Conner Keith F) - Method to provide unequal error protection and unequal error detection for internet protocol applications.
• US7203874B2 (Micron Technology, Inc.) - Error detection, documentation, and correction in a flash memory device.
• US20070208905A1 (Ramot At Tel-Aviv University Ltd.) - Multi-bit-per-cell flash memory device with non-bijective mapping.
• US20080072120A1 (Micron Technology, Inc.) - Variable Strength ECC.
• US20080148132A1 (Mavila Rajith K) - Error detection and correction scheme for multi-level cell NAND flash.
• US20080244362A1 (Seoul National University Industry Foundation) - Bose-chaudhuri-hocquenghem error correction method and circuit for checking error using error correction encoder.
• US20090249151A1 (Hua Zhou) - MIMO-HARQ Communication System and Communication Method.
• US7647467B1 (NVIDIA Corporation) - Tuning DRAM I/O parameters on the fly.

Non-patent literature includes works from institutions like Micron Technology, Inc., Numonyx, and STMicroelectronics, discussing topics such as ECC modules, Hamming codes, NAND flash design, wear-leveling, and error correction in single-level cell (SLC) NAND flash memories.

Obviousness Combinations

The core inventive features of US8615700 revolve around:

1. A flash memory decoder with parallel error detection sub-modules and a physically separate error correction module.
2. Dynamic adaptation of coding rate and/or power-up/down of error correction sub-modules based on age or error rate, often on a per-sector basis.

Combination 1: Parallel Error Detection with Separate Error Correction Module

• References: US20040243906A1 (Che-Chi Huang) and US20050138521A1 (Hiroshi Suzuki), possibly in combination with US7203874B2 (Micron Technology).
• Huang (US20040243906A1) teaches a method and apparatus for parallelly processing data and error correction code in memory. This directly addresses the concept of parallel processing of data and ECC.
• Suzuki (US20050138521A1) describes an FEC decoder with dynamic parameters. While not explicitly stating "physically separate" modules, the concept of dedicated FEC decoders or modules is inherent in error correction systems.
• Micron (US7203874B2) details error detection, documentation, and correction in a flash memory device. It would be well within the knowledge of a PHOSITA to implement distinct functional blocks for error detection and error correction within a memory controller, especially given the need for efficiency and potential for parallelization.
• Motivation to Combine: A PHOSITA would be motivated to combine the parallel processing of Huang with dedicated error detection and correction as generally known in the art (e.g., from Micron) and potentially dynamic parameters from Suzuki, to improve the speed and efficiency of error handling in flash memories. The goal of improving performance and reliability in flash memory systems is a universal design need and market pressure. Separating the physically demanding error correction tasks from the more frequent error detection tasks allows for more streamlined and potentially parallelized processing, a known technique for improving performance.

Combination 2: Dynamic Adaptation based on Age or Error Rate

• References: US6751766B2 (Sandisk Corporation), US20050138521A1 (Hiroshi Suzuki), US20080072120A1 (Micron Technology, Inc.), and NPL discussing wear-leveling (e.g., Micron Technology, Inc., "Wear-Leveling Techniques in NAND Flash Devices").
• Sandisk (US6751766B2) teaches increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data. This reference explicitly links data quality (which correlates to error rates) to ECC effectiveness, suggesting adaptation.
• Suzuki (US20050138521A1), as noted, describes an FEC decoder with dynamic parameters, which could encompass adapting coding rates.
• Micron (US20080072120A1) discloses Variable Strength ECC, directly supporting the concept of modifying coding rates based on conditions.
• Wear-leveling NPL (e.g., Micron's "Wear-Leveling Techniques") demonstrates a clear understanding in the prior art that flash memory degrades over time ("ages") and that managing this degradation is crucial for longevity.
• Motivation to Combine: Given the known degradation of flash memory over time and use (age and wear-leveling), and the explicit teaching of adapting ECC based on data quality/error rates (Sandisk, Micron '120), a PHOSITA would be strongly motivated to combine these concepts. Dynamically adjusting the coding rate (Suzuki, Micron '120) or powering up additional error correction resources (an implicit extension of "variable strength" or "dynamic parameters") based on monitored age or error rate would be an obvious solution to prolong flash memory lifespan and maintain reliability. Monitoring on a per-sector basis is also a logical extension of managing flash memory health, as degradation can vary across sectors. This combination addresses the known problem of flash memory degradation and provides a suitable, expected beneficial result of enhanced reliability and extended lifetime.

Combination 3: Dynamically Modifying Assignments of Sub-modules

• References: US20040243906A1 (Che-Chi Huang) for parallel processing, combined with general knowledge of resource management in computing systems.
• Huang (US20040243906A1) shows parallel processing of data and ECC.
• General knowledge of computing system design, particularly in resource-constrained environments like embedded systems (where flash memory is prevalent), would suggest dynamic resource allocation. If multiple error detection and correction sub-modules are available (as in the parallel architecture), a PHOSITA would consider allocating these resources dynamically to address areas of higher error rates or older sectors, especially if some modules can be powered down for efficiency.
• Motivation to Combine: Given a parallel architecture (Huang), and the motivation to adapt to varying error rates across sectors (from Combination 2), a PHOSITA would naturally consider dynamically assigning these parallel resources (error detection and correction sub-modules) to optimize performance and power. If a sector has a high error rate, dedicating more powerful or additional error correction sub-modules to it, or changing which error detection sub-module processes it, would be a logical step to improve efficiency and maintain data integrity. This is a "known technique" applied to similar devices to improve them in the same way.

In summary, the individual elements of parallel error detection, separate error correction modules, dynamic adaptation of coding rates, and monitoring flash memory age/error rates were present in the prior art. A PHOSITA would have been motivated to combine these elements to address the well-known challenges of flash memory degradation, aiming for improved reliability, longevity, and efficiency in flash memory systems.