US 6788602

I'll search for authoritative records on US 6788602, including any 2026 CAFC activity.

Let me check the specific CAFC appeal docket and any 2026 activity.

US Patent 6,788,602 — Verification Summary

Important caveat up front: I could not directly query USPTO PatentCenter/PAIR or the CAFC's PACER/CM-ECF dockets. My searches surfaced Google Patents, Justia, the Stanford NPE Litigation Database, Plainsite, and Docket Alarm. I found no 2026 Federal Circuit docket activity tied to patent number 6788602. Everything below that is sourced comes from those secondary databases plus the patent text itself; where I lack authoritative confirmation, I flag it.

Bibliographic data (confirmed by multiple sources)

Abstract

A semiconductor memory device is provided including one or more bit lines, one or more word lines, and a dummy word line coupled to a positive bias. A memory cell and a dummy cell are coupled to a bit line and may be coupled to a word line and dummy word line respectively. Coupling the dummy word line to a positive bias at least during an erase operation prevents the dummy cells from being over-erased, which occurs when the dummy word line is coupled to ground.

Independent claims — plain language

Claim 1 (semiconductor memory device): A memory device with (a) a memory cell, (b) a dummy word line arranged at an edge of a memory array and coupled to the memory cell, (c) a control logic that supplies a positive bias to the dummy word line during an erase operation, and (d) at least one bit line coupled to the memory cell.

Claim 7 (semiconductor memory array): An array having a memory cell; at least one bit line running in a first direction and coupled to the memory cell; and at least one dummy word line arranged at an edge of a memory array, running in a second direction perpendicular to the bit line, and coupled to the memory cell — wherein a positive bias is selectively supplied to the dummy word line at least during erase operation.

Claim 11 (method of forming a semiconductor memory device): Steps of coupling a bit line to a memory cell; providing a dummy word line at an edge of a memory array; coupling the dummy word line to the memory cell; and supplying a positive bias to the dummy word line. (Note: despite the "forming" preamble, the recited steps are fabrication/connection and biasing steps rather than a pure operating method — worth flagging if claim scope is ever at issue.)

Dependent claims in brief

• 2–3: column decoder driving the bit line; sense amplifier coupled to the bit line.
• 4–5: word line perpendicular to the bit line coupled to another memory cell; row decoder driving that word line.
• 6: control logic continuously supplies the positive bias.
• 8–10: column decoder on the bit line; word line in the second direction coupled to another memory cell; row decoder on that word line.
• 12–15: second word line/bit line combination, with first voltage to bit line and second to word line; first > second (erase) or first < second (program).
• 16–17: positive bias continuously supplied; positive bias greater than zero volts during programming operations.

Technical gist

The problem: dummy word lines at the array edge are conventionally tied to ground, so the dummy cells are perpetually weakly erased → over-erasure → bit-line ("BD") leakage during reads of real cells. The fix: bias the dummy word line positive (specifically stated as >2.5 V during erase in one embodiment; examples at 2.6 V and 3.7 V during erase, ~0 V during programming), which weakly programs the dummy cells instead. The spec's measured data claim leakage increase after 30,000 cycles falls from ~0.28 µA (prior art, grounded dummy WL) to ~0.00044 µA (2.6 V) or an actual decrease (~0.00021 µA) at 3.7 V, including after 4-hour/150 °C bake.

Litigation / post-grant history (from the patent record)

• Macronix Int'l Co., Ltd. v. Toshiba Corp. et al, No. 3:17-cv-00462 (S.D. Cal., filed Mar. 7, 2017) — Stanford NPE Litigation Database lists this as the only civil case involving 6788602.
• ITC Investigation 337-TA-1046 (Google Patents lists it under this family).
• IPR2017-01864, Toshiba Corp. et al. v. Macronix Int'l Co., Ltd., filed July 26, 2017 — the patent record indicates Settlement (petitioners Toshiba Corporation, Toshiba Memory Corporation, Toshiba America Electronic Components).
• CAFC appeal 18-2316 — listed on the Google Patents family page. I could not independently verify from search results which order was appealed or the outcome; treat the linkage as reported-by-database rather than confirmed.

Uncertainty flags

• No USPTO-maintained litigation or CAFC docket entries for 2026 involving 6788602 appeared in my searches. That is a negative search result, not proof of absence — I did not have direct docket access.
• The Stanford NPE database returned only one case; ITC/CAFC entries come from aggregator labels, so the full litigation history may be incomplete.
• Note the discrepancy between the dates supplied to me (system date 2026-09-30; prompt-stated date April 26, 2026). Neither affects the patent's status, which is expired.

I'll research litigation involving US patent 6788602. Let me start with searches across the sources you named.

Let me dig into the specific cases identified.

Litigation Involving U.S. Patent No. 6,788,602

Important scoping note first: I searched for the exact number 6788602 (and the corresponding U.S. Patent No. 6,788,602, "Memory Device and Operation Thereof," Macronix International Co., Ltd.). I excluded results for similar numbers (e.g., the frequently co-asserted '360 patent = 6,552,360 and '417 patent = 8,035,417). Findings below.

The Stanford NPE Litigation Database lists exactly one district court case involving this patent, and all known assertions of the '602 patent arose from a single, consolidated dispute between Macronix and Toshiba. There is no evidence of any assertion of this patent by an NPE/non-practicing entity.

1. Macronix International Co., Ltd. v. Toshiba Corporation et al.

Sources: Stanford NPE Litigation Database (https://npe.law.stanford.edu/patent/6788602); PlainSite docket (https://www.plainsite.law/courts/california-southern-district-court/macronix-international-co-ltd-v-toshiba-corporation-et-al/5pm4ga8ha/).

2. In the Matter of Certain Non-Volatile Memory Devices and Products Containing Same — ITC Inv. No. 337-TA-1046

'602-specific procedural history:

• April 27, 2018 — ALJ Initial Determination: No violation of Section 337. Among other findings, the ALJ found the accused products do not directly infringe the asserted claims of the '602 patent, and found Macronix had not established a domestic industry.
• October 9, 2018 — Commission determination: The Commission reviewed and reversed in part. Specifically, it (1) reversed the ID's finding that the accused products do not directly infringe the asserted claims of the '602 patent (holding the ID "erroneously transforms apparatus claims into method claims via claim construction" and that "coupled to" requires only a structure providing an electrical path), (2) affirmed the ID's indirect-infringement and invalidity findings as to the '602 patent, and (3) reversed the ID's finding that Macronix failed to establish a domestic industry in the process of being established. The Commission found a violation of Section 337 and issued a limited exclusion order and cease and desist orders.
• November 13, 2018 — Remedial orders rescinded: In view of the Macronix–Toshiba settlement agreement, the Commission found the conditions justifying the remedial orders no longer existed and rescinded them under 19 U.S.C. § 1337(k) and 19 C.F.R. § 210.76(a) (published Nov. 19, 2018).

Sources: Federal Register 82 FR 17687 (Apr. 12, 2017); ALJ ID (Apr. 27, 2018, public version); Federal Register Nov. 19, 2018; Oblon/Mondaq summary (https://www.mondaq.com/unitedstates/international-trade-investment/[754630](/patent/754630)/).

3. Toshiba Corporation v. Macronix International Co., Ltd. — IPR2017-01864 (PTAB)

(An administrative trial, not district court litigation, but it is the IPR challenging the '602 patent and is a "known proceeding" involving it.)

Sources: Patexia case summary (https://services.patexia.com/lawsuits/Toshiba-Corporation-v-Macronix-International-Co-Ltd-id-76901); PTAB filings via Docket Alarm; Google Patents legal-events entry for IPR2017-01864.

4. Court of Appeals for the Federal Circuit — Case No. 18-2316

Google Patents' "litigation" section for US6788602 lists a U.S. case filed in the Court of Appeals for the Federal Circuit, Case No. 18-2316 (source: Unified Patents). I could not independently confirm the parties, the lower proceeding appealed from, or the disposition of this appeal through the searches I ran, and I will not speculate. Given the timing (2018) and the parties' settlement of the ITC and district court matters in October 2018, this is plausibly an appeal arising out of the related '602/'360/'417 dispute, but that is an inference, not a confirmed fact. I recommend verifying directly via PACER/CM-ECF for the Federal Circuit docket.

Related items (flagged, not counted)

• IPR2017-01632 (Toshiba v. Macronix, PTAB, filed June 19, 2017) challenges U.S. Patent No. 8,035,417, not 6,788,602 — it is part of the same dispute but is not litigation "involving 6788602."
• A joint motion in IPR2017-01632 refers to "IPR2018-01864 ... which challenges U.S. Patent No. 6,788,602." Per your instruction to interpret identifiers literally, I note it as written; however, on its face this appears to be a typographical reference to IPR2017-01864, since IPR2018-01864 does not otherwise appear in the record for the '602 patent. Flagging rather than auto-correcting.
• Macronix v. Phison Electronics — reports indicate Macronix also sued Phison in 2018 over Phison products incorporating Toshiba flash memory. I did not confirm that the '602 patent was asserted in that case; treat it as unverified for '602 purposes.

Settlement outcome (context for all '602 matters)

The three U.S. fora above (S.D. Cal., ITC, and PTAB) were resolved by a Macronix–Toshiba settlement signed around October 4, 2018, with final contracts completed by October 9, 2018. Reported terms: Toshiba (covering Toshiba Corporation, Toshiba Memory Corporation, Toshiba America, Inc., Toshiba America Electronic Components, Inc., Toshiba America Information Systems, Inc., and Toshiba Information Equipment (Philippines), Inc.) agreed to pay Macronix US$40 million for the U.S. disputes — US$80 million total including a prior US$40 million settlement for non-U.S. disputes — plus a cross-license of approximately 30 patents each. Macronix characterized the ITC outcome (Oct. 9, 2018) as a favorable determination that Toshiba infringed its patents. (Sources: Macronix/TWSE material information disclosures, Oct. 8 & 11, 2018; Taiwan and Japanese trade press.)

Summary answer to your question

Yes, litigation involving US 6,788,602 is known, and it is confined to a single dispute:

1. Macronix International Co., Ltd. v. Toshiba Corporation et al., No. 3:17-cv-00462, S.D. Cal., filed March 7, 2017 — stayed, dismissed Oct. 11, 2018 (settlement).
2. ITC Inv. No. 337-TA-1046, filed March 7, 2017 — Commission found a Section 337 violation (Oct. 9, 2018) and issued exclusion/cease-and-desist orders; orders rescinded Nov. 13, 2018 after settlement.
3. IPR2017-01864, PTAB, filed July 26, 2017 — terminated Oct. 17, 2018 (settlement); no final written decision.
4. CAFC No. 18-2316 — listed by Google Patents/Unified Patents; parties and disposition unverified in my search.

If you need the CAFC appeal details confirmed, I can dig further into the Federal Circuit docket and the ITC/PTAB appeal records — just say the word.

I'll pull authoritative records on the one proceeding the structured feed appears to have missed, plus the related appeal.

Key details are emerging. Let me nail down the termination decision, the CAFC appeal, and whether any other proceeding exists.

Proceedings overview

The canonical structured feed says zero AIA proceedings; the patent's own record says one. Before answering, I have to flag a direct contradiction with the "PTAB proceedings on file" block supplied to me. The Google Patents record for US 6,788,602 (fetched 2026-09-30, https://patents.google.com/patent/US6788602/en) contains an explicit legal-events entry: "2017-09-12 — IPR — Aia trial proceeding filed before the patent and appeal board: inter partes review… TRIAL NO: IPR2017-01864 — Opponent name: TOSHIBA CORPORATION, TOSHIBA MEMORY CORPORATION, T…", and a litigation entry labelled "(Settlement)." I located and corroborated that proceeding on the merits (petition, institution decision, SAS-modified institution, supplemental briefing, joint termination motion). Treat the ODP "no proceedings" result as an ingest gap, not as evidence of absence.

Bottom line: one proceeding, IPR2017-01864, instituted on 2018-01-29, terminated by joint settlement on 2018-10-17 with no Final Written Decision. That means not a single claim of US 6,788,602 was canceled, confirmed, or even adjudicated by the PTAB. The patent remains intact as issued — but it also expired 2022-09-17, its FCC/licensing window has closed, and the settlement stripped the only petitioner of any estoppel. Both halves of that sentence matter to a defendant today.

IPR2017-01864 — Toshiba Corporation, Toshiba Memory Corporation, and Toshiba America Electronic Components, Inc. v. Macronix International Co., Ltd.

(This is the only proceeding; nothing was invalidated, so nothing outranks it.)

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2017-07-26 (Notice of Accord Filing Date 2017-08-15, Paper 6)
• Status: "Terminated-Settled" (verbatim from the structured aggregator records). Plain English: instituted, fully briefed, oral-argument requests on file, and then killed by a joint motion to terminate roughly seven weeks before the statutory FWD deadline. No Final Written Decision issued.
• Judge panel: Jason M. Repko (author of the final disposition), Jennifer S. Bisk, Ken B. Barrett (reported at https://services.patexia.com/lawsuits/Toshiba-Corporation-v-Macronix-International-Co-Ltd-id-76901; also corroborated by Docket Alarm's panel-filtered index and https://ai-lab-cl-prod.azurewebsites.net/case/ptab/IPR2017-01864/toshiba-corp-v-macronix-intl-co-ltd). Note the aggregators label Repko as "Judge Writing the Final Decision" — there was no FWD; Patexia's "Decision Date Oct 17, 2018" is the termination date.
• Petition grounds: Claims 1–12 and 16 challenged. Two grounds, both § 102/§ 103 only — no § 112 ground was asserted:
  • Ground 1 — § 102 anticipation by Kurata (Japanese Published Patent Application H10-275484; Exs. 1003/1004). Petitioner mapped Kurata's edge "gate signal line SV" (5 V during erase) onto the claimed biased dummy word line.
  • Ground 2 — § 103 obviousness over Maruyama (US 6,272,049) in view of Lee (US 6,258,668) (Exs. 1005/1006). Maruyama supplied the edge dummy word lines with "a predetermined potential"; Lee supplied the conventional FN-tunneling word-line erase mechanism to resolve Maruyama's ambiguity. Petitioner's expert: Dr. Noel R. Strader II (Ex. 1007). Patent Owner's expert: Dr. David Kuan-Yu Liu (Exs. 2001/2005). Petitioner's counsel: DLA Piper (Limbach, Park, Sekimura); Real parties-in-interest included Toshiba America, Inc., Toshiba America Information Systems, Inc., and Toshiba Information Equipment (Philippines), Inc.
• Institution decision: 2018-01-29 (Paper 10) — partially instituted. The Board instituted only on Ground 2 (Maruyama + Lee obviousness) and refused the Kurata anticipation ground, finding "that Petitioner has not demonstrated a reasonable likelihood of prevailing on this ground of unpatentability." That finding is quoted from the institution decision at Paper 10, pp. 9, 12, 16, as recited verbatim in Macronix's Supplemental Response (https://www.docketalarm.com/cases/PTAB/IPR2017-01864/Inter_Partes_Review_of_U.S._Pat._6788602/docs/06-19-2018-Patent_Owner/Response-16-Patent_Owners_Supplemental_Response.pdf).
• Post-SAS modification: Following SAS Institute, Inc. v. Iancu, 138 S. Ct. 1348 (2018), the Board modified its institution decision (Paper 13, p. 2) to bring the previously-denied Kurata § 102 ground into trial as well, and authorized supplemental briefing (Paper 14, pp. 2–3). Macronix filed a Supplemental Response on 2018-06-19 (Paper 16) attacking Kurata on three grounds: (i) impermissible piecemeal combination of Kurata's separate embodiments (Net MoneyIN v. VeriSign, 545 F.3d 1359, 1369–71 (Fed. Cir. 2008)); (ii) unsupported inherency allegations; and (iii) a conclusory expert declaration. It also argued Kurata's "gate signal line SV" is neither a "dummy word line" nor "arranged at an edge of a memory array," and does not disclose a "control logic" (claims 1–6), a "column decoder" (claims 2, 8), or a "continuous[]" positive bias (claims 6, 16). Petitioner replied (Paper 25, 2018-09); Patent Owner sur-replied (Paper 30, 2018-10-03). The parties also cross-briefed constructions of "memory array" from the parallel ITC proceeding (Papers 22, 23), and both sides requested oral hearing (Papers 26, 27, September 2018).
• Final Written Decision: None. It never issued. Per 35 U.S.C. § 318(a) the Board was not obligated to decide the merits once the case settled pre-merits. Consequently there is no claim-level verdict to report — no independent claim canceled, no dependent claim sustained, no panel reasoning on patentability. Any statement that claims 1–12 or 16 "survived an IPR" is technically true but substantively hollow: they were never decided.
• Settlement / termination: 2018-10-12 — Joint Motion to Terminate (Paper 31) and Joint Request to File Settlement Documents as Business Confidential Information (Paper 32); proceeding closed 2018-10-17. The Board entered judgment and terminated without rendering a final written decision, and the settlement agreement was treated as confidential business information under 35 U.S.C. § 317(b) and 37 C.F.R. § 42.74(c) — the substantive terms (royalty, covenant not to sue, cross-license) are not public. What is public: the settlement was global. The ITC rescinded the remedial orders in Inv. No. 337-TA-1046 on 2018-11-13, expressly on the ground that "In view of the settlement agreement between Macronix and Toshiba, the Commission finds that the conditions justifying the remedial orders no longer exist" (83 Fed. Reg. (2018-11-19), https://www.govinfo.gov/content/pkg/FR-2018-11-19/pdf/FR-2018-11-19.pdf). That ends the district court case (Macronix Int'l Co. v. Toshiba Corp., No. 3:17-cv-00462 (S.D. Cal., filed 2017-03-07)) mid-flight as well.
• Appeal: None from this proceeding — nothing was appealable, since no FWD issued. Separately, the Google Patents family page lists CAFC No. 18-2316 for this family; I could not verify that docket's subject matter, parties, or disposition from the sources available to me, and there is no FWD in IPR2017-01864 that could have been appealed on 2018 timing. Treat 18-2316 as unverified and do not cite it as IPR-appeal authority. (Note the trap: an unrelated 2019 CAFC opinion, Papst Licensing v. Apple, 18-1987, addresses a different IPR2016-01864 — different patent, different parties. Do not conflate.)
• Defensive value: Low, in both directions. You cannot walk into court and say "claims 1–12 and 16 were held valid" (no FWD ever issued), and the patent owner cannot say "my claims survived an IPR challenge" (the Board never reached the merits, and it had already found the Kurata ground failed the reasonable-likelihood threshold). The durable defensive asset from this episode is not the PTAB outcome — it is three undecided prior-art theories that remain live (see estoppel discussion below) plus the ITC's 2017–2018 construction fight over "memory array," which was contested between these same parties and is now sitting in the public record, unsettled.

Strategic summary

Claim status: everything is UNTESTED. Claims 1–12 and 16 were challenged and then abandoned via settlement — never canceled, never confirmed. Claims 13, 14, 15, and 17 were never challenged at all in any AIA proceeding. So the complete declared claim set (1–17) stands exactly as issued on 2004-09-07. There is no eIPR/IPR certificate under § 318(b) to point to, because no FWD ever issued. Anyone advising a client "claim 1 is dead" or "claims 1–5 were canceled" is simply wrong — and the opposite error, treating the patent as "hardened" because it "survived an IPR," is equally wrong. It survived nothing; it settled.

Estoppel: the single most important fact. Because IPR2017-01864 was terminated by joint request under 35 U.S.C. § 317(a) before the Office decided the merits, no § 315(e) estoppel attached to Toshiba or its real parties in interest. That is the statute's own text, not a gloss: termination under § 317 means "no estoppel under section 315(e) shall attach to the petitioner, or to the real party in interest or privy of the petitioner." Two practical consequences for a current defendant: (1) Toshiba (and its RPI/privies) remain free to raise Kurata, Maruyama + Lee, or anything they reasonably could have raised, in any later forum; and (2) conversely, you get no benefit from Toshiba's work product — you are not a "privy" unless you actually are, and the § 315(e)(2) bar cuts only against petitioners, not against strangers to the proceeding. For a defendant not in Toshiba's chain, every ground is fair game, subject only to the § 315(b) one-year bar running from service of a complaint.

Pattern signals: this was a two-front, single-petitioner campaign that settled globally. Toshiba was a serial but disciplined petitioner — it filed IPR2017-01864 on the '602 patent and, on the same day-of-service theory, IPR2017-01632 on sibling US 8,035,417 (same field, same counsel at DLA Piper, overlapping panel members, Tech Center 2800). No defensive aggregator (Unified Patents, RPX, etc.) appears anywhere in the chain — this was competitor-versus-competitor, not troll-versus-industry. Macronix, not a troll, asserted three patents ('602, '360/US 6,552,360, '417) against Toshiba simultaneously in the ITC (337-TA-1046, instituted 2017-04-12) and the S.D. Cal., then resolved everything in the October 2018 global settlement. Macronix did not pursue any PTAB appeal, and there is no evidence of a second, follow-on petitioner on the '602 patent after the 2018 settlement.

The dispositive practical point for 2026: the patent is expired and the damages window is closed. Per the patent record, the adjusted expiration is 2022-09-17 and the legal status is Expired – Lifetime. Even setting aside that no claim was ever invalidated, an expired patent cannot support prospective injunctive relief, and the recoverable period for past damages is bounded by the six-year lookback under § 286 (i.e., roughly 2020-09-30 forward) against an expiration ceiling of 2022-09-17 — a narrow, two-year sliver. Combined with the § 315(b) one-year clock for anyone served in 2017, the realistic defensive posture is: threat value only.

Recommended next steps

1. Correct the record internally before anything else. The "PTAB proceedings on file" block returned zero for this patent, and that is incorrect. Reconcile your PTAB source against the patent's own legal-events trail (IPR2017-01864, terminated 2018-10-17). If your docketing, FTO, or licensing tooling relies on the empty result, it will under-report this patent's history.
2. There is no FWD to link. I will not manufacture one. The absence of a Final Written Decision is the headline finding, and the correct citation for the disposition is the 2018-10-12 Joint Motion to Terminate (Paper 31) and the 2018-10-17 termination/judgment entry, retrievable via PTAB E2E (https://ptacts.uspto.gov/ptabs/apps/patent-trial-and-appeal-board/proceedings) and indexed at https://www.docketalarm.com/cases/PTAB/IPR2017-01864/Inter_Partes_Review_of_U.S._Pat._6788602/. If you need the termination order itself, pull it from E2E — I sourced the date and posture from aggregator dockets plus Macronix's own filings, which is strong but not a substitute for the paper.
3. If you are a defendant and hold a demand letter citing claims 1–12 or 16: your argument is not "these claims were invalidated." It is: (a) the patent expired 2022-09-17, (b) the only asserted-claim challenge was abandoned without adjudication, so the patent owner can claim no PTAB validation to bolster the presumption of validity, and (c) the Board already found on 2018-01-29 that the Kurata § 102 ground failed even the reasonable-likelihood threshold — a low bar — meaning the anticipation theory is at minimum contested and the patent owner's own 2018-06-19 supplemental response gives you a fully developed rebuttal roadmap (piecemeal-combination under Net MoneyIN; inherency defects; conclusory expert testimony).
4. Prior-art grounds still available to you: all of them. Kurata (JP H10-275484), Maruyama (US 6,272,049), and Lee (US 6,258,668) are unencumbered by estoppel against a non-privy defendant, and — importantly — you are not limited to them. The petition asserted only § 102/§ 103; no § 112 ground was ever pleaded, so written-description/enablement attacks on the "control logic," "arranged at an edge of a memory array," and "continuously supplies" limitations are untouched territory. Note also that claim 11's "method of forming" preamble recites biasing steps rather than fabrication steps (flagged in the earlier-generated summary) — an indefiniteness/mixed-category argument is unexplored.
5. Verify the estate's licensing status. The global settlement and the 2018 ITC rescission mean Toshiba is very likely licensed or covenanted. If a current assertion targets you in the same product space, confirm whether the settlement's scope (confidential) or a covenant flowing to Toshiba's supply chain moots the exposure — and whether Macronix retains any unlicensed targets at all.
6. Do not rely on CAFC 18-2316 without pulling the docket. It is listed on the family page but unverified as to parties, issues, and outcome, and it cannot be an appeal of this IPR because there was no FWD. Confirm via PACER/CM-ECF or CourtListener before citing.

Confidence and gaps. High confidence: filing date, challenged claim set, both grounds, the 2018-01-29 partial institution on Ground 2 only, the SAS-driven reinstatement of the Kurata ground, the 2018-06-19 supplemental response, the October 2018 joint termination, and the 2018-11-13 ITC rescission. Medium confidence: the exact panel name spelling (sources render it "Jennifer S. Bisk" / "Jennifer B. Bisk" inconsistently) and the precise termination order date (2018-10-17 per aggregators; the motion itself was 2018-10-12). Unknown / unverifiable with available access: the confidential settlement terms; the substance and disposition of CAFC No. 18-2316; and the full text of the institution decision and Papers 13–14, which I know only through Macronix's quotations of them. I did not have direct USPTO PTAB E2E or PACER access, and the ODP feed for AIA trials on this patent came back empty.

I'll search for assignment records and ownership chain evidence for US 6788602.

Now let me check for any post-issuance transfers, NPE listings, and the current owner status.

Let me check for any post-issuance transfers and confirm Macronix's current operating status.

Assignment & Ownership Chain — US 6,788,602 B2

Data-access caveat (carried forward): I again could not query USPTO PatentCenter or the Assignment Search API directly. The chain below is reconstructed from the recorded-assignment entry as surfaced by Plainsite's mirror of USPTO Assignment 13180/360, cross-checked against the Google Patents legal-events table and against a litigation document in which the patent owner states its own chain of title. Where a field is unverified, I say so.

Inventors

Pattern notes.

• All three inventors assigned to the same employer on the same date, and the assignment was filed with the application on the filing date (executed 2002-07-29; recorded 2002-08-09, the same day the application was filed). That is the signature of a standard employee "assignment-of-assignors-interest" filed in the application package, not a negotiated acquisition.
• Employer attribution is inferred, not documented: the assignment is from three individuals to Macronix and nothing on its face recites employment. Taiwanese fabless/IDM practice almost always routes inventor assignments through the employer preregistration, and the inventors' subsequent filings are consistent with Macronix employment — but I did not find a separate employment-agreement or inventor-declaration record confirming it.
• No mass-departure pattern detected. There is no recorded re-assignment, and no evidence surfaced of any of the three leaving Macronix within 12 months of filing. Note that this signal is normally undetectable from the assignment record alone — departure from an employer is not a recorded event, so this should be read as "no evidence found," not "confirmed no departures."

Original assignee

Macronix International Co., Ltd. (also rendered "Macronix International Company, Ltd." on the 2002 assignment face), No. 16 Li-Hsin Road, Science-Based Industrial Park, Hsinchu, Taiwan.

• Primary business: Integrated device manufacturer (IDM) of non-volatile memory — NOR Flash, NAND Flash, and mask ROM. Founded 1989 in Hsinchu Science Park.
• Did they ship a product embodying the claims? The claims cover a memory array architecture with a positively-biased dummy word line. Macronix is a volume NOR/NAND/ROM manufacturer whose arrays use edge dummy word lines, so the claims read on its core product line rather than on a standalone article. In its own litigation papers Macronix describes itself as "a leading innovator of non-volatile memory semiconductor solutions" and recites R&D spend of >$150M (2015), >$200M (2014) and >$170M (2013). This is an operating-company patent.
• Current status: Operating. Publicly listed (TWSE: 2337). Active R&D and patent filing through at least 2025 — USPTO PatentsView-derived data shows ~1,381 US grants assigned to Macronix in the 2015–2025 window, ranking #310 by volume, with primary CPC concentration in G11C (static stores) at 627 patents. Its 2022 sustainability report states 8,894 granted patents worldwide as of end-2022.
• No bankruptcy, no dissolution, no merger. Nothing in the record indicates a Chapter 7/11, an asset fire-sale, or an entity conversion.

Assignment timeline

The Assignment Center record for this patent contains exactly one recorded assignment. The full chain is:

• 2002-07-29 (executed) / recorded 2002-08-09 — Reel 013180/0360
  • Conveyance: Assignment of Assignors Interest (original inventor assignment)
  • Assignors: Jen-Ren Huang; Ming-Hung Chou; Hsin-Chien Chen (three individual inventors, joint)
  • Assignee: Macronix International Company, Ltd., Science-Based Industrial Park, Hsin-chu, Taiwan, ROC
  • Correspondent: Yitai Hu, Finnegan, Henderson, Farabow, Garrett & Dunner, LLP, 1300 I Street, N.W., Washington, D.C. 20005. This is the sole correspondent of record in this chain. I found no recurrence of Yitai Hu as a recording correspondent across other patents in my searches — he appears once here. A single appearance is not a finding under your recurrence test, and Finnegan is a large general-practice IP firm that does both operating-company and NPE work; nothing about this correspondent suggests a shell-entity recording mill.
  • Context: Ordinary employee-to-employer assignment filed with the original application — not an acquisition, reorg, securitization, or transfer-to-asserter.

No further recorded conveyances exist. Confirming negative evidence:

• The Google Patents legal-events table for US 6,788,602 lists only: the 2002-08-09 assignment; patent grant (2004); maintenance-fee payments at the 4-year (2007-12-11), 8-year (2011-09-22) and 12-year (2015-12-24) annuities; and the 2017 IPR petition. No post-issuance assignment, security agreement, merger, change of name, or license record appears. Fee payments by the original owner are themselves evidence that Macronix held title continuously through at least 2015.
• Macronix's own complaint in Macronix Int'l Co., Ltd. v. Toshiba Corp. et al., No. 3:17-cv-00462 (S.D. Cal., filed 2017-03-07) pleads at ¶27: "Macronix owns by assignment the entire right, title, and interest in and to the '602 Patent." That is a party admission of continuous ownership fifteen years after the original assignment.
• No assignment to any Macronix IP-holding subsidiary (e.g., no "Macronix IP Holdings" vehicle) appears in the record. Macronix is known to litigate in its own name together with Macronix America, Inc. as a wholly owned operating subsidiary — which is what the ITC and district-court pleadings show — rather than through a licensing SPV.

If this were a chain that no longer had records, I would stop here. It does have records — but only the original one, and that is itself the finding: title has never left the original assignee.

Timeline diagram

timeline
    title Ownership of US 6788602
    2002 : Filed by Huang Chou and Chen
         : Assigned to Macronix
    2004 : Patent issued to Macronix
    2007 : First maintenance fee paid
    2011 : Second maintenance fee paid
    2015 : Third maintenance fee paid
    2017 : Macronix sues Toshiba
         : Toshiba files IPR
    2022 : Patent term expires

NPE / troll-pattern signals

Verdict

Operating-company assertion.

Justification. The only recorded assignment is Reel 013180/0360 (executed 2002-07-29, recorded 2002-08-09), an ordinary employee-to-employer assignment from inventors Huang, Chou and Chen to Macronix International Co., Ltd. — an operating Taiwanese non-volatile-memory IDM (TWSE: 2337) that is still filing and being granted US patents as of 2025. Title never left Macronix: no post-issuance conveyance, security interest, or change-of-name record exists, and Macronix paid the 4-, 8- and 12-year maintenance fees in 2007, 2011 and 2015 in its own name. Macronix then asserted the '602 patent itself, as plaintiff, against a direct competitor in Macronix Int'l Co., Ltd. v. Toshiba Corp. et al., No. 3:17-cv-00462 (S.D. Cal., filed 2017-03-07), pleading that it "owns by assignment the entire right, title, and interest" — and the Stanford NPE Litigation Database classifies the asserter as a "Product company," not an NPE. A serial litigant is not the same thing as a non-practicing entity; this is a product company suing competitors over its own R&D output.

Verification links: assignment search — https://assignment.uspto.gov/patent/index.html and https://assignmentcenter.uspto.gov/ (search patent number 6788602); full text and legal events — https://patents.google.com/patent/[US6788602B2](/patent/US6788602B2)/en.

Residual uncertainty. (a) I could not query the Assignment Center directly, so an unrecorded or recently-recorded post-2017 conveyance cannot be affirmatively excluded — the Google Patents events table is a mirror and can lag. (b) The patent's term has expired (adjusted expiration 2022-09-17 per Google Patents; status "Expired – Lifetime"), so any residual assignment question is largely academic unless a pre-expiration damages tail is at issue. (c) Whether the three inventors remained at Macronix past 2003 is not derivable from the assignment record; treat the "no departures" observation as a negative search result only.

I'll research the prior-art references cited on the face of US 6,788,602, verifying each against USPTO/Google Patents records.

Let me verify the remaining cited references individually.

Now let me check the remaining cited references and the IPR invalidity grounds.

Prior Art Analysis — US 6,788,602 ("Memory device and operation thereof")

Scope and method note. I could not open USPTO PatentCenter/PAIR directly; my identifier-level searches hit Google Patents (which mirrors the USPTO front-page citation data for this patent), FreePatentsOnline, and patent-image PDFs. Results are reported literally, with no auto-correction of numbers. One flag up front: the front page of US 6,788,602 lists "Patent Citations (13)" while an earlier aggregation of the same page lists "Citations (11)" — the 13-item list adds US 5,566,386 and US 5,592,427 (the two additional members of the Fujitsu 5,402,380 family). I treat the 13-item set as the full examiner-cited set and note the 11-item set is a subset.

Also note: the date supplied in this task (April 26, 2026) differs from the system date used in the earlier-generated sections (2026-09-30). This does not affect the prior-art analysis — the patent is expired and all cited art predates filing.

A. The patent under examination (identifier confirmation)

• US 6,788,602 B2, appl. 10/214,770, filed 2002-08-09, granted 2004-09-07, "Memory device and operation thereof," Macronix International Co., Ltd.; inventors Jen-Ren Huang, Ming-Hung Chou, Hsin-Chien Chen.
• Independent claims 1 (device), 7 (array), 11 (method); dependents 2–6, 8–10, 12–17.
• Point of novelty (relevant to every §102 question below): a dummy word line arranged at the edge of a memory array that is selectively/continuously supplied a positive bias at least during an erase operation (spec: >2.5 V; embodiments 2.6 V and 3.7 V during erase, ~0 V during program) so the dummy cells are weakly programmed rather than over-erased.

B. Most relevant prior art — ranked conclusion first

Applying a limitation-by-limitation test to claims 1, 7 and 11, none of the examiner-cited references appears to disclose all limitations of any independent claim simultaneously — in particular, none discloses "control logic for supplying a positive bias to the dummy word line during an erase operation" in combination with an edge-arranged dummy word line. The cited art is therefore best characterized as §103 material (sub-combinations), not §102 material, except as noted for individual subordinate claims.

Ranked by relevance to the '602 claims:

C. Reference-by-reference analysis

1. US 6,574,133 B2

• Full citation: US 6,574,133 B2, "Nonvolatile ferroelectric memory device having dummy cell circuit," Kabushiki Kaisha Toshiba (Takashima et al.).
• Dates: priority/filed 2000-09-05; granted 2003-06-03.
• Disclosure (verified from the specification text): a ferroelectric memory whose dummy cell circuit generates the reference bit-line potential; dummy cell portions with paraelectric capacitors; a dummy word line (DWL), dummy plate lines, and control circuits for the dummy cell; dummy cells connected to bit lines via selection transistors.
• §102 potential: Does not anticipate claims 1, 7 or 11 — it lacks any control logic supplying a positive bias to a dummy word line during erase, and lacks an edge-of-array dummy word line as claimed. It is nonetheless the strongest cited reference for the "dummy word line + dummy cell + bit line" sub-combination (claims 1, 4, 7, 9, 11, 12 in their structural aspects).
• Timing caveat: its grant date (2003-06-03) is after the '602 filing date (2002-08-09), so it cannot be §102(a)/(b) art; its only §102 theory is pre-AIA §102(e) (U.S. patent granted on an earlier-filed application). Worth flagging because a superficial date check would wrongly treat it as full prior art.

2. US 5,659,503 A

• Full citation: US 5,659,503 A, "Nonvolatile semiconductor memory having an improved reference voltage generating circuit," NEC Corporation.
• Dates: filed 1995-06-29; granted 1997-08-19.
• Disclosure (verified): memory array of floating-gate cell transistors with word lines (WL1–WLm) and bit lines (BL1–BLn); a dummy cell (DMC) used to generate reference voltage Vref; the dummy cell's control gate is "ceaselessly" held at a selection-level voltage (the power-supply voltage Vcc) during reading; reference voltage compared with the selected bit-line level; the spec expressly notes read-out voltage drift with cumulative write/erase count.
• §102 potential: The positive-level dummy gate during read is the closest cited teaching to the claimed positive bias on a dummy word line, but (i) it is a read condition, not erase, and (ii) the '602 claims require the dummy word line to be at the array edge. Accordingly it does not anticipate claims 1, 7 or 11; it is a serious §103 reference against the "positive bias to dummy word line" element.

3. US 5,463,587 A

• Full citation: US 5,463,587 A, "Nonvolatile semiconductor system," Seiko Epson Corporation.
• Dates: filed 1992-03-25; granted 1995-10-31.
• Disclosure (verified): memory transistors with floating-gate/control-gate; at least one dummy memory transistor with a threshold-voltage-change speed different from the memory transistor; means for injecting/releasing electrons into the dummy transistor and detecting its threshold to prevent over-erasing; the background expressly states that over-erasure shifts Vt to a depletion state, causing leak current into the bit line and making the cells on that bit line unreadable.
• §102 potential: Same problem as the '602 (over-erase → bit-line leakage) and uses dummy devices, but the fix is threshold-verify on a dummy transistor, not biasing a dummy word line positive during erase. It does not anticipate claims 1, 7, 11; it is a strong §103 reference for motivation to combine and for dependent-claim context (claims 4, 9, 12–15, which recite word-line/bit-line voltage relationships).

4. JP H06-223587 A

• Full citation: JP H06-223587 A, "Nonvolatile semiconductor memory device," Toshiba Corp.
• Dates: filed 1993-01-28; published 1994-08-12.
• Disclosure: Japanese-language nonvolatile semiconductor memory device publication; the title/classification place it in the EEPROM/flash array domain. I was not able to retrieve and read the full text in this run.
• §102 potential: Unverified. At title level it is a candidate for the array/word-line organization of claims 1/4/7/9, but I cannot responsibly assign a claim mapping without the text. Treat as a §103-context citation pending full-text review; note it is a foreign publication, so §102(b)/(a) status depends on its 1994 publication date (it is, on its face, more than one year before the '602 filing).

5. US 6,198,681 B1

• Full citation: US 6,198,681 B1, "Sense amplifier for low voltage memory arrays," Micron Technology, Inc. (inventor Leonard Forbes).
• Dates: filed 2000-02-28; granted 2001-03-06.
• Disclosure (verified): a sense amplifier coupled to first/second bit lines; claim 10 recites bit lines each coupled to memory cells and a dummy cell; claim 12 recites storage cells comprising at least one dummy cell having a predetermined value stored therein; source-follower/current-sink sense circuitry.
• §102 potential: Relevant only to the sense-amplifier and bit-line/dummy-cell aspects — i.e., claims 3 and (in part) claims 1 and 7. It discloses no dummy word line, no array-edge dummy word line, and no erase-time positive bias; it cannot anticipate claims 1, 7 or 11.

6. US 2002/0050616 A1

• Full citation: US 2002/0050616 A1, "Nonvolatile semiconductor memory device with reliable verify operation," Fujitsu Limited.
• Dates: filed 2000-10-30; published 2002-05-02.
• Disclosure: pre-grant publication directed to verify-operation reliability in a nonvolatile semiconductor memory (program/erase verify architecture).
• §102 potential: As a published application published 2002-05-02, before the '602 filing (2002-08-09), it is available as prior art (§102(a); and §102(e)(1) for US-originated publications). It bears on verify/erase-related claims but does not disclose the positive-bias-on-edge-dummy-word-line feature; does not anticipate claims 1, 7 or 11; possible §103 support against claims 12–15 voltage-relationship dependents.

7. JP H11-134881 A

• Full citation: JP H11-134881 A, "Nonvolatile multi-value memory and method of erasing data thereof," Sanyo Electric Co., Ltd.
• Dates: filed 1997-10-31; published 1999-05-21.
• Disclosure: nonvolatile multi-value (multi-level) memory and its data-erase method.
• §102 potential: Relevant to erase methodology aspects that appear in claims 11–15 (erase voltage relationships); it does not disclose a dummy word line at the array edge with an erase-time positive bias. Does not anticipate claims 1, 7 or 11. Full text not retrieved in this run — mapping is provisional.

8. US 5,297,077 A

• Full citation: US 5,297,077 A, "Memory having ferroelectric capacitors polarized in nonvolatile mode," Kabushiki Kaisha Toshiba.
• Dates: filed 1990-03-30; granted 1994-03-22.
• Disclosure: ferroelectric-capacitor nonvolatile memory (cell/plate-line architecture).
• §102 potential: Ferroelectric cell architecture; no dummy word line, no erase-time positive bias. No §102 read on claims 1, 7 or 11; at most background for the memory-cell element (claims 1, 7, 11 in the generic sense).

9. US 5,402,380 A

• Full citation: US 5,402,380 A, "Nonvolatile semiconductor memory device having a status register and test method for the same," Fujitsu Limited.
• Dates: filed 1993-03-17; granted 1995-03-28.
• Disclosure: nonvolatile memory with a status register and associated test method.
• §102 potential: Relates to test/status circuitry, not to dummy word-line biasing. No anticipation of claims 1, 7 or 11. It is, however, catalogued as part of the Fujitsu family below.

10. US 5,566,386 A

• Full citation: US 5,566,386 A, same title as US 5,402,380 (Fujitsu, nonvolatile semiconductor memory device having a status register and test method);
• Dates: filed 1993-03-17 (as listed on the front page); granted 1996-10-15.
• §102 potential: Same assessment as US 5,402,380 — no anticipation of claims 1, 7 or 11. Listed only in the 13-item citation set (absent from the 11-item set), which explains the citation-count discrepancy flagged in Section A.

11. US 5,592,427 A

• Full citation: US 5,592,427 A, "Semiconductor memory having a sense amplifier with load transistors having different load characteristics," Fujitsu Limited.
• Dates: filed 1993-03-17; granted 1997-01-07.
• Disclosure: sense-amplifier load-transistor design.
• §102 potential: Sense-amplifier detail only → at most claim 3 context. No anticipation of claims 1, 7 or 11.

12. US 6,094,371 A

• Full citation: US 6,094,371 A, "Memory device with ferroelectric capacitor," Fujitsu Limited.
• Dates: filed 1998-07-29; granted 2000-07-25.
• Disclosure: ferroelectric-capacitor memory device.
• §102 potential: Ferroelectric cell architecture; no dummy word line and no erase-time positive bias. No anticipation of claims 1, 7 or 11.

13. US 6,111,777 A

• Full citation: US 6,111,777 A, "Ferroelectric memory," Kabushiki Kaisha Toshiba.
• Dates: filed 1998-10-08; granted 2000-08-29.
• Disclosure: ferroelectric memory device/array.
• §102 potential: As with the other ferroelectric references, no teaching of the claimed dummy-word-line erase bias. No anticipation of claims 1, 7 or 11.

D. The prior art actually asserted against the '602 (most probative for §102/§103)

The examiner citations above were not the art that was litigated. In IPR2017-01864 (Toshiba Corp./Toshiba Memory Corp./Toshiba America Electronic Components v. Macronix; filed 2017-07-26; challenged claims 1–12 and 16; terminated 2018-10-17 on settlement, no final written decision), the petitioners relied on two grounds:

1. Anticipation under §102 by Kurata — JP H10-275484.
2. Obviousness under §103 over Maruyama (US 6,272,049) in view of Lee (US 6,258,668).

Per the previously generated litigation section (which I am building on and not repeating), the Board instituted only on the §103 ground initially, rejecting the Kurata anticipation ground; after SAS Institute v. Iancu it modified institution to include Kurata. I could not independently re-verify these three reference numbers or their contents in this run (tool budget exhausted); I therefore report them as recorded in the prior section, flagged as unverified. The key analytic point stands regardless: the only anticipation theory advanced against the '602 in a contested proceeding was a single-reference §102 theory (Kurata), and the Board did not find it reasonably likely to succeed at institution. That is meaningful corroboration for the conclusion in Section B that the '602's independent claims are not readily anticipated.

Also relevant (not prior art, but showing the concept's subsequent footprint): US 6,987,696 B1 (AMD, "Method of improving erase voltage distribution for a flash memory array having dummy wordlines"), which cites the '602 family, and US 2008/0007999 A1 / US 7,652,931 B2 / US 11,009,571 A1 / US 7,830,724 B2 (Samsung, NAND cell strings) citing it. These are post-'602 and cannot be §102 art against it.

E. Bottom line on §102

No single cited reference discloses the limitation that gives the '602 its scope — a dummy word line at the array edge that is driven to a positive bias at least during erase, so the dummy cells are weakly programmed rather than over-erased. Any invalidity case on the independent claims has to run through §103 (e.g., US 5,659,503's positive dummy-cell gate in read + US 5,463,587's over-erase/bit-line-leakage teaching + an edge-dummy-line structure such as US 6,574,133), which is exactly the theory shape the IPR petitioners used — and which never reached a final written decision.

Caveats

• The §102 mappings for JP H06-223587 A and JP H11-134881 A are provisional; I retrieved titles/dates but not full text, so I have not verified their disclosures.
• The asserted IPR art (Kurata JP H10-275484; Maruyama US 6,272,049; Lee US 6,258,668) is carried over from the previously generated litigation section and was not re-verified in this run.
• I did not have direct USPTO PAIR/PatentCenter access; front-page citation data is as mirrored by Google Patents and FreePatentsOnline.
• Claim-scope caution carried over from the litigation section: in the ITC proceeding the Commission reversed the ALJ on claim construction, holding "coupled to" requires only a structural electrical path and that reading the apparatus claims of the '602 as method claims was error. That construction affects how the "coupled to the memory cell" limitations in claims 1/7/11 would be read against any of the above references.

I'll research the specific prior-art references cited in the '602 record, including the IPR grounds of record, before building the §103 analysis.

Let me pull the Kurata ground details and the ITC invalidity findings, plus a couple of the examiner-cited references.

Let me verify the Maruyama reference (U.S. 6,272,049) and pull the ITC invalidity findings.

Obviousness Analysis of U.S. Pat. No. 6,788,602 Under 35 U.S.C. § 103

Scope note. This builds on the two prior sections (patent verification and litigation history) and does not repeat them. Per your instruction, I use the prior-art material of record on the Google Patents page for US6788602 — i.e., the "Citations (11)" / "Patent Citations (13)" lists (the examiner-cited art) — and I supplement it with the prior art actually put in issue in the administrative record (Kurata, Maruyama, Lee), because the § 103 case of record was built on the latter, not the former. I flag explicitly where I am relying on secondary characterizations rather than the primary documents.

A contradiction I must flag at the outset. The task header says "Current Date: April 26, 2026," while the source fetch timestamp and system date are 2026‑09‑30. This does not affect the § 103 analysis (priority date 2002‑08‑09; patent expired 2022‑09‑17), but the date discrepancy remains unresolved from the earlier sections.

1. Framework and critical date

• Priority/critical date: August 9, 2002 (filing date = priority date; no earlier priority claim on the face).
• Governing law: pre-AIA § 102/§ 103 (application filed before March 16, 2013).
• Legal test: Graham v. John Deere factors — scope/content of the prior art, differences between the prior art and the claims, level of ordinary skill, and objective indicia. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), predictable variations, design choices among a finite set of identified solutions, and "obvious to try" combinations are all citable rationales.

Level of ordinary skill (POSITA). From the IPR record, both experts addressed this, but I could not retrieve the exact stipulated definition in this session. Based on the subject matter, the likely definition is a bachelor's degree in electrical engineering (or equivalent) plus roughly 2–3 years of experience in nonvolatile semiconductor memory design, or a master's degree with less experience — i.e., a person familiar with flash EEPROM cell operation, erase mechanisms (Fowler‑Nordheim tunneling and hot‑carrier effects), and the problem of over-erasure. Flag: this is my reconstruction, not a quoted stipulation.

Claim construction issues that drive the § 103 analysis (drawn from the IPR/ITC record, not from my own construction):

2. The prior art of record, tiered by probative value

Tier 1 — examiner-cited art on the face of the patent (the "Prior Art section of this page"):

• US 5,297,077 (Toshiba) — ferroelectric capacitors
• JPH 06-223587 (Toshiba) — nonvolatile semiconductor memory device
• US 5,402,380, US 5,566,386, US 5,592,427 (Fujitsu) — nonvolatile memory with a status register; sense amplifier with load transistors of different characteristics
• US 5,463,587 (Seiko Epson) — nonvolatile semiconductor system
• US 5,659,503 (NEC) — improved reference voltage generating circuit
• JPH 11-134881 (Sanyo) — nonvolatile multi-value memory and erase method
• US 6,094,371, US 6,111,777 (Fujitsu; Toshiba) — ferroelectric memory
• US 6,198,681 B1 (Micron) — sense amplifier for low-voltage memory arrays
• US 6,574,133 B2 (Toshiba) — nonvolatile memory device having a dummy cell circuit
• US 2002/0050616 A1 (Fujitsu) — nonvolatile memory with reliable verify operation

Tier 2 — the prior art actually litigated (NOT in the Citations list; the examiner never cited it):

• Kurata — Japanese Published Patent Application H10‑275484, Hitachi, filed March 31, 1997 (Appl. H9‑79784), published October 13, 1998 (Heisei 10), "A Nonvolatile Semiconductor Memory Device"
• Maruyama — U.S. Patent No. 6,272,049 (Maruyama et al.)
• Lee — U.S. Patent No. 6,258,668 (Lee et al.)

Tier 3 — not prior art (flagging so it is not misused): US 6,987,696 B1 (AMD, "Method of improving erase voltage distribution for a flash memory array having dummy wordlines"), priority July 6, 2004, appears in the "Families Citing this family" list. It post-dates the '602 priority date and therefore cannot be § 102/§ 103 art against the '602, notwithstanding the striking similarity of subject matter. Same for US 7,650,931 / US 7,830,724 (Samsung NAND, priority 2006) in the "Cited By" list.

Candid assessment of Tier 1. The examiner-cited set is, as a § 103 vehicle, weak on the core inventive concept. Most of it is ferroelectric-memory, sense-amplifier, reference-voltage, or verify-circuitry art; it does not teach biasing a dummy word line positive during an erase operation. Its real utility in a § 103 attack is (a) as evidence of the general knowledge of POSITAs regarding dummy cells/dummy word lines and peripheral circuitry, and (b) to supply the routine dependent-claim elements (decoders, sense amps, word lines). Notably, the two references in Tier 1 that are closest to the field — US 6,574,133 (dummy cell circuit in a nonvolatile memory) and US 6,198,681 (sense amplifier for memory arrays) — are still not, standing alone, a § 103 case against independent claims 1, 7, or 11.

3. Ground 1 — Kurata (JP H10‑275484)

As § 102: Toshiba's primary theory was anticipation. Petitioner mapped: memory cells (M11, M21); dummy cells (MTR1, MTR2) at the array edge in the second embodiment (Fig. 5, ¶ [0020]); a dummy word line (SV) at the array edge coupled to those cells; a control circuit supplying a positive 5 V bias to SV during erase; and bit lines (D1, D2) coupled to the cells — onto claims 1, 7, and 11.
Source: Petition analysis summary, https://ai-lab-cl-prod.azurewebsites.net/case/[ptab](/ptab)/IPR2017-01864/doc/summary/1

But the Board rejected those limitations as not disclosed "as arranged in the claim," finding Petitioner had not shown a reasonable likelihood of prevailing, and refused institution on Kurata. After SAS Institute, Inc. v. Iancu, 138 S. Ct. 1348 (2018), the Board modified institution to add Kurata anyway (Paper 13 at 2). Macronix's supplemental response argued three defects: (1) impermissible piecemeal combination of separate Kurata embodiments (Net MoneyIN v. VeriSign, 545 F.3d 1359, 1369–71 (Fed. Cir. 2008)); (2) unsupported inherency; (3) conclusory expert testimony.
Source: https://www.docketalarm.com/cases/PTAB/IPR2017-01864/Inter_Partes_Review_of_U.S._Pat._6788602/06-19-2018-Patent_Owner/Response-16-Patent_Owners_Supplemental_Response/

As § 103: Kurata is better deployed as a secondary reference supplying the erase-time positive bias on the line coupled to edge cells, than as a standalone anticipatory reference. Two features make it valuable:

1. Kurata's claim 1 requires, during a write operation, that the MOS transistor/dummy cell be turned ON — before a positive voltage is applied to the memory cell gate — to equalize data and source lines. That is a positive gate bias on the dummy-cell line during programming, which is directly material to claim 17 ("positive bias is greater than zero volts during programming operations") — the claim the IPR petitioners never challenged.
2. Its characterization of the MTR1/MTR2 devices as being "of a structure similar to memory cells" supports the Board's functional construction of "dummy cell," defeating a structural-difference argument.

Weakness: the SV line is described in Kurata as a gate signal line, not a word line, and its purpose is suppressing hot-electron injection at unselected cells — not preventing dummy-cell over-erasure. Macronix's expert (Dr. Liu) attacked exactly this. A § 103 case built solely on Kurata risks the "different principle of operation" rebuttal.

4. Ground 2 — Maruyama in view of Lee (the instituted § 103 ground)

This is the strongest and only ground the Board actually instituted on, and it is the core of any § 103 case against claims 1–12 and 16.

Maruyama (US 6,272,049) supplies:

• A flash memory with two memory cell arrays, each with normal memory cells and dummy cells (D0–D7);
• Dummy word lines (TDWL, BDWL) arranged at the edge of each respective array;
• A teaching that during an erase cycle, "a predetermined potential" is supplied to the dummy word lines to release electrons from the floating gates.
  (Characterizations per IPR2017‑01864 Petition and Petition-analysis summary. The primary-document snippet I retrieved for US 6,272,049 — "Non-volatile semiconductor memory device having increased operating speed" — confirms top/bottom arrays with cells coupled to bit lines and reference/dummy cells, consistent with dummy rows at array edges, but I could not independently verify the "predetermined potential during erase" passage from the reference itself in this session. Treat the erase-biasing teaching as sourced from the IPR record.)

The gap: Maruyama is ambiguous whether the "predetermined potential" is applied to the dummy word line or to the dummy source line. That ambiguity is the entire battlefield.

Lee (US 6,258,668) supplies: the conventional flash erase mechanism — applying a high positive voltage directly to the word lines to induce Fowler‑Nordheim tunneling between floating gate and control gate — plus a rationale for using different layers for programming versus erasing to balance insulation degradation.
(Sourced from the IPR Petition/ID summary; I did not retrieve the Lee document itself.)

Why a POSITA would combine them (the motivation analysis):

1. Same field, same problem, same mechanism. Maruyama and Lee are both nonvolatile/flash EEPROM references addressing erase of floating-gate cells via Fowler‑Nordheim tunneling. KSR rationale: combination of prior-art elements according to known methods to yield predictable results.
2. Resolving an ambiguity with a known, specific technique. Where a primary reference is ambiguous between two candidate structures/operations, it is proper to look to a second reference that expressly teaches one of them. Lee removes Maruyama's ambiguity by expressly teaching the erase bias on the word line. KSR rationale: "obvious to try" — a finite, identified, predictable set of options (word line vs. source line).
3. The result is a predictable consequence. If the dummy word line is biased positive during erase, the dummy cells are weakly programmed rather than over-erased. That is a straightforward and predictable electrical consequence, and the '602 specification itself relies on exactly that mechanism ("dummy cells 270j and 275j are only weakly programmed," 4:9–17). Predictable results weigh toward obviousness.
4. Art-recognized problem. Over-erasure of flash cells and the resulting bit-line leakage were well-known, extensively addressed problems in the art (see the "Similar Documents" set on the '602 page: US 6,044,932, "Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM"; US 6,314,027, "Flash memory device capable of preventing an over-erasure"; US 6,062,803; EP 0 857 346 B1). This supplies the "design incentive" and "market forces" rationale.

Macronix's rebuttals of record (which the ALJ appears to have credited, at least in part):

Source: https://www.docketalarm.com/cases/PTAB/IPR2017-01864/Toshiba_Corporation_v._Macronix_International_Co._Ltd/docs/04-30-2018-Patent_Owner/Exhibit-2001-Declaration_of_Dr_David_Kuan_Yu_Liu.pdf

5. Additional § 103 combinations from the face-of-patent art

Ground 3 — US 6,574,133 (Toshiba, dummy cell circuit) + Lee (or Kurata).
US 6,574,133 supplies the structural predicate (a nonvolatile memory with a dummy cell circuit and dummy lines in the array) and, being cited on the face of the '602, is presumptively analogous art. Combined with Lee's express teaching of high positive word-line erase bias, the combination yields claims 1, 7, and 11. KSR rationale: applying a known technique (erase bias on a word line) to a known device (dummy cells in a memory array) ready for improvement, to obtain a predictable benefit. Caveat: I could not retrieve the disclosure of US 6,574,133 in this session; its value here rests on its title/field and face-of-patent status, not on verified text. A real § 103 ground would need its actual disclosure.

Ground 4 — Dependent claims, routine elements.

• Claims 2, 8 (column decoder): US 6,198,681 (Micron, low-voltage memory arrays) and US 5,402,380 (Fujitsu) show conventional decoders/sense paths. Nearly any flash memory reference supplies this; the '602 itself concedes it ("as is commonly done").
• Claims 3, 8 (sense amplifier): US 6,198,681 is directly on point ("sense amplifier for low voltage memory arrays"); US 5,592,427 (Fujitsu) also describes sense amplifiers. Mere incorporation of known peripheral circuitry — no patentable weight.
• Claims 4–5, 9–10 (word line perpendicular to bit line; row decoder): JPH 06‑223587 and US 5,463,587 show conventional word-line/row-decoder arrangements. Again routine.
• Claims 12–15 (first voltage on bit line, second on word line; relative magnitudes): These are the standard program/erase bias relationships. The '602 specification itself states them in conventional terms (erase: WL ≈ −3 V vs. BL = 7.5 V; program: WL = 11.5 V vs. BL = 5 V). Lee teaches erase by high positive word-line voltage. A POSITA reading any flash EEPROM reference would find the claimed voltage relationships routine.
• Claim 16 ("continuously"): rises or falls with claim 6.
• Claim 17 (>0 V on dummy word line during programming): as noted above, Kurata's claim 1 requires turning the dummy cell ON during a write operation — arguably a positive gate bias on the dummy-cell line during programming — which makes claim 17 vulnerable to a § 103 (or § 102) attack that the petitioners never raised.

6. Claim-by-claim strength assessment

7. Objective indicia (secondary considerations)

I found no evidence of record of unexpected results, copying, licensing-due-to-patent-strength, long-felt-but-unmet need, or commercial success tied to this patent. The specification's own data (leakage increase falling from ~0.28 µA to ~0.00044 µA at 2.6 V, or an actual decrease at 3.7 V) is at most evidence of a predictable improvement, not an unexpected one — the mechanism (weak programming instead of over-erasure) is precisely what the prior art would predict. Also note the internal inconsistency at the heart of the disclosure: the specification says the positive bias is "continuously applied ... at least during an erase operation" (which is self-contradictory) and that during programming "a bias greater than or equal to 0 volts" is supplied — yet FIG. 3/FIG. 4 both describe 0 V during programming, which does not support claim 17's "greater than zero volts during programming operations." That disconnect is worth pressing.

8. Why the § 103 case is not airtight — candid bottom line

1. The examiner never cited Kurata, Maruyama, or Lee. The face-of-patent art (Tier 1) does not, alone, render claims 1, 7, or 11 obvious. Any § 103 case must be built on art the examiner did not have.
2. The Board's institution decision refused the Kurata ground on the low "reasonable likelihood" threshold, and institution on Maruyama+Lee does not signal likely invalidation — institution decisions are non-final and non-precedential.
3. No final written decision exists. IPR2017‑01864 was terminated on October 17, 2018 by settlement, so there is no adjudicated § 103 holding on the '602.
4. The ITC found no violation. The ALJ's April 27, 2018 Initial Determination found no violation of Section 337 (including a finding adverse to invalidity as to the '602). The Commission's October 9, 2018 review reversed the no-direct-infringement finding, affirmed the indirect-infringement and invalidity findings, and reversed the domestic-industry finding, then found a violation and issued exclusion/cease-and-desist orders — which were rescinded on November 13, 2018 after settlement. Flag: the record as summarized to me says the Commission "affirmed the ID's ... invalidity findings as to the '602 patent." Given that the Commission nonetheless found a violation after reversing the infringement finding, the only internally consistent reading is that the ID's "invalidity findings" were findings that the claims were not invalid, and the Commission affirmed them. I could not directly verify the direction of that finding, so treat it as a strong pro-validity data point rather than a confirmed legal conclusion.
5. The settlement means all of the above is untested. The $40M/$80M+ cross-license outcome is a commercial settlement, not a validity determination.

Net: On the record of this page, the strongest § 103 theory is Maruyama (US 6,272,049) in view of Lee (US 6,258,668) against claims 1–12 and 16, with Kurata (JP H10‑275484) as either an alternative primary reference or, more usefully, as the reference that supplies both the erase-time positive bias and — for claim 17 — a positive dummy-cell line bias during programming. The face-of-patent citations (Tier 1) are useful only for the routine dependent-claim elements and as evidence of the ordinary skill level. The realistic probability of invalidating claims 1, 7, and 11 is moderate, not high; dependent claims 2–5 and 8–15 are highly likely obvious if the independent claims fall; claim 6/16 is the weakest of the challenged set; and claim 17 is the most interesting untested target.

If you want, I can now (a) attempt to pull the actual text of US 6,272,049 and US 6,258,668 to verify the erase-bias teachings I've relied on secondhand, or (b) build a full element-by-element claim chart for claim 1 against Maruyama + Lee.