US 6166979

I'll verify this patent against live sources before summarizing.

Let me do a couple more targeted checks for litigation and family members.

US 6,166,979 — Analysis Summary

Verification note: I checked live sources. The bibliographic data below is confirmed by the authoritative full text you supplied (Google Patents, fetched 2026‑09‑24) and corroborated by an independent citation of "US6166979A … 1995‑09‑13 … 2000‑12‑26 … Kabushiki Kaisha Toshiba … Nonvolatile semiconductor memory device and method for using the same" and by the prior‑art table in US 6,937,520 ("6166979 | December 26, 2000 | Miyamoto"). I did not find any CAFC 2026 docket entry or district‑court/ITC proceeding that names this patent. Details and caveats are in the last section.

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1. Bibliographic data

The issued patent is a divisional whose parent was itself a continuation of the 1995 application, so the 1995‑09‑13 priority date is the effective date for the subject matter carried through from US 5,831,900.

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2. Abstract (as issued)

A nonvolatile semiconductor memory device includes nonvolatile memory cells (C), constant voltage circuits for applying one of different verify voltages to control gates of the nonvolatile memory cells C in response to control data introduced into the memory device from the exterior, and writing and sensing circuit circuits for applying a potential to drains of the nonvolatile memory cells C in response to write data introduced into the memory device and for detecting and amplifying currents between drains and sources of the nonvolatile memory cells. By dividing the memory cell array 501 and a serial register 502 into some parts and by connecting an external SRAM 503 so as to progress the transfer of data from the memory cell array 501 to the serial register 502 and the transfer of data from the serial register 502 to the external SRAM 503 in parallel, the read speed is increased.

Note: the abstract describes the disclosure broadly (multi‑level NAND, verify‑voltage generation, flag cells, ping‑pong register/SRAM pipelining), but the claims as issued are directed to sense‑circuit architecture — dual sense amplifiers per bit line with one or two bus lines. This is a classic case of the claims being narrower than the abstract/specification.

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3. Plain‑language overview of the independent claims

Claims 1, 3, 7, 10, 13, 14 and 15 are independent (claim 16 is independent as well, but its text is truncated in the source text supplied — see caveats). All of them share the same preamble: a memory cell array of nonvolatile cells in a matrix, one common word line per row, one common bit line per column, and sense circuits that detect/amplify the bit‑line potential and hold the corresponding data.

Claim 1 — two sense amps, two data buses.
Each sense circuit has a first sense amplifier tied to the bit line through a first MOS transistor, a second sense amplifier tied to the same bit line through a second MOS transistor, a first bus line from the first sense amp's output through at least one first column gate, and a second bus line from the second sense amp's output through at least one second column gate. In plain terms: one bit line is readable by two independent amplifiers feeding two independent I/O paths, so two different threshold levels of the same cell can be captured/latched without waiting for a second bit‑line precharge‑and‑discharge cycle.

Claim 3 — two sense amps, one shared data bus.
Same dual‑amplifier structure as claim 1, but the two amplifier outputs share a single bus line, with a column gate that selectively connects one output or the other. This is the reduced‑pin/pin‑count‑conserving version — the specification states that one data‑bus pair is acceptable "if they are alternatively made to appear on the data bus by appropriate switching of the column gates."

Claim 7 — like claim 1, but the second amp attaches directly.
Identical to claim 1 except the second sense amplifier is connected to the bit line not through a second MOS transistor. The second MOS transistor (Q4′) in the specification is only needed if the second amplifier is also used for data loading during programming; where slower data load is acceptable, "the MOS transistor Q4′ may be omitted." Claim 7 captures that structural alternative.

Claim 10 — like claim 3, but the second amp attaches directly.
Same as claim 3, with the second sense amplifier connected to the bit line without an intervening second MOS transistor, and a column gate alternatively connecting the two amplifier outputs to the single bus.

Claim 13 — full circuit‑level implementation, two buses.
A highly structural claim reciting the complete sense circuit: first/second MOS transistors; first/second sense amplifiers; a first bus line (I/O line plus inverted I/O line) connected to the two terminals of the first amplifier through a first column gate; a second bus line (I/O plus inverted I/O) connected to the two terminals of the second amplifier through a second column gate; a third MOS transistor between the first amplifier's first terminal and ground (controlled by a first signal — i.e., the set/reset device); fourth and fifth MOS transistors in series between the first amplifier's second terminal and ground, the fourth gated by a second signal and the fifth gated by the bit line (the sensing/inversion path); and a mirror‑image sixth, seventh and eighth MOS transistor set for the second amplifier. In plain terms: the schematic of FIG. 7/17 turned into claim language, with differential buses.

Claim 14 — same detailed circuit, single shared bus.
Recites the same eight‑transistor/per‑amplifier arrangement, but with a single bus line having an I/O line and an inverted I/O line, the I/O line being selectively connected to the first terminals of both sense amplifiers and the inverted I/O line to the second terminals, through a column gate.

Claim 15 — mixed configuration.
A first sense amplifier connected to the bit line through a first MOS transistor, a second sense amplifier connected to the bit line (no intervening transistor), two bus lines each with an I/O line and an inverted I/O line routed through respective column gates, and a second MOS transistor connected between a "firs[t]…" — the claim text is cut off in the supplied document at that point.

Claim 16 — independent per the claim count of 16, but its full text was not present in the source text provided; I will not guess at its scope.

Dependent claims. 2, 5, 8, 11 add that the bus line(s) comprise a line/inverted‑line pair. 4, 9 and 12 add a precharge circuit coupled to the bit line. Claim 6 is an anomaly: it reads "The nonvolatile semiconductor memory device according to claimed 3, further including a precharge circuit coupled to said bit line" — textually it duplicates claim 4's limitation and contains what appears to be a typographical error in the dependency reference. I am flagging this because it is a real feature of the printed claim set, not something to silently normalize.

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4. What the invention actually does (context from the specification)

The 1995 priority application attacked four problems with then‑existing multi‑level NAND flash: (1) a 2ⁿ‑value cell needed n sense amplifiers, bloating array area; (2) the number of reference cells was fixed at design time; (3) sense‑amplifier area was too large to track cell distribution across a chip; and (4) NAND reads were slow. The disclosed solutions were (a) replacing reference cells with constant‑voltage generating circuits (200–202, 203) so the number of levels is programmable, (b) multi‑step incrementing write‑verify programming (FIGS. 2–4), (c) flag cells/flag memory 302 storing the number of levels stored per block or chip, and (d) the pipelined register‑plus‑external‑SRAM read scheme of FIGS. 21–25. This divisional's claims, however, are all aimed at the two‑sense‑amplifiers‑per‑bit‑line concept used in the FIG. 17/18 read‑speed enhancement, not at the multi‑level programming or flag‑cell subject matter.

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5. Litigation / CAFC docket check — result and caveats

Finding: I found no CAFC 2026 docket entry, and no district‑court or ITC filing, that identifies US 6,166,979 by number. Searches of the patent number returned only patent‑office and citation‑table hits (including its use as prior art against US 6,937,520), plus an unrelated Brazilian state‑registry PDF where "6166979" happens to be a company registration number — not a patent reference.

Things I found that are adjacent but that I cannot attribute to this patent:

• An ITC § 337 opinion (Toshiba v. Hynix NAND flash matter, USITC Pub. 4010) describes "the '969 patent and the '449 patent" as relating to a NAND array of serially connected storage transistors. "'969" is a three‑digit shorthand that does not resolve to 6,166,979, and I could not confirm which full patent number it denotes. Treat this as unverified.
• The 2006 Lexar v. Toshiba ITC complaint asserted US 6,801,979, 6,397,314 and 6,978,342 — 6,801,979 is a different patent number from 6,166,979 and must not be conflated with it.
• Various Toshiba NAND litigation materials ('178, '188, '270, '573, '819, '949, '367 patents) surfaced in searches but none is 6,166,979.

Two identifier disambiguation points, stated literally:

1. JP 6166979 A (JP H6‑166979, published 14‑06‑94) appears repeatedly in search results, including in PCT search reports. This is a distinct, unrelated Japanese publication that happens to have the same digit string. It is not the US patent.
2. US 6,167,219 (Miyamoto et al., 12/2000) and US 5,965,914 (Miyamoto) appear in citation tables alongside 6,166,979. These are separate patents by the same inventor; they are not this patent.

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6. Uncertainty statement

• The claim text supplied ends mid‑claim 15, so claim 16's scope is unknown to me. I have deliberately not described it.
• The abstract in the record is broader than the claims; anyone assessing infringement or validity should work from the issued claims (1–16) and the prosecution history of the 09/300,402 division, neither of which is fully available from the source text provided.
• The Google Patents "legal status" line ("Expired – Lifetime," anticipated expiration 2016‑09‑12) carries its own disclaimer that it is an assumption and not a legal conclusion; I relay it as such. Because the patent has expired, it cannot be asserted for ongoing infringement in 2026.
• I have no authoritative confirmation of any litigation or appeal involving this specific patent, and I would rather state that plainly than infer it from adjacent Toshiba NAND matters.

Primary source: https://patents.google.com/patent/US6166979/en

I'll research litigation involving US patent 6166979.

Initial results are not on point. Let me try the specific litigation databases.

Let me try more targeted searches on litigation databases and the patent's technology/owner.

Litigation Search Report — U.S. Patent No. 6,166,979

Patent identified (per your instruction, interpreted literally):

• US 6,166,979 B1 — "Nonvolatile semiconductor memory device and method for using the same"
• Application No. 09/300,402; filed 1999-04-27; granted 2000-12-26
• Division of Ser. No. 09/136,305 (filed Aug. 19, 1998); priority date 1995-09-13
• Inventor: Junichi Miyamoto; Original/Current Assignee: Toshiba Corp.
• Legal status: Expired – Lifetime (anticipated expiration 2016-09-12)
• Related family members surfaced: US 5,831,900 (parent) and US 6,331,960 B1 (continuation)

Result: No litigation found

I was unable to identify any litigation — district court, ITC, or appellate — in which U.S. Patent No. 6,166,979 was asserted. No plaintiff/defendant pairs, case numbers, jurisdictions, filing dates, or outcomes can be reported, because none were located for this specific patent number.

A few things worth flagging for your diligence file:

1. No results on the litigation trackers I could reach. Searches of the Unified Patents litigation portal and general web/patent-litigation docket sources returned zero hits tying "6,166,979" (or "6166979") to a case caption or docket. I could not retrieve PACER or Docket Navigator directly (paywalled), so this is not a fully exhaustive negative.

2. Do not confuse the following look-alikes — they are NOT US 6,166,979:

   • JP 6166979 A (published 14-06-1994) — a Japanese laid-open application number that appears in PCT search reports. This is the most common false positive returned by search engines for the string "6166979."
   • A Brazilian state registry entry ("6166979 IF MARIE CAFETERIA E PADARIA LTDA") — an unrelated corporate registration number.
   • Toshiba cases involving other patents that search engines surfaced and that are unrelated to the '979 patent, e.g., Intellectual Ventures I LLC v. Toshiba Corp. (D. Del., patents '788, '742, '431, '819, '270); Toshiba Corp. v. Imation Corp. (DVD patents '966/'751); Li Second Family Ltd. P'ship v. Toshiba Corp. (U.S. 4,946,800); Wang Laboratories v. Toshiba (module patents); Tierra Intelectual Borinquen v. Toshiba (E.D. Tex. 2:13-cv-00047). None of these asserted the '979 patent.

3. Practical significance of the expiration date. The patent's term reached its anticipated expiration on 2016-09-12. Any U.S. infringement action would have had to be filed on or before that date to reach pre-expiration damages (subject to the six-year § 286 look-back). This materially narrows the window in which an assertion could have occurred and is consistent with the absence of any identified suit.

4. Sibling patents are the more likely candidates. If the purpose of this search is to clear a product or build a licensing picture, I'd recommend separately running U.S. 5,831,900 and U.S. 6,331,960 (both in the same family, same 1995 priority), as family members — not the '979 patent itself — are more commonly the asserted claims.

Recommended next steps to convert this into a definitive clearance

• Query Docket Navigator and Lex Machina by patent number (both support exact U.S. patent-number search, including Complaint exhibits filed as IPR/ITC art).
• Pull the USPTO Patent Assignment Abstract for Reel/Frame history on 6,166,979 to confirm whether assignment/licensing activity ever occurred (which often coincides with assertion).
• Check ITC EDIS for Section 337 investigations naming the patent in the "patents asserted" field.
• Check the PTAB for any IPR/PGR/CBM involving the patent (none found in accessible search, but confirm on the PTAB API).

Bottom line: Based on the sources I could access, there is no known litigation involving U.S. Patent No. 6,166,979. I cannot positively rule out an assertion that appears only in a paywalled docket database, but I found nothing suggesting one exists, and the patent's expiration in 2016 makes a recent suit unlikely.

I'll start by verifying the structured data against public sources — the ODP block says no AIA trials, but PTAB activity can predate or postdate ODP ingest, so let me check.

Initial searches found no PTAB hits. Let me run more targeted queries to be thorough before concluding.

Let me check for litigation/assertion history and any petition referencing this patent number directly.

I hit the tool-step limit mid-verification, so I'll report what the structured data and my searches established, and flag explicitly what remains unverified.

Proceedings overview

Zero AIA trial proceedings. The USPTO ODP "PTAB proceedings on file" block returns no IPR, PGR, or CBM proceeding for US 6,166,979 — no active trials, no claims invalidated, no claims sustained, no settlements, no institution denials — which means there is no PTAB-based validity ruling to lean on and, more importantly, no § 315(e)(2) estoppel to hide behind: the patent's defensive value for a defendant does not come from the Board, it comes from the fact that the patent expired on 2016-09-12 and the § 286 six-year damages lookback has now closed.

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No proceedings to report

I searched Google Patents / the ODP record for US 6,166,979, and ran open-web queries pairing the patent number ("6,166,979" / "US6166979") with IPR, PGR, CBM, Unified Patents, and Toshiba/NAND multi-level terms. No petition, institution decision, Final Written Decision, or Federal Circuit appeal surfaced. Per the operating rule in my instructions, the ODP structured block is canonical and the default is "no PTAB activity on file" — so I am stating that plainly rather than manufacturing a proceeding number.

• Type: N/A — no AIA trial ever instituted or petitioned on this record.
• Filed: N/A
• Status: N/A (patent itself: Expired – Lifetime, anticipated expiration 2016-09-12)
• Judge panel: None.
• Petition grounds: None on file.
• Institution decision: None.
• Final Written Decision: None. No claim of this patent has ever been canceled or confirmed by the PTAB.
• Settlement / termination: N/A
• Appeal: No CAFC appeal from a PTAB FWD exists (there is no FWD to appeal).
• Defensive value: Because no IPR was ever run, every claim 1–16 remains legally untested at the Board — but the patent is expired, so the practical defense is expiration and damages-window math, not invalidity.

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Patent posture that matters more than the (empty) PTAB record

Relevant bibliographic anchors from the authoritative full text:

• US 6,166,979, "Nonvolatile semiconductor memory device and method for using the same," inventor Junichi Miyamoto, assignee Toshiba Corp.
• Priority 1995-09-13; this application (09/300,402) filed 1999-04-27 as a division of Ser. No. 09/136,305 (filed 1998-08-19); related continuation US 6,331,960 B1 (app. 09/641,722, filed 2000-08-21).
• Granted 2000-12-26; 16 claims; statutory term ended 2016-09-12 (20 years from the 1996-09-12 / 1995-09-13 priority chain).
• Claim set is the dual-sense-amplifier architecture: independent claims 1, 3, 7, 10, 13, 14, and 15 each recite a first sense amplifier on the bit line through a first MOS transistor and a second sense amplifier (through a second MOS transistor, or directly), with bus/IO line routing through column gates.

Damages-window arithmetic (the real defense): an expired patent cannot be infringed after 2016-09-12, and 35 U.S.C. § 286 bars recovery for infringement more than six years before the complaint is filed. As of today (2026-10-01), a complaint would reach back only to 2020-10-01 — after expiration. On its face that leaves no recoverable infringement period at all (subject to caveats about § 286 tolling, pre-suit notice periods, and any earlier-filed complaints you may have already received).

Strategic summary

Canceled vs. sustained vs. untested. Nothing is canceled and nothing is sustained — the entire claim set (1–16) is untested at the PTAB and effectively untestable in commerce, because the patent is expired. If a demand letter cites any claim of 6,166,979, the correct posture is not "let's petition for IPR" (you cannot meaningfully enjoin an expired patent, and the Board is unlikely to institute on a patent with no live infringement exposure) but rather "what date was the accused conduct, and when was the complaint filed?"

Estoppel landscape. Because no IPR/PGR was ever filed, § 315(e)(2) estoppel is a blank slate. No petitioner, real party in interest, or privy is barred from any ground. In practice there is nobody to file: the patent's § 102/§ 103 exposure is now purely academic, and the more useful invalidity evidence would be whatever the defendant already holds from the related family (US 5,831,900 and US 6,331,960) and the ISSCC '95 multi-level flash paper cited in the specification itself.

Pattern signals. No repeat-petitioner pattern exists because there is no petitioner at all. No defensive aggregator (Unified Patents or similar) appears in this patent's chain on the public record. Toshiba is the sole original and current assignee listed. There is no CAFC appeal to trace.

Caveat on scope of my search. The ODP block covers AIA trials only. I did not finish verifying (a) ex parte reexamination or reissue filings, (b) district court cases where invalidity of 6,166,979 was adjudicated, or (c) whether any IPR was filed in the 2012–2016 window while the patent was still in force, e.g., during the Toshiba v. Hynix / Toshiba NAND disputes of that era. My open-web searches returned nothing on any of these, but absence of a hit is weaker evidence for pre-2012-era district court history than for the PTAB record itself. Treat those three as open verification items, not as confirmed negatives.

Recommended next steps

1. Lead with expiration, not invalidity. The patent expired 2016-09-12 and the § 286 lookback now reaches only to conduct on or after 2020-10-01 — after expiration. Build the defense on that timeline first; it disposes of most assertion theories without an IPR.
2. If a demand letter or complaint exists, date-lock the accused conduct. Identify the earliest and latest accused acts. If all accused conduct predates 2020-10-01, the damages claim is time-barred under § 286 (flag any tolling or prior-complaint arguments the other side might raise).
3. Do not budget for an IPR. There is no active PTAB proceeding to monitor — no institution deadline, no oral hearing, no statutory one-year FWD date — and petitioning on an expired, unassertable patent is generally poor use of fees.
4. Complete the gap-check I could not finish. Pull the file histories of US 6,166,979, US 5,831,900, and US 6,331,960 and confirm no ex parte reexamination/reissue; run a PTAB E2E and CourtListener search on the patent number for any pre-2012 or unindexed filing. If all come back negative, the "no PTAB activity on file" conclusion is fully hardened and can be stated to a court or counterparty without qualification.
5. Document the null result. A well-asserted patent of this vintage would ordinarily have drawn an IPR; the absence here is a signal the patent was likely never commercially enforced to judgment in this family during its term — useful context for a Rule 11 or § 285 posture if the demand letter overstates the patent's strength.

I'll research this patent's assignment history across the sources you named.

Let me pull the Google Patents legal events and try the assignment databases directly.

Let me try to reach the assignment records directly and check for any Toshiba→Kioxia/Toshiba Memory transfers.

Assignment & Ownership Analysis — US 6,166,979

Source note up front: the authoritative patent text (Google Patents, fetched 2026-09-24) and the Google Patents legal-events mirror were retrievable. The USPTO Assignment Center (assignmentcenter.uspto.gov) was not directly queryable from this environment — its API requires a key and the legacy assignment lookup pages did not return patent-specific records through the available search tooling. No reel/frame numbers are asserted below, because none were retrieved. Anything I could not verify is labeled as such rather than filled in.

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Inventors

• Single-inventor filing. The patent lists only Miyamoto. No joint inventors are named in the granted text.
• Employer attribution is inferential, not documentary. The fetched record names the inventor as "Junichi Miyamoto" with no residence/employer field, and the assignee of record is Toshiba Corp. For a 1995-priority Japanese corporate memory-device filing, Toshiba employment is the near-certain case, but I did not retrieve the executed inventor→Toshiba assignment document, so I am flagging this as presumed rather than confirmed.
• Departure pattern: no data. With one inventor and no retrieved assignment chain, the "all inventors departed within 12 months" red flag cannot be evaluated. There is no evidence of inventor departure, and equally no evidence against it. Do not read the absence as exculpatory.
• Family context (from the authoritative text): this application (09/300,402, filed 1999-04-27) is a division of Ser. No. 09/136,305 filed 1998-08-19, which traces to US 08/713,856 (1996-09-12) that issued as US 5,831,900. A further continuation (09/641,722, 2000-08-21) issued as US 6,331,960 B1. Same sole inventor, same assignee — a classic single-family, single-owner prosecution cluster.

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Original assignee

Kabushiki Kaisha Toshiba (Toshiba Corp.), 1-1 Shibaura 1-chome, Minato-ku, Tokyo, Japan.

• Named on the issued patent: Yes — Google Patents lists Original Assignee and Current Assignee as Toshiba Corp.
• Primary line of business (1995–2000): diversified electronics and electrical equipment manufacturer; NAND flash memory was a core, product-shipping business line (Toshiba commercialized NAND flash, invented at Toshiba in 1987).
• Did they ship a product embodying the claims? Almost certainly yes, and this is the substance of the patent rather than an incidental filing: the disclosure is a full multi-level (multi-value) NAND flash architecture — write-verify sequencing (FIGS. 2–4), sense-amplifier bit-to-bit verify with batch verify detecting circuit (FIG. 7), word-line drive voltage generation (FIG. 8), row decode/word-line drive (FIGS. 9–11), and a pipelined read path into an external SRAM (FIGS. 21–25). This is implementation-grade material for Toshiba's multi-level NAND product line, not a paper patent.
• Current status: Toshiba remains an operating company (restructured — accounting scandal 2015, memory business divested to a Bain Capital-led consortium in 2018). Google Patents lists Toshiba Corp as current assignee, and the patent's legal status is "Expired – Lifetime" with an anticipated expiration of 2016-09-12.
• Timing point worth noting: the anticipated expiration (2016-09-12) predates the Toshiba Memory spinoff (2017) and the Kioxia rebrand (2018–2019). Any later memory-business IP transfer would have had no term left to convey here, and no such transfer is reflected for this patent in the record I could access.

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Assignment timeline

Finding: no post-issuance assignment is reflected for US 6,166,979.

The Google Patents legal-events record for US 6,166,979 contains only prosecution and term events — no "Assignment" entries:

Because no assignment document was retrieved, I cannot supply the three fields your template requires — reel/frame, conveyance type, and correspondent of record. I am deliberately not reconstructing them: the correspondent is precisely the field your brief identifies as the highest-value tell, and inventing it would corrupt the analysis.

• What this most likely means: the chain never left Toshiba. No record of a Toshiba → Toshiba Memory → Kioxia transfer, no LLC transferee, no asserter. The absence of any post-issuance assignment is itself the finding.
• What remains genuinely unverified: whether an inventor→Toshiba assignment was recorded during original prosecution (routine, and almost certainly yes), and whether Assignment Center holds a record that simply is not surfaced in the Google Patents mirror. Both should be confirmed by a direct Assignment Center query before this section is treated as conclusive.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 6166979) and https://assignment.uspto.gov/patent/index.html

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Timeline diagram

timeline
    title Ownership of US 6166979
    1995 : Japanese priority filed
    1996 : US parent filed as 08 713 856
    1999 : Divisional filed by Toshiba
    2000 : Patent issued to Toshiba
         : Continuation filed as US 6331960
    2016 : Patent expired
         : No assignment ever recorded

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NPE / troll-pattern signals

Net: zero of eight signals present; one (correspondent recurrence) unevaluable due to the retrieval gap.

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Verdict

Insufficient data (no records, or only the original assignment).

US 6,166,979 issued to Kabushiki Kaisha Toshiba on 2000-12-26 and its Google Patents legal-events record contains no post-issuance assignment — only the 1996/1999 prosecution dates, the 2000-08-21 continuation link to US 6,331,960 B1, and the 2016-09-12 anticipated expiration. The patent is Expired – Lifetime, and Toshiba Corp remains the listed current assignee, so there is no NPE chain to characterize: none of the eight troll-pattern signals is present, and the one signal that would matter most here (a recurring correspondent across LLC links) is unevaluable because no assignment document, and therefore no correspondent of record, was retrieved.

Confidence limitation, stated plainly: I could not query the USPTO Assignment Center directly from this environment. The "no assignment" finding rests on the Google Patents legal-events mirror. Before relying on this, run the patent number through https://assignmentcenter.uspto.gov/ and confirm (a) whether any inventor→Toshiba assignment is recorded with a reel/frame and correspondent, and (b) that post-issuance events are absent. If Assignment Center returns records I could not see, signal #3 and the verdict should be re-run against the actual correspondent names.

I'll research the prior art cited against US 6,166,979, starting with the patent's own citation records.

The general searches aren't returning the citation list. Let me go directly to the patent's citation records on patent databases.

Let me pull the specific citation tables from the patent databases.

Prior-Art Analysis — U.S. Patent No. 6,166,979

Bottom line up front

I was not able to retrieve the official "References Cited" front page for US 6,166,979 from the authoritative patent text supplied for this project, and my external searches did not return that citation table either. The Google Patents text provided in the authoritative source jumps from the Abstract/Description straight to the Claims and omits the front-page "References Cited" (U.S. Patent Documents / Foreign Patent Documents / Other Publications) block entirely.

Because of the strict rule against fabricating citations, I will not invent examiner-cited references. Below I (a) document exactly what I could and could not verify, (b) give you the only intra-family documents I can confirm by number, and (c) provide a clearly-labeled candidate prior-art set with a § 102 claim-mapping so the analysis is actionable — with every candidate flagged as unverified against the official citation list.

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1. Patent confirmed (literal interpretation of "6166979")

I found an independent directory listing confirming the number/title pairing at everypatent.com ("Patent 6166979: Nonvolatile semiconductor memory device and method for using the same" — http://www.everypatent.com/idx/pdir3219.html). No similar-number substitution was made; the JP 6166979 A false positive noted in the earlier litigation section was excluded.

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2. The data-availability gap (the crux of this task)

What I searched and what came back:

• Searches on US6166979 + "citations / prior art / References Cited" returned unrelated patents' citation tables (e.g., EP1033280A3, JP2010534352A, US9450092, US20090231929A1) — none of which is the '979 front page.
• The Google Patents authoritative fetch (per the source header) does not reproduce the front-matter citation list; it contains the classifications, definitions, abstract, description and claims only.
• uspto.report has a page for the sibling US 5,831,900 (https://uspto.report/patent/grant/[5831900](/patent/5831900)) but the returned excerpt contained only the description, not the citation table.

Consequence: Any statement that "reference X is cited on the face of the '979 patent" would be an unverifiable assertion on my part. I am therefore explicitly declining to present a citation list as if it were the official one.

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3. Intra-family documents (the only ones I can confirm by number)

These are related-family documents, not necessarily examiner citations, but they are the references most likely to appear in the '979 front matter and are the correct starting point for § 102/§ 103 analysis:

Internal inconsistency worth flagging (as required by the cross-reference rules):
The specification text states the application "is a division of Ser. No. 09/136,305 filed Aug. 19, 1998," whereas the Google Patents bibliographic data lists the priority claim as coming from US 08/713,856 (1996-09-12, which issued as US 5,831,900). These two statements are not obviously reconcilable as a single chain and I am recording the discrepancy rather than auto-correcting it. This matters for § 102(e)/§ 103 date analysis of the family.

Important legal point: Family members sharing the same inventive entity (Miyamoto) are not "by another" under pre-AIA § 102(e), so US 5,831,900 and US 6,331,960 do not anticipate the '979 claims on these facts.

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4. Candidate prior art for § 102 analysis — NOT VERIFIED as official citations

The claims of '979 (all of them) are directed to a specific sense-circuit architecture with two sense amplifiers per bit line (the FIG. 17 "two-way access" embodiment in the specification). Claims 1, 3, 7, 10, 13, 14 and 15 are independent; claims 2, 4–6, 8–9, 11–12 are dependent, adding only (i) a bus line pair = line + inverted line, and (ii) a precharge circuit coupled to the bit line.

Genuine anticipation under § 102 therefore requires a single reference disclosing two sense amplifiers (or two latches) connected to the same bit line / same memory cell, with the claimed column-gating. The candidate universe is the mid-1990s nonvolatile sense-amplifier art. Representative candidates (each flagged as unconfirmed against the '979 citation list):

I want to be explicit: the four rows above are candidates I can identify from the technical field, not references I confirmed are cited on the '979 patent. Treat them as search seeds, not results. Do not put any of them in a chart as a "cited reference" without checking the front page.

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5. Claim-by-claim § 102 mapping (structural framework)

Because I cannot confirm the actual citations, here is the mapping by limitation that any § 102 reference would have to satisfy:

Reading of the claim families: Claims 1–12 are the architectural genus (bus-per-SA vs. shared bus; gated-vs-direct second SA). Claims 13–15 are the detailed circuit species. Any anticipation of 1/3/7/10 requires a reference showing two sense amplifiers per bit line in a flash/NAND array with the recited gating — which is the point the '979 specification itself frames as the improvement over the referenced ISSCC '95 Digest architecture (single sense amp per level). Anticipation of 13–15 would require the specific transistor topology.

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6. What I could NOT determine (stated rather than fabricated)

1. The literal contents of the '979 front-page citation list (U.S. and foreign patent documents, non-patent literature). Not retrievable from the authoritative text or my searches.
2. Whether any non-patent literature (e.g., the cited ISSCC '95 Digest of Technical Papers, p. 133) was formally listed as a reference rather than only discussed in the Background. The Background discusses it but this does not establish it as an official citation.
3. Whether any candidate above was actually cited, or merely appears in the same technical neighborhood.

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7. Steps that would close this out definitively

1. Pull the front page of US 6,166,979 directly from USPTO Patent Center / Patent Public Search (App. 09/300,402) or the granted-PDF image — this is the single action that supplies the verification this task needs.
2. Cross-check the parent US 5,831,900 front page (its list is likely nearly identical given the division relationship).
3. Run the exact citation list through the § 102/§ 103 review, mapping each reference to the claim families in § 5 above.
4. Confirm no family-member self-citation issue (§ 102(e) "by another") and reconcile the 09/136,305 vs. 08/713,856 priority discrepancy flagged in § 3.

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Summary

• Patent 6,166,979 is confirmed (Toshiba, Miyamoto, multi-level NAND, app. 09/300,402).
• I could not retrieve the official cited-references list, and I have not fabricated one. The authoritative source omits it.
• The only numbered references I can assert with confidence are the family documents US 5,831,900, US 6,331,960, and (flagged) US 5,965,914.
• I supplied a candidate prior-art set and a limitation-by-limitation § 102 mapping for the actual claims (which are all directed to two-sense-amplifiers-per-bit-line sense circuits), clearly marked as unverified pending retrieval of the front page.

Please run the front-page pull in Step 1 above and I will map each confirmed citation to its anticipating claim(s) precisely.

I'll gather the prior-art record for this patent before analyzing. Let me pull the front-page references and related family/prior-art documents.

The provided page text lists only "prior art keywords" (mos transistor, terminal, line, sense amplifier, bit line) rather than a formal reference table. Let me locate the actual cited references and family/prior-art documents.

Let me try to pull the actual front-page U.S. patent references cited on US 6,166,979 and its parent.

Obviousness Analysis — U.S. Patent No. 6,166,979 under 35 U.S.C. § 103

Analyst note on sources. The authoritative page freeze you supplied for https://patents.google.com/patent/US6166979/en does not contain the statutory "References Cited" table (the front‑page US‑patent citation list). The only content in the page's Prior Art block is:

• Prior art date: 1995‑09‑13
• Prior art keywords: mos transistor, terminal, line, sense amplifier, bit line
• Family/priority pointers: priority claimed from US 08/713,856 → US 5,831,900 A; division of Ser. No. 09/136,305 (1998‑08‑19); continuation US 09/641,722 → US 6,331,960 B1

Because no enumerated reference list was on the page, I built the grounds below from (i) the art the patent itself admits (the ISSCC '95 paper, plus the multi‑level flash architecture described in the Background), and (ii) the prior art that surfaced in live searches of citation tables and ITC/IPR records that quote this technology — principally US 5,172,338. I flag confidence levels for each. I did not fabricate reference numbers.

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1. Legal framework applied

A § 103 analysis follows Graham v. John Deere (scope/content of prior art; differences; PHOSITA level; secondary considerations) as refined by KSR Int'l v. Teleflex, 550 U.S. 398 (2007): a combination of known elements is obvious where it yields only predictable results, where there is a design incentive or market force, or where the number of identified, predictable solutions is small. All art relied on below is in the same field of endeavor (semiconductor memory devices) and is therefore analogous art as a matter of law; even if characterizable as DRAM art, it is reasonably pertinent to the problem the '979 patent addresses — reading memory cells fast.

PHOSITA (as of the 1995‑09‑13 critical date): an electrical engineer with a B.S./M.S. and 3–5 years designing CMOS memory peripheral circuits — sense amplifiers, column decoders/gates, precharge circuits, and multi‑level/threshold‑window read schemes — with working knowledge of both DRAM dual‑sense‑amplifier column architectures and EEPROM/flash multi‑state sensing.

Caveat on effective date. The '979 claims are directed to the FIG. 17/18 dual‑sense‑amplifier read‑speed embodiment. Assuming § 120 benefit flows to the 1995 priority application (the specification is common across the family), the critical date is 1995‑09‑13. If any claim term lacks written‑description support in the 1995 application, the effective date shifts to 1998‑08‑19 (09/136,305) or 1999‑04‑27. Either way, the references below predate all three dates, so the analysis is stable.

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2. The claims at issue (focus of the rejection)

Dependents 2, 5, 8, 11 (differential bus = line + inverted line); 4, 9, 12 (precharge circuit on the bit line). Claim 6 is a typo anomaly ("according to claimed 3, further including a precharge circuit coupled to said bit line" — duplicating claim 4). Claims 1, 3, 7, 10 and 13 are the representative independent claims; all share the same inventive kernel: more than one sense amplifier sensing the same bit line, feeding out through column‑gated bus(es).

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3. Prior art relied upon

PA‑1 — Admitted prior art (the patent's own Background). US 6,166,979, col. 1, expressly describes and adopts the multi‑level flash memory of ISSCC '95 Digest of Technical Papers, p. 133, including its architecture "using flash cells as its reference cells to control the current flow into the reference cells." The Background also admits the conventional read flow and its cost: 3t_R + 3t_S + t_conv = 111.8 µs for a four‑value read, and problem (4): "Reading from a NAND flash memory takes time against the demand for high‑speed reading." This is applicant‑admitted prior art usable in a § 103 rejection. Confidence: high (quoted verbatim in the supplied patent text).

PA‑2 — US 5,172,338 (Mehrotra, Harari & Lee; SanDisk; "Multi‑state EEPROM read and write circuits and techniques"; issued 1992‑12‑15; reexam. cert. B1). The '338 patent discloses, for a cell storing K states, providing K‑1 (preferably K) reference levels and comparing the addressed cell to the K reference cells using k sense amplifiers in parallel, which the specification states "is preferable … because of speed." The specification further discloses parallel verify across a chunk of cells with per‑cell latches that inhibit further programming once verified. The quotation below is reproduced in the International Trade Commission's In re Certain Flash Memory Circuits opinion (Inv. No. 337‑TA‑615, USITC Pub. 3046), citing CX‑2 at col. 11, lines 56–61:

"if each memory cell is to store K states, then at least K − 1, or preferably K reference levels need be provided. In one embodiment, the addressed cell is compared to the K reference cells using k sense amplifiers in parallel. This is preferable for the 2‑state case because of speed…"

Confidence: high that the patent exists with this disclosure (multiple independent corroborations: USITC Pub. 3046 at pdf pp. 12–22; USITC Pub. 3970; the IEEE Milestone background document hosting its face page; the JP counterpart JP 2002‑528845 quoting the same passage).

PA‑3 — US 5,095,344 (Harari; multi‑level EEPROM sense/read circuitry). Surfaced repeatedly as the companion reference to '338 (US 5,092,344/5,095,344 appear together in the JP 2002‑528845 discussion of using 3 or 4 reference currents/levels). Confidence: medium‑high.

PA‑4 — Conventional dual‑amplifier column‑read architecture (DRAM‑type). In the IPR record for a DRAM sense‑amplifier patent (Petition/Expert Declaration, IPR2017‑01414/01415), the combination Inoue (FIG. 6 cross‑coupled flip‑flop sense amplifier on a bit‑line pair), Min (multi‑column array with SA₁…SA_N), and Hamade (a "drive circuit 9 … provided for each bit line pair" forming a column read amplifier that drives read‑only data lines RI/RI̅ through a column read signal) is described. Hamade thus discloses two sense amplifiers per bit‑line pair plus a column‑gated differential read path — structurally the '979 claim‑1 topology in DRAM form. URL: https://cmosedu.com/jbaker/expert_witness/2017/IPR2017_01414.pdf. Confidence: medium on exact bibliographic data; I am relying on the quoted expert/Petition characterization, not on the face of Hamade, which I did not retrieve.

PA‑5 — WO 98/25272 (sense amplifier with stepped control signal; two‑stage amplification, precharge transistor, bit‑line equalization). Surfaced in search (WO1998025272A1). Its claims recite a precharge transistor, an equalizing transistor, and a two‑stage sense amplifier — directly relevant to dependents 4/9/12 and to the detailed circuit claims. Confidence: medium‑high that it exists with that content (the claim text was in the search return).

Non‑prior‑art for § 103 — family members. US 5,831,900 (parent) and US 6,331,960 B1 (continuation) share the '979 priority and disclosure; they are not available as prior art and are listed only to mark the metes of the family.

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4. Grounds of rejection

Ground 1 — Claims 1, 2, 7, 8, 15 (dual sense amplifier on one bit line, two buses)

Primary: PA‑2 (US 5,172,338), in view of the admitted multi‑level architecture of PA‑1.

Motivation / rationale. (a) PA‑2 expressly teaches the reason to put multiple sense amplifiers on one cell: speed ("preferable … because of speed"). (b) PA‑1 admits the multi‑level read‑time problem (111.8 µs) and its stated object is high‑speed reading. (c) Placing a second amplifier on the same bit line with a column‑gated output path is the predictable use of a known technique to improve a similar device in the same way (KSR at 417). (d) The alternative — re‑precharging the bit line and re‑sensing per threshold level — is exactly the slow path the '979 patent criticizes, so the artisan has a finite, identified set of solutions (duplicate the sense amp, or time‑multiplex one amp); both are within the claims' contemplation. Reasonable expectation of success is high: the elements are standard CMOS building blocks and only the count of amplifiers changes.

Claim 7 (second amplifier connected directly to the bit line, no second MOS transistor) is met by the same combination and, in addition, is obvious as the mere omission of a selection transistor whose only function (per the '979 specification: "in a specification where slower data load is acceptable … the MOS transistor Q4' may be omitted") is to permit data loading during programming. Omission of a non‑critical, functionally optional element with no change in the recited read function is a per se obvious design choice. Claim 15 (1st SA via transistor, 2nd SA direct, two differential buses) is the same combination; its truncated tail cannot be separately assessed.

Claim 2 / 8 (bus = line + inverted line): differential (true/complement) I/O is the default in semiconductor memory and is disclosed by PA‑4's RI/RI̅ pair and by the inherent differential output of the cross‑coupled latch sense amplifiers of PA‑2/PA‑4.

Ground 2 — Claims 3, 10, 11, 12 (single, shared column‑gated bus)

Primary: Ground 1 combination, further in view of the conventional column‑gate multiplexer.

Claim 3 differs from claim 1 only in reciting one bus with a column gate that selectively connects one or the other amplifier output. The '979 specification itself concedes this is a known pin‑count trade‑off: "a single couple of data bus lines is also acceptable if they are alternatively made to appear on the data bus by appropriate switching of the column gates." Where the applicant's own specification characterizes a claimed alternative as an acceptable, known option, the claim is obvious over the art that discloses the multi‑bus version plus the ubiquitous column multiplexer. KSR ("a finite number of identified, predictable solutions"). Claim 10 is the same as claim 3 with the second amplifier direct — obvious for the § 4/claim‑7 reasons.

Ground 3 — Claims 4, 9, 12 (precharge circuit coupled to the bit line)

Primary: PA‑2 and/or PA‑5. Bit‑line precharge/equilibration is the foundational, ubiquitous step of every dynamic sensing scheme; PA‑5 recites a precharge transistor and an equalizing transistor in express terms, and PA‑2's read/verify relies on precharged bit lines. Adding a precharge circuit to a flash/EEPROM bit line is the paradigm of a predictable, art‑recognized improvement. Note: the record shows the '979 patent's own prosecution resulted in the duplicate claim 6 ("according to claimed 3, further including a precharge circuit"), which is strong evidence that even the applicant treated the precharge limitation as routine and non‑distinguishing.

Ground 4 — Claims 13 and 14 (full transistor‑level recitations)

Primary: Ground 1 combination, further in view of PA‑2/PA‑4 (cross‑coupled flip‑flop sense amplifier) and routine circuit design.

Claims 13/14 recite the FIG. 7 sense amplifier as: a cross‑coupled latch, a reset/activation transistor (Q3/Q‑third MOS, gate driven by a first signal), and a series read/invert stack (fourth and fifth MOS transistors, the fifth gated by the bit line). Every one of these is textbook: a CMOS latch sense amplifier with a set/reset device and a bit‑line‑sampling transistor is disclosed in PA‑2 and PA‑4 (Inoue FIG. 6 latch with clocked Q_P3/Q_N10 supply/ground switches; Hamade's amplifiers). Converting that known amplifier into the claimed dual‑amplifier/per‑amplifier‑transistor‑stack form is arranging old elements to perform their known functions, which KSR holds obvious. Claim 14's only delta over claim 13 is the single shared differential bus, addressed in Ground 2.

Ground 5 — Claim 16

Cannot be assessed: the claim text is truncated in the source. I will not guess at its scope. If it tracks the FIG. 18 read‑timing scheme (strobing at successive verify levels while holding one precharge), the Ground‑1 combination plus PA‑2's parallel comparison remains the primary ground, but this is expressly provisional.

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5. Why a PHOSITA would have combined these teachings (motivation, consolidated)

1. Same field, same problem. All references address sensing the state of nonvolatile/charge‑storage memory cells with sense amplifiers. KSR and the analogous‑art cases require no more for combinability.
2. Express, self‑evident motivation to duplicate the amplifier per bit line. PA‑2 literally states plural sense amplifiers in parallel are preferable for speed — the exact object the '979 Background sets out (problem (4)). The motivation is not synthesized by the analyst; it is on the reference's face.
3. Admitted problem + express object in the '979 patent. The patent admits that re‑reading a multi‑level cell iteratively is slow and states its object as high‑speed reading. A reference teaching "use k parallel sense amplifiers for speed" directly answers the admitted need — the "design incentive … [and] market force" prong of KSR.
4. Predictable result / reasonable expectation of success. Adding a second sense amplifier, a coupling transistor, and a column‑gated output path are standard, low‑risk circuit moves; the outcomes (faster sensing, unchanged array operation) are entirely predictable.
5. Finite solution space. Faced with multi‑level read latency, the artisan has essentially two known options — time‑multiplex one amplifier, or multiply amplifiers. Both approaches are what the claims recite in their alternative independent forms (claims 1/7 vs. 3/10).
6. No teaching away. Nothing in PA‑1–PA‑5 suggests using multiple sense amplifiers on a bit line is inoperable or disfavored. (One might argue the '979 patent's verify‑programming statement — "a single sense amplifier is sufficient regardless of the numbers of multiple levels" — teaches away from multiple amplifiers, but that statement concerns the write/verify path, whereas the claims at issue target the read path; the specification affirmatively uses two amplifiers there. Any teaching‑away argument fails on the claims' own field of use.)

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6. Secondary considerations

Nothing in the record supplied evidences objective indicia attaching to these claims. The '979 specification's stated advantages (small sense‑amplifier area; variable level count via constant‑voltage circuits; block‑level flag storage) inure to the multi‑level programming / flag‑cell subject matter that the '979 claims do not cover — an important asymmetry: the commercial value narrative of the specification belongs to the family's other claims, not to claims 1–16 of this divisional. There is also no § 103 nexus between the "flexibly determine multiple levels" benefit and the dual‑sense‑amplifier claim elements. Unexpected results, long‑felt need, and industry praise would need affirmative evidence (e.g., a product embodying the dual‑amplifier feature that succeeded because of it); none appears here.

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7. Confidence, contradictions, and open items

• Confidence: high that claims 1, 3, 4, 7–12, and (on the structural reading) 13–15 are obvious over PA‑1 + PA‑2 + conventional column‑gate/precharge design. The dual‑amplifier‑per‑bit‑line concept and its speed rationale are both squarely in the admitted prior art and in US 5,172,338.
• Confidence: medium for the DRAM‑architecture mapping (PA‑4, Hamade/Inoue/Min) as a secondary ground, because I could retrieve it only through the IPR expert‑declaration characterizations, not the references' face pages.
• Caveats / uncertainties (stated rather than bridged): (i) the front‑page "References Cited" table was not present in the supplied page text, so the examiner‑of‑record art could not be evaluated; (ii) the truncated claims 15 and 16 were not fully analyzed; (iii) I did not verify the bibliographic data of PA‑3 and PA‑5 on their face pages; (iv) the prior‑art keyword set (mos transistor, terminal, line, sense amplifier, bit line) is consistent with, but does not itself prove, a field‑of‑search that places the claimed elements in the art.
• Contradiction flag: there is no contradiction between the previously generated sections and this one — the earlier summary correctly identified the claims as sense‑circuit‑directed and the abstract as broader than the claims. This analysis builds on that finding rather than restating it.
• Practical note: the patent is recorded as Expired – Lifetime (anticipated 2016‑09‑12), so § 103 obviousness bears on historical validity/defensive use, not on prospective infringement. Any invalidity contention should be run against the FIG. 17/18 embodiment's actual written‑description support in the 1995 application to confirm the critical date used above.

Primary source: https://patents.google.com/patent/US6166979/en · ITC corroboration of PA‑2: https://www.usitc.gov/publications/337/pub3046.pdf and https://www.usitc.gov/intellectual_property/documents/pub3046.pdf · DRAM‑architecture combination (PA‑4): https://cmosedu.com/jbaker/expert_witness/2017/IPR2017_01414.pdf · Parent/family: https://uspto.report/patent/grant/[5831900](/patent/5831900)