US 12133429

I'll search for authoritative information on this specific patent number and any associated 2026 litigation.

Let me check for the specific 2026 litigation docket and any CAFC activity tied to this patent.

Let me look deeper at the 2026 litigation and check the Federal Circuit docket.

US Patent 12,133,429 B2 — Analyst Summary

Search scope note: I searched for the exact identifier "12133429" and cross-checked against the full patent text. USPTO Patent Center and PACER were not accessed directly; bibliographic data below is from the patent's own front-page/Google Patents record, and litigation data is from third-party docket aggregators. Items I could not verify authoritatively are flagged.

---

1. Bibliographic Data

Family / related applications:

• US 18/822,176 — continuation, filed 2024-08-31, published US 2024/0423035 A1, status Pending
• CN 114613825 B (granted 2024-09-06); CN 119110631 B (granted 2025-11-07); WO 2023168754 A1 (PCT, ceased)

Prior art cited of record (8): CN105321957A; CN112310044A; CN112670304A; CN113826210A; CN113871420A; US2021/0134846A1 (Innolux); US2022/0157919A1 (BOE); US2023/0122411A1 (Hefei BOE). One non-patent citation: the International Search Report/Written Opinion dated 2022-11-30 for PCT/CN2022/082256.

---

2. Abstract (verbatim)

"A display panel and a display device are provided. The display panel includes a shielding layer, a pixel driving circuit layer located on the shielding layer and including a plurality of pixel driving circuits at least partially overlapping the shielding layer, and a power supply line electrically connected to a plurality of through holes of the shielding layer disposed in the pixel driving circuit layer. A converging line between adjacent through holes are arranged according to a shortest distance between the adjacent through holes."

---

3. Independent Claims — Plain-Language Overview

The patent has 20 claims, of which two are independent: claim 1 (a display panel) and claim 11 (a display device). Claim 11 is independent in form but incorporates claim 1 by reference.

Claim 1 — Display panel (the core claim)

A display panel divided into a display region and a non-display region on at least one side, comprising:

1. A substrate.
2. A shielding layer on the substrate — made up of (a) multiple shielding blocks and (b) a converging wire electrically connected to those blocks, with the converging wire sitting on at least one side of the blocks. (The shielding layer is the "bottom shielding metal" that blocks the pixel circuits from below.)
3. A pixel driving circuit layer on the shielding layer — containing pixel driving circuits in the display region, each at least partly overlapping a corresponding shielding block.
4. Multiple power supply lines on the side of the shielding layer facing away from the substrate, electrically connected to the converging wire through a plurality of through holes.
5. The distinguishing limitation: the segment of the converging wire between two adjacent through holes is disposed according to the shortest distance between those two adjacent through holes — i.e., the wire takes the direct/straight path between neighboring contact holes rather than a meandering or serrated path.

Practical meaning: By routing the converging wire along the shortest path between adjacent power-supply contact vias, the expected current path stays inside the metal's boundary, avoiding the charge-accumulation "tips" of serrated bottom-shielding-metal edges that caused ESD explosions in prior designs. (Specification: "expected current path... is conducted along the shortest distance," reducing charge accumulation at the shielding layer boundary and ESD damage.)

Claim 11 — Display device

A display device comprising the display panel of claim 1, further specified as an organic light-emitting diode (OLED) panel. Its only added technical limitation over claim 1 is the OLED character of the panel. (Claims 12–20 are merely the claim 1–10 features re-stated in device form.)

Dependent-claim scaffolding (context for the independent claims)

• Claims 2–3: the inter-hole segment is linear; optionally the whole converging wire is linear and the overlapping through holes are arranged in a line.
• Claims 4–6: the converging wire is a first converging wire with wider first connection sections (arc/oval periphery) joined by narrower second connection sections; power lines connect to the first connection sections; each first connection section serves a column of shielding blocks.
• Claims 7–8: non-display region split into first (with bending sub-region) and second non-display regions, with first and second converging wires respectively.
• Claims 9–10: layer stack of the pixel driving circuit layer (semiconductor layer, first insulating layer, first gate metal, second insulating layer, second gate metal, third insulating layer, plus a fourth insulating layer and second conductive layer), with the through holes penetrating specified layers and second through holes being wider than first through holes.

---

4. 2026 Litigation / Docket Findings

District court (the operative 2026 case)

• Case: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. v. Samsung Display Co., Ltd., [Walmart Inc.](/litigations/by-defendant/Walmart%20Inc.), and Best Buy Co., Inc., No. 2:26-cv-00228, U.S. District Court for the Eastern District of Texas, Marshall Division (Judge Rodney Gilstrap).
• Filed: March 19, 2026 (docket records). A First Amended Complaint appears in the record (aggregator shows a filing date of March 24, 2026 — see uncertainty note).
• Plaintiff: Wuhan China Star (a TCL CSOT subsidiary — reflected in press coverage describing the case as "TCL CSOT v. Samsung").
• Patents asserted in the amended complaint: US 12,133,429 (the '429 patent), US 11,957,031 ('031), and US 11,257,891 ('891).
• For the '429 patent: the complaint asserts at least independent claim 1; the allegation tracks the claim-1 elements, with the contested feature being whether the accused panels' converging wire is "disposed according to a shortest distance" between adjacent through holes.
• Accused products (as identified in the complaint): Samsung Display "Accused OLED Display Panels," incorporated into consumer devices such as the Google Pixel 8 series, Pixel 9 series, and Pixel 10 series phones (including Fold models), plus tablets/wearables and replacement-panel channels.
• Relief theories: direct, induced, contributory, and willful infringement.

Federal Circuit (2026)

• Appeal No. 26-1092, Wuhan China Star Optoelectronics Semiconductor Dis v. Samsung Display Co., Ltd. — a nonprecedential ORDER posted April 8, 2026 on the CAFC's official site. The docket line lists Origin: PTO.

Important caveat: I found no Federal Circuit docket entry that is expressly identified as an appeal concerning the '429 patent. Appeal 26-1092 shows an origin at the PTO, which suggests it arises from a PTAB proceeding — consistent with the related dispute in which Wuhan China Star filed IPR petitions (e.g., IPR2023-00941, IPR2023-01075, IPR2024-00620) against Samsung Display patents — rather than from the E.D. Tex. '429 case. I therefore cannot confirm that 26-1092 involves US 12,133,429, and I am not asserting that it does.

---

5. Explicit Uncertainty Notes

• Docket provenance: The E.D. Tex. details come from third-party aggregators (Unified Patents/Darts-IP link on the patent page, plus docket-analysis sites), not from PACER directly. Minor date discrepancies exist (complaint 03/19/2026 vs. 03/24/2026 for the first amended complaint).
• CAFC linkage: Appeal 26-1092 is confirmed to exist (April 8, 2026 nonprecedential order), but its subject patent is unverified; "Origin: PTO" indicates a PTAB-origin appeal, not necessarily this patent.
• Inventor attribution anomaly: A third-party "patent leaderboard" page lists a "Xing Wu" with 9 patents attributed to Hefei BOE Optoelectronics, including 12,133,429. That attribution conflicts with the patent's own front page (sole inventor "Xing Wu," assignee Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.). I treat the patent front page / assignment record as authoritative and flag the aggregator entry as likely erroneous conflation of two different inventors.
• No reissue, disclaimer, or PTAB trial record specific to the '429 patent was found in the searches performed; Google Patents shows no "Cited by examiner" PTAB challenge to this patent, and no IPR/CBM number tied to 12,133,429 appeared in results.

I'll search litigation databases for this specific patent number.

Let me dig into the specific EDTX case and the TCL/CSOT assertion.

Let me verify case details and check for any additional proceedings (ITC, UPC, other districts).

Litigation involving U.S. Patent No. 12,133,429

One litigation is known. Below are the verified details.

---

Case 1 — Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. v. Samsung Display Co., Ltd., [Walmart Inc.](/litigations/by-defendant/Walmart%20Inc.), and Best Buy Co., Inc.

Sources:

• Google Patents family/litigation link for US12133429B2: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A26-cv-00228 (from the patent page: https://patents.google.com/patent/[US12133429](/patent/US12133429)/en)
• Justia docket listing (EDTX patent cases, 2:2026cv00228): https://dockets.justia.com/browse/court-txedce/noscat-10/nos-830?page=17
• First Amended Complaint text (EDTX, 2:26-cv-228, Marshall Division): https://ai-lab-cl-prod.azurewebsites.net/case/dct/txed/2:26-cv-00228/doc/analysis/8
• Law360, "TCL Unit Fires Back At Samsung With Its Own OLED Patent Suit" (Mar. 20, 2026)
• ZDNet Korea (2026-03-23): https://zdnet.co.kr/view/?no=20260323210003
• OLED-Info / IPVerse litigation note (Mar. 21, 2026)

---

Important caveats and disambiguation

1. Docket cause-of-action code is odd. The Justia entry lists the cause of action as "15 U.S.C. § 1126" rather than 35 U.S.C. § 271. The complaint text itself pleads patent infringement under 35 U.S.C. § 1 et seq. (including § 271), so the § 1126 code appears to be a docketing artifact. I am flagging it rather than silently correcting it.

2. This is a counterstrike in a broader TCL/CSOT–Samsung Display dispute. Samsung Display sued Wuhan CSOT and TCL CSOT in N.D. Tex. No. 3:25-cv-01430 (filed June 2025), asserting U.S. 11,594,578, U.S. 7,414,599 and U.S. 9,330,593. That case does not involve the '429 patent and should not be listed as '429 litigation. Likewise, Samsung Display's EDTX suits against BOE (2:23-cv-00309; 2:25-cv-00412, -00426, -00430) do not involve the '429 patent.

3. No ITC, UPC, or CAFC proceeding on the '429 patent was found. My searches surfaced an ITC investigation (Inv. No. 337-TA-1351) and numerous PTAB IPRs in the wider Samsung Display/CSOT OLED dispute, but none asserting or challenging U.S. 12,133,429. A CAFC appeal exists in the dispute (No. 26-1092, Wuhan China Star … v. Samsung Display), but it arises from PTAB IPR2024-00620 and concerns the '593 patent — not the '429 patent.

4. Legal-status dates on the patent itself: the patent (app. 17/764,557) is Active; prior-art date listed as 2022-03-11; anticipated expiration 2042-03-22. A continuation, U.S. App. 18/822,176 (US 2024/0423035 A1), is pending. Neither is itself litigation.

5. Verification limits. I did not have direct PACER or Unified Patents portal access in this session; the case number and court are corroborated by the Google Patents litigation link and by an independent docket aggregator, and the complaint text confirms the case number and the three asserted patents. If you need certified docket-level precision (e.g., exact service dates, answers, or any motion to transfer to Judge Gilstrap's docket), a PACER pull on 2:26-cv-00228 is the appropriate next step.

I'll verify the proceeding data and check for any publicly available developments before writing up.

PTAB / AIA Trial Analysis — US 12,133,429 B2 ("Display panel and display device")

Data cutoff: 2026-09-18. Source of record for the proceeding list: USPTO Open Data Portal snapshot supplied in this prompt. Claim text, family data, and cited art come from the full patent text (Google Patents, fetched 2026-09-18).

---

Proceedings overview

One (1) AIA trial proceeding is on file against US 12,133,429: IPR2026-00487, filed 2026-09-17 by Samsung Display Co., Ltd. — status Pending; zero claims invalidated, zero claims sustained, zero settlements, zero institution denials.

Bottom-line defensive posture: the patent is entirely untested at the PTAB. There is no final written decision, no institution decision, and no public petition yet. All 20 claims — independent claims 1 and 11 and dependents 2–10 and 12–20 — stand unadjudicated, so any current demand letter citing claims 1–20 is citing live claims. What a defendant does have is (a) confirmation that a well-resourced adversary (Samsung Display, the largest OLED panel maker and a co-defendant in the underlying Texas suit) considers the patent worth attacking, and (b) a short window in which to align with, join, or design around that petition before the institution decision lands.

---

IPR2026-00487 — Samsung Display Co., Ltd. v. Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2026-09-17
• Status: Pending (verbatim from the structured data). Plain-English gloss: petition filed one day before this analysis; the Board has not yet accorded a filing date, and no preliminary response or institution decision is on the record.
• Judge panel: Not yet public. The PTAB does not typically name the three-APJ panel until the institution decision issues (or, in some cases, on a POPR-stage order). No panel names should be assumed.
• Petition grounds: Not yet public / unknown. I will not guess. The petition has not surfaced on PTAB E2E or in third-party mirrors as of 2026-09-18, and the structured feed supplies no grounds field. For planning purposes only, the eight references cited on the face of the patent are the obvious candidate pool: CN105321957A, US20220157919A1, US20210134846A1, CN113826210A, CN113871420A, CN112310044A, CN112670304A, US20230122411A1. Treat that list as inference, not fact — Samsung Display may well have assembled art that never appeared in prosecution. Statutory basis cannot be stated with confidence either, though IPRs are limited to § 102/§ 103 on patents and printed publications (no § 112 grounds available in IPR).
• Institution decision: None. Not yet due. Under § 314(b), if patent owner files a preliminary response, the Director's decision is due within 3 months of that response; absent a POPR, institution is due by roughly 6 months from the notice according filing date. Practical planning dates: POPR due ≈ 2026-12-17 (3 months from filing) and institution decision by ≈ 2027-03-17, barring extensions. Note the standing risk from Revvo Technologies v. Cerebrum Sensor Technologies (IPR2025-00632, Director Review 2026) and the February 2026 Director Review vacaturs — institution is not a rubber stamp, particularly where claim constructions diverge between the Board and the district court.
• Final Written Decision: None. No FWD has issued, so no claim of US 12,133,429 has been canceled or sustained. Any statement to the contrary would be false. Under § 316(a)(11), if instituted around 2027-03, the FWD would be due ≈ 2028-03-17 (one year from institution, extendable up to six months for good cause).
• Settlement / termination: None. No termination on the record. The parties are adverse in co-pending district court litigation (below), which makes a near-term settlement less likely than the reverse — captive-respondent dynamics cut both ways here.
• Appeal: None — nothing appealable yet. No FWD, so no Federal Circuit jurisdiction under § 319. No CAFC docket number exists.
• Defensive value: For a defendant other than Samsung Display, this petition is the most valuable single piece of information about this patent — but it is a petition, not a holding. Two concrete uses: (1) consider a § 315(c) joinder motion once institution is granted, which avoids a separate petition and its estoppel tail — but note the Facebook v. Windy City line of authority limits a joined party to the petitioner's existing grounds and bars new substantive arguments; and (2) if you are separately threatened and outside Samsung Display's privity chain, the § 315(b) one-year clock is running from your service date, and filing your own petition with a distinct, non-redundant ground is the only way to preserve it.

---

Litigation context for the same patent (not an AIA proceeding, but it is what drives the petition)

The IPR did not appear in a vacuum. The '429 patent is one of three patents asserted against Samsung Display in a Texas action filed 2026-03-19:

• Asserting party: CSOT / TCL China Star Optoelectronics Technology Co., Ltd. (with Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. as patent owner of record).
• Patents asserted together: US 12,133,429; US 11,957,031; US 11,257,891.
• Court / case: Texas Eastern District Court, 2:26-cv-00228 (per the patent record's litigation link; the Unified Patents portal entry supplied on the patent page is a database link, not evidence that Unified Patents is a party — there is no defensive aggregator in this chain).
• Accused products (per press reporting): Google Pixel 8 / 9 / 10-series smartphones and other tablet/wearable panels supplied by Samsung Display; Walmart and Best Buy named as downstream distributors.
• The countervailing case: Samsung Display's earlier suit against Wuhan China Star, TCL China Star, and Vican Inc., N.D. Tex. 3:25-cv-01430 (filed 2025), asserting US 11,594,578; 7,414,599; 9,330,593. Amended scheduling order entered 2026-05-12: claim construction hearing 2026-09-16 before Judge Karen Gren Scholer, fact discovery due 2027-01-08, trial docket beginning 2027-10-05. (CourtListener docket 70468030)
• Samsung Display's IPR was filed 2025-09-17 → 2026-09-17, roughly six months after the E.D. Tex. complaint and inside the § 315(b) one-year window.

---

Strategic summary

Claim status: 20 of 20 claims UNTESTED; none canceled, none sustained. Independent claim 1 covers the core structural combination (substrate → shielding layer with shielding blocks and a converging wire → pixel driving circuit layer → power supply lines connected to the converging wire through through-holes, where the converging wire between two adjacent through-holes is disposed according to the shortest distance between them). Independent claim 11 recites a display device comprising the claim 1 panel and adds "wherein the display panel is an organic light-emitting diode (OLED) panel." Claims 2–10 and 12–20 add narrowing structure: linear converging wire (3, 13), the alternating first/second connection sections with arc-shaped peripheries (4–6, 14–16), the bending sub-region split (7–8, 17–18), and the stacked-layer / dual-diameter through-hole architecture (9–10, 19–20). Because nothing has been construed or canceled, there is no surviving-claim list to give you — the whole claim set is live, and claim 1 is the broadest and therefore the most exposed target.

Estoppel landscape. § 315(e)(2) estoppel attaches only after a final written decision, and there is none — so today no estoppel runs against anyone. That changes in two ways worth planning around. First, if Samsung Display is instituted and an FWD issues (projected ≈ 2028-03-17), Samsung Display and its real parties in interest and privies are barred from re-litigating before the district court any ground raised or that reasonably could have been raised. Whether that bar reaches co-defendants Walmart and Best Buy depends entirely on privity — retailers sued as downstream distributors are usually not privies of the panel supplier, so do not assume the retail defendants get the estoppel benefit of Samsung's IPR. Second, for any other defendant being threatened (e.g., by CSOT on the sibling patents 11,957,031 and 11,257,891), the entire prior-art space remains open: no ground has been litigated, no § 315(e) bar exists, and a petition filed within one year of your service date preserves everything.

Pattern signals. This is a single IPR on a single patent of a three-patent assertion, filed by a party that is simultaneously the primary defendant in the Texas case and the plaintiff in an overlapping N.D. Tex. case — i.e., a classic counter-assertion posture rather than a defensive-aggregator strategy. Expect the companion IPRs against 11,957,031 and 11,257,891 to have been filed in the same window; I found no confirming record for those, and the structured feed covers only this patent, so I will not assert numbers I cannot verify. Notably absent: no Unified Patents or other aggregator filing, no ex parte reexam, and no § 315(a) declaratory-judgment bar issue apparent on this record. The patent owner's family also carries a live continuation, US 18/822,176 (US 2024-0423035 A1, published 2024-12-19), plus CN114613825B and CN119110631B — meaning invalidating the '429 claims in an IPR does not neutralize the family, and new claims can be prosecuted in the continuation. Any settlement or license you negotiate should expressly cover the continuation and the CN family.

---

Recommended next steps

1. Pull the petition the day it publishes. Monitor PTAB E2E / PTAB Center for IPR2026-00487 and confirm the real parties in interest and any § 315(a)/(b) challenge. Also check USPTO Patent Center for application 17/764,557 and its file wrapper.
2. Calendar the statutory dates. POPR ≈ 2026-12-17; institution decision due ≈ 2027-03-17; if instituted, FWD due ≈ 2028-03-17 (6-month extension available for good cause). Oral hearing, if scheduled, typically falls 2–3 months before the FWD (~late 2027 / early 2028).
3. If you are a defendant outside Samsung Display's privity chain: do not wait. A § 315(c) joinder motion is cheap but confines you to the petitioner's grounds (Facebook v. Windy City). If you hold materially different art, a standalone petition filed within one year of your service date is the only way to lock in that ground — and to preserve § 315(e)(2) estoppel in your favor, which requires getting to an FWD yourself.
4. Do not treat the '429 as narrowed. No FWD exists. Any invalidity or non-infringement position for 2026–2027 must be built on the claim language as issued, read against the specification's "shortest distance between adjacent through-holes" requirement — which is the natural narrow construction hook a defendant would want (the prosecution-history and specification support a fairly specific geometric requirement, and whether Samsung Display's art teaches that geometry is the crux of claim 1).
5. Sibling-patent exposure. CSOT asserted US 11,957,031 and US 11,257,891 alongside the '429. If a demand letter or complaint reaches you on those, the same analysis applies but with even less public PTAB data — treat them as virgin targets and preserve your own filing windows.

Caveat on completeness: everything above the "Litigation context" heading is grounded in the structured PTAB feed and the patent text. The grounds, panel, petition content, and any parallel IPRs on the sibling patents are not yet public and are flagged as unknown rather than inferred — I have deliberately not manufactured claim-level outcomes, judge names, or settlement terms for a proceeding that is one day old.

I'll verify the assignment record and litigation activity before reconstructing the chain.

Let me check the assignment record details and the 2026 litigation's asserted patents.

Ownership & Assignment Reconstruction — US 12,133,429 B2

Patent: "Display panel and display device" • App. 17/764,557 (371(c) of PCT/CN2022/082256) • Priority 2022-03-11 (CN 202210237733.1) • Filed 2022-03-22 • Granted 2024-10-29 • Anticipated expiration 2042-03-22 • Status: Active
Sources: Google Patents legal-events record for US12133429B2; USPTO Assignment Center search target (https://assignmentcenter.uspto.gov/, patent no. 12133429); E.D. Tex. docket 2:26-cv-00228; N.D. Tex. docket 3:25-cv-01430; NCPSS business registry (Tianyancha).

---

Inventors

Pattern note: Single-inventor application — unusual for a panel-architecture (multi-layer TFT + shielding) filing, which normally lists a process/integration team. No evidence of inventor departure: nothing in the file or the corporate record indicates Wu left the assignee, and no subsequent assignment signed by Wu appears. There is no "all inventors left within 12 months → fire-sale" pattern here; this is a classic employee-invention capture inside a large captive R&D organization (≈6,058 employees on social insurance at the assignee per Chinese registry data).

---

Original assignee

Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. (武汉华星光电半导体显示技术有限公司)

• Address of record: Room 305, Building C5, Optics Valley Biological Innovation Park, No. 666 Gaoxin Ave., Donghu New Technology Development Zone, Wuhan, Hubei 430077, CN (the same address appears in Samsung Display's pleadings).
• Registered: 2016-10-24; status 存续 (in-existence / operating); registered capital RMB 21,000,000,000.
• Ownership: TCL China Star Optoelectronics Technology Co., Ltd. (TCL CSOT) ~62.4%; Wuhan Guanghua Semiconductor Display Industry Development Fund LP ~36.2%; Wuhan Optics Valley Industrial Investment Co. ~1.4%. TCL CSOT is the panel arm of TCL Technology Group Corp. (publicly listed; TCL Electronics/TCL Technology filings are the natural SEC-equivalent disclosure channel — note this is a PRC-listed group, not an SEC registrant).
• Primary line of business: design/manufacture/sale of 6th-generation flexible LTPS-AMOLED display panels and modules (business scope amended 2023-12-19 to "electronic components manufacturing, display device manufacturing and sales").

Does it ship a product embodying the claims? Yes, on the pleaded record. Samsung Display's N.D. Tex. complaint (3:25-cv-01430, ¶¶9–11) alleges Wuhan CSOT "knowingly suppl[ies] OLED displays" for TCL 10 Pro / TCL 20 Pro 5G / TCL 30 5G smartphones and for aftermarket OLED screen assemblies — i.e., the accused commercial product is the assignee's own panel output.

Current status: Operating. No insolvency, dissolution, or restructuring event appears in the record. (Note: a separate, unrelated SEC EDGAR hit for the string "12133429" is a Lighting Science Group Corp. filing identifier from 2012 — a coincidental accession-number match, not this patent.)

---

Assignment timeline

Important limitation, stated plainly: Google Patents' legal-events record shows the assignment transaction (date, assignor, assignee, conveyance type) but does not expose reel/frame numbers or the correspondent of record. I could not retrieve those fields from the sources available to me. Rather than fabricate a reel/frame, I am reporting the entry as it exists and flagging the gap below.

• executed on or before 2022-04-01 / recorded 2022-04-01 — Reel not retrievable from available sources (verify at USPTO Assignment Center, patent 12133429)
  • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: Wu, Xing (sole)
  • Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
  • Correspondent: not disclosed in the retrieved record — no repeat-correspondent finding can be made either way. To complete this field, pull the recorded cover sheet from Patent Assignment Search (search by patent number 12133429, or by assignor "WU, XING" with the 2022 recording window).
  • Context: Initial employee-invention assignment — the routine capture of a company engineer's invention by the employer, executed after the 2022-03-11 CN priority filing and the 2022-03-22 PCT filing, recorded ~10 days after the PCT filing date.

No further recorded assignments. No post-issuance transfer, no security interest, no license recordation, no name change, no release. Related family members (CN114613825B, CN119110631B, US 2024/0423035 A1 pending continuation filed 2024-08-31, WO2023168754A1) remain inside the same corporate group. The original assignee still owns the patent.

If the chains you normally track are NPE chains, the diagnostic here is the absence of a chain. One recorded link, assignor = the human inventor, assignee = the operating employer. That is the signature of a captive corporate portfolio.

---

Timeline diagram

timeline
    title Ownership of US 12133429
    2022 : CN priority filing Mar 11
         : PCT filed Mar 22
         : Inventor assignment recorded Apr 1
    2024 : US patent granted Oct 29
         : Continuation application filed Aug 31
    2026 : Suit filed v Samsung Display Mar 19

---

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
The only recorded conveyance runs from the individual inventor to the operating manufacturer. There is no transfer to any entity bearing an "IP / Patents / Licensing / Holdings / Ventures" suffix, no LLC assignee, and no registered-agent-service address anywhere in the record. The assignee's address (Bldg. C5, Optics Valley Biolake, Wuhan) is a manufacturing/R&D campus, not a service address.

2. Known asserter in the chain — NOT PRESENT.
Neither the current nor any prior assignee matches the standard NPE rosters (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Spangenberg entities). The owner is TCL CSOT's semiconductor-display subsidiary — an operating panel maker. Its litigation posture is the defensive/counter-assertion posture of a large manufacturer, not a licensing program.

3. Repeat correspondent across the chain — NOT PRESENT / UNVERIFIABLE (n = 1).
With a single recorded assignment there is no recurrence to detect, and the correspondent field was not retrievable. Explicitly: I found no evidence linking this patent to a repeat-player NPE recording attorney. Do not read the absence as exoneration of a correspondent I never saw — it is simply an unfilled field.

4. Cascading transfers — NOT PRESENT.
Zero consecutive transfers, let alone chained LLC hops in under 24 months. Twenty-eight months elapsed between the inventor assignment (2022-04-01) and issuance (2024-10-29) with no movement of title.

5. Pre-litigation transfer — NOT PRESENT.
This is the decisive negative. The patent was asserted by the original assignee itself. On 2026-03-19 Wuhan China Star filed 2:26-cv-00228 (E.D. Tex.) against Samsung Display Co., Ltd. (with Walmart and Best Buy named as downstream sellers per secondary reporting). Chinese-language coverage of the complaint identifies US 12,133,429 as the first of three asserted CSOT patents, describing it as an OLED panel structure in which a metal shielding layer beneath the TFT pixel circuit connects to power lines through vias, with vias arranged so current follows the shortest straight path between holes — a faithful match to claim 1 of this patent. No assignment was executed inside the 6-month window before filing, because none was needed: the plaintiff never parted with title.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7/11 for the assignee, no 363 sale, no patent-auction involvement.

7. Privateering — NOT PRESENT.
Privateering requires the operating company to hand the patent to an NPE that asserts on its behalf. Here the operating company is the named plaintiff in its own name, asserting against a direct competitor in a two-way dispute it did not initiate (Samsung Display sued Wuhan CSOT / TCL CSOT in 3:25-cv-01430 (N.D. Tex.), and the parties have been fighting IPRs — IPR2023-00941, -01075, -01221, -2024-00620 — before the PTAB since 2023). Google Patents also carries a Darts-ip "first worldwide family litigation" flag for family ID 81863515, consistent with the same confrontation.

8. Defensive aggregator — NOT PRESENT.
Title has not moved to RPX, AST, LOT Network, Unified Patents, or OIN. The patent is un-neutralized and actively asserted.

---

Verdict

Operating-company assertion.

The chain consists of exactly one recorded link — inventor Xing Wu assigning to Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. under an assignment of interest recorded 2022-04-01 — and that same operating manufacturer remains the owner and is itself the plaintiff pressing the patent. In E.D. Tex. 2:26-cv-00228 (filed 2026-03-19) Wuhan China Star asserts US 12,133,429 (identified as the first of three asserted patents in the complaint) against Samsung Display, a direct competitor that ships accused OLED panels and that separately sued Wuhan CSOT/TCL CSOT in N.D. Tex. 3:25-cv-01430; this is competitor-versus-competitor assertion, not a non-practicing-entity campaign. No shell transfer, no known NPE, no cascading LLC hops, no pre-litigation transfer — every NPE signal on the checklist is absent, and the only unfilled evidentiary cell (the reel/frame and correspondent of record for the single 2022 assignment) cannot change that outcome.

Verification links:

• USPTO Assignment Center — search patent no. 12133429: https://assignmentcenter.uspto.gov/ (legacy front-end: https://assignment.uspto.gov/patent/index.html)
• Google Patents record and legal events: https://patents.google.com/patent/US12133429/en
• E.D. Tex. 2:26-cv-00228 docket entry: https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/2%3A26-cv-00228

Open items to close out the assignment record: (a) reel/frame and page for the 2022-04-01 recording; (b) correspondent of record on that cover sheet; (c) confirm no license or security interest recordation exists against the '429 patent that Google Patents does not surface (assignment records and license recordations both live in the same search index — a keyword search on "12133429" across all conveyance types will catch a lien).

I'll verify the patent record and each cited reference via targeted searches.

Let me verify the content of the examiner-cited references and other key citations.

Let me verify the remaining cited references.

Prior Art Analysis — U.S. Patent No. 12,133,429 B2

"Display panel and display device" · Appl. No. 17/764,557 · Inventor: Xing Wu · Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

---

0. Scope, sources, and verification limits (read first)

What I searched. I attempted targeted lookups for the patent number and for each cited reference. I did not have direct USPTO Patent Center / Patent Examination Data System or PACER access in this session; USPTO Patent Public Search was not reachable as a live endpoint. Accordingly:

• The authoritative record for the citation list is the patent's own front page as captured in the full patent text supplied to me (source: https://patents.google.com/patent/US12133429/en, fetched 2026-09-18). Cross-checked against https://patents.justia.com/patent/12133429.
• For the content of the references, I was able to retrieve and review the full text of two of the eight: US 2022/0157919 A1 and US 2023/0122411 A1. I retrieved only title/assignee/date metadata for the remaining six. I therefore do not state what those six disclose beyond their titles, and I do not assign them §102 target claims on the basis of content I did not read.
• Date contradiction flagged: the task prompt states "Current Date: April 26, 2026," whereas the earlier-generated sections in this analysis were produced under "Today's date: 2026-09-18" and reference a CAFC order posted 2026-04-08. I do not reconcile these; the analysis below is date-agnostic and depends only on the patent's own priority date (2022-03-11).

A structural point that governs everything below. The '429 patent has 20 claims, two independent — claim 1 (display panel) and claim 11 (display device comprising the panel of claim 1, characterised as OLED). Claims 2–10 depend from claim 1; claims 12–20 are the claim 1–10 subject matter restated in device form. Consequence: a reference can only anticipate a dependent claim if it discloses every limitation of claim 1 and the added limitation. This drastically narrows the §102 surface, and it is why the table in §5 has more "none" entries than the prompt's framing might suggest.

---

1. The single limitation that controls the §102 analysis

Claim 1's final wherein-clause is the point of novelty:

"wherein the converging wire between two adjacent ones of the plurality of through holes is disposed according to a shortest distance between the two adjacent through holes."

Every other element of claim 1 (substrate; shielding layer with shielding blocks + a converging wire; pixel driving circuit layer whose circuits overlap the blocks; power supply lines coupled to the converging wire through through holes) is conventional bottom-shielding-metal architecture in OLED backplanes as of the 2022 priority date. The only element with genuine §102 bite is the shortest-path / non-meandering geometry of the converging wire segment between adjacent contact vias, which the specification ties to a functional result (spec: "the expected current path ... is within a boundary of the converging wire and is conducted along the shortest distance ... an accumulation of charges at a boundary of the shielding layer can be reduce[d]").

Anticipation therefore turns on whether any single reference discloses a bottom shielding layer that is parallel-connected to a power/signal line through a plurality of vias and whose inter-via segment is routed along the direct line between those vias. I found no reference that does both on its face.

---

2. Complete list of references of record

The patent's front page lists 8 patent citations plus 1 non-patent citation. Two of the eight carry the Google Patents "cited by examiner" marker (*): US 2022/0157919 A1 and US 2023/0122411 A1. The other six are unmarked and, given that the sole NPL citation is the 17-page ISR/Written Opinion, are most plausibly the documents the ISA identified in the PCT search for PCT/CN2022/082256 rather than art the U.S. examiner independently raised. I flag this as inference, not fact — the citation-by-citation provenance field was not directly retrievable.

§102/§103 availability as of the 2022-03-11 effective filing date: all eight qualify as prior art, on the following theories —

The §102(a)(2) point matters for the two examiner-cited references: their publication dates post-date the '429 priority date, so a superficial date check would wrongly discard them. They survive because their effective filing dates are 2018-10-15 and 2021-02-05 respectively.

---

3. Reference-by-reference analysis

3.1 US 2022/0157919 A1 — the closest reference on the record ★

Description (element mapping to claim 1):

• Display area + area outside it — a display area and a gate-on-array (GOA) area outside the display area → maps to claim 1's display region / non-display region.
• Base substrate — present.
• Shielding layer with blocks — a light shielding layer on the base substrate comprising a plurality of light shielding blocks in the display area, each on the side of a TFT active layer closer to the base substrate, "for shielding light from irradiating on the active layer" → maps to claim 1's shielding blocks overlapping the pixel driving circuits.
• Converging wire — the same light shielding layer also has a first part in the GOA area, a second part in the GOA area ("spaced apart from the first part"), and a third part in the display area, all "in a same layer and compris[ing] a same material" as the shielding blocks.
• Vias and parallel connection — the GOA signal line is connected electrically in parallel with the first part through a plurality of first vias extending through the insulating layer; a first signal line on a planarization layer is connected in parallel with the second part through a plurality of second vias extending through both the insulating layer and the planarization layer; a second signal line in the display area is connected in parallel with the third part through a plurality of third vias in the display area. The GOA signal line is selected from a clock signal line, a start signal line, a high voltage power line, and a low voltage power line; the first signal line's projection covers the clock/start/high-voltage/low-voltage lines.
• Fabrication claim — a method claim reciting forming the light shielding layer, forming an insulating layer, forming a plurality of first vias through the insulating layer in the GOA area, and forming the GOA signal line.

§102 assessment — which claims does it potentially anticipate?

Claim 1: potentially, but with a material gap — I would not plead it as a §102 reference. The element-by-element mapping is unusually close: the reference expressly teaches a bottom light-shielding metal carrying both display-area shielding blocks and non-display-area conductive portions that are resistively paralleled to power/signal lines through a plurality of through holes — i.e., the exact architectural reason a "converging wire" exists in the '429 patent. Two gaps remain, and each is dispositive:

1. "Electrically connected to the plurality of shielding blocks." In the '429 claim 1, the converging wire is electrically connected to the shielding blocks. In BOE '919, the GOA-area first/second parts are described as spaced apart from each other and merely co-planar/co-material with the display-area shielding blocks; the reference does not state that the GOA-area parts are electrically tied to the shielding blocks. On the face of the document, they read as electrically independent parallel-connected strap electrodes.
2. "Disposed according to a shortest distance." The reference is silent on inter-via routing geometry. It discloses the existence of plural vias and parallel connection but not that the inter-via metal follows the shortest path. Under §102, "arranged according to a shortest distance" is not inherent in a generic parallel-connected strap — a designer can equally route a strap with offsets, branches, or a meander, which is precisely what the '429 patent says the prior art did ("serrated edges").

Claim 2 ("linear in arrangement") and Claim 3 ("converging wire linear and the through holes overlappingly disposed ... linear in arrangement"): dependent on claim 1, so no independent §102 exposure unless gap 1 is cured. If a translator or expert declaration established that BOE's GOA strap runs in a straight line with in-line vias, claims 2 and 3 would be the realistic §102 targets, not claim 1.

Claim 9–10 (layer stack and dual-diameter vias): the reference discloses an insulating layer, a planarization layer, and vias penetrating them in different combinations (first vias through the insulating layer; second/third vias through insulating + planarization layers). It does not describe the claim 10 configuration of a first through hole (through the first insulating, second insulating and fourth/interlayer insulating layers) communicating with a second through hole (through the third insulating layer) with the second larger in diameter than the first. No §102 target.

Bottom line: US 2022/0157919 A1 is the primary obviousness reference and the best single shot at claim 1, but on the record as it stands it does not anticipate. The * marker tells you the U.S. examiner considered it and still allowed the case — which is consistent with gaps 1 and 2 being the reason for allowance.

---

3.2 US 2023/0122411 A1 — second examiner-cited reference ★

Description: An OLED array substrate in which the light-shielding layer is multiplexed as the fourth electrode plate of the storage capacitor, and the stack comprises: base substrate → light-shielding layer → buffer layer (with vias) → active layer → gate layer (scan line + driving-TFT gate; second electrode plate) → first interlayer dielectric → first conductive layer (first electrode plate) → second interlayer dielectric → second conductive layer (third electrode plate; sensing connection part) → third interlayer dielectric + first planarizing layer → third conductive layer (data line, power supply line, sensing line) → insulating layer + second planarizing layer → auxiliary cathode layer → anode → cathode. The storage capacitor is formed by three parallel sub-capacitors among these plates. Notably, the reference teaches that "the via holes in the buffer layer and the first interlayer dielectric layer are formed by one patterning process using a halftone mask" and, separately, that the via holes in the third interlayer dielectric layer and the first planarizing layer are formed by one patterning process using a halftone mask.

§102 assessment:

Claim 1: no. The reference describes a light-shielding layer and a power supply line, but it does not describe a converging wire that runs through the non-display region to collect the shielding blocks, nor power supply lines connected to such a wire through a plurality of through holes, nor any inter-via shortest-path geometry. Its light-shielding layer is a capacitor electrode, not a converging collector.

Claims 9 and 10: the strongest §102 exposure of any reference on the record — for claim 10 in particular.

• Claim 9 recites a stack of semiconductor layer / first insulating layer / first gate metal layer / second insulating layer / second gate metal layer / third insulating layer, with a first conductive layer on the third insulating layer and through holes penetrating the first, second and third insulating layers. US 2023/0122411 A1 discloses this stack in substance: active layer, gate layer, first and second interlayer dielectrics carrying two capacitor-electrode conductive layers, a third interlayer dielectric + first planarizing layer, and a third conductive layer carrying the power supply line.
• Claim 10 recites first through holes penetrating the first insulating layer, the second insulating layer and the fourth (interlayer) insulating layer, second through holes penetrating the third insulating layer, the first and second holes communicating, and the second through hole being wider than the first. BOE's express teaching of halftone-mask single-patterning formation of vias spanning multiple dielectric layers is the standard technique for producing exactly the tapered/stepped, differing-diameter stacked via profile claim 10 recites.

However — because claims 9 and 10 both depend from claim 1, and the reference does not disclose claim 1's converging wire, the reference cannot anticipate claims 9–10; it can only invalidate them in combination with a claim 1-satisfying primary reference (e.g., US 2022/0157919 A1). This is the market-standard §103 two-reference combination against the '429 patent, and any invalidity contention would very likely be built on exactly this pair.

---

3.3 CN 105321957 A

Description: Not retrievable in this session. Beyond the title, assignee and dates, I cannot state what this reference discloses without reading it, and I decline to construct a description from the title. What can be said from the record: it is a thin-film-transistor substrate disclosure from LG Display — i.e., a backplane structure reference, likely directed to TFT layer stacking and/or via formation in an active-matrix substrate.

§102 assessment: No target claims identified. On the title and assignee alone, its plausible relevance is to the layer-stack and via-formation dependent claims (9, 10) as background, not to independent claim 1 — claim 1 requires a non-display-region converging wire and a plurality of through holes to power supply lines, which a TFT-substrate reference predating flexible-OLED bottom-shielding architecture by six years is unlikely to disclose. Recommendation: obtain the CN 105321957 A specification and a certified English translation before relying on or discounting it; its 2016 publication date makes it the earliest art of record and therefore the best "general state of the art" citation under §103.

---

3.4 CN 112310044 A

Description: Not retrievable in this session. Title and assignee indicate a display substrate (backplane) disclosure with a fabrication-method claim set, from BOE's Hefei display-substrate entity.

§102 assessment: No target claims identified. The title is generic to the entire field of the '429 patent; without the specification I cannot map it to any claim. Given the assignee (a BOE display-substrate affiliate) and the publication date (fourteen months before the '429 priority date), this is a plausible §103 companion reference on layer stacking, planarization, and via formation (claims 9–10), and is unlikely to reach the claim 1 shortest-path limitation.

---

3.5 CN 112670304 A

Description: Not retrievable in this session. Title and assignee indicate an array substrate / display panel structure reference from an OLED-panel maker (Govisionox), filed roughly fourteen months before the '429 critical date.

§102 assessment: No target claims identified, on the same basis as §3.4 — generic title, specification not reviewed. Its likely utility, if any, is as a §103 secondary reference on array-substrate layout or shielding/electrode geometry, possibly to claims 4–6 (the wider first connection sections / narrower second connection sections geometry) if it happens to disclose variable-width conductive sections. This is a hypothesis to be tested, not a finding.

---

3.6 US 2021/0134846 A1

Description: Not retrievable in this session. I confirmed the citation exactly as recorded on the patent front page (filing 2019-11-01, publication 2021-05-06, assignee Innolux Corporation). Note that Innolux is a prolific filer of "Display device" applications, and I was unable to isolate the specific document US 2021/0134846 A1 in my searches; the results returned adjacent Innolux applications with different numbers. I will not describe this reference's disclosure.

§102 assessment: No target claims identified. Innolux's display-device portfolio in this period is heavily LCD/light-shielding-pattern oriented (compare, e.g., the same assignee's US 9,910,311 B2, "Display device with conductive wire and light-shielding pattern having different curvatures," which relates curved conductive wires projected onto a light-shielding pattern) — but US 2021/0134846 A1 itself may or may not be in that line, and I make no assertion. If it does concern the interaction between a conductive wire's curvature and a light-shielding pattern's boundary, it would be directly on point against claim 1's "shortest distance" premise (it would show that the opposite design choice — a deliberately curved wire relative to a light-shield edge — was known), and would be a high-value §103 reference. This is the highest-priority reference to retrieve.

---

3.7 CN 113826210 A

Description: Not retrievable in this session. A BOE display-substrate disclosure with a preparation-method claim set. Note the filing date 2020-04-21 is close to that of US 2022/0157919 A1's PCT (2019-03-21) and to the same corporate family of thin-film-backplane work; the two may share subject matter.

§102 assessment: No target claims identified. Same reasoning as §3.4. Plausible §103 relevance to the layer stack / via architecture of claims 9–10.

---

3.8 CN 113871420 A

Description: Not retrievable in this session. A BOE display substrate + display device structure reference, published approximately two and a half months before the '429 critical date — the latest-published of the six Chinese references of record.

§102 assessment: No target claims identified on the record I reviewed. Because it published so close to the critical date and shares a subject-matter field with the two examiner-cited BOE references, it is a candidate §103 secondary reference for claims 4–10. Retrieve and translate.

---

3.9 Non-patent citation — International Search Report / Written Opinion

Description: This is not prior art and cannot be used under §102 or §103 to invalidate any claim. It is, however, the single most useful prosecution document on the record, because it contains the ISA's claim-by-claim relevance coding (the X/Y/A category letters) and the passages the ISA relied on for each of the six Chinese/Innolux references. It will tell you exactly which claims the ISA thought each reference reached, which is effectively a free roadmap for the invalidity analysis.

§102 assessment: Not applicable — §102 and §103 require "prior art" consisting of patents, printed publications, public use/sale, or (for §102(a)(2)) U.S. patents/applications. An ISR is none of these as to the '429 claims. Action item: pull the ISR/WO and its translation — this should be the first document obtained.

---

4. Secondary set — art cited in the family (not of record in the U.S. case)

The patent page lists 8 documents cited in other members of family ID 81863515 (i.e., appearing on the search reports of the CN 114613825 / CN 119110631 / WO 2023168754 counterparts). These are not citations of record against US 12,133,429 and should not be presented as such — but two are of unusual interest:

Two observations. (1) CN 112736122 A (published 2021-04-30) and CN 112259582 B are the patentee's own earlier work on display panels — the closest thing to an admission of what the patentee itself considered its prior architecture, and therefore the most probative art for establishing the state of the art in bottom-shielding-metal OLED backplanes immediately before the '429 filing. (2) CN 114122055 A has a publication date of 2022-03-01, which is after the '429 critical date of 2022-03-11? No — 2022-03-01 is ten days before 2022-03-11, so it is available only if its priority/filing date (2020-08-26) is relied on; as a CN publication it is a printed publication only as of its publication date, which does pre-date the critical date. It is usable. I note this because the ten-day margin is easy to misread.

---

5. Consolidated §102 exposure table

---

6. Bottom line

1. No reference of record, on the record as it stands, anticipates independent claim 1 or claim 11. The shortest-distance inter-via limitation is the reason. The two examiner-cited references were considered during prosecution and the case still issued, which is consistent with that conclusion.

2. The only serious anticipation candidate is US 2022/0157919 A1, and it fails on two specific points I can identify and articulate — (i) it does not disclose that the non-display-area light-shielding portion is electrically connected to the display-area shielding blocks, and (ii) it is silent on the routing geometry between adjacent vias. Whether a challenger can close those gaps turns on the figures of that reference (which I reviewed in text form, not as drawings) and on whether the linear arrangement of its GOA strap and its vias is visible there.

3. The invalidity case that would actually be run is a §103 combination: US 2022/0157919 A1 as primary (bottom light-shield layer paralleled to power/signal lines through plural vias) + US 2023/0122411 A1 as secondary (three-conductive-layer stack, planarization, halftone-mask multi-layer/differing-diameter via formation) — targeting claim 1 and its dependents, and separately claims 9–10.

4. Nothing in the record addresses the ESD-rationale limitation in a way that is clearly adverse, which is unsurprising: the patent's stated problem ("serrated edges" of bottom shielding metals causing ESD explosions at serration tips) is a defect of the prior geometry, and the claimed cure (straight-line shortest-path routing) is, by design, the absence of a feature rather than the presence of one — a drafting choice that makes anticipation hard and obviousness arguments correspondingly harder.

7. What I could not verify (stated plainly)

• I did not retrieve the full text of CN 105321957 A, CN 112310044 A, CN 112670304 A, US 2021/0134846 A1, CN 113826210 A, or CN 113871420 A. For those six I have supplied bibliographic data only and have not asserted what they disclose or what they anticipate. Any §102 assignment for them would be fabrication.
• I did not read the ISR/Written Opinion for PCT/CN2022/082256.
• The citation provenance (which references the examiner cited versus which the ISA cited) is my inference from the Google Patents "cited by examiner" markers on the front page as transcribed; it is not confirmed against USPTO file-wrapper records.
• Chinese-language references require certified English translations before they can carry weight in a §102/§103 analysis. Machine translations are useful for triage only.
• The five earliest reference contents and the drawings of all eight references remain unexamined. The drawings matter disproportionately here, because the dispositive question for every claim-1-based §102 theory is a geometric one.

Next steps, in order of value: (1) obtain the ISR/WO and translation for PCT/CN2022/082256; (2) obtain and translate US 2021/0134846 A1; (3) obtain the six Chinese references with translations; (4) pull the USPTO file wrapper for Appl. 17/764,557 to see the examiner's actual reasons for allowance and the applicant's arguments on the "shortest distance" limitation — the argument that carried the case is the argument a challenger must defeat.

I'll research the cited prior-art references to ground the §103 analysis.

Let me characterize the remaining cited references.

Two more targeted searches to reduce uncertainty on the remaining references.

Obviousness Analysis — U.S. Patent No. 12,133,429 B2

Display panel and display device — 35 U.S.C. § 103

Analyst note on dates: the task header states the current date is April 26, 2026; my system date is 2026-09-18. Nothing in this analysis turns on that difference, but I flag it per the operating rules. All prior-art status determinations below are made against the '429 patent's effective filing date of March 11, 2022 (Chinese priority Appl. No. 202210237733.1; the U.S. national phase was filed March 22, 2022).

Scope note: I analyzed only the eight references cited of record on the face of US 12,133,429 B2, plus the one non-patent citation (the ISR/Written Opinion of 2022-11-30). I retrieved and read substantial text for US 2022/0157919 A1 and US 2023/0122411 A1 and the abstract/summary of CN 113871420 A/B. For CN 113826210 A, CN 112310044 A, CN 112670304 A, CN 105321957 A, and US 2021/0134846 A1 I was only able to confirm bibliographic data and, for some, family-level abstract content; where I map those references to claim elements I have flagged it as provisional / unverified. This matters: any invalidity contention built on those five would need full-text and figure verification before it is filed.

---

1. Legal framework and the level of ordinary skill

Framework. Under Graham v. John Deere, obviousness requires (1) the scope and content of the prior art, (2) the differences between the prior art and the claims, (3) the level of ordinary skill, and (4) objective evidence of non-obviousness. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a combination is obvious where the improvement is a "predictable variation," a "simple substitution of one known element for another," a use of "known technique[s] ... to improve similar devices in the same way," or the pursuit of a "known design need or market pressure" with a finite number of identified, predictable solutions. Critically, the motivation to combine need not be found in the references themselves — it may come from the knowledge, creativity, and common sense of the POSITA, from the nature of the problem, or from the prior art's teaching of the same problem.

POSITA. A person having ordinary skill in the art here would hold a Bachelor's degree in electrical engineering, materials science, physics, or a related discipline, with at least 2–3 years of experience in the design of active-matrix display backplane layouts (TFT array design, OLED pixel-driver integration, mask/layer budgeting, and ESD/layout-rule engineering for flexible substrates), or equivalent experience. This is a layout-engineering art: the ordinary artisan works daily with layer stacks, via placement, bus-line routing, and ESD design rules.

---

2. Claim 1 — scope, and the one term that decides this case

Claim 1 requires:

1. a display region and a non-display region on at least one side of it;
2. a substrate;
3. a shielding layer on the substrate comprising (a) a plurality of shielding blocks and (b) a converging wire electrically connected to the shielding blocks, the converging wire lying on at least one side of the blocks;
4. a pixel driving circuit layer on the shielding layer, whose pixel driving circuits lie in the display region and each at least partially overlap a corresponding shielding block;
5. power supply lines on the side of the shielding layer away from the substrate, electrically connected to the converging wire through a plurality of through holes;
6. the characterizing limitation: "the converging wire between two adjacent ones of the plurality of through holes is disposed according to a shortest distance between the two adjacent through holes."

Elements 1–5 are, as shown below, the everyday currency of bottom-shielding-metal OLED backplane design circa 2018–2021. The whole case turns on element 6.

Construction of element 6. The specification is the best guide, and it defines the phrase twice, consistently:

• "Since the shortest distance between the adjacent through holes 90, i.e., a virtual line segment 107, can represent an expected current path between the adjacent through holes 90, the expected current path that is approximately linear can be located within a boundary of the converging wire 20." (Description, FIG. 1–3 embodiment)
• Claim 2 then says the same thing in geometric terms: "the converging wire between the two adjacent through holes is linear in arrangement." And claim 3: "the converging wire is linear in arrangement and the plurality of through holes overlappingly disposed on the converging wire are linear in arrangement."

Two consequences follow, and they cut in opposite directions:

• Read broadly (and it is what the specification says): the limitation is satisfied by a straight conductor segment joining two adjacent via landings — i.e., by any straight bus bar with two or more vias. That is an extremely weak limitation, because a straight bus with vias in a row inherently places the inter-via segment along the straight line between the vias (which is by definition the shortest distance). Under this reading, the limitation adds essentially nothing over the prior-art straight shield bus lines discussed below.
• Read narrowly (as the FIG. 2–3 geometry — wide arc/oval "first connection sections" with narrow, linear "second connection sections" joined between the midpoints of the arc sections — might suggest), claim 1 is a narrow layout claim, and the infringement question in CSOT v. Samsung Display will be whether the accused panel's converging wire meets it. A narrow reading helps validity but hurts the plaintiff; the patentee cannot have it both ways.

I note the phrase "disposed according to a shortest distance" is also vulnerable to a § 112(b) challenge as functional/result-oriented language ("according to" describes the designer's intent or a result, not a definite structure). The § 103 analysis below proceeds on the broad reading and then stress-tests the narrow one.

---

3. Prior-art status of the references of record (against a 2022-03-11 effective filing date)

Two points of care:

• The two BOE U.S. publications post-date the '429 priority date but were effectively filed years earlier; they therefore qualify as § 102(a)(2) art (as publications of applications effectively filed before the claimed invention's effective filing date, naming different inventors). They are not available as § 102(a)(1) printed publications. A rejection must be pleaded under the correct subsection.
• There is no common ownership (BOE, Innolux, LG Display, Kunshan Go-Visionox vs. Wuhan China Star/TCL CSOT), so the § 102(b)(2)(C) exception does not apply.

---

4. The prior art, element by element

4.1 US 2022/0157919 A1 (BOE) — the primary reference

This is the closest reference, and it is uncannily on point. Its specification discloses, verbatim:

• "a light shielding layer on the base substrate; an insulating layer on a side of the light shielding layer away from the base substrate; wherein the GOA signal line [is] on a side of the insulating layer away from the light shielding layer, and is connected electrically in parallel with a first part of the light shielding layer, the first part being in the GOA area; wherein the display substrate comprises a plurality of first vias extending through the insulating layer in the GOA area; and the GOA signal line is electrically connected to the first part of the light shielding layer through the plurality of first vias respectively, thereby connecting the GOA signal line and the first part of the light shielding layer electrically in parallel." (¶ [0012], claim 12)
• "the light shielding layer further comprises a plurality of light shielding blocks on the base substrate and in the display area, a respective one of the plurality of light shielding blocks on a side of an active layer of the plurality of thin film transistors closer to the base substrate for shielding light from irradiating on the active layer; and the first part of the light shielding layer and the plurality of light shielding blocks are in a same layer and comprise a same material." (¶ [0013])
• "an orthographic projection of the respective one of the plurality of light shielding blocks on the base substrate covers an orthographic projection of the active layer of the plurality of thin film transistors on the base substrate." (¶ [0019])
• "the GOA signal line is selected from a group consisting of a clock signal line, a start signal line, a high voltage power line, and a low voltage power line." (¶ [0021]); "the first signal line is a power signal line" (¶ [0022]); and the first signal line is "in a same layer as the relay electrode" — i.e., a source/drain-type metal on a planarization layer above the vias.
• The reference even recites the via-into-multiple-insulating-layers variant: "a plurality of second vias extending through the insulating layer and the planarization layer in the GOA area ... the first signal line is electrically connected to the second part of the light shielding layer through the plurality of second vias respectively." (¶ [0014])
• And it recites "at least one opening in the second part of the light shielding layer" (¶ [0015]) — i.e., a patterned, non-serrated shield outline.

Mapping to claim 1: substrate ✔; shielding layer with light-shielding blocks in the display area underlying TFT active layers ✔; pixel driving circuits in the display region at least partially overlapping the blocks ✔ (indeed the reference requires complete coverage of the active layer); a signal/power line located on the far side of the shielding layer, in a layer above a planarization layer, connected to a part of the shielding layer through a plurality of vias ✔. The non-display region/GOA area and the flex-bending context are inherent in the reference's flexible-OLED premise (¶ [0003]).

Where it falls short of claim 1: (i) it does not in terms call the bus a "converging wire electrically connected to the shielding blocks" — its first/second/third parts of the shielding layer are described as spaced apart from one another (the parts are separately placed in parallel with different signal lines, and each is connected to its own line). It therefore does not squarely disclose the "collector/bus" architecture in which one wire gathers the display-area shield blocks. (ii) It does not expressly recite the geometry of the segment between adjacent vias.

Both gaps are filled by the other art of record.

URL: https://patents.google.com/patent/US20220157919A1/en

4.2 CN 113871420 A/B (BOE) — the second primary reference

The Eureka/Patsnap machine summary of the grant (CN 113871420 B) shows precisely the missing "shield blocks tied together and tied to a power line through vias" architecture, in the fourth metal/third conductive layer:

• "A shielding connection part is provided on the display substrate to connect the shielding layer and the power line ... to ensure that the shielding layer is not in a floating state, prevent signal interference, and reduce the voltage drop of the power line."
• "the shielding layer is connected to at least one of the plurality of first power lines through the first shielding connection portion to receive the first power supply voltage; the plurality of first power lines are located on the side of the first shielding connection portion away from the substrate, the shielding layer is located on the side of the first shielding connection portion near the substrate ..."
• "the shielding layer is connected to the first shielding connection portion through a first via, and the first shielding connection portion is connected to the at least one first power line through a second via."
• "the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer ... the shielding layer is connected to the first shielding connection portion through a first via penetrating the first insulating layer, and the first shielding connection portion is connected to the at least one first power line through a second via penetrating the second and third insulating layers ..."
• "the orthographic projections of the first via and the second via on the substrate do not overlap; the first power line includes a protrusion ..."
• The shield itself has "a cutout area and a shielding area" with sub-pixel opening areas through the shield.

This reference therefore supplies: (a) the converging architecture (a shielding layer whose areas/patterns are tied together and then tied to a power line); (b) the plural-via connection from a power line above down to the shield; and (c) even the nested/differential via structure (first via through one insulating stack, second via through a different stack) that claim 10 recites. The "protrusion"/non-overlapping via projections tell the artisan that the via landings are distinct features whose placement drives local shield-pad geometry — i.e., exactly the design problem the '429 addresses.

URL: https://eureka.patsnap.com/patent/CN113871420B (abstract and claim summary)

4.3 US 2023/0122411 A1 (Hefei BOE Joint Technology) — primary for claims 9–10

This reference teaches the same multi-metal-layer backplane with a light-shielding layer multiplexed as a capacitor electrode plate and a chain of connecting parts linking that layer upward:

• "the fifth connecting part 65 ... is also connected to the light-shielding layer 100 through the via holes provided in the first interlayer dielectric layer 600 and the buffer layer 200";
• "the power supply line 30 is connected to the seventh connecting part 67 through via holes disposed in the third interlayer dielectric layer 1000 and the first planarizing layer 1100";
• and, decisively for claim 10, the reference expressly teaches fabricating stacked vias of different widths/depths with a single half-tone mask: "via holes may be formed through one etching process using a half-tone mask when forming the via holes in the third interlayer dielectric layer 1000 and the first planarizing layer 1100 ... via holes with different depths ..." and "the via holes on the two film layers may also be formed by successive etching in two steps."

URL: https://patents.google.com/patent/US20230122411A1/en

4.4 The remaining five — role and status

These are not the load-bearing references for claim 1; their function is to corroborate that each subsidiary concept was known, and to supply the ESD-motivation teaching.

• CN 112310044 A (Hefei BOE Display Tech., pub. 2021-02-02) — Display substrate, preparation method thereof and display device. Provisional mapping. It was cited twice (ISR and U.S. examiner), so the examiner treated it as material. On the record available to me I cannot attribute specific structures to it.
• CN 113826210 A (BOE, pub. 2021-12-21) — Display substrate, preparation method thereof and display device. Provisional mapping. Same caveat.
• CN 112670304 A (Kunshan Go-Visionox, pub. 2021-04-16) — Array substrate and display panel. Go-Visionox's contemporaneous family (e.g., US 2022/0157860 A1 / US 12,034,012 B2) is directed to a shielding layer connected to a fixed-potential terminal and covering an orthogonally-projected wire-wrapping segment; and CN 114361136 B, by overlapping inventors/assignee, is directed to joining the free ends of like-signal traces around a hole region expressly "to reduce the number of free ends ... so as to realize electrostatic protection" — i.e., ESD control by trace-end geometry in an array substrate. If CN 112670304 A's full text contains analogous ESD-end-management or shielding-to-power-line teachings, it becomes a strong secondary reference on the motivation prong. Verify before relying on it.
• CN 105321957 A (LG Display, pub. 2016-02-10) — Film transistor substrate, display panel comprising the same and manufacture method. Unverified. Title/assignee only. Likely general array-substrate/via/layer-stack art; useful for the "these are all routine backplane expedients" narrative and possibly for the flexible/bending-region aspects of claims 7–8.
• US 2021/0134846 A1 (Innolux, pub. 2021-05-06) — Display device. Unverified as to content. Innolux's co-pending 2021–2022 work is heavily directed to auxiliary electrode lines connected to main lines through vias to reduce impedance and increase cross-sectional area of routed lines (see Innolux's US 2023/0238390 and US 2023/0176632 discussion), and to shielding layers connected to a ground trace through conductive through holes (Innolux's US 2013/0321304). If the '846 publication follows its family's pattern, it is probative on the "connect the shield/signal line through plural vias to lower impedance" motivation.

---

5. Grounds of rejection

Ground 1 — BOE '919 in view of CN 113871420 A (claims 1–10)

Claim 1. BOE '919 discloses every structural element except the express "converging wire electrically connected to the shielding blocks" and the inter-via geometry; CN 113871420 A supplies both, disclosing a shielding layer whose areas are connected together and tied to a first power line through a plurality of vias (indeed through a series of vias in different insulating stacks, with distinct via landings whose projections do not overlap because a protrusion of the power line is landing there).

Claim 2 ("linear in arrangement"). This is the natural, indeed the inevitable, geometry once the artisan is told that adjacent vias lie along a bus: the shortest path between two pad centers is the straight line. CN 113871420 A's "protrusion" landing geometry and BOE '919's "a second signal line ... extends in a first direction" reinforce that bus lines are drawn straight in this art.

Claim 3 (whole wire linear, holes collinear). Straight bus bars with collinear via farms are the paradigm of peripheral routing; BOE '919's "first signal line extends in a first direction" and its GOA-area vias are linear by construction. Also, note the '429's own claim 3 covers, in substance, a straight power/shield bus — a structure CN 113871420 A and CN 113826210 A depict.

Claims 4–6 (wide first connection sections with arced peripheries, narrow linear second connection sections, one section per column of blocks). Routine pad-and-neck routing: the artisans widen metal where a via lands (to respect via enclosure/overlap design rules and to spread current) and narrow it between landings (to save area and capacitance). BOE '919 requires a planarization-layer signal line landing on shield-area parts and expressly contemplates multiple vias per part. CN 113871420 A's "protrusion" at each via is a pad. The "one first connection section per column of pixel driving circuits" is nothing more than the standard column-wise subdivision of a shield into blocks (BOE '919, ¶ [0013]: "a plurality of light shielding blocks ... in the display area").

Claims 7–8 (bending sub-region; first and second converging wires on both sides). The '429 expressly concedes its panel is a flexible OLED panel bent at a bending region, and BOE '919's premise is a flexible OLED display. Routing a bus on both sides of the display region (double-sided feed) is the textbook way to halve the IR drop and the RC delay along a shield/power bus — a recognized design objective that CN 113871420 A states in terms ("reduce the voltage drop of the power line").

Claims 9–10 (layer stack; first via penetrating layers 42/44/46; second via penetrating layer 481, second hole wider than first). BOE '919 itself discloses the arrangement in which "the GOA signal line" is below the planarization layer and the "first signal line" is above it, with "a plurality of second vias extending through the insulating layer and the planarization layer" and "a plurality of first vias extending through the insulating layer" separately defined (¶¶ [0012], [0014]) — i.e., via stacks terminating at different levels, exactly as claim 10 requires. CN 113871420 A's "first via penetrating the first insulating layer" plus "second via penetrating the second and third insulating layers" is the same teaching. For the diameter differential, US 2023/0122411 A1 supplies the express expedient: form the upper (organic/planarization) via wider than the lower via — and do it in a single half-tone-mask etch ("via holes with different depths"). Forming the opening through a thick organic planarization layer wider than the opening through a thin inorganic stack is also simply the consequence of the isotropic/tapered etch characteristic of organic layers, discussed at length across the BOE literature in this very family (e.g., the slope-angle passages in BOE's US 2023/0252945).

Ground 2 — CN 113871420 A as primary, BOE '919 as secondary (claims 1–10)

Reversing the roles is equally available and probably more robust on the "converging wire" element, because CN 113871420 A is the reference that starts from a shielding layer that is explicitly connected (in parallel) to the power line through vias to prevent the shield from floating and to reduce power-line IR drop. BOE '919 then supplies: (a) the display-region light-shielding blocks underlying the TFT active layers; (b) the explicit identification of the line as a high-voltage power line / power signal line; and (c) the multi-level via stacks. Combination is a two-reference substitution of a known connection scheme onto a known shield geometry.

Ground 3 — any of the above further in view of CN 105321957 A (LG Display), US 2021/0134846 A1 (Innolux), CN 112310044 A, CN 112670304 A, or CN 113826210 A (claims 1–10, motivation and geometry)

If any of these discloses either (i) a converging/gathering routing geometry in a peripheral region, or (ii) an ESD-drive geometry (avoiding sharp metal tips, tapering, or tying off free trace ends), then the motivation to route the shield bus along the straight short path between adjacent vias — rather than along a sawtooth — becomes express rather than inferred. Kunshan Go-Visionox's "at least two wirings transmitting the same signal have their free ends connected to each other ... to reduce the number of free ends ... to achieve electrostatic protection" (CN 114361136 B) is a direct analog of the '429's stated rationale, and it appears in the same assignee's portfolio as cited reference CN 112670304 A. Verify then plead.

Ground 4 — claim 11 (the display-device claim)

Claim 11 adds only that the display panel is an OLED panel. Every reference of record is an OLED/AMOLED backplane reference; BOE '919's field statement recites OLED expressly. Claim 11 is obvious a fortiori.

---

6. Motivation to combine — articulated rationales (the KSR prong)

A petition or § 282(b) contention should plead the following rationales, each tied to record evidence:

1. Same field, same problem, same solution. All references address the interface between a flexible substrate and overlying inorganic layers in an OLED backplane, and the interference/floating problem of a bottom light-shielding or shield metal underlying the pixel driving circuit. KSR permits combination where references are from the same field of endeavor and address the same problem. BOE '919 and CN 113871420 A are both BOE OLED backplane applications, both expressly aimed at the shielding layer ↔ power/signal line connection through vias.

2. Explicit statement of the design objective. CN 113871420 A: "ensure that the shielding layer is not in a floating state, prevent signal interference, and reduce the voltage drop of the power line." BOE '919: "connecting the GOA signal line and the first part of the light shielding layer electrically in parallel." Parallel/multi-via connection is the known technique for lowering the effective sheet resistance of a thin shield and reducing IR drop — the two references independently employ it. A POSITA seeking lower shield resistance and a lower-VDD-drop power bus would apply it as a matter of routine design optimization. This is KSR's "known technique to improve similar devices in the same way."

3. Predictable result, finite solution space. Given a shield bus and a set of vias feeding it, there are only a finite number of ways to draw the metal between two adjacent vias: straight, or some detour. The straight line is the minimum-length path, hence minimum resistance (R = ρL/W for fixed width), minimum metal area (hence minimum parasitic capacitance to neighboring conductors and minimum intrusion into the bezel), minimum current-crowding, and — critically — minimum perimeter, which is the parameter that governs field concentration. This is the paradigm of a "predictable variation."

4. The proposed modification does not change the principle of operation of the primary reference. The shield still shields; the power line still supplies the shield; the vias still land where they landed. The change is confined to the in-plane outline of metal between two already-existing via landings. KSR endorses such combinations.

5. Design incentives / market pressure. Bezel narrowing and IR-drop reduction in flexible OLED modules are persistent consumer-driven pressures (BOE '919 motivates itself on exactly this: "it becomes more and more difficult to accommodate the more and more complicated integrated circuits in the margins of a display panel"). Reducing shield-bus metal area in the non-display region serves that pressure directly.

6. The patentee's own admission of the problem and its direction of solution. The '429's Background concedes the prior art used bottom shielding metals whose "serrated edges" caused "ESD explosions ... at tips of serrations." An admission that serrated edges cause the problem, taken with the observation that serrations are what you get when a bus line meanders between non-collinear vias, points directly to the solution of drawing the bus along the straight path between vias. KSR allows the artisan's common sense and the background of the invention to supply the motivation. Note also that the '429's stated benefit — reducing charge accumulation at the boundary, hence reducing ESD damage — is a result that follows predictably from removing perimeter/sharp-tip geometry, not a newly discovered mechanism. See In re Kao / In re Montgomery line of authority: a result that is the inherent or predictable consequence of a structural change cannot carry patentability.

7. A "why-not" gap. There is no teaching away. None of the record references teaches that a shield bus should be routed around, offset from, or zig-zagged relative to its vias; nor is there any asserted criticality in the '429 specification for any particular angle, offset, or radius (the specification's only "arc" disclosure concerns the pad, not the inter-via segment, and no numerical ranges are recited anywhere in apparatus claims 1–10).

---

7. Dependent-claim summary chart

---

8. Weaknesses of the obviousness case, and the counterarguments the patentee will press

I would be doing the client a disservice to present the above as an open-and-shut case. The following are the real vulnerabilities, ranked.

(a) The examiner saw these references and allowed the claim. All eight references are on the face of the patent (six from the ISR of 2022-11-30, two added by the U.S. examiner — US 2022/0157919 A1 and US 2023/0122411 A1, both asterisked in the Google Patents citation list). The Notice of Allowance was mailed 2024-06-24 and the issue fee followed. A defendant must therefore explain what the examiner missed: namely, (i) the proper combination of the two BOE U.S. publications (the examiner appears to have cited them individually, not in combination with CN 113871420 A), and (ii) the articulated rationale that routing a bus segment along the straight inter-via path is a predictable design choice — a rationale that is not a "reference" and therefore cannot appear in a search report. This is the single most persuasive way to frame the contention.

(b) The "converging wire" element may not be fully anticipated. None of the references retrieved discloses, in express terms, a single wire that collects/gathers the display-region shield blocks and then feeds them from the power line at spaced vias, with the inter-via segment following the straight path. CN 113871420 A's shield is described as having a cutout/hollow area with connection portions located in opening areas of sub-pixels — the "bus" there may be a distributed connection portion rather than a literal periphery-running converging wire. If the patentee can show that the references' shield-to-power connection is a local, per-pixel connection rather than a peripheral converging bus, claim 1 survives on that structural distinction, and the case then reduces to whether a peripheral collecting bus was known. This is the crux issue to brief, and it cannot be resolved without the figures of CN 113871420 A and CN 112310044 A.

(c) The narrow reading is dangerous for the patentee but protects the claim. If the claim is construed to require the FIG. 2–3 geometry (arc-periphery pads joined by narrow straight necks between midpoints), then the prior art's straight-bus-with-vias does not anticipate, and the motivation to move from a uniform-width straight bus to the specific pad-and-neck arrangement is weaker. Critically, however, the '429 specification ties the benefit to the straight line between adjacent holes, not to the pads — "the expected current path ... is conducted along the shortest distance between the adjacent through holes" — so the pads are decorative and the asserted advantage flows entirely from the straight segment. Under KSR, a claim whose advance consists of the straightness of a conductor between two contact points is on very thin ice.

(d) § 112(b) pressure. "Disposed according to a shortest distance between the two adjacent through holes" is a result/functional limitation whose metes and bounds depend on an unstated comparison. A defendant will argue indefiniteness in the alternative and, at minimum, will argue that under Williamson v. Citrix the limitation should be construed narrowly to the disclosed algorithm (draw the connecting segment as a straight line between the two hole centers) — which then makes the prior art's straight bus a literal read.

(e) The ESD advantage may be characterized as inherent, not inventive. Because the specification's entire stated advantage is reduced charge accumulation / reduced ESD at the shield boundary, and because the prior art shield outlines in the record include rounded openings and explicit boundary geometries (BOE '919's openings; CN 113871420 A's cutout area; the "included angle ... ranges from 20° to 30°" boundary tapering in BOE's US 2023/0252945), the patentee will have to identify a structural difference that produces the advantage, not merely assert the advantage. That is a two-edged sword: it also means a defendant may defeat the secondary-considerations story if the patentee cannot show that the advantage is attributable to a feature absent from the prior art.

(f) The five unverified references. Do not build a ground on CN 112310044 A, CN 112670304 A, CN 113826210 A, CN 105321957 A, or US 2021/0134846 A1 until full texts and figures are pulled. The ISR's citation of six documents as category "Y" (implied) does not by itself tell us which claim elements they map to.

---

9. Objective evidence (secondary considerations)

At the time of writing I have no evidence of record on any Graham factor beyond the litigation posture itself. Two observations for the file:

• Nexus risk. The '429's stated advantage (ESD robustness of the bottom shield) is a product-reliability benefit that is difficult to measure and even more difficult to link to the claimed geometry as against the many other differences between the accused panels and the prior art. Any assertion of commercial success of the accused Samsung panels would fail the nexus requirement for the same reason — the success is plainly attributable to Samsung's own design, not to the '429.
• The '429 has no independent, non-accused adoptees on the record. The only citing family member found was CN 118785771 B (BOE, priority 2024-09-11) — a later, unrelated BOE filing. That is not evidence of industry praise, licensing, or copying in the § 103 sense.
• Copying / deliberate design-around. The complaint in E.D. Tex. 2:26-cv-00228 pleads willfulness. Willfulness pleadings sometimes buttress a copying narrative, but copying of a patentee's product (rather than of the claimed design) does not establish non-obviousness, and absent evidence of access to the '429 specification (published only 2024-02-29 and granted 2024-10-29 — after the accused Pixel 8 panels), the copying theory is chronologically strained on this record.

---

10. Bottom line

• Claim 1 is, in my assessment, more likely than not invalid under § 103 on the strength of US 2022/0157919 A1 in view of CN 113871420 A (and/or with US 2023/0122411 A1 for the via-stack refinements), provided the petitioner frames the "shortest distance" limitation as the predictable, optimal-layout choice it is and does not simply rely on the examiner's citation to the two BOE publications. Confidence: moderate (~60–65%), driven mostly by the possibility that the "converging wire electrically connected to the shielding blocks" element is not squarely disclosed in the record art and by the risk that the panel adopts a narrow construction of "disposed according to a shortest distance."
• If claim 1 is construed narrowly to require the FIG. 2–3 pad-and-neck architecture, validity is considerably more defensible, and the practical fight shifts to infringement — which is precisely the opposite of what a plaintiff asserting this patent wants.
• Claims 2, 3, 9, 11, and 12–20 are the easiest to invalidate (claims 2/3/12/13 because they restate the straight-line geometry, 9/19 because the layer stack is conventional and expressly disclosed in BOE '919's first/second-via passages, and 11/12–20 because they add only "OLED").
• Claims 10 and 20 are the next easiest given US 2023/0122411 A1's express half-tone/multi-depth via teaching and CN 113871420 A's differential via stacks — though the specific "diameter of second hole > diameter of first hole" recitation will need either the half-tone-mask passage or a design-rules/process-conditions argument.
• Claims 7 and 8 (bending region; dual converging wires) are the hardest on the record as it stands, because the flexible-bend architecture and double-sided bus feed are more likely to be found in CN 105321957 A or the Kunshan Go-Visionox art than in the two BOE publications I could fully verify. Pull those two full texts before finalizing the ground.
• Recommended additional art to search (not of record, all potentially pre-2022-03-11): the EP 3 866 144 / US 11,695,017 family (BOE, "first gathering portion" — an expressly converging routing geometry for grouped wire segments, priority 2018-10-11); BOE's US 2023/0252945 (shield-layer edge/slope geometry in the peripheral region); and Samsung Display's own US 2022/0123098 A1 / US 11,882,738 (shielding layer on a planarization layer overlapping embedded driving circuit, effective filing 2022-01-03). The "gathering portion" concept in the EP 3 866 144 family is, on its face, the closest thing in the art to the '429's "converging wire" and should be evaluated first.

---

Flagged contradictions with the previously generated sections

1. The prior "Patent summary" states the '429 has no IPR or PTAB record. Nothing in this analysis disturbs that; the prior art discussed here is all examiner-cited or ISR-cited art, none of it a PTAB challenge.
2. The prior "Patent summary" flags a third-party attribution of "Xing Wu" to Hefei BOE. That is relevant here only as a caveat: US 2023/0122411 A1 is a Hefei BOE Joint Technology reference whose named inventors are not Xing Wu, so the two "Wu" identities remain distinct and the aggregator error does not create any common-ownership issue that would remove US 2023/0122411 A1 as prior art. If, contrary to the front page, the '429 were ever shown to share ownership with a cited BOE reference, § 102(b)(2)(C) would become a live issue — but nothing on this record supports that.
3. The prior sections describe the '429 as a counterstrike in the TCL CSOT–Samsung Display dispute. That posture is consistent with a § 103 analysis: the '429's asserted claim 1 is broad, layout-level subject matter of exactly the kind that the crowded BOE/LG/Innolux OLED backplane art of 2018–2021 tends to render obvious.