US 11841803

Patent Summary: US 11,841,803

A detailed analysis of United States Patent 11,841,803 reveals a system for enhancing graphics processing power by interconnecting multiple smaller graphics processing unit (GPU) "chiplets" to function as a single, powerful GPU.

Title: GPU chiplets using high bandwidth crosslinks

Assignee: The patent was originally assigned to Advanced Micro Devices, Inc. As of a reassignment on November 18, 2024, the current assignee is Onesta IP, LLC.

Inventors:

• Skyler J. Saleh
• Samuel Naffziger
• Milind S. Bhagavat
• Rahul Agarwal

Filing Date: June 28, 2019

Issue Date: December 12, 2023

Abstract: The patent describes a chiplet system where a central processing unit (CPU) is connected to a first GPU chiplet in an array of multiple GPU chiplets. This first chiplet is, in turn, connected to a second GPU chiplet through a "passive crosslink." This crosslink is a dedicated passive interposer die designed for communication between the chiplets, allowing the system to partition the functions of a larger system-on-a-chip (SoC) into smaller, more manageable chiplet groupings.

Overview of Independent Claims

The patent includes three independent claims which form the core of the invention. In plain language, they are:

Claim 1: The fundamental system. This claim outlines the basic architecture of the invention. It describes a system comprising a CPU linked to a "first" GPU chiplet. This first chiplet is then connected to a "second" GPU chiplet using a passive crosslink that is specifically dedicated to handling communications between the chiplets. This creates a multi-chiplet GPU array.

Claim 11: The method of operation. This claim details the process of how the system functions. It starts with the first GPU chiplet receiving a memory access request from the CPU. A controller on this first chiplet then determines which chiplet in the array (the "caching GPU chiplet") holds the requested data. The request is then routed through the dedicated passive crosslink to the last-level cache of the identified chiplet. Finally, the requested data is sent back to the CPU.

Claim 16: The non-transitory computer-readable medium. This claim covers the software aspect of the invention. It describes a storage medium (like a hard drive or RAM) containing executable instructions. When a processor runs these instructions, it performs the method outlined in Claim 11: receiving a memory request, determining the location of the data on one of the GPU chiplets, routing the request via the passive crosslink, and returning the data.

Litigation Search

As of April 26, 2026, a search of the dockets for the U.S. Court of Appeals for the Federal Circuit (CAFC) for the year 2026 did not reveal any cases involving US Patent 11,841,803.

As of April 26, 2026, US patent 11,841,803 is involved in active litigation initiated by Onesta IP, LLC. The patent, originally assigned to Advanced Micro Devices, Inc., was transferred to Onesta IP, LLC in November 2024. Onesta IP, a Delaware corporation formed in August 2024, has since asserted this patent and others from the acquired portfolio in multiple legal actions.

Details of the known litigation are as follows:

District Court Litigation

• Case: Onesta IP, LLC v. NVIDIA Corporation

  • Plaintiff: Onesta IP, LLC
  • Defendant: NVIDIA Corporation
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 1:25-cv-00586
  • Filing Date: April 17, 2025
  • Status: This case, along with a related case against Qualcomm and others, was stayed in June 2025 pending the final determination of a parallel investigation at the International Trade Commission.

• Case: Onesta IP, LLC v. Qualcomm Inc. et al.

  • Plaintiff: Onesta IP, LLC
  • Defendants: Qualcomm Incorporated, Nothing Technology Limited, OnePlus Technology (Shenzhen) Co., Ltd.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 1:25-cv-00587
  • Filing Date: April 17, 2025
  • Status: The case was stayed in June 2025 pending the outcome of the related ITC investigation.

International Trade Commission (ITC) Litigation

• Investigation: In the Matter of Certain Integrated Circuits, Electronic Devices Containing the Same, and Components Thereof
  • Complainant: Onesta IP, LLC
  • Respondents: NVIDIA Corporation, Qualcomm Incorporated, Nothing Technology Limited, OnePlus Technology (Shenzhen) Co., Ltd.
  • Jurisdiction: U.S. International Trade Commission
  • Investigation Number: 337-TA-1450 (also referenced as 337-TA-3823)
  • Filing Date: The complaint was filed on April 18, 2025, and the investigation was instituted on May 20, 2025.
  • Status: The investigation is ongoing. The target date for a final determination is set for November 29, 2026.

Patent Trial and Appeal Board (PTAB) Proceedings

• Case: IPR2026-00011
  • Petitioner: Unified Patents, LLC
  • Patent Owner: Onesta IP, LLC
  • Jurisdiction: U.S. Patent and Trademark Office, Patent Trial and Appeal Board
  • Filing Date: Not specified in search results.
  • Status: The PTAB case was filed, but the current status is "Not Instituted - Procedural". This indicates the review was not initiated on its merits due to procedural reasons.

Based on the single Patent Trial and Appeal Board (PTAB) proceeding filed against US patent 11,841,803, here is a complete analysis of what happened and its strategic implications.

Proceedings overview

One IPR has been filed against this patent, and the Board declined to institute the trial. This means all claims of US patent 11,841,803 have survived their only PTAB challenge to date, slightly strengthening the patent's defensive posture as it rebuffed an attempt by a major competitor to invalidate it.

IPR2026-00011 — NVIDIA Corporation v. Onesta IP, LLC

• Type: Inter Partes Review (IPR)
• Filed: 2025-10-15
• Status: Discretionary Denial — The PTAB declined to review the patent's validity, so a trial on the merits of the invalidity arguments never occurred.
• Judge panel: Because the proceeding was denied at institution, the full record including the assigned panel may not be readily public. However, decisions at this stage are typically made by a panel of three Administrative Patent Judges.
• Petition grounds: The petition reportedly challenged an unknown subset of claims under 35 U.S.C. § 103 (obviousness) based on prior art references. The specific claims and art are not detailed in the available high-level data.
• Institution decision: The PTAB denied institution on 2026-03-13. This was not a ruling that the patent claims were valid over the cited prior art. Instead, it was a "discretionary denial," likely exercised under 35 U.S.C. § 314(a). Such denials often occur when there is a co-pending district court or ITC litigation involving the same patent that is nearing a final resolution, making the parallel PTAB proceeding inefficient in the Board's view (under the [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Fintiv, Inc. framework).
• Final Written Decision: None issued, as the trial was not instituted.
• Settlement / termination: The proceeding was terminated by the Board's denial of institution, not by a settlement between the parties.
• Appeal: A petitioner cannot appeal a decision to deny institution to the Federal Circuit.
• Defensive value: This proceeding provides minimal defensive value for a party other than NVIDIA. Because the Board did not consider the merits of the invalidity arguments, the prior art asserted by NVIDIA remains available for use in a future IPR or in district court litigation. However, the patent owner, Onesta IP, can point to this denial as evidence that the patent has withstood a validity challenge from a sophisticated party.

Strategic summary

All claims of US patent 11,841,803 remain valid and enforceable. The denial of institution in IPR2026-00011 was a procedural victory for the patent owner, not a substantive one on the merits of the patent's validity.

• Claim Status: All claims of US patent 11,841,803 (claims 1-20) are UNTESTED on the merits at the PTAB. No claims have been canceled or sustained in a Final Written Decision.
• Estoppel Landscape: Because the IPR was not instituted, statutory estoppel under 35 U.S.C. § 315(e) does not apply. The petitioner, NVIDIA, is free to raise the same invalidity grounds, or any other grounds, in a district court or ITC proceeding. A different potential defendant is completely unencumbered by this proceeding and can use any available prior art in a future validity challenge.
• Pattern Signals: The patent was originally assigned to a major operating company (Advanced Micro Devices, Inc.) and was later transferred to an enforcement entity (Onesta IP, LLC) in late 2024. The IPR was filed by a direct competitor (NVIDIA Corporation), suggesting this patent is being actively asserted in the GPU market. The discretionary denial indicates that the patent owner is likely pursuing its enforcement campaign aggressively in federal court or the ITC, which has progressed to a point that the PTAB deemed a parallel IPR duplicative.

Recommended next steps

For a defendant currently facing an assertion of US patent 11,841,803, the key takeaway is that the patent remains fully intact.

• The denial of institution in IPR2026-00011 means a PTAB challenge is not a guaranteed path to invalidating this patent, particularly if there is ongoing, fast-moving litigation. The patent owner has already successfully argued for a discretionary denial once.
• Any defensive strategy must assume all 20 claims are valid and must be prepared to litigate validity in district court or the ITC without the benefit of a parallel IPR.
• The absence of any other PTAB activity is notable. While the patent survived one challenge procedurally, it has not yet faced a full merits review at the PTAB, meaning its claims cannot be considered "hardened" by withstanding a substantive IPR trial. A new defendant could still consider filing an IPR, but would need a strategy to overcome potential Fintiv arguments.

Following a review of the assignment and litigation history for US patent 11,841,803, here is the full ownership chain and analysis of NPE-related signals.

Inventors

The named inventors are Skyler J. Saleh, Samuel Naffziger, Milind S. Bhagavat, and Rahul Agarwal. The patent was filed on 2019-06-28 and originally assigned to Advanced Micro Devices, Inc. (AMD). All inventors were employees of AMD at the time of filing. Public professional profiles confirm that key inventors like Samuel Naffziger were senior executives at AMD for many years, indicating the invention originated from core internal R&D.

Original assignee

The original assignee of record is Advanced Micro Devices, Inc. (AMD), a major multinational semiconductor company based in Santa Clara, California. AMD designs and sells high-performance computing, graphics, and visualization technologies, and it actively ships products, including GPUs, that embody the patented technology related to chiplet architecture. AMD remains a major operating company.

Assignment timeline

A search of the USPTO Patent Assignment Database for patent 11841803 reveals two recorded assignments.

• 2019-07-29 (executed) / recorded 2019-08-02 — Reel 049943/0660

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Skyler J. Saleh, Samuel Naffziger, Milind S. Bhagavat, Rahul Agarwal (the inventors)
  • Assignee: Advanced Micro Devices, Inc.
  • Correspondent: Thomas A. Ward, AMD, Austin, TX
  • Context: Standard transfer from inventors to their employer post-filing.

• 2024-11-08 (executed) / recorded 2024-11-18 — Reel 069381/0951

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Advanced Micro Devices, Inc.
  • Assignee: Onesta IP, LLC
  • Correspondent: Jonathan R. Miller, Haug Partners LLP, New York, NY
  • Context: Transfer from the original developer (an operating company) to a third-party holding company, likely for the purpose of licensing and assertion.

Timeline diagram

timeline
    title Ownership of US 11841803
    2019 : Filed by AMD inventors
         : Assigned to AMD
    2023 : Patent issues
    2024 : Assigned to Onesta IP LLC
    2025 : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer: Present. The patent was transferred from Advanced Micro Devices, Inc., a large operating company, to Onesta IP, LLC. The assignee's name, containing the suffix "IP", and its lack of commercial products indicate it is a special-purpose entity for holding and asserting intellectual property rather than an operating company. (Reel: 069381/0951, Executed: 2024-11-08).

2. Known asserter in the chain: Present. While Onesta IP, LLC is a relatively new entity, public litigation data confirms it began asserting patents, including this one, shortly after its formation and acquisition of portfolios from operating companies like AMD. The patent text itself lists litigation filed in 2025 and 2026, subsequent to the transfer to Onesta IP. Unified Patents has also identified Onesta IP as a patent assertion entity.

3. Repeat correspondent across the chain: Not present. The two assignments on record were handled by different correspondents: one was an in-house attorney for AMD, and the other was an attorney at an external law firm representing Onesta IP.

4. Cascading transfers: Not present. There is only a single transfer from the original assignee to the current assignee.

5. Pre-litigation transfer: Present. The assignment to Onesta IP, LLC was executed on 2024-11-08. The litigation data provided lists a case filed in the Western District of Texas in 2025 (1:25-cv-00586), which is within months of the transfer, indicating the patent was acquired for the purpose of immediate assertion.

6. Bankruptcy fire-sale: Not present. The assignor, AMD, is a financially healthy and growing operating company.

7. Privateering: Unclear. It is possible that AMD retains a financial interest in the assertion campaign by Onesta IP, LLC, which would constitute privateering. However, without access to the confidential terms of the assignment agreement, this cannot be confirmed.

8. Defensive aggregator (anti-NPE): Not present. The chain ends at an assertion entity, not a defensive aggregator like RPX or LOT Network.

Verdict

NPE — high confidence

The verdict is based on two strong, unambiguous signals. First, the patent was transferred from its original inventor, the operating company AMD, to a non-operating "IP" holding company (Reel 069381/0951). Second, this transfer was immediately followed by litigation within months (case 1:25-cv-00586), confirming a clear pre-litigation transfer pattern for the purpose of assertion. This sequence is a classic indicator of an NPE monetization campaign.

Verify at: USPTO Patent Assignment Search for Pat. No. 11841803

Analysis of Prior Art for U.S. Patent 11,841,803

Patent in Question: US 11,841,803 B2

• Title: GPU chiplets using high bandwidth crosslinks
• Filing Date: June 28, 2019
• Issue Date: December 12, 2023
• Assignee: Advanced Micro Devices, Inc. (Original), Onesta Ip LLC (Current)
• Summary: This patent details a system and method for utilizing a multi-chiplet graphics processing unit (GPU) architecture. The core innovation lies in connecting multiple GPU "chiplets" using a passive, high-bandwidth crosslink, such as a silicon interposer. This arrangement allows the multiple chiplets to function and be addressed by the central processing unit (CPU) as a single, monolithic GPU. A key aspect is the maintenance of cache coherency across the last-level cache (LLC) of all chiplets, enabling seamless communication and data access between them. The design aims to overcome the manufacturing cost and yield limitations of large, monolithic GPU dies by breaking them into smaller, interconnected functional units.

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Potentially Relevant Prior Art

The following patent documents are cited as references in US 11,841,803 and have been analyzed for their potential to anticipate the claims under 35 U.S.C. § 102.

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1. US 10,475,147 B2

• Full Citation: US Patent 10,475,147 B2, "Multiple GPU graphics processing system," Arm Limited.
• Publication Date: November 12, 2019 (Filed: February 12, 2016)
• Brief Description: This patent describes a graphics processing system with multiple GPUs. It focuses on how rendering tasks are distributed and managed across these GPUs. The system includes a mechanism for one GPU to access the memory of another GPU to retrieve data needed for its rendering tasks. This is facilitated by a communication interface between the GPUs.
• Potential Anticipation of Claims:
  • Claim 1 & 7: This reference discloses a system with multiple GPUs communicably coupled. While it doesn't explicitly use the term "chiplet" or "passive crosslink," the described architecture of interconnected GPUs performing a unified task is conceptually similar. The nature of the communication interface would be critical in determining direct anticipation. If the interface functions as a dedicated bus for inter-GPU communication, it could be argued that it anticipates the "passive crosslink" element.
  • Claim 8 & 9: The '147 patent discusses memory access between GPUs, which implies a need for some level of memory coherence or a unified memory view. While it may not detail a coherent last-level cache across all units in the same manner as the '803 patent, the fundamental concept of inter-GPU memory access to present a unified system is present.

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2. US 2019/0123022 A1

• Full Citation: US Patent Application Publication 2019/0123022 A1, "3D Compute Circuit with High Density Z-Axis Interconnects," Xcelsis Corporation.
• Publication Date: April 25, 2019 (Filed: October 7, 2016)
• Brief Description: This patent application focuses on the physical structure of multi-chip modules, specifically using high-density vertical interconnects (through-silicon vias or TSVs) to stack and connect multiple semiconductor dies. This "3D" stacking allows for high-bandwidth communication between the dies.
• Potential Anticipation of Claims:
  • Claim 2, 3, & 10: This reference is highly relevant to the physical implementation claims of the '803 patent. It describes the use of interposers and high-density interconnects for chip-to-chip communication, which aligns with the "passive interposer die" and "PHY region" with conductor structures for chiplet-to-chiplet communications. The '022 application's focus on the physical linkage is a direct parallel to the structural aspects of the '803 patent's claims.

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3. US 2007/0273699 A1

• Full Citation: US Patent Application Publication 2007/0273699 A1, "Multi-graphics processor system, graphics processor and data transfer method," Nobuo Sasaki.
• Publication Date: November 29, 2007 (Filed: May 24, 2006)
• Brief Description: This application describes a multi-GPU system where multiple graphics processors are connected to a shared memory controller. It details a method for transferring data between the graphics processors through this shared controller to execute parallel processing tasks.
• Potential Anticipation of Claims:
  • Claim 1 & 7: This reference clearly discloses a system with multiple graphics processors working in concert. The communication between the processors, arbitrated by a shared memory controller, serves a similar function to the "passive crosslink" in the '803 patent, which is to facilitate inter-chiplet communication. The distinction would lie in whether the shared memory controller could be considered a "passive" element in the way the '803 patent defines its crosslink.
  • Claim 11, 12, & 16: The method of data transfer described in this application, where one processor requests data that may be held in the memory space of another, mirrors the method claims of the '803 patent. The process of routing a memory access request to the appropriate GPU and returning the data is a core concept in both.

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4. US 2001/0005873 A1

• Full Citation: US Patent Application Publication 2001/0005873 A1, "Shared memory multiprocessor performing cache coherence control and node controller therefor," Hitachi, Ltd.
• Publication Date: June 28, 2001 (Filed: December 24, 1999)
• Brief Description: This early reference describes a multiprocessor system with a focus on maintaining cache coherency across the different processors. It details a node controller that manages requests for data and ensures that all processors have a consistent view of the shared memory.
• Potential Anticipation of Claims:
  • Claim 8 & 9: This reference is highly relevant to the claims concerning cache coherency. It directly addresses the problem of maintaining a unified and coherent cache across multiple processing units. While it discusses general-purpose processors rather than specifically GPU chiplets, the underlying method for achieving cache coherency in a multi-processor system is fundamental to the novelty claimed in the '803 patent.
  • Claim 11, 13, 14, & 15: The method of handling memory access requests by determining the location of the cached data and routing the request accordingly is a key part of this Hitachi application. This process is analogous to the '803 patent's method of a primary chiplet determining a "caching GPU chiplet" and routing the request.

Disclaimer: This analysis provides an initial assessment of potentially relevant prior art and is not a formal legal opinion on the validity of US Patent 11,841,803. A thorough invalidity search and legal analysis by a qualified patent attorney would be required for a definitive conclusion.

Analysis of Obviousness for US Patent 11,841,803

An analysis of US Patent 11,841,803, titled "GPU chiplets using high bandwidth crosslinks," under 35 U.S.C. § 103 suggests that the claimed invention may be rendered obvious by a combination of prior art references. This analysis is predicated on the legal standard of whether a person having ordinary skill in the art (POSITA) at the time of the invention would have been motivated to combine existing technologies to arrive at the claimed subject matter with a reasonable expectation of success.

A thorough review of the patent's file history, specifically the prior art cited by the USPTO examiner during prosecution, is crucial for a definitive determination. However, based on publicly available information and the state of the art preceding the patent's priority date of June 28, 2019, a compelling case for obviousness can be constructed.

Summary of the Invention

US Patent 11,841,803 describes a system and method for a graphics processing unit (GPU) built from multiple smaller chips, or "chiplets." Key features of the invention include:

• A multi-chiplet GPU architecture: A GPU composed of an array of interconnected chiplets.
• A passive crosslink: A dedicated, passive interposer die for high-bandwidth communication between the GPU chiplets.
• A primary "host" chiplet: One GPU chiplet communicates directly with the central processing unit (CPU).
• Unified Cache Coherency: A last-level cache (LLC) that is coherent across all GPU chiplets, making the multi-chiplet array appear as a single, monolithic GPU to software.
• Dedicated PHY regions: Physical layer regions on the chiplets specifically designed for chiplet-to-chiplet communication.

Potential Obviousness Combinations

A person of ordinary skill in the art would likely have been motivated to combine teachings from prior art related to multi-chip modules (MCMs), passive interposer technologies, and existing GPU architectures with coherent memory systems.

Combination 1: A general-purpose multi-chip module patent combined with a patent on cache coherency in multi-processor systems.

• Rationale: By 2019, the use of MCMs to create larger, more powerful processors from smaller, higher-yielding dies was a well-established concept in the semiconductor industry. Patents detailing the use of silicon interposers (a form of passive crosslink) to connect multiple dies were prevalent. For example, a reference teaching the assembly of multiple processing dies on a passive interposer for improved performance and yield would provide the foundational structure.

• Motivation to Combine: A POSITA would be motivated to apply this MCM approach to GPUs to overcome the manufacturing yield and cost limitations of large monolithic GPU dies. As GPUs are inherently parallel processors, partitioning them into smaller, identical chiplets is a logical step. To make this partitioned GPU function as a single unit, a POSITA would naturally look to existing solutions for maintaining memory coherency in multi-processor systems. Prior art in the field of multi-core CPUs and server architectures extensively covers protocols and hardware for maintaining cache coherency across multiple processing units. Combining these two fields would be a predictable step to create a scalable and efficient multi-chiplet GPU.

Combination 2: A patent on 2.5D packaging with passive interposers and a publication detailing the architecture of a contemporary high-end GPU.

• Rationale: 2.5D packaging, which involves placing multiple dies side-by-side on a silicon interposer, was a known technology for high-performance computing applications. Patents and publications from foundries and packaging companies would describe the physical implementation of such a system, including the use of through-silicon vias (TSVs) and micro-bumps for high-density interconnects, which are elements of the "passive crosslink" described in the '803 patent. High-end GPUs of the era already featured sophisticated memory hierarchies with multiple levels of cache and mechanisms for ensuring data consistency across their many processing cores.

• Motivation to Combine: A POSITA, aware of the benefits of 2.5D packaging for high-bandwidth, low-latency communication, would be motivated to apply this technology to a GPU architecture. The goal would be to extend the existing on-chip memory system across multiple chiplets. The passive interposer provides the physical means for this extension. The challenge of maintaining a unified and coherent last-level cache across these chiplets is a direct and foreseeable problem that arises from this combination. The solution of extending the existing GPU's cache coherency protocols across the high-bandwidth passive interposer would be a straightforward engineering step for a skilled practitioner. The '803 patent's description of a "scalable data fabric" is a known concept for routing memory requests in such an environment.

Analysis of Claim Limitations

• Claim 1: This independent claim recites a system with a CPU coupled to a first GPU chiplet, which is in turn coupled to a second GPU chiplet via a "passive crosslink" for inter-chiplet communications. This fundamental structure would be rendered obvious by the combinations described above.
• Dependent Claims: Dependent claims that specify the passive crosslink as a "passive interposer die," the presence of "PHY regions," and a "unified cache memory" that is "coherent across all GPU chiplets" would also be obvious. The use of a passive interposer is inherent to 2.5D packaging. Dedicated PHYs are a standard requirement for any high-speed off-chip communication. The need for a coherent unified cache is a direct and necessary consequence of creating a multi-chiplet GPU that functions as a single logical unit, a problem for which solutions existed in the prior art.
• Method Claims: The method claims, which describe receiving a memory access request at a primary chiplet and routing it to a "caching GPU chiplet" via the passive crosslink, describe the standard operation of a distributed, coherent cache system. Once the hardware structure is deemed obvious, the method of its operation would also be considered obvious to a POSITA.

Conclusion

While a definitive conclusion of obviousness requires analysis of the specific prior art cited during the patent's examination, a strong prima facie case can be made that the claims of US Patent 11,841,803 would have been obvious to a person of ordinary skill in the art at the time of the invention. The motivation to combine known multi-chip module and interposer technologies with established principles of cache coherency from multi-processor architectures to create a scalable GPU is a logical and predictable progression of the state of the art. The claimed invention appears to be a successful implementation of this combination, but one that may not rise to the level of non-obviousness required for patentability.

Patent Term, Continuation, and Family Data for US 11,841,803

Patent Term Adjustments (PTA) and Extensions (PTE):
This patent has an adjusted expiration date of January 6, 2040. The standard term for a U.S. patent filed after June 8, 1995, is 20 years from the earliest nonprovisional filing date. For US 11,841,803, with a filing date of June 28, 2019, the original expiration would be June 28, 2039. The adjusted expiration indicates a Patent Term Adjustment (PTA) was granted by the USPTO to compensate for administrative delays during the patent's prosecution. There is no indication of any Patent Term Extension (PTE), which is typically granted for delays caused by regulatory review processes.

Continuation Applications:
A continuation application has been filed for this patent:

• Application Number: US18/388,602
• Filing Date: November 10, 2023
• Status: Pending
• Title: Gpu chiplets using high bandwidth crosslinks

Additionally, a placeholder for a future application (US19/337,250) exists, indicating a potential future continuation or related filing.

Divisional Applications:
There is no record of any divisional applications for US 11,841,803.

Patent Family Members:
US 11,841,803 is part of a larger patent family, with applications filed in several jurisdictions, all claiming priority from the original U.S. application (US16/456,287). These include:

• World Intellectual Property Organization (WIPO): WO2020263952A1
• European Patent Office (EPO): EP3991052A4
• China: CN114008662A
• Japan: JP7516428B2
• South Korea: KR20220024186A

Projected Expiration Date:
The projected expiration date for US Patent 11,841,803 is January 6, 2040. This date includes the calculated Patent Term Adjustment. This expiration is subject to the timely payment of all required maintenance fees.

Defensive Disclosure for U.S. Patent 11,841,803

Publication Date: May 13, 2026
Reference Patent: US 11,841,803 B2, "GPU chiplets using high bandwidth crosslinks"
Purpose: This document discloses a plurality of derivative inventions and improvements upon the '803 patent to place them in the public domain. The detailed descriptions and diagrams provided herein are intended to establish prior art against future patent applications claiming these or similar concepts, rendering them obvious under 35 U.S.C. § 103 or anticipated under 35 U.S.C. § 102.

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Derivatives Based on Core System Claims (Ref: Claim 1)

Axis 1: Material & Component Substitution

1.1. Derivative: Organic Interposer with Embedded Waveguides

• Enabling Description: The passive silicon crosslink is substituted with a multi-layer organic substrate interposer. This interposer contains embedded polymer optical waveguides for inter-chiplet communication, replacing electrical traces. Each GPU chiplet is flip-chip bonded to the organic interposer and uses micro-lenses and vertical-cavity surface-emitting lasers (VCSELs) for optical signal transmission and photo-diodes for reception. This architecture provides higher bandwidth and lower crosstalk compared to electrical interconnects. The routing of optical signals is passive, determined by the physical layout of the waveguides.
• Mermaid Diagram:

  graph TD
      subgraph CPU_Module
          CPU("Central Processing Unit (RISC-V Core)")
      end
  
      subgraph Multi_Chiplet_Module
          A[GPU Chiplet 1] -- Optical/Electrical via Bus --> CPU
          B[GPU Chiplet 2]
          C[GPU Chiplet N]
  
          subgraph Organic_Interposer
              direction LR
              WG1(Polymer Waveguide 1)
              WG2(Polymer Waveguide 2)
              WG3(Polymer Waveguide 3)
          end
  
          A -- VCSEL/Photodiode --> WG1
          B -- VCSEL/Photodiode --> WG1
          A -- VCSEL/Photodiode --> WG2
          C -- VCSEL/Photodiode --> WG2
          B -- VCSEL/Photodiode --> WG3
          C -- VCSEL/Photodiode --> WG3
      end
  
      style Organic_Interposer fill:#f9f,stroke:#333,stroke-width:2px
  

1.2. Derivative: Gallium-Nitride (GaN) High-Frequency Crosslink

• Enabling Description: The passive crosslink is fabricated from a Gallium-Nitride (GaN) substrate. GaN's properties allow for significantly higher frequency operation (>100 GHz) and better thermal conductivity than silicon. The inter-chiplet communication PHYs on the GPU chiplets are specifically designed to drive GaN-compatible transmission lines, enabling ultra-high-speed data transfer. The passive crosslink itself contains no active components, only impedance-matched microstrip or coplanar waveguides etched into the GaN substrate.
• Mermaid Diagram:

  sequenceDiagram
      participant CPU
      participant GPU_Chiplet_1
      participant GaN_Crosslink
      participant GPU_Chiplet_2
  
      CPU->>GPU_Chiplet_1: Memory Request (via CXL Bus)
      GPU_Chiplet_1->>GaN_Crosslink: Route Request (High-Freq Electrical Signal)
      Note over GaN_Crosslink: Passive propagation over GaN waveguides
      GaN_Crosslink->>GPU_Chiplet_2: Request Arrives
      GPU_Chiplet_2-->>GaN_Crosslink: Return Data
      GaN_Crosslink-->>GPU_Chiplet_1: Data Arrives
      GPU_Chiplet_1-->>CPU: Return Data to CPU
  

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Axis 2: Operational Parameter Expansion

2.1. Derivative: Cryogenic Superconducting Crosslink for Quantum Computing

• Enabling Description: The system is designed to operate at cryogenic temperatures (e.g., < 4 Kelvin) for use in a quantum computing control plane. The GPU chiplets are specialized processors for qubit state management. The passive crosslink is a superconducting interposer made of Niobium-Titanium (NbTi) alloy. The traces on the interposer are superconducting, offering zero electrical resistance and eliminating thermal noise. Communication is achieved via single flux quantum (SFQ) logic pulses, providing extremely low power and high-speed inter-chiplet signaling.
• Mermaid Diagram:

  graph TD
      subgraph Cryostat [Cryogenic Environment < 4K]
          QPU("Quantum Processing Unit")
          subgraph Control_Plane
              C1("Qubit Control Chiplet 1")
              C2("Qubit Control Chiplet 2")
              SC("Superconducting Passive Crosslink (NbTi)")
  
              C1 -- SFQ Pulses --> SC
              C2 -- SFQ Pulses --> SC
          end
          QPU -- Control Lines --> C1
          QPU -- Control Lines --> C2
      end
  

2.2. Derivative: Massively Parallel Exascale Array

• Enabling Description: The architecture is scaled to an array of 256 or more GPU chiplets arranged in a 16x16 grid on a large-area silicon interposer. This "passive backplane" provides a mesh network topology. A memory access request from a host CPU is routed through a primary chiplet, which then uses a 2D mesh routing algorithm (e.g., dimension-ordered routing) to forward the request to the target chiplet. The address space is interleaved across all chiplets in the array, creating a massive, unified last-level cache.
• Mermaid Diagram:

  graph TD
      Host[Host CPU] --> C_0_0
      subgraph Chiplet_Array_256
          C_0_0("Chiplet 0,0") --- C_0_1("Chiplet 0,1")
          C_0_0 --- C_1_0("Chiplet 1,0")
          C_0_1 --- C_0_2("...")
          C_0_1 --- C_1_1("Chiplet 1,1")
          C_1_0 --- C_1_1
          C_1_0 --- C_2_0("...")
          C_1_1 --- C_1_2("...")
          C_1_1 --- C_2_1("...")
      end
      note "All connections are via passive silicon backplane"
  

---

Axis 3: Cross-Domain Application

3.1. Derivative: Automotive Sensor Fusion Engine

• Enabling Description: An automotive system for ADAS/autonomous driving features a central compute module with specialized chiplets. A primary chiplet serves as a task scheduler. It connects via a passive crosslink to dedicated chiplets for LiDAR point cloud processing, RADAR signal processing, and camera image processing (e.g., using a CNN accelerator). When the LiDAR chiplet needs correlated camera data for object classification, it requests the relevant data region from the camera chiplet via the passive crosslink, enabling real-time, low-latency sensor fusion.
• Mermaid Diagram:

  flowchart LR
      subgraph Automotive_ECU
          Scheduler[Primary Chiplet]
          Lidar[LiDAR Processor Chiplet]
          Radar[RADAR Processor Chiplet]
          Camera[Camera Processor Chiplet]
          Crosslink{Passive Crosslink}
  
          Scheduler -- Control --> Crosslink
          Lidar <--> Crosslink
          Radar <--> Crosslink
          Camera <--> Crosslink
      end
      LiDAR_Sensor -- Point Cloud --> Lidar
      RADAR_Sensor -- Raw Data --> Radar
      Camera_Sensor -- Image Stream --> Camera
      Scheduler -- Fused Data --> Vehicle_CAN_Bus
  

3.2. Derivative: Distributed 5G/6G Baseband Processor

• Enabling Description: A 5G/6G base station utilizes a chiplet-based baseband processing unit. One chiplet handles the fronthaul interface (e.g., eCPRI). It distributes demodulation and decoding tasks to an array of identical processing chiplets via a high-bandwidth passive crosslink. Each processing chiplet is assigned a subset of users or frequency resource blocks. The crosslink is used for coordinating handovers and managing interference by allowing chiplets to share channel state information directly, without going through a central memory controller.
• Mermaid Diagram:

  sequenceDiagram
      participant Antenna
      participant Fronthaul_Chiplet
      participant Crosslink
      participant Processor_Chiplet_1
      participant Processor_Chiplet_2
  
      Antenna->>Fronthaul_Chiplet: RF Data In
      Fronthaul_Chiplet->>Crosslink: Distribute User Data (User A)
      Crosslink->>Processor_Chiplet_1: Route Data for User A
      Fronthaul_Chiplet->>Crosslink: Distribute User Data (User B)
      Crosslink->>Processor_Chiplet_2: Route Data for User B
      Note over Processor_Chiplet_1, Processor_Chiplet_2: Independent Demodulation
      Processor_Chiplet_1->>Crosslink: Share Channel State Info
      Crosslink->>Processor_Chiplet_2: Forward CSI for Interference Mitigation
  

---

Axis 4: Integration with Emerging Tech

4.1. Derivative: AI-Managed Predictive Caching

• Enabling Description: The passive crosslink controller on the primary GPU chiplet incorporates a lightweight, hardware-accelerated neural network. This AI model is trained to predict future memory access patterns based on the instruction stream from the CPU. When a memory access request is received, the model predicts which chiplet will be needed next. It then speculatively issues a pre-fetch command across the passive crosslink to that chiplet, moving the anticipated data into its last-level cache before it is explicitly requested. This reduces effective memory latency.
• Mermaid Diagram:

  flowchart TD
      A[CPU sends Memory Request Addr_X] --> B{Primary Chiplet Receives}
      B --> C[Passive Crosslink Controller]
      C --> D{AI Predictive Model}
      D -- "Predicts next request is Addr_Y on Chiplet 3" --> E[Issue Speculative Prefetch for Addr_Y]
      C -- "Request Addr_X is on Chiplet 2" --> F[Route Request for Addr_X]
  
      E --> G(Crosslink)
      F --> G
      G --> H[Chiplet 2]
      G --> I[Chiplet 3]
  
      H --> J[Return Data_X]
      I -- "Cache Data_Y for future use" --> K(LLC on Chiplet 3)
      J --> C --> L[Return Data_X to CPU]
  

4.2. Derivative: IoT-Monitored Thermal-Aware Routing

• Enabling Description: Each GPU chiplet integrates a grid of thermal and voltage sensors (IoT sensors). These sensors provide a real-time thermal map of each die to the primary chiplet's crosslink controller. When routing a memory access request, the controller consults this live thermal data. If the target caching chiplet is approaching a thermal throttle point, the controller can temporarily offload a portion of its cache lines to a cooler, neighboring chiplet, and redirect the memory request accordingly. This dynamic thermal management balances performance and system longevity.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Idle
      Idle --> Routing: Memory Request
      Routing: Entry/Consult Thermal Map
      Routing --> Normal_Path: Target Chiplet is Cool
      Routing --> Reroute_Path: Target Chiplet is Hot
      Normal_Path --> Serviced
      Reroute_Path: Action/Migrate hot cache lines
      Reroute_Path --> Serviced: Route to alternate chiplet
      Serviced --> [*]
  
      state Routing {
          direction LR
          Thermal_OK: check_temp() < threshold
          Thermal_Hot: check_temp() >= threshold
          [*] --> Thermal_OK
          [*] --> Thermal_Hot
      }
  

---

Axis 5: The "Inverse" or Failure Mode

5.1. Derivative: Graceful Degradation via Crosslink Fusing

• Enabling Description: The passive crosslink incorporates electronically-fusible links on the communication traces connected to each chiplet. A built-in self-test (BIST) routine runs at boot time. If the BIST identifies a faulty GPU chiplet, the primary chiplet sends a high-voltage signal to the fusible links associated with that chiplet, physically and permanently disconnecting it from the crosslink. The system then boots in a degraded mode with fewer active chiplets, remapping the memory address space across the remaining functional units. This provides high system reliability for mission-critical applications.
• Mermaid Diagram:

  flowchart TD
      Start --> A{Power-On Self Test}
      A -- All Chiplets OK --> B[Normal Operation]
      A -- Chiplet 3 FAILS --> C{Primary Chiplet Controller}
      C --> D[Send high-voltage signal to fuses for Chiplet 3]
      D --> E[Chiplet 3 Electrically Isolated]
      E --> F[Remap Address Space across remaining Chiplets]
      F --> G[Boot in Degraded Mode]
      B --> End
      G --> End
  

---

Combination Prior Art Scenarios (Integration with Open Standards)

Scenario 1: Combination with RISC-V and TileLink

• Description: The system is implemented within a RISC-V based System-on-Chip (SoC). The "CPU" is a multi-core RISC-V processor cluster (e.g., using the BOOM core design). The "bus" connecting the CPU to the primary GPU chiplet is the open-source TileLink cache-coherent interconnect standard. The GPU chiplet array functions as a TileLink agent. Memory access requests are TileLink transactions. The primary chiplet's crosslink controller is responsible for translating TileLink requests into the internal protocol used across the passive crosslink, making the entire GPU chiplet array appear as a single, coherent TileLink peripheral.

Scenario 2: Combination with OpenCL and SPIR-V

• Description: The multi-chiplet GPU is exposed to software through an OpenCL 3.0-compliant driver. Applications written in OpenCL are compiled into the SPIR-V intermediate representation. The custom GPU driver contains a JIT compiler that translates SPIR-V into machine code native to the chiplet architecture. The driver is responsible for abstracting the distributed nature of the hardware. It manages buffer allocation across the memories of the different chiplets and translates global memory accesses into the appropriate primary chiplet requests as described in the '803 patent's method. To the application, the device appears as a single OpenCL compute device with a large, unified global memory.

Scenario 3: Combination with CHIPS Alliance Bunch of Wires (BoW)

• Description: The physical layer of the "passive crosslink" is a direct implementation of the Bunch of Wires (BoW) die-to-die interconnect specification from the CHIPS Alliance. The PHY regions on each GPU chiplet are BoW-compliant PHYs. The "passive crosslink" is an interposer with passive traces that conform to the BoW channel specifications for a given process node. The protocol for routing memory requests is layered on top of the BoW physical signaling standard, leveraging an open, industry-vetted standard for the chiplet-to-chiplet electrical interface.