Prior art

The following prior art references are cited in US Patent 10931286, based on the information provided:

• U.S. Patent No. 9,748,961 B2 to Tabula, Inc.

  • Full Citation: US9748961B2
  • Publication/Filing Date: Publication date: 2017-08-29; Filing date: 2015-04-07.
  • Brief Description: This patent describes an implementation of related clocks.
  • Potential Anticipated Claims: The patent text for 10931286 explicitly states that "the prior art sought to address this problem by including a clock domain crossing circuit in the FPGA, however, these circuits inherently add a delay to the processing that takes place in the FPGA, which is not desirable since high frequency trading may include timestamps that are accurate to the microsecond such that even small delays may present a large problem." Therefore, any claims in US10931286 that rely on a clock domain crossing circuit for synchronization, or those that aim to reduce latency caused by such circuits, could potentially be anticipated. Specifically, claims relating to "phase matching between a receiver clock and a transmitter clock used in the field programmable gate array" without introducing unnecessary delay are the focus of US10931286.

• U.S. Patent No. 10,826,502 B1 to Nima Badizadegan

  • Full Citation: US10826502B1
  • Publication/Filing Date: Publication date: 2020-11-03; Filing date: 2018-11-05.
  • Brief Description: This patent is titled "Field programmable gate array with external phase-locked loop," similar to US10931286. It addresses the same core problem of synchronizing receiver and transmitter clocks in an FPGA.
  • Potential Anticipated Claims: Given the identical title and problem statement, this patent is highly relevant. US10931286 states, "The present invention generally relates to a field programmable gate array and an external phase controller providing phase matching between a receiver clock and a transmitter clock used in the field programmable gate array." Claims within US10931286 detailing the overall system architecture, the use of an external phase controller, a phase detector, and an adjustable oscillator to achieve phase alignment between receiver and transmitter clocks are highly likely to be anticipated or rendered obvious by US10826502B1. Since the inventor, Nima Badizadegan, is the same for both patents, it would require analysis under 35 U.S.C. 102(b)(1)(A) for grace period exceptions if the filing dates overlap. However, without further details on the specific claims, it can be stated generally that the core inventive concept of an FPGA system with external PLL for phase matching is present in this prior art.

• U.S. Patent No. 10,771,069 B1 to Nima Badizadegan

  • Full Citation: US10771069B1
  • Publication/Filing Date: Publication date: 2020-09-08; Filing date: 2019-02-21.
  • Brief Description: This patent is titled "Field programmable gate array with internal phase-locked loop."
  • Potential Anticipated Claims: While US10931286 emphasizes an external phase-locked loop, US10771069B1 describes an internal PLL. Claims in US10931286 that broadly describe components of an FPGA system (e.g., deserializer, serializer, computational circuitry, clock pins) and the general need for clock synchronization could potentially be anticipated by US10771069B1, especially if the claims do not explicitly restrict the PLL to being external. Claims in US10931286 that focus on the advantages of an external PLL over an internal one, such as reduced latency for high-frequency trading applications, would differentiate it.