Obviousness

To analyze the obviousness of US Patent 10931286 under 35 U.S.C. § 103, we must consider whether the claimed invention as a whole would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention, based on the prior art. The legal standard for obviousness requires identifying (1) the scope and content of the prior art, (2) the differences between the prior art and the claims at issue, (3) the level of ordinary skill in the pertinent art, and (4) any secondary considerations of non-obviousness. A combination of prior art elements is obvious if there was an apparent reason to combine them, such as to achieve a predictable result.

Given the patent's focus on field programmable gate arrays (FPGAs) and external phase-locked loops (PLLs) for low-latency clock synchronization in high-frequency trading, a PHOSITA would likely be an electrical engineer or computer architect with experience in high-speed digital design, FPGAs, and clocking architectures.

The PTAB challenges section of the previously generated analysis identifies the primary prior art references cited in IPR2026-00212 against US10931286 as:

• US 2018/0176043 to Badizadegan
• US 2018/0227189 to Nielson et al.
• US 8,248,095 to Elshoff et al.

Without the full text of these references, the following analysis relies on the general subject matter implied by their patent identifiers and the context of the IPR challenge (obviousness under § 103).

Obviousness Analysis of Independent Claims 1 and 2

Core Problem Addressed by US10931286: The patent aims to solve the technical problem of synchronizing receiver-side and transmitter-side clock signals within an FPGA without introducing unnecessary latency, particularly in applications like high-frequency trading, where conventional on-chip clock domain crossing (CDC) circuits add undesirable delays. The solution involves an external phase control circuit.

Combination of Prior Art: Badizadegan (US '043) in view of Nielson et al. (US '189) and Elshoff et al. (US '095)

Assumed Disclosures of Prior Art:

1. US 2018/0176043 to Badizadegan: As an earlier publication by the same inventor, this reference is highly likely to disclose fundamental aspects of FPGA-based high-frequency trading systems, including data reception (deserialization), processing, and transmission (serialization), and the general need for clock synchronization within FPGAs. It may also describe the inherent latency problems associated with traditional on-chip CDC circuits.
2. US 2018/0227189 to Nielson et al.: This reference likely discloses advanced transceiver architectures and clocking schemes within FPGAs, potentially including techniques for generating receiver-side and transmitter-side clocks, possibly using on-chip PLLs/DLLs. It may also address methods for data integrity and high-speed data throughput.
3. US 8,248,095 to Elshoff et al.: This patent likely teaches the use of external phase-locked loops (PLLs) or similar external clock control circuits for precise frequency and phase synchronization of electronic systems. It could describe the components of a phase control circuit, including phase detectors, phase controllers, and adjustable oscillators, and their application in maintaining clock alignment.

Motivation to Combine:
A PHOSITA facing the recognized latency issues of internal FPGA clock domain crossing (as likely taught by Badizadegan '043) would be motivated to seek alternative synchronization methods to achieve the low-latency processing critical for applications like high-frequency trading. Given that Nielson et al. '189 likely describes advanced FPGA transceiver and clock generation, and Elshoff et al. '095 teaches external PLLs for precise clock control, a PHOSITA would find it obvious to combine these teachings.

The motivation would be to leverage the high-speed data handling capabilities of FPGA transceivers (Nielson et al.) and the precise, low-latency phase control offered by external PLL systems (Elshoff et al.) to overcome the limitations of internal CDC circuits (Badizadegan '043). This combination would lead to a predictable improvement in overall system latency by offloading the complex and latency-sensitive phase alignment to a dedicated external circuit, thereby freeing up FPGA resources and accelerating critical data paths.

Obviousness of Independent Claim 1 (System Claim):

Independent Claim 1 describes an FPGA system with an external phase control circuit that achieves phase alignment between receiver and transmitter clocks with a fixed phase difference, explicitly stating that the "first set of operations does not include clock domain crossing operations that delays processing."

• FPGA Components: Badizadegan '043 and Nielson et al. '189 would likely disclose the core FPGA components: a first interface with reference clock and data pins, a deserializer to convert serial data to parallel and generate a receiver-side clock, computational circuitry, a serializer to convert parallel data to serial and generate a transmitter-side clock, and a second interface with clock output pins.
• External Phase Control Circuit: Elshoff etall. '095 would likely disclose the elements of an external phase control circuit, including a phase detector to compare clock signals, a phase controller to determine adjustments, and an adjustable oscillator to generate a controlled clock signal.
• Combination and Phase Alignment: A PHOSITA, aware of the latency problems of on-chip CDC circuits (Badizadegan '043) and equipped with knowledge of both FPGA transceivers (Nielson et al. '189) and external PLLs (Elshoff et al. '095), would be motivated to connect the receiver-side and transmitter-side clock outputs from the FPGA to an external phase detector (as taught by Elshoff et al. '095). The output of this external phase detector would then feed into an external phase controller and adjustable oscillator (Elshoff et al. '095) to generate a precisely controlled clock signal for the FPGA's serializer. This combination directly leads to the "transmitter side clock signal and the receiver side clock signal are phase aligned so that there is a fixed phase difference between the third phase and the fifth phase" feature, and the elimination of internal CDC operations for critical paths to minimize latency.

Therefore, the system claimed in Independent Claim 1, which combines known FPGA data path elements with an external, actively adjusting phase control loop to achieve low-latency clock synchronization, would have been obvious to a PHOSITA.

Obviousness of Independent Claim 2 (Method Claim):

Independent Claim 2 details a method for processing data in an FPGA system, particularly market data to generate order entry data, using an iterative external phase control loop for clock synchronization.

• FPGA Data Processing: Badizadegan '043 and Nielson et al. '189 would likely teach the steps of receiving serial data and a first clock, deserializing it to parallel data and a receiver-side clock, performing computational operations (including trading algorithms as a known application for FPGAs in HFT), and then serializing the processed data into a second serial data stream.

• External Iterative Phase Control Loop: Elshoff et al. '095 would likely describe the method of an external phase-locked loop for maintaining clock synchronization, which inherently involves an iterative process of:

  • Generating a second clock signal by an adjustable oscillator.
  • Generating a wire rate clock based on the second clock signal.
  • Generating an interim transmitter side clock signal by a serializer.
  • Transmitting clock signals to an external phase detector.
  • Generating an output by the phase detector based on a comparison.
  • Determining adjustment information by a phase controller.
  • Transmitting adjustment information back to the adjustable oscillator.
  • Repeating this loop until the phase difference is below a threshold.

• Combining for Low-Latency HFT: A PHOSITA seeking to improve latency in FPGA-based HFT (as taught by Badizadegan '043) would be motivated to apply the external, iterative phase control methods of Elshoff et al. '095 to the clock signals generated and used within the FPGA transceiver data paths described by Nielson et al. '189. The steps of transmitting the receiver-side clock and the interim transmitter-side clock out of the FPGA to an external phase detector, and then feeding adjustment information back to an external adjustable oscillator that drives the FPGA's transmitter clock, directly implements the external phase control loop of the method claim. This approach directly addresses the latency problem by removing the need for on-chip CDC circuits in the critical path and is a predictable outcome of combining these known techniques.

Therefore, the method claimed in Independent Claim 2, which outlines the iterative external phase control for low-latency clock synchronization in an FPGA for financial trading, would have been obvious to a PHOSITA.

Limitation:
This analysis is based on the general understanding of the cited prior art given their patent numbers and the context of the IPR challenge. A definitive obviousness determination would require a thorough review of the full text of US 2018/0176043 to Badizadegan, US 2018/0227189 to Nielson et al., and US 8,248,095 to Elshoff et al., including their detailed disclosures and claims.