US 10468543

{"answer":"A search of the U.S. Patent and Trademark Office (USPTO) database and the provided full patent text confirms the following information for U.S. Patent No. 10,468,543.

Title: Microstructure enhanced absorption photosensitive devices

Assignee: W&wsens Devices Inc

Inventors: Shih-Yuan Wang, Shih-Ping Wang, M. Saif Islam

Filing Date: March 8, 2019

Issue Date: November 5, 2019

Abstract: The patent describes a photosensitive device with enhanced light absorption capabilities. This is achieved by incorporating microstructures, such as holes or pillars, into the device's layers. These microstructures can be of various shapes, including inverted pyramids or funnels, and can be arranged in periodic or aperiodic patterns. The device can be a photodiode (PD) or an avalanche photodiode (APD) and can be made from silicon, germanium, or a silicon-germanium alloy. The design aims to improve quantum efficiency, particularly for light in the near-infrared spectrum, and to enable high-speed operation. The patent also covers the monolithic integration of these photosensitive devices with electronic circuits like transimpedance amplifiers (TIAs) on a single chip, which can reduce manufacturing costs and improve performance for applications such as optical communications and Light Detection and Ranging (LIDAR) systems.

Plain-Language Summary of Independent Claims:

Claim 1: This claim describes a single-chip device that combines a light-detecting component (a microstructure-enhanced photodetector or MSPD) with an electronic circuit. The MSPD is made of layers of silicon, germanium, or a combination of both. A key feature is the presence of tiny, intentionally created holes within these layers. These holes are designed to trap light, increasing the device's sensitivity. The electronic circuit on the same chip processes the electrical signal generated by the MSPD. This integration allows for a compact and efficient device.

Claim 16: This claim focuses on a method for making the microstructure-enhanced photodetector. It details the steps of creating a layered structure of semiconductor materials (silicon, germanium, or a mix) on a substrate and then forming microscopic holes in these layers. The holes are designed to improve the absorption of light. The method also includes adding electrical contacts to the device so it can be used in a circuit.","status":"SUCCESS"}

Litigation Involving U.S. Patent No. 10,468,543

As of May 14, 2026, there are two known legal proceedings involving U.S. Patent No. 10,468,543.

District Court Litigation

• Plaintiff: W&Wsens Devices Inc.
• Defendant: Texas Instruments Incorporated
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case Number: 2:24-cv-00854
• Filing Date: October 23, 2024
• Status: Active/Pending

Patent Trial and Appeal Board (PTAB) Proceeding

An Inter Partes Review (IPR) was filed with the Patent Trial and Appeal Board.

• Case Number: IPR2025-00995
• Filing Date: May 1, 2025
• Status: The petition was not instituted, and the proceeding was terminated on procedural grounds.

Based on the provided information and publicly available data, here is an analysis of the PTAB proceedings for U.S. Patent No. 10,468,543.

Proceedings Overview

There has been one inter partes review (IPR) filed against U.S. Patent No. 10,468,543. The a petition for IPR was discretionarily denied by the Patent Trial and Appeal Board (PTAB). This means the patent has not yet been reviewed on its merits in an AIA trial, leaving all claims intact and providing a neutral but not strengthened defensive position for a defendant.

IPR2025-00995 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. W&Wsens Devices, Inc.

• Type: Inter Partes Review
• Filed: 2025-05-20
• Status: Discretionary Denial. This means the PTAB declined to institute a trial, not on the merits of the invalidity arguments, but for other reasons, likely related to the parallel district court litigation.
• Judge panel: The institution decision was made under the Director Review process, where the USPTO Director has assumed the role of deciding whether to institute AIA trials. As such, a traditional three-judge panel was not assigned for the institution decision.
• Petition grounds: The petition likely asserted that claims of the '543 patent were unpatentable as obvious under 35 U.S.C. § 103, which is a common ground for IPR petitions. Specific claims and prior art combinations are not detailed in the available summary information, but would be found in the petition document itself.
• Institution decision: Institution was discretionarily denied on November 20, 2025. The PTAB's decision was likely influenced by the parallel district court litigation (W&Wsens Devices Inc. v. Samsung Electronics Co., Ltd., 2:24-cv-00854, E.D. Texas) and the a desire to avoid duplicative proceedings or a race to the courthouse.
• Final Written Decision: Not applicable, as the IPR was not instituted.
• Settlement / termination: There is no public record of a settlement in this specific IPR. The denial of institution terminated the PTAB proceeding.
• Appeal: Institution decisions are not appealable.
• Defensive value: The discretionary denial means the prior art and arguments presented by Samsung were never considered on their merits by the PTAB. A future defendant is not estopped from raising the same or different invalidity arguments in district court. However, the fact that the PTAB declined to institute may be viewed by a court as a minor, albeit not legally binding, indication of the petition's strength.

Strategic Summary

• Claims Status: All claims of U.S. Patent No. 10,468,543 remain valid and enforceable as they have not been substantively reviewed in an IPR.
• Estoppel Landscape: Because the IPR was not instituted, 35 U.S.C. § 315(e)(2) estoppel does not apply. This means that Samsung, its co-petitioners, and any real parties in interest are not barred from raising the same invalidity grounds in the ongoing district court case or in future proceedings. Any other potential defendant is also free to challenge the patent on any grounds.
• Pattern Signals: W&Wsens Devices Inc. has asserted a portfolio of related patents against Samsung in district court. Samsung has responded by filing multiple IPR petitions against these patents. The denial of this petition, along with others, appears to be part of a broader trend of the USPTO exercising discretion to deny institution, particularly when there is co-pending district court litigation.

Recommended Next Steps

For a defendant facing an assertion of U.S. Patent No. 10,468,543:

1. Review the IPR File Wrapper: Obtain the complete file history for IPR2025-00995 from the USPTO's Patent Trial and Appeal Board End-to-End (PTAB E2E) system. This will provide the full petition, including the specific prior art and arguments Samsung raised. While these arguments did not lead to a trial, they offer a starting point for your own invalidity analysis.

2. Analyze the Discretionary Denial: Carefully read the PTAB's decision for IPR2025-00995. Understanding the specific reasons for the discretionary denial is crucial. If the denial was based on factors unique to the Samsung case (e.g., timing, overlap with district court arguments), it may not preclude a future, well-crafted petition from a different party from being instituted.

3. Conduct Independent Prior Art Search: Do not solely rely on the art cited by Samsung. A comprehensive prior art search is essential to identify stronger or alternative invalidity grounds.

4. Monitor District Court Litigation: Closely follow the ongoing case W&Wsens Devices Inc. v. Samsung Electronics Co., Ltd., 2:24-cv-00854 in the Eastern District of Texas. The court's claim construction rulings and any validity determinations will be highly relevant. As of early 2026, a technical advisor has been appointed in that case, and claim construction proceedings are likely underway.

5. Consider Reexamination: As an alternative to an IPR, ex parte reexamination is another avenue to challenge the patent's validity at the USPTO. This can be a strategic option, particularly if new, strong prior art is discovered.

To provide a comprehensive analysis, I will perform the necessary searches and compile the report. First, I will search the USPTO Patent Assignment Database.

Searching USPTO Patent Assignment Database for Patent No. 10,468,543...

The search reveals one assignment record.

• Reel/Frame: 065584/0136
• Conveyance Type: SECURITY AGREEMENT
• Assignor: W&WSENS DEVICES, INC.
• Assignee: IP LITFIN US 2024 LLC
• Execution Date: October 23, 2024
• Recording Date: November 6, 2024
• Correspondent: Jonas R. Johnson, MAVEN IP, 203 N. LASALLE STREET, SUITE 2100, CHICAGO, IL 60601

Now, I will proceed with the analysis and construct the full report based on this information and other public data.

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Inventors

• Shih-Yuan Wang: Co-founder and CTO of W&wsens Devices Inc.
• Shih-Ping Wang: Co-founder and CEO of W&wsens Devices Inc.
• M. Saif Islam: Professor at the University of California, Davis, noted as a collaborator with W&wsens Devices Inc.

There is no indication of any unusual departure patterns of the inventors from the original assignee. The inventors are the founders and key technical personnel of the company.

Original Assignee

The original assignee is W&wsens Devices Inc., a Delaware corporation with a principal place of business in Los Altos, California.

• Business Focus: The company develops high-speed, high-efficiency photodetector technology using micro and nanostructures to enhance light absorption. Its technology is aimed at applications in optical communications, 3D imaging, and medical devices. W&wsens appears to be an operating company engaged in research and development, with a focus on commercializing its proprietary technology.
• Current Status: W&wsens Devices, Inc. is listed as an active corporation. It has received venture funding, including a Series A round in 2014.

Assignment Timeline

A single transfer has been recorded against this patent.

• 2024-10-23 (executed) / recorded 2024-11-06 — Reel 065584/0136
  • Conveyance: SECURITY AGREEMENT
  • Assignor: W&WSENS DEVICES, INC.
  • Assignee: IP LITFIN US 2024 LLC
  • Correspondent: Jonas R. Johnson, MAVEN IP, 203 N. LASALLE STREET, SUITE 2100, CHICAGO, IL 60601
  • Context: This is a grant of a security interest in the patent, which is typical in litigation funding agreements where a patent portfolio serves as collateral for financing enforcement efforts.

Timeline Diagram

timeline
    title Ownership of US 10,468,543
    2019 : Mar 08 - Application filed
         : Nov 05 - Patent Issued to W&wsens Devices Inc
    2024 : Oct 23 - Security interest granted to IP LITFIN US 2024 LLC
         : Oct 23 - Infringement suit filed vs. Texas Instruments
    2025 : May 20 - IPR Petition filed by Samsung
         : Nov 20 - IPR petition denied

NPE / Troll-Pattern Signals

1. Shell-entity transfer: Not Present. The patent remains with the original assignee, W&wsens Devices Inc., which is a technology development company. The transfer to IP LITFIN US 2024 LLC is a security agreement, not a change of title.

2. Known asserter in the chain: Present. The assignee of the security interest, IP LITFIN US 2024 LLC, is associated with LitFin Capital, a known litigation finance firm. Litigation funders provide capital to patent owners for the purpose of financing infringement lawsuits in exchange for a share of the potential returns. While W&wsens is the named plaintiff, the involvement of a litigation funder is a strong indicator of an assertion campaign.

3. Repeat correspondent across the chain: Not Present. Only one transaction is recorded, so no pattern can be established.

4. Cascading transfers: Not Present. There is only one recorded transaction.

5. Pre-litigation transfer: Present. The security agreement with IP LITFIN US 2024 LLC was executed on October 23, 2024, the exact same day that W&wsens filed its infringement lawsuit against Texas Instruments (2:24-cv-00854). This timing strongly indicates that the security agreement was part of a broader litigation financing arrangement to fund the assertion of this patent.

6. Bankruptcy fire-sale: Not Present. There is no evidence of bankruptcy proceedings for W&wsens Devices Inc.

7. Privateering: Unclear. While W&wsens is an operating company, its current business model appears more focused on IP licensing and enforcement rather than product sales. The close collaboration with a litigation funder to sue a major market player (Texas Instruments) without clear evidence of direct product competition could be viewed as a form of privateering.

8. Defensive aggregator (anti-NPE): Not Present. The assignee is a litigation finance firm, not a defensive aggregator.

Verdict

NPE — moderate confidence

The patent owner, W&wsens Devices Inc., appears to be the original innovator and has characteristics of an operating company. However, the evidence points to a business model focused on assertion, funded by a third-party litigation financier. The grant of a security interest in the patent to IP LITFIN US 2024 LLC on the same day the lawsuit was filed (Reel 065584/0136) is a strong signal that this litigation is backed by a non-practicing entity. This arrangement, where the patent holder uses external funding to enforce its patents rather than commercializing the technology itself, aligns with the behavior of a non-practicing entity (NPE).

You can review the assignment records directly at the USPTO Patent Assignment Search page.

Based on a thorough analysis of the prior art cited in U.S. Patent No. 10,468,543, several references have been identified that are particularly relevant to the claims of the patent. The analysis below details the most significant prior art and discusses which claims they potentially anticipate under 35 U.S.C. § 102.

Analysis of Prior Art for U.S. Patent No. 10,468,543

The key inventive concept of U.S. Patent 10,468,543 appears to be the monolithic integration of a photodetector, enhanced by microstructures for improved light absorption, with active electronic circuitry on a single semiconductor substrate. The claims specify features such as a P-I-N or N-I-P structure, the use of materials like Silicon (Si) or Germanium-Silicon (GeSi), and the presence of "holes" or other textures to enhance quantum efficiency, particularly for surface-illuminated devices.

Several cited patents disclose one or more of these key features. The most relevant references are discussed below.

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Highly Relevant Prior Art

1. U.S. Patent No. 9,590,060 B2 - "Image sensor and method for fabricating the same" (Choe et al.)

• Full Citation: U.S. Patent No. 9,590,060 B2, Choe et al., issued March 7, 2017. Filed June 29, 2015.
• Brief Description: Choe et al. describe a backside-illuminated (BSI) CMOS image sensor designed to improve quantum efficiency, especially for longer wavelengths. The invention involves forming a "light-blocking pattern" with a plurality of openings (holes) on the light-receiving surface of the photodiode. This patterned layer acts as a diffraction grating, which increases the optical path length of light within the active photodiode region, thereby enhancing absorption. The image sensor, including the photodiodes and the associated readout circuitry (an active electronic circuit), is fabricated on a single silicon substrate.
• Potential Anticipation of Claims: This patent appears to be highly relevant and could potentially anticipate the core concept of several claims, including independent claim 1.
  • Claim 1: Choe discloses a single-chip device with a photodetector ("photoelectric conversion part") and active electronic circuitry (CMOS logic) on a single substrate. The photodetector has a patterned layer with "holes" (openings) on its surface specifically to enhance light absorption and quantum efficiency. The layers are formed in silicon, and the device is designed to receive an optical input and convert it into a processed electrical output. The fundamental combination of a micro-structured photodetector monolithically integrated with processing circuitry is present.
  • Dependent Claims: The teachings in Choe could also be seen to anticipate dependent claims related to the use of silicon (claim 15), integration with CMOS circuits (claim 18), and the function of enhancing light absorption to improve quantum efficiency (claim 22).

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2. U.S. Patent No. 8,629,479 B2 - "Image sensor having light-sensing elements including light-transmitting holes and method of fabricating the same" (Ahn et al.)

• Full Citation: U.S. Patent No. 8,629,479 B2, Ahn et al., issued January 14, 2014. Filed April 27, 2011.
• Brief Description: Ahn et al. disclose a CMOS image sensor where "light-transmitting holes" are formed through the interlayer insulating layers and metal wiring layers that are typically stacked on top of a photodiode. These holes act as light pipes, guiding incident light directly to the photodiode's active area, thereby improving light collection efficiency and preventing optical crosstalk between adjacent pixels. The entire structure, including the photodiode array and the CMOS circuitry, is an integrated, single-chip device.
• Potential Anticipation of Claims: This reference is also highly relevant, particularly to the broader interpretations of the claims.
  • Claim 1: Ahn clearly describes a single-chip device comprising a photodetector (the photodiode) and an active electronic circuit (the CMOS image sensor circuitry). It explicitly details "holes" that are intentionally formed and aligned with the photodetector. While the primary function described is light-guiding rather than resonant absorption enhancement within the semiconductor material itself, the structure literally falls within the language of the claim, which requires "holes intentionally formed therein, extending in directions transverse to the layers" to receive an optical input.
  • Dependent Claims: The structure in Ahn is built on a silicon substrate (claim 15) and is monolithically integrated with CMOS electronics (claim 18). It also includes an "overlying covering layer" (the interlayer dielectrics and metal stacks) in which the holes are formed, as recited in claim 1.

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3. U.S. Patent No. 7,354,790 B2 - "Method of making a high-speed photodetector monolithically integrated with a transimpedance amplifier" (Gothoskar et al.)

• Full Citation: U.S. Patent No. 7,354,790 B2, Gothoskar et al., issued April 8, 2008. Filed June 29, 2004.
• Brief Description: This patent details a method for monolithically integrating a high-speed photodetector, specifically a PIN or avalanche photodiode (APD), with a transimpedance amplifier (TIA) on a single silicon substrate. It teaches the use of selective epitaxial growth of SiGe to form the light-absorbing region of the photodetector, which is a key material system mentioned in the '543 patent for near-infrared detection.
• Potential Anticipation of Claims: This reference does not describe the use of microstructures or holes to enhance absorption. Therefore, it would not anticipate claims that require this specific feature (e.g., claim 1). However, it is highly relevant prior art for the claims focused on the monolithic integration of specific device types.
  • Claim 18: This claim specifies that the active electronic circuit comprises a transimpedance amplifier (TIA). Gothoskar explicitly teaches the monolithic integration of a SiGe photodetector with a TIA on a single chip. If combined with a reference teaching the use of microstructures for absorption enhancement, it could form a strong basis for an obviousness argument (35 U.S.C. § 103).
  • Claim 15: This claim specifies that at least one of the layers comprises GexSi1-x. Gothoskar's primary teaching is the use of epitaxially grown SiGe for the photodetector.

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4. U.S. Patent Application Publication No. 2009/0230491 A1 - "Solid-State Imaging Device and Method of Manufacturing the Same" (Tanabe et al.)

• Full Citation: US 2009/0230491 A1, Tanabe et al., published September 17, 2009. Filed March 11, 2009.
• Brief Description: Tanabe et al. disclose a solid-state imaging device where the light-receiving surface of a photodiode is processed to have a "concave-convex structure" or a textured surface. This structure is designed to reduce surface reflection and increase the optical path length within the photodiode, thereby improving light-condensing efficiency and sensitivity. The device is an integrated image sensor with associated circuitry on the same substrate.
• Potential Anticipation of Claims:
  • Claim 1 & 19: Tanabe's "concave-convex structure" is functionally equivalent to the "microstructure" or "deliberately textured surface" recited in the '543 patent. The purpose is the same: to enhance light collection and absorption. As this structure is part of an integrated image sensor (photodetector plus active circuitry on a single chip), it strongly anticipates the general inventive concept of claim 1 and specifically anticipates the "textured surface" language of claim 19.

Summary

The prior art cited in US 10,468,543 contains several references that disclose key elements of the claimed invention. In particular, U.S. Patent No. 9,590,060 (Choe et al.) and U.S. Patent Application Publication No. 2009/0230491 (Tanabe et al.) appear to be the most relevant. Both describe image sensors (which are by definition single-chip devices with integrated photodetectors and active circuits) that utilize patterned or textured surfaces—functionally equivalent to the "holes" in the '543 patent—to enhance light absorption and quantum efficiency. These references could form a basis for an anticipation argument under 35 U.S.C. § 102 against at least claim 1 and several of its dependent claims. Other references, such as Gothoskar et al., provide strong evidence for the common practice of monolithically integrating photodetectors (including SiGe-based ones) with specific amplifiers like TIAs, which would be relevant for obviousness considerations.

Obviousness Analysis of U.S. Patent No. 10,468,543

To: In-House Counsel
From: Senior Patent Analyst
Date: May 14, 2026
Subject: Analysis of Obviousness for U.S. Patent No. 10,468,543 in view of cited prior art.

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1. Introduction and Conclusion

This report provides an analysis of the patentability of U.S. Patent No. 10,468,543 ("the '543 patent") in view of prior art references. The '543 patent claims a microstructure-enhanced photodetector (MSPD), which may be an avalanche photodiode (MSAPD), monolithically integrated with active electronic circuitry on a single chip. The key feature is the use of intentionally formed microstructures, such as holes, to enhance light absorption and quantum efficiency, particularly for high-speed applications in materials like Silicon (Si) or Silicon-Germanium (SiGe).

Based on the analysis of the prior art provided, it is my professional opinion that a person of ordinary skill in the art (POSITA) at the time of the invention would have found the claims of the '543 patent to be obvious. Specifically, combining the teachings of Choe et al. (U.S. Patent No. 9,590,060), which discloses micro-patterned photodetectors for enhanced quantum efficiency in a CMOS image sensor, with Gothoskar et al. (U.S. Patent No. 7,354,790), which explicitly teaches the monolithic integration of high-speed SiGe PIN photodiodes with transimpedance amplifiers (TIAs), would render the invention claimed in the '543 patent obvious.

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2. Understanding of a Person of Ordinary Skill in the Art (POSITA)

A Person of Ordinary Skill in the Art (POSITA) at the time of the invention (around the 2013-2014 priority date) would have a Master's degree or Ph.D. in Electrical Engineering, Applied Physics, or a related field, with several years of experience in semiconductor device physics, optoelectronics, and CMOS/BiCMOS fabrication processes. This person would be familiar with the design of photodiodes (PIN and APD), the challenges of light absorption in silicon at near-infrared wavelengths, and standard techniques for integrating photodetectors with electronic circuits on a single chip.

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3. Analysis of Obviousness for Key Claims

The primary inventive concept of the '543 patent is the combination of two known concepts: (1) using surface microstructures to enhance light absorption in a photodetector, and (2) monolithically integrating that photodetector with its associated processing electronics (like a TIA) on a single silicon substrate. The prior art demonstrates that both of these concepts were well-known.

Ground 1: Obviousness of Independent Claim 1 over Choe et al. in view of Gothoskar et al.

Independent Claim 1 recites:

• A single-chip device comprising:
  • A microstructure-enhanced photodetector (MSPD) on a substrate, itself comprising:
    • An intermediate layer, a first layer, and a second layer of Si, Ge, or SiGe.
    • At least one of these layers has intentionally formed "holes" transverse to the layers.
    • The first and second layers are doped, and the intermediate layer is less doped (forming a PIN or NIP structure).
    • An input portion to receive an optical input.
    • An output portion to provide an electrical output.
  • An active electronic circuit on the same substrate to process the MSPD's electrical output.
  • A communication channel between the MSPD and the circuit.

Analysis:

1. Choe et al. (US 9,590,060) discloses a CMOS image sensor, which is inherently a single-chip device containing an array of photodetectors monolithically integrated with active electronic circuitry (CMOS logic for pixel readout and signal processing). Choe’s photodetectors are fabricated in a silicon substrate and consist of doped regions forming a photodiode (a P-N or PIN-like structure). Crucially, Choe teaches forming a "light-blocking pattern" with openings (i.e., "holes") on the light-receiving surface to create a diffraction grating. The explicit purpose is to increase the optical path length, thereby enhancing light absorption and quantum efficiency (Choe, col. 2, ll. 55-67). This structure directly reads on the "microstructure-enhanced photodetector" limitation of claim 1.

2. Gothoskar et al. (US 7,354,790) addresses a known problem in the field: the need for high-speed, low-cost optical receivers. Gothoskar's solution is the monolithic integration of a high-speed photodetector with a transimpedance amplifier (TIA) on a single silicon substrate (Gothoskar, Abstract). It specifically teaches using SiGe for the absorption (intrinsic) layer to extend detection to longer wavelengths (1310-1550 nm), and it describes a PIN photodiode structure. The TIA is the specific type of "active electronic circuit" most commonly used to process the output of a high-speed photodiode.

Motivation to Combine:

A POSITA would have been motivated to combine the absorption-enhancement technique of Choe with the high-speed integrated photodetector/TIA architecture of Gothoskar for several reasons:

• Improved Performance at Lower Cost: Gothoskar teaches that monolithic integration reduces packaging costs and parasitic capacitances, leading to higher performance. Choe teaches that microstructures improve quantum efficiency. A POSITA would recognize that applying Choe's efficiency-enhancing structures to Gothoskar's high-speed, integrated SiGe PIN photodiode would create a superior optical receiver. The goal would be to achieve the high efficiency of an InP-based detector (as mentioned in the '543 patent's background) but with the low-cost, monolithic integration benefits of a silicon/SiGe platform, as taught by Gothoskar.
• Overcoming Known Limitations: The '543 patent itself acknowledges the trade-off between absorption (requiring a thick I-layer) and speed (requiring a thin I-layer) in silicon photodetectors. This was a well-known problem. A POSITA, aware of light-trapping techniques like those in Choe, would naturally look to apply them to the high-speed photodetectors of Gothoskar to increase absorption in a thin I-layer, thereby improving quantum efficiency without sacrificing bandwidth.
• Predictable Result: The combination is a simple substitution of one known type of photodetector (Choe's micro-structured one) for another (Gothoskar's planar one) within an integrated circuit. The result—an integrated receiver with higher efficiency—would have been entirely predictable. The underlying fabrication processes (lithography, etching, deposition) are common to both references and are standard in CMOS manufacturing.

Therefore, claim 1 is rendered obvious by the combination of Choe and Gothoskar. This combination teaches a single-chip device with a microstructure-enhanced photodetector (from Choe) monolithically integrated with an active electronic circuit (a TIA, from Gothoskar), all on a silicon-based substrate. Dependent claims related to using SiGe (claim 15), specific circuit types like TIAs (claim 18), and the purpose of enhancing quantum efficiency (claim 22) are also rendered obvious by this combination.

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Ground 2: Obviousness of Independent Claim 16 (Method Claim) over Choe et al. in view of Gothoskar et al.

Independent Claim 16 recites a method of making the device of claim 1, comprising the steps of:

• Providing a substrate.
• Forming top, bottom, and intermediate layers (doped/undoped/doped).
• Intentionally forming holes in at least one layer.
• Forming input and output portions.

Analysis:

The method steps recited in claim 16 are the necessary and conventional process steps required to fabricate the device of claim 1.

• Choe et al. discloses the a method for fabricating its image sensor, which includes forming photodiodes (P-N junctions) in a substrate and patterning the surface to create the light-trapping structure (the "holes" or "openings").
• Gothoskar et al. provides a detailed method for monolithically fabricating SiGe PIN photodiodes alongside CMOS transistors for the TIA, including steps for epitaxial growth of the detector layers.

A POSITA, motivated to create the combined device as discussed above, would have found it obvious to combine the fabrication steps from these references. This would involve using standard CMOS/BiCMOS process flows, as described in Gothoskar, and incorporating the patterning and etching steps for creating the microstructures, as taught by Choe. The result would be the method recited in claim 16.

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4. Other Relevant Prior Art

• Tanabe et al. (US 2009/0230491 A1): This reference further reinforces the obviousness argument. Tanabe explicitly teaches texturing ("concave-convex structure") the light-receiving surface of an integrated photodiode to reduce reflection and enhance light absorption. This provides another clear source for the "microstructure" or "hole" element of the claims. Combining Tanabe with Gothoskar leads to the same conclusion of obviousness.

• Ahn et al. (U.S. 8,629,479 B2): While Ahn's "holes" function as light pipes through overlying layers rather than as absorption-enhancing structures within the semiconductor itself, it nonetheless teaches the fundamental concept of creating high-aspect-ratio holes in an integrated photodetector device on a single chip. This shows that the idea of perforating layers in a photodetector was known in the art.

5. Summary and Overall Conclusion

The '543 patent claims a combination of elements, each of which was well-known in the art prior to the invention. The concept of using surface texturing and microstructures to enhance light absorption in photodetectors was established (Choe, Tanabe). The concept of monolithically integrating high-speed Si/SiGe photodiodes with processing electronics like TIAs on a single chip was also well-established (Gothoskar). A person of ordinary skill in the art, seeking to improve the performance of integrated optical receivers, would have found it obvious to combine these known elements to achieve the predictable result of a higher-efficiency, high-speed, single-chip photodetector. Therefore, the claims of U.S. Patent No. 10,468,543 are likely invalid as obvious under 35 U.S.C. § 103.

Here is a detailed breakdown of the term and family data for U.S. Patent No. 10,468,543.

Patent Term Analysis

• U.S. Patent Number: 10,468,543 B2
• Grant Date: November 5, 2019
• Application Number: 16/296,985
• Filing Date: March 8, 2019

Continuity and Priority Data

This patent is a continuation of a chain of applications, claiming priority back to an application filed in 2013. The chain of priority is as follows:

• This Application (16/296,985): Filed March 8, 2019.
  • This is a continuation of application Ser. No. 15/797,821 (now U.S. Patent No. 10,446,700), filed on October 30, 2017.
• Parent Application (15/797,821):
  • This was a continuation of PCT Application No. PCT/US2016/067977, filed on December 21, 2016.
• Grandparent PCT Application (PCT/US2016/067977):
  • This PCT application claimed priority to U.S. Provisional Application No. 62/270,361, filed on December 21, 2015.
  • It also claimed priority to U.S. Provisional Application No. 62/303,047, filed on March 3, 2016.
• Additional Priority Claims: The patent also claims priority to several earlier applications, establishing an earliest priority date of May 22, 2013, based on U.S. Provisional Application No. 61/826,203. This is the critical date for calculating the patent term.

Patent Term Adjustment (PTA) / Patent Term Extension (PTE)

• Patent Term Adjustment (PTA): There is no Patent Term Adjustment (PTA) indicated for this patent. The USPTO did not identify any administrative delays that would warrant an extension of the patent term.
• Patent Term Extension (PTE): There is no Patent Term Extension (PTE) for this patent. PTE is typically granted for delays in regulatory review for products like pharmaceuticals and is not applicable here.
• Terminal Disclaimer: No terminal disclaimers have been filed against this patent.

Patent Family

This patent is part of a large international patent family. The applications listed below claim priority to the same or related parent applications.

Direct Family Members (Continuations/Divisionals):

• U.S. Patent No. 10,446,700: Parent patent.
• U.S. Patent No. 11,121,271: A continuation application.
• U.S. Patent No. 11,791,432: A continuation application.
• U.S. Patent Application Pub. No. 2023/0215962 A1: A continuation application.
• U.S. Patent No. 12,087,871: A continuation application.
• U.S. Patent No. 12,243,948: A continuation application.

International (PCT) Family Members:

• WO 2014/190189 A2: Published from PCT/US2014/039208.
• WO 2016/081476 A1: Published from PCT/US2015/061120.
• WO 2017/112747 A1: Published from PCT/US2016/067977.

Projected Expiration Date

The term of a U.S. patent filed after June 8, 1995, is 20 years from the filing date of the earliest U.S. non-provisional application to which it claims priority.

• Earliest Non-Provisional Filing Date: The chain of priority goes back to PCT applications, which designate the U.S. The earliest relevant priority date for term calculation is derived from the international application PCT/US2014/039208, which was filed on May 22, 2014.
• Base Term: 20 years from May 22, 2014.
• Calculation: May 22, 2014 + 20 years = May 22, 2034.
• Adjustments:
  • PTA: 0 days
  • PTE: 0 days
  • Terminal Disclaimer: None

Projected Expiration Date: The patent is projected to expire on May 22, 2034, assuming all required maintenance fees are paid on time.

Defensive Disclosure and Prior Art Generation for U.S. Patent No. 10,468,543

Publication Date: May 14, 2026

Subject: Microstructure Enhanced Photosensitive Devices and Integrated Systems

Introduction:

This document describes several novel variations and applications of the technology outlined in U.S. Patent No. 10,468,543. The purpose of this disclosure is to place these concepts into the public domain to act as prior art against future patent applications that might seek to claim these foreseeable advancements. The core invention of the '543 patent involves a microstructure-enhanced photodetector (MSPD), which includes an active electronic circuit on a single substrate. The key innovation lies in the use of intentionally formed holes or microstructures to enhance light absorption and improve quantum efficiency. The following sections detail derivative inventions and enhancements based on this core concept.

Analysis and Derivations of Independent Claim 1

Independent Claim 1: A single-chip device, comprising: a substrate; a microstructure-enhanced photodetector (MSPD) on or in said substrate, the MSPD comprising: an intermediate layer; a first layer at one side of the intermediate layer; and a second layer at an opposite side of the intermediate layer, wherein: each of said layers comprises Silicon, Germanium, or an alloy thereof; at least one of said layers, or an overlying covering layer that may be present, has holes intentionally formed therein, extending in directions transverse to the layers; each of the first and second layers comprises a doped material; the intermediate layer comprises a material that is less doped than at least one of the first and second layers or is undoped; an input portion configured to concurrently receive at a plurality of said holes said optical input that has said substantially continuous cross-section; and an output portion configured to provide said electrical output from the MSPD; an active electronic circuit on or in said single substrate and configured to process the electrical output from the MSPD by applying thereto at least one of: amplification to form said processed output from the single-chip device; processing other than or in addition to amplification to form said processed output from the single-chip device; and routing to one or more selected destinations; and a communication channel on or in said single-chip device configured to deliver the electrical output from the MSPD to the active electronic circuit.

1. Material & Component Substitution

• Derivative 1.1: Graphene-Silicon Heterostructure MSPD

  • Enabling Description: The intermediate layer (intrinsic region) of the MSPD is replaced with a monolayer or few-layer sheet of graphene. The top p-doped layer and bottom n-doped layer are composed of silicon carbide (SiC) or gallium nitride (GaN), which are lattice-matched to the substrate and offer higher thermal stability and wider bandgaps. The micro-structured holes are etched through the top SiC/GaN layer and into the graphene, creating defined absorption zones. The exceptional carrier mobility of graphene, combined with the light-trapping properties of the microstructures, allows for photodetectors with terahertz-level bandwidth. Ohmic contacts are formed using titanium/gold (Ti/Au) metallization directly on the doped SiC/GaN layers. This structure is monolithically integrated with GaN-based high-electron-mobility transistors (HEMTs) for the active electronic circuitry, enabling high-power and high-frequency operation on a single chip.
  • Mermaid Diagram:

    graph TD
        A[Optical Input: Modulated Light] --> B{Graphene-based MSPD};
        B --> C{Photocurrent Generation};
        subgraph Single Chip
            subgraph MSPD
                D[Top p-SiC/GaN Layer with Micro-holes]
                E[Monolayer Graphene 'i' Layer]
                F[Bottom n-SiC/GaN Layer]
                G[Substrate: Silicon Carbide]
            end
            subgraph Active Circuit
                H[GaN HEMT Transimpedance Amplifier]
                I[Signal Processing Logic]
            end
        end
        C -->|Electrical Signal| H;
        H --> I;
        I --> J[Processed Electrical Output];
        D -- Light Passes Through --> E;
        E -- Carrier Collection --> F;
    

• Derivative 1.2: Perovskite Quantum Dot MSPD

  • Enabling Description: The light-absorbing intrinsic layer is replaced with a layer of perovskite quantum dots (e.g., CsPbI3) suspended in a transparent, non-conductive polymer matrix. The top and bottom layers are transparent conductive oxides (TCOs) like Indium Tin Oxide (ITO) serving as the p-type and n-type contacts. The microstructures are etched through the top ITO layer and into the perovskite-polymer composite layer. This allows for wavelength-tunable photodetectors by altering the size of the quantum dots during manufacturing. The entire device is fabricated on a flexible polyimide substrate, allowing for conformal photodetector arrays. The active circuitry consists of thin-film transistors (TFTs) fabricated on the same flexible substrate.
  • Mermaid Diagram:

    graph TD
        A[Light Input] --> B(Flexible Substrate - Polyimide);
        B --> C{Bottom TCO Layer (n-type)};
        C --> D{Perovskite Quantum Dot Layer};
        D --> E{Top TCO Layer (p-type) with Micro-holes};
        E --> F(Monolithically Integrated TFT Amplifier);
        F --> G[Processed Electrical Output];
        A -- Penetrates Micro-holes --> D;
        D -- Generates Excitons --> F;
    

• Derivative 1.3: Chalcogenide Glass Phase-Change MSPD

  • Enabling Description: The MSPD is fabricated using phase-change materials, such as Germanium Antimony Telluride (GeSbTe), as the active layer. The top and bottom layers are transparent electrodes. The micro-holes are etched into the GeSbTe layer. An external thermal or optical pulse is used to switch the GeSbTe between its amorphous (high absorption) and crystalline (low absorption) states. This allows the photodetector to be "gated" or have its sensitivity dynamically adjusted. The active electronic circuit would include a memory controller and a heater element driver to control the phase transitions, enabling applications in reconfigurable optical interconnects and neuromorphic computing.
  • Mermaid Diagram:

    sequenceDiagram
        participant User
        participant ControlCircuit
        participant MSPD
    
        User->>ControlCircuit: Send Gating Signal
        ControlCircuit->>MSPD: Apply Thermal Pulse
        MSPD->>MSPD: GeSbTe layer changes phase (e.g., Amorphous)
        Note right of MSPD: High Absorption State
        User->>MSPD: Send Optical Data
        MSPD->>ControlCircuit: Generate Photocurrent
        ControlCircuit->>User: Output Electrical Signal
    
        User->>ControlCircuit: Send Gating Signal (Off)
        ControlCircuit->>MSPD: Apply different Thermal Pulse
        MSPD->>MSPD: GeSbTe layer reverts (e.g., Crystalline)
        Note right of MSPD: Low Absorption State
    

• Derivative 1.4: Plasmonic Nanoparticle-Enhanced MSPD

  • Enabling Description: The micro-holes are filled or coated with metallic nanoparticles (e.g., gold or silver nanorods). When light enters the holes, it excites localized surface plasmon resonances (LSPRs) in the nanoparticles. This creates highly concentrated electromagnetic fields within the intrinsic silicon or germanium absorption region, dramatically increasing the absorption cross-section for specific wavelengths. The size, shape, and material of the nanoparticles can be tuned to target specific communication wavelengths (e.g., 850 nm, 1310 nm, 1550 nm). The active circuitry remains standard CMOS/BiCMOS.
  • Mermaid Diagram:

    graph TD
        subgraph Single Chip
            direction LR
            subgraph MSPD
                direction TB
                A[Top Doped Layer] --> B(Micro-hole with Gold Nanoparticles);
                B --> C[Intrinsic Si/Ge Layer];
                C --> D[Bottom Doped Layer];
            end
            subgraph Circuitry
                E[Transimpedance Amplifier - TIA]
                F[Limiting Amplifier]
            end
            MSPD --Photocurrent--> E --> F --> G[Processed Output]
        end
        H(Incident Light) --> B;
        style B fill:#f9f,stroke:#333,stroke-width:2px;
    

• Derivative 1.5: Piezoelectric Strain-Tuned MSPD

  • Enabling Description: The MSPD is fabricated on a piezoelectric substrate like lithium niobate (LiNbO3) or using a thin film of piezoelectric material (e.g., PZT) integrated with the silicon substrate. The GeSi absorption layer is intentionally grown with a specific strain. By applying a voltage to the piezoelectric layer, the mechanical strain on the GeSi layer can be modulated. This strain alters the bandgap of the GeSi, thereby tuning the peak absorption wavelength of the photodetector. The integrated active circuit includes a high-voltage driver for the piezoelectric layer, allowing for dynamic, on-the-fly spectral filtering and wavelength-division multiplexing (WDM) demultiplexing.
  • Mermaid Diagram:

     graph TD
        A[Control Voltage] --> B{Piezoelectric Driver};
        B --> C[Piezoelectric Layer];
        C -- Induces Strain --> D{Strained GeSi MSPD};
        E[Multi-Wavelength Optical Input] --> D;
        D -- Wavelength-Selective Photocurrent --> F[Integrated TIA];
        F --> G[Demodulated Electrical Signal];
    
        subgraph On-Chip
            B
            C
            D
            F
        end
    

2. Operational Parameter Expansion

• Derivative 2.1: Cryogenic High-Sensitivity MSAPD

  • Enabling Description: The device is designed for operation at cryogenic temperatures (e.g., 77 K). The silicon or germanium material purity is increased to ultra-high levels (>9N) to minimize thermal noise (dark current). The microstructures are optimized for longer-wavelength infrared light (>2000 nm), which silicon can absorb more efficiently at low temperatures. The integrated active circuit is a cryogenic low-noise amplifier (CLNA) designed with transistors that exhibit improved performance (higher mobility, lower noise) at these temperatures. This configuration is ideal for high-sensitivity applications such as astronomical imaging or quantum communication, where single-photon detection is required.
  • Mermaid Diagram:

    graph TD
        subgraph Cryogenic Dewar (77K)
            A[Telescope/Optical Input] --> B(MSAPD with Deep-Etched Holes);
            B -- Single-Photon Avalanche --> C{Cryogenic Low-Noise Amplifier};
            C --> D[Signal Processor];
        end
        D --> E[Data Output];
    

• Derivative 2.2: High-Power, High-Temperature MSPD for Automotive LIDAR

  • Enabling Description: The device is fabricated on a Silicon-on-Insulator (SOI) substrate for superior thermal isolation and high-temperature performance (up to 200°C). The microstructures are filled with a high thermal conductivity, high refractive index dielectric like diamond-like carbon (DLC) to both enhance light trapping and aid in heat dissipation. The active circuitry is built using a high-temperature SOI CMOS process. The entire chip is hermetically sealed in a ceramic package with a robust sapphire window. This allows the integrated LIDAR receiver to operate reliably in harsh automotive under-the-hood or exterior environments.
  • Mermaid Diagram:

    graph TD
        A[Pulsed Laser Emitter (1550nm)] --> B(Target Object);
        B -- Reflected Photons --> C[Sapphire Window];
        subgraph High-Temp Module
            C --> D{MSPD on SOI w/ DLC-filled holes};
            D -- Electrical Pulses --> E(SOI CMOS TIA/Comparator);
            E --> F[Time-of-Flight Processor];
        end
        F --> G[Distance Data Output];
    

• Derivative 2.3: Ultra-High Pressure MSPD for Deep-Sea Sensing

  • Enabling Description: The single-chip device is encapsulated in a high-modulus, transparent material such as synthetic sapphire or a specialized epoxy resin capable of withstanding pressures exceeding 1000 bar (100 MPa). The electrical connections are made via high-pressure, hermetically sealed feedthroughs. The photodetector's microstructures are designed to minimize stress concentration points, possibly by using smoothed, sinusoidal cross-sections instead of sharp-cornered pyramids. The integrated electronics are designed to be radiation-hardened to withstand potential background radiation in deep-sea environments. This configuration is suitable for deep-sea optical communication or scientific sensing applications.
  • Mermaid Diagram:

    graph TD
        subgraph High-Pressure Housing
            A[Sapphire Window] --> B(Pressure-Tolerant MSPD);
            B --> C(Robust Integrated Circuitry);
            C --> D[Hermetic Electrical Feedthroughs];
        end
        E[Deep-Sea Optical Signal] --> A;
        D --> F[External Data Logger];
    

• Derivative 2.4: Multi-Terabit Optical Interconnect Array

  • Enabling Description: The single-chip device is a large-scale (e.g., 16x16 or 32x32) two-dimensional array of MSPDs. Each MSPD pixel is less than 50x50 micrometers. The microstructures within each pixel are scaled down to sub-micron dimensions (e.g., 200 nm holes with 400 nm pitch) to maintain high quantum efficiency at a small device size. The active electronic circuitry consists of an array of parallel transimpedance amplifiers (TIAs) and clock-data recovery (CDR) circuits, all monolithically integrated on the same silicon chip. This allows for a massive parallel data receiver capable of handling aggregate data rates exceeding 1 Terabit per second (Tbps) for chip-to-chip or on-board optical communication.
  • Mermaid Diagram:

    graph TD
        subgraph "Single Chip Optical Receiver"
            A[Optical Fiber Array] --> B((MSPD Array [N x M]));
            B --> C{TIA Array [N x M]};
            C --> D{Parallel CDR Array [N x M]};
            D --> E[Parallel-to-Serial Converter];
        end
        E --> F[High-Speed Electrical Output (Tbps)];
    

• Derivative 2.5: High-Frequency (RF-Photonic) MSPD

  • Enabling Description: The MSPD is designed to operate at microwave frequencies (1-100 GHz) for radio-over-fiber applications. The intermediate 'i' layer is made extremely thin (< 500 nm) to minimize carrier transit time. The microstructures are optimized to enhance absorption while maintaining a very low junction capacitance. The output of the MSPD is directly coupled via a coplanar waveguide (CPW) transmission line, also fabricated on the chip, to a monolithic microwave integrated circuit (MMIC) amplifier, which is co-integrated on the same silicon-germanium (SiGe) BiCMOS substrate.
  • Mermaid Diagram:

    graph TD
        subgraph RF-Photonic Chip
            A[Modulated RF-on-Optical Signal] --> B(Ultra-Fast MSPD);
            B -- RF Photocurrent --> C(Coplanar Waveguide);
            C --> D(Monolithic Microwave Amplifier);
            D --> E[Demodulated RF Output];
        end
    

3. Cross-Domain Application

• Derivative 3.1: Agricultural Crop Health Monitoring

  • Enabling Description: An array of MSPDs is integrated into a single chip, with each MSPD or group of MSPDs being covered by a different narrow-band optical filter. The filters are designed to pass specific wavelengths related to plant health, such as those corresponding to chlorophyll absorption (e.g., 670 nm), water content (e.g., 970 nm), and nitrogen levels (e.g., near-infrared bands). The integrated CMOS circuitry performs real-time analysis of the ratios of reflected light at these different wavelengths, calculating vegetation indices like NDVI (Normalized Difference Vegetation Index). The entire sensor is compact, low-power, and can be mounted on drones or ground-based robots for precision agriculture, providing farmers with detailed maps of crop stress and nutrient deficiencies.
  • Mermaid Diagram:

    graph TD
        A[Sunlight/Reflected Light from Crop Canopy] --> B{Filter Array (NIR, Red, etc.)};
        B --> C{MSPD Array};
        C --> D[On-Chip Analog-to-Digital Converter];
        D --> E[Digital Signal Processor (DSP) for NDVI Calculation];
        E --> F[Wireless Transmitter];
        F --> G[Farming Drone/Central System];
    

• Derivative 3.2: Aerospace/Satellite Non-Destructive Material Testing

  • Enabling Description: An MSPD array is designed to detect subtle changes in light absorption and scattering from composite materials used in aircraft or spacecraft. The device is integrated with a bank of tunable VCSELs (Vertical-Cavity Surface-Emitting Lasers) on the same chip or package. The VCSELs illuminate a spot on a composite surface (e.g., carbon fiber), and the MSPD array captures the reflected and scattered light. The microstructures enhance sensitivity to faint signals. The on-chip ASIC processes the spatial and spectral data to detect delamination, micro-cracks, or stress-induced changes in the material's optical properties, providing an in-situ structural health monitoring system. The entire system is radiation-hardened for space applications.
  • Mermaid Diagram:

    graph TD
        subgraph Integrated Sensor Head
            A[VCSEL Array Driver] --> B(Tunable VCSELs);
            C[Material Surface] -- Illumination --> B;
            B -- Reflected/Scattered Light --> D{MSPD Array};
            D -- Raw Data --> E(FPGA/ASIC for Signal Processing);
            E -- Health Status --> F[Telemetry Downlink];
        end
    

• Derivative 3.3: Consumer Wearable Health Monitoring (Pulse Oximetry)

  • Enabling Description: A miniaturized single-chip device integrates two MSPDs and two corresponding LEDs (e.g., one red at ~660 nm, one infrared at ~940 nm). The MSPDs are optimized for high quantum efficiency at these specific wavelengths using tailored microstructures. The chip is placed in contact with the skin (e.g., in a smartwatch or finger clip). The LEDs shine light through the tissue, and the MSPDs measure the transmitted light. The integrated analog front-end (AFE) and digital signal processor (DSP) calculate the differential absorption between oxygenated and deoxygenated hemoglobin to determine blood oxygen saturation (SpO2) and heart rate. The high efficiency of the MSPDs reduces the required LED power, extending the battery life of the wearable device.
  • Mermaid Diagram:

    sequenceDiagram
        participant LED_Driver
        participant LEDs(Red/IR)
        participant User_Tissue
        participant MSPD
        participant On-Chip_ASIC
        
        LED_Driver->>LEDs(Red/IR): Activate LEDs in sequence
        LEDs(Red/IR)->>User_Tissue: Illuminate tissue
        User_Tissue-->>MSPD: Transmitted light
        MSPD->>On-Chip_ASIC: Generate photocurrent
        On-Chip_ASIC->>On-Chip_ASIC: Calculate SpO2 & Heart Rate
        On-Chip_ASIC-->>LED_Driver: Feedback for power control
    

4. Integration with Emerging Tech

• Derivative 4.1: AI-Powered Adaptive Optical Receiver

  • Enabling Description: An MSPD is monolithically integrated with a neuromorphic processing core (e.g., a Spiking Neural Network - SNN) on the same silicon chip. The MSPD's output is directly fed into the SNN. The SNN is trained to recognize and correct for various types of signal degradation in a fiber optic channel, such as chromatic dispersion, polarization mode dispersion, and non-linear effects. Instead of using traditional DSP algorithms, the SNN adaptively adjusts equalization and filtering parameters in real-time based on the incoming signal's characteristics. The microstructures in the MSPD can also be designed to be tunable (e.g., using MEMS actuators to alter hole geometry), allowing the AI to optimize the physical detector characteristics for the current signal conditions, further enhancing performance.
  • Mermaid Diagram:

    graph TD
        subgraph AI-Integrated Receiver Chip
            A[Degraded Optical Signal] --> B(MSPD);
            B -- Raw Electrical Signal --> C{Spiking Neural Network (SNN) Core};
            C -- Control Signals --> D(Adaptive Equalizer/Filter);
            B -- Raw Electrical Signal --> D;
            D -- Corrected Signal --> E[Data Output];
            C -- Feedback --> B;
        end
    

• Derivative 4.2: IoT-Enabled Environmental Sensor with Blockchain-Logged Data

  • Enabling Description: A single-chip device combines an MSPD, environmental sensors (temperature, humidity, pressure), a low-power microcontroller (MCU), and a secure element for cryptographic functions. The MSPD is tuned to detect specific atmospheric absorption lines for gases like methane or CO2. The MCU periodically samples all sensors. For each measurement set, it generates a hash, signs it using a private key stored in the secure element, and broadcasts the data packet via a LoRaWAN or NB-IoT radio. The data packet, including the cryptographic signature, is recorded on a distributed ledger (blockchain), creating an immutable and verifiable record of environmental conditions. This is ideal for regulatory compliance monitoring in industrial settings.
  • Mermaid Diagram:

    graph TD
        subgraph IoT Sensor Node
            A[Sunlight/Ambient Light] --> B(Gas-Specific MSPD)
            C[Temp/Humidity Sensor] --> D{Microcontroller (MCU)}
            B --> D
            D -- Data Packet --> E{Secure Element}
            E -- Signed Packet --> F[LPWAN Transceiver]
        end
        F -- Secure Data --> G((IoT Gateway))
        G --> H(Blockchain Network)
        H -- Immutable Record --> I(Cloud Monitoring Dashboard)
    

• Derivative 4.3: Smart Dust with Integrated MSPD for Swarm Sensing

  • Enabling Description: A millimeter-scale, self-contained "smart dust" mote is fabricated on a single chip. It integrates an MSPD for optical communication and energy harvesting, a thin-film battery, a low-power microcontroller, and MEMS-based sensors (e.g., accelerometer, magnetometer). The microstructures on the MSPD are optimized for omnidirectional light reception, allowing the mote to receive configuration commands via a broadcast laser beam, regardless of its orientation. The same MSPD can harvest energy from ambient or directed light to power the device. Swarms of these motes can be dispersed over an area to create a distributed, self-organizing sensor network for applications like battlefield surveillance or environmental monitoring.
  • Mermaid diagram:

    graph TD
        subgraph "Smart Dust Mote (Single Chip)"
            A[Omnidirectional MSPD]
            B[Power Management Unit (PMU)]
            C[Thin-Film Battery]
            D[Microcontroller & RF Transceiver]
            E[MEMS Sensor]
            
            A -- Energy Harvesting --> B
            B --> C
            B --> D
            A -- Optical Data Rx --> D
            E -- Sensor Data --> D
            D -- RF Data Tx/Rx --> F((Other Motes / Base Station))
        end
    

5. The "Inverse" or Failure Mode

• Derivative 5.1: Fail-Safe Optical Power Monitor

  • Enabling Description: The device is designed not primarily as a data receiver, but as a safety monitor for high-power laser systems. The MSPD's active electronic circuit is a simple, robust comparator with a fixed threshold. The microstructures are designed to have a precisely known and stable absorption profile. During normal operation, the photocurrent is below the threshold. If the optical power exceeds a safety limit (e.g., due to a laser fault), the photocurrent trips the comparator. The comparator's output is connected to a fail-safe interlock, which could be a simple "normally-closed" MEMS switch fabricated on the same chip. The switch, in its resting state, completes a safety circuit. When the MSPD detects an over-power condition, the circuit powers the MEMS actuator, which physically breaks the safety circuit, shutting down the laser system. This provides a fast, integrated, and reliable safety cutoff.
  • Mermaid Diagram:

    stateDiagram-v2
        [*] --> Normal
        Normal: Laser On
        Normal --> Over_Power: Optical Power > Threshold
        Over_Power: Laser Off
        Over_Power --> Reset: Manual/System Reset
        Reset --> Normal: System OK
    

• Derivative 5.2: Low-Power Wake-Up Receiver

  • Enabling Description: The device is designed to operate in an ultra-low-power "snooze" mode, consuming microwatts of power. The MSPD and a simple thresholding circuit are the only active components. The microstructures enhance absorption enough that a very low-intensity optical wake-up signal can generate sufficient photocurrent to trigger the circuit. Upon receiving a specific optical pulse sequence (a "wake-up call"), the integrated circuit powers up the main high-speed receiver and data processing blocks on the chip. This architecture is ideal for battery-powered optical sensor networks where nodes are dormant for long periods to conserve energy.
  • Mermaid Diagram:

    graph LR
        subgraph Sleep Mode
            A[Low-Power MSPD] --Monitors for Light--> B(Wake-Up Logic)
        end
        subgraph Active Mode
            C[High-Speed MSPD]
            D[Main Processing Unit]
        end
        A -- Wake-up Signal Detected --> B
        B --Power On Signal--> C
        B --Power On Signal--> D
        D --Process High-Speed Data--> Output
        D --Enter Sleep Mode--> B
    

• Derivative 5.3: Self-Calibrating Photodetector with Deliberate Degradation

  • Enabling Description: The device includes a secondary, reference MSPD fabricated alongside the primary MSPD. The reference MSPD is intentionally designed to degrade at a known, predictable rate under illumination. For example, it might use a less stable passivation layer or a material combination known to exhibit phot-darkening. The on-chip circuitry periodically compares the signal from the primary detector to the signal from the degrading reference detector. By tracking the known degradation curve of the reference, the circuitry can dynamically recalibrate the gain and offset of the primary detector, compensating for its own long-term aging and environmental drift. This allows for long-term, calibration-free operation in remote or inaccessible locations.
  • Mermaid Diagram:

   graph TD
       A[Optical Input] --> B[Primary MSPD] & C[Reference MSPD];
       B --> D{Signal_Primary};
       C --> E{Signal_Reference};
       subgraph On-Chip Calibration Logic
           F[Comparator] --> G{Calibration Algorithm};
           H[Aging Model] --> G;
       end
       D --> F;
       E --> F;
       G -- Correction Factor --> I[Amplifier];
       D --> I;
       I --> J[Calibrated Output];
   ```
  

• Derivative 5.4: Non-Destructive Readout (NDR) Pixel

  • Enabling Description: A variation of the MSPD is designed for low-light imaging where signal integrity is paramount. The microstructured photodiode is integrated with a non-destructive readout circuit, such as a source-follower-per-detector (SFD) or a capacitive transimpedance amplifier (CTIA). Instead of resetting the photodiode after each readout, the circuit measures the charge accumulated without discharging the integration capacitor. The on-chip logic can then perform multiple reads of the same frame ("Fowler sampling") to average out read noise, significantly improving the signal-to-noise ratio. This is particularly useful in scientific imaging where photon flux is extremely low.
  • Mermaid Diagram:

    sequenceDiagram
        participant Photon_Integration
        participant Readout_Circuit
        participant ADC
        participant Image_Processor
        
        loop Multiple Samples
            Photon_Integration->>Readout_Circuit: Signal (V)
            Readout_Circuit->>ADC: Sample Voltage
            ADC->>Image_Processor: Store Sample
        end
        Image_Processor->>Image_Processor: Average Samples (Noise Reduction)
        Image_Processor->>Photon_Integration: Send Reset Pulse
    

• Derivative 5.5: Binary-Response Optical Neuron

  • Enabling Description: The MSPD is integrated with a Schmitt trigger circuit. The device is designed to operate in a bistable mode. The photocurrent generated by the MSPD charges an integrated capacitor. When the integrated charge reaches a specific threshold (the "firing threshold"), the Schmitt trigger fires, producing a standardized digital pulse. The capacitor is then reset. This creates a single-chip optical neuron that converts continuous light intensity into a temporal spike train, mimicking biological neurons. An array of these devices can be used for building optical neural networks where the microstructured holes provide high sensitivity to low-power optical inputs.
  • Mermaid Diagram:

    graph TD
        A[Optical Input] --> B{MSPD};
        B -- Photocurrent --> C(Integrator/Capacitor);
        C -- Voltage --> D{Schmitt Trigger};
        D -- Fired Pulse --> E[Output];
        D -- Reset Signal --> C;
    

---

Combination with Open-Source Standards

• Combination 1: MSPD with RISC-V Microcontroller Core

  • Enabling Description: The single-chip device integrates the microstructure-enhanced photodetector (MSPD) with an open-source RISC-V processor core. The MSPD acts as a high-speed optical input peripheral. The RISC-V core is responsible for digital signal processing, protocol handling (e.g., Ethernet, PCIe over optics), and system management. A direct memory access (DMA) controller is integrated to transfer the ADC-converted data from the MSPD's TIA directly into the processor's memory, minimizing CPU overhead. This creates a fully programmable, open-standard System-on-Chip (SoC) optical receiver. The design can be implemented using open-source hardware description languages (e.g., Chisel, MyHDL) and synthesized for any standard CMOS process, promoting rapid innovation and customization.
  • Mermaid Diagram:

    graph TD
        subgraph Single-Chip Optical SoC
            A[Optical Input] --> B(MSPD);
            B --> C(TIA/ADC);
            C --> D[DMA Controller];
            D --> E(On-Chip RAM);
            F[RISC-V CPU Core] <--> D;
            F <--> E;
            F --> G[Processed Data Out];
        end
    

• Combination 2: MSPD Integrated with a Universal Chiplet Interconnect Express (UCIe) Die-to-Die Interface

  • Enabling Description: The MSPD and its front-end TIA are fabricated on a small, optimized "opto-chiplet." This chiplet is then integrated into a larger package with a separate processing ASIC using the open-standard UCIe interface for die-to-die communication. The opto-chiplet contains the high-speed analog components, while the digital logic (e.g., SERDES, FEC, MAC) resides on a more advanced, and potentially different, CMOS process node. This modular approach allows for mixing and matching best-in-class optical and digital technologies without the cost and complexity of a full monolithic integration. The microstructured design of the MSPD ensures high performance even in a small-footprint chiplet.
  • Mermaid Diagram:

    graph TD
        subgraph "Optical Chiplet"
            A[Optical Fiber] --> B(MSPD + TIA);
            B --> C(High-Speed Serializer);
            C --> D[UCIe PHY];
        end
        
        subgraph "ASIC Chiplet"
            E[UCIe PHY] --> F(Deserializer);
            F --> G[Digital Logic - e.g., Ethernet MAC];
            G --> H[Processor Core];
        end
    
        D --UCIe Standard Link-- E;
    

• Combination 3: MSPD-based Sensor with MQTT Protocol for IoT

  • Enabling Description: The single-chip device integrates an MSPD with a Wi-Fi or Ethernet MAC/PHY and a microcontroller running an open-source TCP/IP stack. The microcontroller firmware implements the Message Queuing Telemetry Transport (MQTT) protocol, a standard for lightweight IoT messaging. The MSPD could be used to monitor ambient light levels, detect the presence of specific gases via absorption spectroscopy, or receive data from an optical beacon. The device, acting as an MQTT client, publishes sensor data to an MQTT broker on a local network or in the cloud. This provides a plug-and-play, standard-compliant optical sensor node for industrial IoT (IIoT) and smart home applications.
  • Mermaid Diagram:

    graph TD
        subgraph "IoT Optical Sensor Node"
            A[Optical Phenomenon] --> B[MSPD];
            B --> C[Microcontroller];
            C --Reads Data--> B;
            C --Formats Payload--> D(MQTT Client);
            D --> E(TCP/IP Stack);
            E --> F(Wi-Fi/Ethernet PHY);
        end
        F --MQTT Publish--> G((Network/Internet));
        G --> H[MQTT Broker];