US 9997556

I'll verify the patent details against live sources before summarizing.

US 9,997,556 B2 — Verification Summary

Source of truth: The full patent text supplied in the prompt, sourced from https://patents.google.com/patent/US9997556/en (fetched 2026‑09‑24). Live search results corroborate the bibliographic data below (Espacenet citing-documents record listing "IMAGE SENSOR," inventor HWANG SUN‑HA, applicant SK HYNIX INC, priority 2016‑10‑06, publication US2018102392 A1 / US9997556 B2).

Bibliographic Data

Abstract (verbatim)

"An image sensor includes: a pixel array including a plurality of unit pixels that are arrayed in two dimensions, wherein each of the plurality of the unit pixels includes: a substrate that including a photoelectric conversion element; a recess pattern formed in the substrate to overlap with the photoelectric conversion element and correspond to a center of the photoelectric conversion element; a first gate suitable for filling at least the recess pattern; a second gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a first diagonal direction; and a third gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a second diagonal direction which intersects with the first diagonal direction."

Technology in Plain Language

This is a back‑illuminated stacked CMOS image sensor pixel. The photoelectric conversion element (photodiode) sits underneath the pixel transistors, so the pixel can approach ~100% fill factor. A recess (trench) pattern is etched into the substrate at the center of the photodiode, and the transfer gate fills it — giving a vertical transfer path from the photodiode to the floating diffusion, with the gate's upper portion extending laterally to overlap the floating diffusion. The active regions are laid out along diagonal directions D1 and D2 (≈±45° to the row/column axes) rather than the usual row/column bars; this lets the trench sit at the photodiode center while still leaving room for the reset, drive, and select gates at the pixel corners. The substrate is monocrystalline with a (100) surface plane, and the channel‑length direction of each transistor is aligned to the <100> crystallographic direction, which the specification asserts has higher carrier mobility than <110> (the direction that would result from conventional row/column‑oriented bars).

Independent Claims — Plain‑Language Overview

⚠️ Uncertainty flag: The authoritative full text supplied to me does not include a claims section — the description is truncated mid‑sentence ("the wel…") and no claim listing appears. The three independent claims below are inferred from the three "In accordance with an embodiment of the present invention" paragraphs in the Summary, which conventionally mirror the independent claims. I cannot state the exact claim numbers, total claim count, or precise claim language with authority. A USPTO PatentCenter / Patent Public Search lookup of the granted claims would be required to confirm.

Independent Claim A — 3‑transistor (3T) pixel with diagonal gate layout (first embodiment):
An image sensor with a 2‑D array of unit pixels. Each unit pixel has: a substrate containing a photoelectric conversion element; a recess pattern in the substrate overlapping the photodiode and located at the photodiode's center; a first gate filling at least that recess (the transfer gate); a second gate over the substrate, overlapping the photodiode, adjacent to the first gate in a first diagonal direction; and a third gate over the substrate, overlapping the photodiode, adjacent to the first gate in a second diagonal direction that intersects the first.

Independent Claim B — 4‑transistor (4T) pixel with an added fourth gate (second embodiment):
Same substrate/recess/first‑gate structure as Claim A, plus: a second gate on a first side of the first gate in the first diagonal direction; a third gate adjacent in the second diagonal direction; and a fourth gate on a second (opposite) side of the first gate in the first diagonal direction.

Independent Claim C — 4‑transistor read‑out circuit with crystallographic‑orientation limitation (third embodiment):
An image sensor comprising a photoelectric conversion element generating photocharges, plus a transfer transistor (to a floating diffusion), a reset transistor (initializing the floating diffusion), a drive transistor (gate coupled to the floating diffusion, generating the image signal), and a selection transistor (outputting the image signal). All four are formed in a monocrystalline substrate whose surface crystal face is a (100) plane and whose crystallographic direction corresponding to the channel‑length directions of all four transistor channels is the <100> direction (Miller Indices).

Representative dependent‑claim subject matter (from the Summary's "may further include" paragraphs): floating diffusion confronting the third gate; a first active region with the recess at one end and the FD at the other; first‑gate first/second regions; a second active region with bar‑shaped regions extending along D1/D2 joined by coupling regions; a P‑type well overlapping the photodiode; a pick‑up region; pixel arrays subdivided into N×M sub‑arrays with row/column‑symmetric unit pixels; and shared‑pixel sub‑arrays (1×2 and 2×2) in which some gates are dummy gates included only for layout symmetry and production‑yield stability.

Litigation / Docket Check

I searched for CAFC 2026 dockets and USPTO records specifically naming 9,997,556 and found no case, IPR/PGR, or ITC investigation asserting or challenging this patent. Search results did surface SK hynix‑related patent matters, but none of them name US 9,997,556 — for example:

• Monolithic 3D v. SK hynix / Kioxia, USITC Investigation No. 337‑TA‑1492 (instituted 2026‑03‑26; target date 2027‑08‑30), concerning HBM and 3D NAND.
• Advanced Memory Technology (AMT) v. SK hynix, U.S. District Court for the Eastern District of Texas (filed Dec. 2024), DRAM/flash patents; several SK hynix IPR petitions were denied institution.
• MonolithIC 3D v. SK hynix, E.D. Tex. No. 2:26‑cv‑00393, and v. NVIDIA, No. 7:26‑cv‑00190, both over 3D‑stacking patents.
• Earlier Netlist v. SK hynix matter, settled 2021.

Caveat: A null search result is not proof of absence. My search tools are not a direct, authoritative query of the USPTO PatentCenter assignment/transaction history or of PACER/CAFC dockets. A definitive litigation check should be run against PACER, the CAFC docket, the USPTO Patent Trial and Appeal Board (PTAB) API, and the ITC EDIS system using the exact number 9,997,556.

Notes on the Source Text

• The supplied text contains OCR/typographical artifacts (e.g., "FIGS, 5 A and 5 B," "second gate insulating layer 2308," "first gate insulating layer 320 E," "the first u t pixel," "figures 5A and 5B" truncated as "FIGS. 5A and 5B"). These are transcription noise, not claim terms, and I have not auto‑corrected them.
• The description contains a self‑inconsistency worth noting for anyone charting claims: in the second (4T) embodiment the text describes the fourth gate's channel direction with reference to "substrate 200" rather than the 4T embodiment's substrate 300 — apparently a copy‑edit error in the specification.

I'll search for litigation involving US patent 9997556 across patent litigation sources.

Let me search more targeted litigation sources.

Let me try more specific sources for this patent's litigation history.

Litigation Search Report: US Patent No. 9,997,556

Bottom line

I found no litigation naming US Patent No. 9,997,556 ("Image sensor," SK hynix Inc.) in any of the sources searched.

I want to be explicit that this is a null result based on the searches I was able to run, not a definitive "no litigation exists" finding. I could not reach a source that provides a comprehensive, authoritative litigation docket for this specific patent.

What US 9,997,556 is

Per the authoritative patent text you provided (Google Patents, fetched 2026-09-24):

The patent claims a stacked CMOS image sensor with a recess pattern at the center of a photoelectric conversion element, gate electrodes oriented along diagonal directions, and a monocrystalline substrate whose channel-length direction is the <100> direction.

Sources searched and what they returned

• Google Patents (full text for US9997556) — The furnished record shows no litigation section; it lists only prosecution/assignment events (filed 2017-04-07, assigned to SK Hynix, published 2018-04-12, granted 2018-06-12). No "Litigation" or "Related litigation" entries.
• General web searches for "US9997556," "9,997,556," and variants — No district-court, ITC, or Federal Circuit matter referencing this patent number. Results returned other, different patents (e.g., 10,998,755 / 9,735,755 / 8,891,298 families) and unrelated SK hynix suits — none of which is the patent you asked about. Per your strict rule, I did not treat those similar numbers as matches.
• Unified Patents portal / PTAB-related pages surfaced — No PTAB (IPR/PGR) proceeding naming 9,997,556 was returned. (Note: PTAB proceedings are not district-court litigation, but they are relevant context and likewise appear absent.)
• RPX Empower and Docket Alarm results — Surfaced active NPE suits against SK hynix (e.g., Vervain, LLC v. SK hynix Inc., 1:26-cv-00259 (W.D. Tex., filed Feb. 3, 2026); MonolithIC 3D Inc. v. SK Hynix Inc., 2:26-cv-00145 (E.D. Tex.)), but none of these pleadings reference 9,997,556 as an asserted patent. Those cases involve different patents (e.g., NAND controller/storage patents and monolithic 3D patents).

Important caveats / limitations

• I did not obtain a hard confirmation from a primary litigation database (e.g., a Docket Alarm "litigation for patent 9,997,556" page, an RPX litigation page for this patent, or PACER). My tool calls hit the step limit before I could open such a page directly.
• A negative result from these searches should not be treated as conclusive. Many patent litigation databases (Lex Machina, Docket Navigator, RPX, Unified Patents portal) are paywalled or not fully indexed by general web search. A patent can be asserted in a case that does not surface through open search.
• This patent has a relatively narrow profile: a 2018-granted SK hynix image-sensor patent. Such patents are commonly used defensively or in cross-licensing rather than asserted offensively, which is consistent with (but does not prove) the absence of litigation.

Recommended next steps to confirm

If you need a definitive answer, I suggest querying a dedicated litigation database directly:

1. Docket Alarm or Docket Navigator — search "US9997556" for district court and PTAB matters.
2. RPX Empower (litigation.rpxcorp.com) — patent-level page for 9,997,556.
3. Unified Patents Portal — https://portal.unifiedpatents.com/litigation/caselist (search this patent) and the PTAB caselist.
4. USPTO Patent Center / Global Dossier — check the "Litigation" or assignment/reexamination tabs for the application 15/482,208.

I can complete those targeted lookups if you can re-run me, or confirm the specific competitor/market (e.g., which image-sensor products) you suspect may be accused, which would let me focus the search on specific pleadings.

I'll start by verifying the structured data against live sources, since the ODP ingest may lag recently-filed proceedings.

No hits yet. Let me check litigation, Unified Patents, and patent-specific databases.

Let me try a few more targeted checks before concluding.

Proceedings overview

Total AIA trial proceedings on file: 0. As of 2026-09-30, there are no inter partes reviews, post-grant reviews, or covered business method reviews involving US 9,997,556 ("Image sensor," SK hynix Inc., inventor Sun-ha Hwang) — the structured "PTAB proceedings on file" block reflects an empty USPTO ODP result set, and my web searches for a proceeding number, a petitioner, or a FWD disposition tied to 9,997,556 / US15/482,208 returned no matches. Breakdown by status is therefore: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0. Defensive posture: no help and no harm from the Board. The patent is completely untested — not "hardened by surviving two IPRs," and not "narrowed by a cancellation." Every claim that exists is UNTESTED at the PTAB, and no petitioner estoppel exists under § 315(e)(2).

Proceedings

None to report. I will not invent proceeding numbers, panels, or dispositions. For the record, the following candidate sources were checked and produced no hit for this patent:

• USPTO ODP structured block supplied in this prompt (canonical list) — empty.
• USPTO PTAB E2E / PTAB Center public-information search (via web search for the patent number plus IPR/PGR/CBM terms) — no proceeding pages.
• Search for the patent number against petitioner-side litigation and IPR briefing text (which routinely cites the challenged patent number) — no hits.
• Search for "9,997,556" combined with SK hynix, image sensor, Federal Circuit, and RPX/Unified Patents — no hits.

Caveat on confidence: my searches were web-index based, not a direct query of the PTAB E2E API or Docket Alarm / Lex Machina. A recently filed petition (filed within roughly the last 90 days) can sit unindexed or unpublicized, since a petition is only publicly viewable after the Board's mailing date work. I flag that limitation explicitly rather than asserting a negative I cannot fully prove. The structured ODP block remains the best available evidence, and it says zero.

Strategic summary

Claim status: entirely UNTESTED. No claim of 9,997,556 has been canceled, confirmed, or even instituted upon. Because there is no Final Written Decision, I cannot tell you which claims survive — the honest answer is that all of them are live as issued. The patent granted 2018-06-12 on an application filed 2017-04-07, claiming KR priority 10-2016-0128837 filed 2016-10-06, with an anticipated expiration of 2037-04-07. The claim set as disclosed in the specification presents at least three independent-claim families: (i) a three-gate unit pixel with a recess pattern centered on the photoelectric conversion element and second/third gates offset along intersecting diagonal directions; (ii) a four-gate variant adding a fourth gate on the opposite side of the first gate along the first diagonal; and (iii) a circuit-level claim in which transfer, reset, drive, and selection transistors all sit in a monocrystalline substrate whose surface is a (100) plane with channel-length directions along <100>. I note the geometry-and-crystallography limitations in family (iii) as the plausible § 103 battleground, but I expressly do not have a verified claim listing and will not assign claim numbers.

Estoppel landscape: empty, and that cuts in the defendant's favor. With no IPR/PGR ever filed, there is no § 315(e)(2) estoppel barring anyone. Any prior-art ground a defendant wants to run — § 102 anticipation, § 103 obviousness, printed publications, patents, and (with the right supporting evidence) prior public use or systems art — remains fully available at the Board and in district court. There is also no § 325(d) risk of "same art previously presented" beyond what the examiner considered during prosecution, and no adverse Board claim construction to work around. Equally, there is no petitioner-side record to mine for admissions.

Pattern signals: none. No petitioner has filed multiple IPRs on this patent (there is no petitioner at all). The patent owner has not pursued any PTAB appeal, because there is nothing to appeal — no adverse FWD, no ex parte appeal decision surfaced. No defensive aggregator (Unified Patents, RPX, or similar) appears anywhere in the chain for this patent. The owner of record is SK hynix Inc., an operating semiconductor manufacturer, not an NPE or monetization vehicle — which is itself the most probative signal here. Operating-company patents of this vintage in the image-sensor space are typically asserted defensively in cross-licensing negotiations or in captive supplier/customer disputes, not in the serial-assertion campaigns that generate IPR traffic. The absence of PTAB activity is therefore best read as consistency with a patent being used as a portfolio/negotiating asset, not as a patent that has repelled challengers.

Recommended next steps

1. Do not litigate on the assumption that an IPR is auto-filed or already exists. There is no FWD to link to, no disposition to quote, and no canceled claim to point a demand letter at. If opposing counsel or a plaintiff represents that this patent has been "upheld" or "invalidated" at the PTAB, demand the proceeding number — per the record above, none exists.

2. Establish your real procedural posture first — availability windows are closed for two of the three AIA vehicles. The patent granted 2018-06-12, so:

• PGR is time-barred (35 U.S.C. § 321(c): nine months from grant, i.e., the window closed 2019-03-12). Do not plan a PGR.
• CBM is unavailable — the transitional program sunset for petitions filed after 2020-09-16, and an image-sensor patent is unlikely to qualify as a "covered business method" patent in any event.
• IPR is the only live AIA route, and it is unrestricted in time for a petitioner who has not been served with an infringement complaint more than one year earlier (§ 315(b)). That one-year bar is the gating fact you must confirm today: if you have already been served, the clock may have run, and your only route back to the Board may be a joinder request under § 315(c) to an existing proceeding — of which there is none.

3. Confirm the negative through primary sources before you rely on it. Two minutes of unglamorous checking is worth more than my search results here:

• Query PTAB E2E (https://ptab.uspto.gov) and the PTAB Center using "9997556" as the patent number, and separately "15/482,208" as the application number.
• Query Docket Alarm's PTAB docket and CourtListener's RECAP (https://www.courtlistener.com) for the patent number, and pull the patent's Google Patents "Litigation" / "Similar Documents" tabs (https://patents.google.com/patent/US9997556/en).
• If a proceeding surfaces that ODP has not yet ingested, the operative dates you need are the § 314(b) institution deadline (six months from the petition's filing/accrual date) and the § 316(a)(11) final-written-decision deadline (one year from institution, extendable up to six months for good cause) — those two dates drive the stay analysis and any § 315(b) timing.

4. Read the specification's diagonal-geometry teaching as your invalidity roadmap. The patent's own framing concedes that active regions for pixel transistors "have a bar shape typically extended in the row direction RD or the column direction CD," and that the invention is the diagonal reorientation needed to put the recess pattern at the photodiode center while retaining space for the other transistors. That is an admission of the conventional structure, and it points directly at the art you want: pre-2016 back-illuminated/stacked CIS pixels with buried or recessed transfer gates, vertical transfer gates, and diagonal or rotated active-region layouts. This is precisely the art SK hynix itself was prosecuting in the same period (compare, e.g., its own US 9,929,194 "Image sensor including vertical transfer gate" and the related filings by Na and Kwag listed in the family), and self-owned sibling art is often the most useful § 103 starting point because it is presumptively analogous and shares the field of endeavor.

5. Treat the crystallography limitation as the vulnerability to test. The (100)-surface / <100>-channel-length claim family is a structural recitation with an admitted performance rationale: the specification states that <100> "is known having a higher carrier mobility than other crystallographic directions including the <110> direction." A claim that recites a known-beneficial crystal orientation for a transistor channel, added to an otherwise conventional pixel layout, is a textbook § 103 candidate if any pre-2016 reference in the stacked-CIS space specifies a (100) wafer with <100> channel directions — which standard CMOS process literature routinely does. That is likely to be a more productive ground than attacking the recess-pattern geometry.

I'll verify the assignment record against live sources before reconstructing the chain.

Verification note up front

I could not reach the USPTO Assignment Center's record for this patent directly — https://assignmentcenter.uspto.gov/ is a JavaScript application that my search tools cannot query, and my available searches returned no reel/frame data, no recorded correspondent, and no post-issuance assignment documents for US 9,997,556. What I do have is the authoritative Google Patents legal-events record supplied in the prompt. I will not invent reel/frame numbers or correspondent names. Where a field is unavailable, I say so rather than fill it.

One record exists, and only one. That is the finding.

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Inventors

Pattern notes:

• Single-inventor patent. Unusual for a CIS pixel-layout/device patent, which typically lists a process-integration team. A one-name inventorship list makes the patent harder to tie to an internal R&D group and is mildly consistent with a narrow, individual contribution rather than a platform invention.
• No inventor-departure signal detectable. The prompt's constraint asks me to flag all inventors leaving the original assignee within 12 months of filing as a fire-sale precursor. I have no evidence either way — employment tenures are not public records and I could not verify Hwang's status at SK hynix after 2017. I explicitly decline to infer departure from the absence of later Hwang-filed SK hynix applications in my search results, which was not an exhaustive name search.
• The KR priority application (KR 10-2016-0128837) shares the same sole inventor, consistent with a single-employee invention disclosure filed through SK hynix's Korean IP pipeline.

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Original assignee

SK hynix Inc. — named as original assignee, and per the Google Patents legal events, still the assignee. No change of name has been recorded on this patent (the "SK Hynix Inc." vs. "SK hynix Inc." casing difference across sources is branding, not a recorded Change of Name conveyance).

• Primary line of business: semiconductor memory (DRAM, NAND, HBM). SK hynix is a publicly traded operating company (KRX: 000660), one of the two largest memory manufacturers globally.
• Does it ship a product embodying the claims? Yes, in the relevant product category. SK hynix maintains a CMOS image sensor (CIS) business line, and this patent is directed to precisely that — a back-illuminated stacked CIS pixel. SK hynix's CIS products are the natural embodiment. Caveat: I did not verify that any specific shipping SK hynix part reads on claims 1/10/15 (and per the earlier sections, the granted claim set was not in the supplied text), so "embodying the claims" is a category-level statement, not an element-by-element chart.
• Current status: Operating, solvent, no bankruptcy. No SK hynix Chapter 7/11 or Korean rehabilitation proceeding is relevant to this patent. (The prior litigation section already covers the SK hynix-side NPE suits — Vervain, MonolithIC 3D, USITC 337-TA-1492, Advanced Memory Technology — none of which names this patent.)

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Assignment timeline

Chronological list of every recorded assignment I could document. The record contains exactly one conveyance.

• Executed date not exposed / recorded 2017-04-07 — Reel/Frame: NOT AVAILABLE from the sources I could reach
  • Conveyance: Assignment (of assignors' interest) — recorded as a "reassignment" event; Google Patents renders the instrument type as "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)"
  • Assignor: Sun-ha Hwang (individual inventor)
  • Assignee: SK Hynix Inc.
  • Correspondent: Not available. Google Patents does not surface the recording correspondent, and I could not retrieve the assignment instrument itself. I therefore cannot name the attorney/firm of record, and per the task's own instruction I will not guess. Flag: an unavailable correspondent is a gap that matters for the repeat-player analysis in Signal 3 — it cannot be scored in either direction.
  • Context: Initial employment/prosecution assignment — inventor-to-employer transfer of rights, executed in connection with a company-filed application claiming Korean priority from the inventor's employer's home jurisdiction. This is the routine first link in essentially every corporate-owned patent, not a transfer of any economic consequence.

Note on the date. 2017-04-07 is simultaneously the application filing date and the date Google Patents displays for the reassignment event. I read this as the recording/metadata date surfaced by the events feed, not proof that the assignment instrument was executed that day. Under 35 U.S.C. § 261 the execution date governs; I could not obtain it. Do not treat the 2017-04-07 execution date as verified.

No post-issuance assignment of any kind appears — no sale, no security interest, no merger, no license recordation, no release, no correction, no change of name, and no terminal transfer to a defensive aggregator. Per the task's framing, that is itself the finding: the original assignee still owns the patent, and no third party has ever had a recorded interest in it.

Sources checked for the assignment record: the authoritative Google Patents full text and legal-events feed supplied in the prompt (source URL https://patents.google.com/patent/US9997556/en); repeated open web searches for the patent number, the application number 15/482,208, and the assignor name paired with assignment terminology (all returned zero assignment-document hits); and the Espacenet citing-documents record, which reproduces only bibliographic fields (inventor HWANG SUN-HA, applicant SK HYNIX INC, priority 2016-10-06, US2018102392 A1, US9997556 B2) and carries no assignment section.

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Timeline diagram

timeline
    title Ownership of US 9997556
    2016 : Korean priority filed at SK hynix
    2017 : US application filed
         : Assignment recorded to SK hynix
    2018 : US patent issued
    2037 : Anticipated expiration

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NPE / troll-pattern signals

Cross-reference note (no contradiction to report): the previously generated summary and litigation sections are mutually consistent on the key point — no litigation, no PTAB proceeding, no ITC investigation naming 9,997,556. My assignment findings do not contradict them; they explain that null result: a patent that has never been sold and is held by a solvent operating manufacturer has no NPE transfer link to generate a docket. I found no contradiction between the supplied patent text and the generated sections.

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Verdict

Insufficient data — using the rubric's own definition, because the chain consists only of the original assignment (inventor Hwang → SK Hynix Inc., recorded 2017-04-07; reel/frame not retrievable).

Justification: there is exactly one conveyance in the record, it is the ordinary inventor-to-employer prosecution assignment, and every one of the eight NPE signals scores "not present" or unevaluable. The chain never leaves SK hynix, an operating public memory/CIS manufacturer that ships products in the patent's own technology category — so this is the benign face of "insufficient data," not a hidden-shell-inference case. There is no evidence of any licensing-only entity, no asserter, no cascade, no pre-suit transfer, and no defensive-aggregator neutralization; the only real gap is my inability to pull reel/frame and correspondent from the USPTO Assignment Center UI.

To confirm and close the two open fields, query these directly (I could not reach them):

• USPTO Assignment Search / Assignment Center — https://assignmentcenter.uspto.gov/ (search "9997556" or application "15/482,208") and https://assignment.uspto.gov/patent/index.html — for the reel/frame and correspondent of record on the 2017 filing-date assignment.
• USPTO Patent Center for application 15/482,208 — https://patentcenter.uspto.gov/ — assignment tab, for the executed date of the assignment instrument.
• Google Patents legal events, https://patents.google.com/patent/US9997556/en — the feed corroborating the single 2017-04-07 reassignment.

Caveat, stated plainly: my assignment conclusions rest on the Google Patents events feed plus failed open-web searches. A null and an unretrievable field are not the same as a verified absence. If a chain-of-title opinion is required, the USPTO Assignment Center record must be pulled directly by reel/frame before this is relied upon.

I'll research the patent's citation records and prior art. Let me run several targeted searches.

Let me try to retrieve the actual citation list from the patent page and related sources.

I found the citation list. Let me verify and get details on each reference.

I hit the tool-call limit mid-research, so this report reflects what I was able to verify plus clearly-flagged gaps. Here is my analysis.

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Prior-Art Citation Report — US 9,997,556 B2 ("Image sensor," SK hynix Inc.)

1. Patent verification (confirmed)

Source: Justia patent record https://patents.justia.com/patent/9997556 (which supplied the "Referenced Cited" list below), corroborated by the Google Patents full text furnished in the prompt and by the Espacenet citing-documents record.

Refinement of an earlier flag: The previously generated Patent summary noted that the supplied text had no claims section and that claim numbering could not be stated. My Justia lookup partially resolves this: it confirms claims exist at least through claim 12, and reproduces verbatim the text of claim 11 (sub-array with 1×2 unit pixels; second gate of first pixel = selection gate, third gate of first pixel = drive gate, second gate of second pixel = reset gate, third gate of second pixel = dummy gate) and claim 12 (2×2 sub-array variant). Claim 11 depends from claim 10. This is a refinement, not a contradiction, of the earlier section.

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2. Complete patent-citation list retrieved for US 9,997,556

The "Referenced Cited" (i.e., prior-art references appearing on the face of the patent / cited during prosecution) consists of the following eight U.S. patent documents:

Limitations of this list — please read before relying on it:

• I retrieved the U.S. Patent Documents block only. The Justia record may also contain Foreign Patent Documents and Other References (NPL) blocks that I could not open before hitting the tool limit. The Google Patents "Prior art keywords" for this patent (gate, region, substrate, photoelectric conversion element) suggest the examiner's search was concentrated in the vertical-transfer-gate / stacked-CMOS field, but I cannot confirm whether non-U.S. documents were cited.
• I was not able to pull the full text (abstract/claims/figures) of each individual reference to perform a rigorous, element-by-element § 102 comparison. Titles and technical descriptions below are therefore given with explicit confidence markers; I have not fabricated any title or passage cite. Where I could not verify, I say so.

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3. § 102 legal framework applied

US 9,997,556 is an AIA-first-inventor-to-file case (filed 2017-04-07, priority 2016-10-06). The effective filing date is 2016-10-06. Therefore:

• § 102(a)(1) prior art = references publicly available before 2016-10-06.
• § 102(a)(2) prior art = U.S. patents/application publications that were effectively filed before 2016-10-06, even if published after that date.
• References both published and effectively filed after 2016-10-06 are not § 102 prior art at all (they can only be relevant to § 102(a)(2) if their underlying filing predates the critical date).

This date analysis matters enormously here because three of the eight cited documents are dated after the 2016-10-06 priority date. Anticipation requires that a single reference disclose every limitation of a claim; a § 102 challenge against this patent must therefore clear both the date gate and the "all elements in one reference" gate.

Limitation checklist for the § 102 mapping

From the confirmed claim structure (independent claim 1 and the parallel independent claims; dependent claims confirmed through at least claim 12), a reference must disclose:

• (L1) a pixel array of 2-D unit pixels;
• (L2) a substrate containing a photoelectric conversion element;
• (L3) a recess pattern at the center of the photoelectric conversion element (trench for a vertical transfer path);
• (L4) a first gate filling at least the recess (transfer gate);
• (L5) a second gate overlapping the photodiode and adjacent to the first gate in a first diagonal direction D1;
• (L6) a third gate overlapping the photodiode and adjacent in a second diagonal direction D2 intersecting D1 (the diagonal-corners layout is the signature feature);
• (L7) (4T independent claim) a fourth gate on the opposite side in D1;
• (L8) (crystallographic claim) monocrystalline substrate, (100) surface plane, and <100> channel-length direction for the transistor channels;
• (L9) dependent: FD confronting the third gate; first active region with recess at one end and FD at the other; second active region with bar regions along D1/D2 joined by coupling regions; P-well; pick-up region;
• (L10) dependent (claims 10–12): N×M sub-arrays with row/column-symmetric unit pixels; dummy gates for layout symmetry in 1×2 and 2×2 shared-pixel sub-arrays.

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4. Reference-by-reference analysis

Group A — Pre-2016 issued U.S. patents (§ 102(a)(1) art; comfortably before the critical date)

1. US 5,841,159 — 1998-11-24, "Lee"

• Status: § 102(a)(1) prior art (patented >18 years before the effective filing date).
• Description: I could not verify the title or abstract of this reference. Given its vintage and its position in this list, it is most consistent with a foundational solid-state/CCD or early CMOS image-sensor disclosure cited for background structure (pixel arrangement, photodiode/transfer structure). Confidence in any specific title: low — do not rely on a title I have not confirmed.
• § 102 anticipation potential: Very low. A 1998 document cannot disclose the diagonal (≈±45°) gate layout of L5/L6 or the <100>-channel-direction monocrystalline limitation of L8, and on the record available to me discloses no recess-pattern-at-photodiode-center structure. It cannot anticipate any independent claim (1, or the 4T/3T counterparts) or their dependents. Relevance is essentially § 103/general background.

2. US 6,040,593 — 2000-03-21, "Park"

• Status: § 102(a)(1) prior art.
• Description: Title/abstract not verified. The Google Patents record for this number surfaced in my searches as a page carrying a citation table that includes US 9,997,556 (i.e., it is part of this patent's citation neighborhood), and a related page snippet referenced "Image sensor having self-aligned silicide layer" (US 2008/0258188 A1, United Microelectronics) — but I could not confirm that the silicide title belongs to US 6,040,593 itself rather than to a citing document on the same page. Treat any title for this number as unconfirmed.
• § 102 potential: Very low, for the same date and subject-matter reasons as #1. No plausible anticipation of L5/L6/L8.

3. US 6,184,055 — 2001-02-06, "Yang"

• Status: § 102(a)(1) prior art.
• Description: Not verified. A Google Patents page for this number surfaced in searches with the phrase "CMOS image sensor with equivalent potential diode and method for fabricating the same" in the same result block, and the page's citation table again listed US 9,997,556. I cannot confirm that phrase is the title of US 6,184,055 rather than a neighboring document; flagging as uncertain.
• § 102 potential: Very low. At most it may be relevant to basic CMOS-pixel fabrication background. It cannot anticipate the diagonal layout or crystallographic claims.

4. US 8,748,945 — 2014-06-10, "Shin"

• Status: § 102(a)(1) prior art (issued before 2016-10-06).
• Description: Not verified at element level. This is the first "modern" reference in the list and is the most plausible candidate among Group A for disclosing a vertical transfer gate / recessed transfer structure in a stacked or BSI pixel — the technology family the patent's own background discusses. I could not open its text to confirm.
• § 102 potential: Low-to-moderate — the single most plausible § 102 candidate in Group A, but unconfirmed. If this reference discloses a recess/trench transfer gate at the photodiode with a surrounding transistor set, it would be the closest to L1–L4. However, on the record before me I have no basis to find it discloses the diagonal D1/D2 corner arrangement (L5/L6) or the (100)/<100> orientation limitation (L8), which are the features the specification itself frames as the point of novelty ("the crystallographic direction … is the <100> direction … charges may transfer quickly"). A § 102 rejection on independent claim 1 via this reference would require confirming L5 and L6, which I could not do. Verdict: not established as anticipatory on current evidence.

5. US 9,054,003 — 2015-06-09, "Ahn et al."

• Status: § 102(a)(1) prior art.
• Description: Not verified at element level; likely an image-sensor pixel/stack structure from a large Korean-fab portfolio (the "et al." attribution suggests a corporate filing).
• § 102 potential: Low-to-moderate, unconfirmed, for the same reasons as #4. Nothing in the retrieved material shows disclosure of the diagonal gate layout or the crystallographic orientation limitation.

Group B — Post-priority U.S. application publications (date-gated)

These three carry publication dates after the 2016-10-06 effective filing date and thus are not § 102(a)(1) art. They can only be § 102(a)(2) art if their underlying U.S. applications were effectively filed before 2016-10-06 — a fact I could not verify for any of them (I did not reach their bibliographic "filed/priority" data).

6. US 2017/0018591 A1 — published 2017-01-19, "Yamaguchi"

• § 102 status: Publication is ~3.5 months after the critical date. Qualifies only under § 102(a)(2), and only if effectively filed before 2016-10-06. Because it published so soon after the priority date, an earlier effective filing date is plausible for a JP-origin (Yamaguchi) filing — but this is unverified.
• § 102 potential: Indeterminate. Docket-level note: if it is § 102(a)(2) art, note the limited ground it can support (it cannot be combined into a § 103 attack as § 102(a)(2) art; see § 103(c)(2)/(c)(3) carve-outs for commonly-owned/§ 102(a)(2) art).

7. US 2017/0194372 A1 — published 2017-07-06, "Ha"

• § 102 status: Post-dates the critical date by 9 months. § 102(a)(2)-eligible only if effectively filed before 2016-10-06. Unverified. The surname "Ha" is consistent with the SK hynix image-sensor inventor pool (cf. the caption text "US20170194372 … Ha / Kwag" appears in the same citation neighborhood), which raises a possible common-ownership question relevant to § 103 but not to § 102.
• § 102 potential: Indeterminate.

8. US 2017/0330907 A1 — published 2017-11-16, "Kwag"

• § 102 status: Post-dates the critical date by ~13 months. § 102(a)(2)-eligible only if effectively filed before 2016-10-06. Unverified.
• § 102 potential: Indeterminate.

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5. References that are not prior art (forward citations — listed only to prevent confusion)

Google Patents shows US 9,997,556 B2 appearing in the citation tables of later documents, including its own pre-grant publication US 2018/0102392 A1 (same application — self-citation, never prior art) and various later SK hynix / TSMC / Omnivision image-sensor patents (e.g., US 10,432,831; US 10,218,927; US 10,032,807; US 11,412,166; US 11,538,837; US 11,004,880). These are "cited by" citations flowing out of this patent's family into later art, not prior art against it. Do not chart them as § 102 references.

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6. Bottom line

1. The complete on-face prior-art list I could verify is the eight U.S. patent documents in § 2 — five pre-2016 issued patents (US 5,841,159; 6,040,593; 6,184,055; 8,748,945; 9,054,003) and three post-priority publications (US 2017/0018591; 2017/0194372; 2017/0330907). Foreign/NPL citations, if any, were not confirmed.
2. No reference on this list can be shown, on the evidence I retrieved, to anticipate any claim under § 102. The three oldest references are chronologically and technically remote from the claimed diagonal-corner layout and the (100)/<100> crystallographic limitation. The two 2014–2015 references are the best § 102 candidates but are unconfirmed as to the L5/L6 diagonal-gate and L8 orientation limitations.
3. Three of the eight references (US 2017/0018591, 2017/0194372, 2017/0330907) are date-gated: they are not § 102(a)(1) art and can only be § 102(a)(2) art if their effective filing dates precede 2016-10-06 — which I could not verify.
4. The patent issued on 2018-06-12, roughly 14 months after filing, with the examiner (Thao P Le) citing this short list — consistent with the cited documents having been used for context and the claims being allowed on the diagonal active-region layout + recessed transfer gate at the photodiode center + <100> channel orientation combination.
5. Strongest practical attack vector (if the goal is validity challenge): not § 102 anticipation by any single cited reference, but a § 103 combination — e.g., a vertical-transfer-gate/recessed-gate reference (closest: US 8,748,945 or US 9,054,003) in view of a reference teaching 45°-rotated active-region/crystallographic-orientation engineering. I did not locate such a second reference in the retrieved citation set, because I could not open the full citation records.

What I could not do (explicit gaps)

• Open the full text/abstract/claims of individual references 1–8 to confirm titles, inventors' full names, and the specific passages relied upon by the examiner (e.g., the Form 892/1449 "Examiner's Statement" or the "relevant passages" column).
• Retrieve any Foreign Patent Documents or Non-Patent Literature citations on the face of the patent.
• Verify the effective filing dates of the three post-priority publications.
• Obtain a hard confirmation of claim count and the exact wording of independent claims 1 and its 4T/crystallographic counterparts (the supplied full text lacks a claims section; Justia gave me claims 11–12 only).

Recommended confirmations: pull the granted claims and the complete "References Cited"/IDS from USPTO PatentCenter for application 15/482,208, and the corresponding Google Patents / Espacenet citation tables, to fill the gaps above before any validity opinion is finalized. I can complete that targeted follow-up if you re-run me.

I'll pull the prior-art record for this patent (citations, similar documents, cited-by) before running the §103 analysis.

Let me try to retrieve the actual front-page "References Cited" and "Similar Documents" for this patent.

Let me try Justia and FreePatentsOnline, which reproduce the front-page references.

Scope note before the analysis. You asked me to work from "the Prior Art section of this page." The authoritative full text supplied in the prompt was truncated mid‑description ("…the wel") and contains no claims section and no front‑page "References Cited" list. So I could not read the patent's own prior‑art citations off the page. Two of my retrieval attempts (Justia, FPO front pages) were cut off by the step limit. What follows therefore rests on (a) the patent text itself, (b) the "Similar Documents" / "Citations" records I did retrieve live from Google Patents pages that link to US9997556, and (c) well‑established literature. Every prior‑art date I have not personally verified is flagged [VERIFY]. Nothing below should be filed before those dates are checked in PatentCenter/Espacenet INPADOC.

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Obviousness Analysis — US 9,997,556 B2 ("Image sensor," SK hynix Inc.)

1. Governing framework

• Statute: 35 U.S.C. § 103 (AIA). The application was filed 2017‑04‑07 with a KR priority of 2016‑10‑06, both after 2013‑03‑16, so AIA §§ 102/103 apply with no pre‑AIA transition issue.
• Standard: KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) — a combination of known elements is obvious where it yields predictable results and there was an apparent reason (design incentive, market forces, known technique applied to a known device "ready for improvement"). See also MPEP § 2143 rationales.
• Critical framing: three of the four conceptual ingredients of this patent were, as of October 2016, each independently admitted or well‑documented as known; the fourth (diagonal layout) is a geometric consequence of the third. That is a favorable posture for a § 103 rejection.

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2. Claim scope actually before the examiner (reconstructed with a flag)

⚠️ Flag / contradiction with the earlier section. The previously generated summary states plainly that the supplied text lacks a claims section and that the three "In accordance with an embodiment…" Summary paragraphs were used as a proxy for the independent claims. That remains true. My analysis inherits the same limitation: I am analyzing the disclosed Summary paragraphs, not verified claim language. Claim numbers, dependency structure, and the exact wording of the granted claims must be confirmed before this analysis is used for any purpose requiring the actual claims.

Using those three paragraphs, the independent claims reduce to:

The single most important observation for this analysis: Claim C contains no recess pattern, no diagonal gates, no stacked architecture, and no floating‑diffusion geometry. It is a 4T CMOS image sensor — an architecture in commercial mass production since the late 1990s — plus a substrate orientation selection. Claim C is by far the most exposed of the three.

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3. Person of ordinary skill in the art (POSITA)

A POSITA here would be an M.S.‑level (or B.S. + 3–5 years) semiconductor device/process engineer working on CIS pixel design, familiar with: (i) 3T/4T and shared‑pixel APS circuits; (ii) back‑side‑illuminated and stacked/3D image sensors; (iii) trench/recessed and vertical transfer gates; (iv) crystal‑orientation‑dependent carrier mobility and standard (100) wafer flats (<110>); and (v) layout/OPC practices including dummy gates. This is a routine combination‑arts field, which lowers the motivation threshold under KSR.

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4. Evidentiary basis — the prior art I could actually identify

Documents retrieved from live Google Patents / Espacenet records tied to US9997556, plus standard literature:

P1 — US 2007/0131987 A1 (Kim; Dongbu Electronics), publ. 2007‑06‑14, filed 2006‑12‑08, KR 10‑2005‑0120643 (2005‑12‑09). "Vertical image sensor and method for manufacturing the same." Retrieved: https://patentimages.storage.googleapis.com/45/0e/d3/78c05dd586d318/US20070131987A1.pdf. § 102(a)(1) art. Discloses a trench‑type transfer gate ("FIRST TRENCH TYPE TRANSFER GATE," "SECOND TRENCH TYPE TRANSFER GATE") in a stacked‑photodiode pixel, with the trench bottom below the uppermost photodiode region, and expressly shows an active pixel sensor circuit with reset transistor M1, source‑follower M2, and row‑select M3 — i.e., a 3T read‑out. This is a remarkably close structural reference for the recess‑plus‑3T‑readout core.

P2 — Kurino et al., "Intelligent image sensor chip with three dimensional structure," IEDM 1999, pp. 879–882 (Dec. 5, 1999), DOI 10.1109/IEDM.1999.824289. Retrieved as an "X" document in the search report of WO 2012/003041 A1 (https://patentimages.storage.googleapis.com/32/1d/a8/9274268acdd044/WO2012003041A1.pdf). Printed publication art. The canonical teaching of vertically stacking a photodiode array with the pixel‑transistor/processing layer — the 100 % fill‑factor stacked architecture this patent's background describes as needed.

P3 — US 2009/0242950 A1 (McCarten et al.), publ. 2009‑10‑01. Cited as an X document (paras. [0022]–[0029], Figs. 2–4) against claims 1–3, 6–9, 12–15, 18, 19 of the same stacked‑image‑sensor PCT. [VERIFY content] — I have only the search‑report characterization, not the document itself.

P4 — US 2017/0148833 A1 (Sony), priority 2011‑07‑12, publ. 2017‑05‑25. "Solid‑state imaging device, manufacturing method, and electronic device." Appears in the citation record of US11412166 alongside US9997556 (https://patents.google.com/patent/US11412166). Even though it published after the 2016‑10‑06 priority date, its 2011 effective filing date makes it available under § 102(a)(2) if it names another inventor. [VERIFY effective filing date and named inventors.]

P5 — US 2016/0020237 A1 (Sony), priority 2013‑03‑14, publ. 2016‑01‑21. "Solid state image sensor, manufacturing method thereof, and electronic device." § 102(a)(1) art by publication date. [VERIFY whether it discloses a recessed/vertical transfer gate.]

P6 — US 9,659,987 B2 (TSMC), "Approach for reducing pixel pitch using vertical transfer gates and implant isolation regions," granted 2017‑05‑23. In the citation record of US11412166. § 102(a)(2) art only if effectively filed on or before 2016‑10‑06 — [VERIFY]. The title alone is directly on point for the recess/vertical‑transfer‑gate concept.

P7 — US 9,876,042 B2, "Image sensor having vertical transfer gate and method for fabricating the same." Google Patents lists US9997556 in US9876042's "Similar Documents" cluster (retrieved: https://patents.google.com/patent/US9876042). [VERIFY assignee and effective filing date.] Subject‑matter proximity is high (vertical transfer gate, epitaxial body, charge‑trapping region at the trench side/top surfaces).

P8 — Mobility‑orientation literature and the patent's own admission. Takagi et al., "On the universality of inversion‑layer mobility in Si MOSFETs" (IEEE TED 1994) and the subband‑engineering work (2003); Sze, Physics of Semiconductor Devices (surface‑orientation and current‑flow‑direction dependence of inversion‑layer mobility). Critically, the patent itself concedes the point: "The <100> direction is known having a higher carrier mobility than other crystallographic directions including the <110> direction." That sentence is an admission that the result‑effective variable was known in the art, which the examiner may cite against the applicant.

Non‑prior art (cannot be used; listed so it is not mistakenly relied on): US 9,818,788 B2 (TSMC; filed 2016‑11‑08 — after the 2016‑10‑06 priority date, so not § 102(a)(1) or (a)(2) art) https://patentimages.storage.googleapis.com/20/b8/75/916fcf7544b111/US9818788.pdf; US 2018/0294305 A1 (Janssens/ON Semi; filed 2017‑04‑05) https://patentimages.storage.googleapis.com/2c/2c/7f/71f26a263decf4/US20180294305A1.pdf; US 10,121,806 B2 (OmniVision). These are useful only as evidence of what was routine engineering in the same period — admissible context, not § 103 art.

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5. The invention decomposed into known elements plus one geometric consequence

5.1 Why E4 collapses into E6 — the decisive technical point

The specification states that conventional row/column‑oriented active regions produce a channel‑length crystallographic direction of <110>, and that the diagonal (D1/D2) orientation produces <100>:

"…the pixel transistors … may perform a high‑speed operation whose charge transfer rate is improved more than the case when the channel length direction of the channel is the row direction RD or the column direction CD, because the crystallographic direction of the substrate 200 corresponding thereto is the <110> direction."

On a standard (100) silicon wafer the wafer flat is the <110> direction; the <100> in‑plane directions lie at 45° to the flat. Therefore:

"Active regions extended in the diagonal direction D1/D2" ≡ "channel length aligned to <100> on a (100) wafer."

The diagonal layout is not an independent invention — it is the layout that necessarily results when a designer, working on a standard (100) wafer, chooses the <100> channel direction the patent itself says is known to have higher mobility. Conversely, a POSITA who wanted a <100> channel and kept the conventional row/column‑axis layout would have to specify a wafer cut 45° off‑flat, an exotic and expensive choice; rotating the layout instead is the obvious, cost‑free alternative. This equivalence is the backbone of every ground below.

⚠️ Internal inconsistency to note (and an enablement risk for the patent owner): the sentence after "the horizontal direction, which is the crystallographic direction corresponding to a row direction RD and a column direction CD…" is garbled in every copy of the text I have (the predicate is missing). Read literally, the paragraph as transcribed appears to assign <100> to both the row/column and the diagonal directions — physically impossible on a (100) plane, where in‑plane <100> directions are mutually perpendicular. The intended reading is confirmed by the later sentence assigning <110> to row/column. This is a transcription/specification defect, not something to rely on, but it is worth flagging because a literal reading is self‑contradictory and would support a § 112(a) challenge.

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6. Grounds of rejection

Ground 1 — Claim A (3T + diagonal gates) obvious over P1 in view of P2 and P8

• P1 discloses a vertical/trench‑type transfer gate whose trench is etched from the front surface down past the photodiode interface (E2), together with a 3T active‑pixel read‑out (reset M1, source‑follower M2, row‑select M3).
• P2 (and P3) teaches stacking the photodiode array relative to the transistor layer to maximize fill factor (E1) — the stated purpose in the patent's own Background.
• P8 teaches that inversion‑layer carrier mobility is a function of surface orientation and current‑flow direction, and that <100> on (100) is favored (E6) — a point the specification concedes is "known."
• The combination: placing the trench‑type transfer gate of P1 in the stacked architecture of P2, and arranging the remaining read‑out gates around it. Because the PD now underlies the transistor layer, the trench/transfer gate must sit at the PD center (E5) and the FD must be pushed to the periphery; the remaining gates have nowhere to go but the corners of the pixel, which are the diagonal directions (E4).
• Motivation: (i) fill factor / pixel shrink — an explicit market pressure acknowledged in the patent's Background; (ii) transfer efficiency through a trench gate; (iii) mobility improvement via the known <100> orientation. Each is a separate, independent, known reason to make the change, and the combination yields nothing more than the predictable sum of those benefits. KSR, 550 U.S. at 416–17 ("if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious").

Ground 2 — Claim B (4T + fourth gate on the opposite D1 side) obvious over Ground 1 in view of a 4T/shared‑pixel reference

• Adding a fourth transistor to a 3T pixel (the select transistor, or the transfer/reset pair in a shared arrangement) is the single most standard evolution in CIS design and was ubiquitous long before 2016 (and is recited in the patent's own second embodiment).
• Once four gates must be placed, placing the fourth on the opposite side of the first gate along D1 is dictated by the same symmetry/area constraints that produced the first three placements. It is a duplication of parts / symmetric layout rationale under MPEP § 2143 — a recognized KSR rationale.
• The claim adds no new functional result; the "fourth gate" performs the same role as its counterpart.

Ground 3 — Claim C (crystallography‑only) obvious as an obvious design choice over any 4T CIS reference in view of P8

This is the strongest ground and the one I would lead with.

• Every element but one is a textbook 4T CMOS image sensor: PD, transfer transistor to a floating diffusion, reset transistor, source‑follower drive transistor with gate tied to the FD, and a select transistor. Such pixels are in every CIS datasheet and textbook from the 1990s onward.

• The remaining element — "monocrystalline substrate with a (100) surface and <100> channel‑length direction for all four transistor channels" — is:

  1. a known result‑effective variable (orientation‑dependent mobility, P8);
  2. conceded in the specification itself to be known ("The <100> direction is known having a higher carrier mobility than other crystallographic directions including the <110> direction"); and
  3. applied uniformly to all four transistors, with no teaching of any criticality, threshold, or unexpected interaction between the orientation and the recess/diagonal features.

• Under In re Applied Materials and In re Kao, optimizing a result‑effective variable disclosed in the prior art is obvious absent evidence that the optimized range is critical (i.e., produces a difference in kind, not degree). The patent supplies no comparative data at all for the mobility claim — only an assertion.

• (100) is the default commercial CMOS substrate, and <110>‑flat (100) wafers are the industry norm. No designer "selects" (100); they inherit it. The only affirmative act is choosing the channel direction, which is free and is made for the very reason the specification recites.

• Claim C also lacks the recess, the stacked architecture, and the diagonal limitation. Its only conceivable point of novelty relative to a plain 4T pixel is the orientation of the channel — a result‑effective variable with a known benefit. A § 103 rejection here should be straightforward, possibly even a § 102 rejection if a reference explicitly or inherently discloses channel‑length alignment to <100> on a (100) substrate for all pixel transistors.

Ground 4 — Dependent claims

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7. Motivation to combine — the KSR rationales, consolidated

1. Design incentive / market pressure (explicitly conceded). The Background states the goal is more pixels per area and that this degrades pixel characteristics — the very problem the claims solve. Objective evidence of the problem in the specification itself is a strong motivation source.
2. Known technique applied to a known device ready for improvement. Trench/vertical transfer gates (P1, P6, P7) applied to a stacked image sensor (P2, P3) already recognized as the path to high fill factor.
3. Known, admitted result‑effective variable. Crystal orientation and channel direction (P8 + the specification's admission). No criticality shown.
4. Duplication/symmetry of parts. The fourth gate (Claim B) and the dummy gates.
5. Predictable results. Every claimed feature has an independently known benefit (fill factor, transfer efficiency, mobility, yield uniformity), and the patent claims no synergy or emergent behavior among them. Where a claimed invention is "the product of … a finite number of identified, predictable solutions," it is obvious. KSR, 550 U.S. at 421.

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8. Anticipated rebuttals from the patent owner, and responses

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9. Where this analysis is weak (be honest about it)

1. I could not retrieve the examiner's actual reference list for US9997556. My grounds are built from Google Patents "Similar Documents"/"Citations" clusters and a 2007 trench‑transfer‑gate publication, not from the record of art actually considered. The art‑of‑record may be narrower or different.
2. P6 (US 9,659,987) and P7 (US 9,876,042) need effective filing dates before they can be used as § 102(a)(2) art. If either was effectively filed after 2016‑10‑06, it drops out.
3. P3 and P5 need content verification. I have only titles/search‑report characterizations, not the paragraphs that would actually map to the claimed recess.
4. The claims themselves are unverified (see § 2). If the granted claims are meaningfully narrower than the Summary paragraphs — e.g., if they recite a specific recess‑to‑PD‑center relationship, a specific angular range, or a particular overlap between the gate and the FD — the analysis above still applies, but the mapping must be redone against real claim language.
5. The "inherence" shortcut for the diagonal limitation is arguable, not airtight. The 45° relationship between <100> and the (100) wafer flat depends on process convention (flat orientation), not physics; a theoretical wafer could be cut with <100> flats. Frame this as obviousness (layout rotation is the cheap route to a <100> channel), not as inherency.
6. No conclusion on validity. This is an infringement‑side/validity‑side screening analysis, not a legal opinion, and it is prepared without the file history, the claims, or the actual art of record.

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10. Recommended verification steps before relying on any of this

1. Pull the granted claims and the "References Cited" front page for US 9,997,556 from USPTO PatentCenter / Patent Public Search (application 15/482,208) or the granted‑patent PDF.
2. Pull the file wrapper (Office actions, any § 103 rejections, any applicant admissions/arguments) — an applicant admission about <100> mobility in the remarks would be highly probative.
3. Verify effective filing dates for US 9,659,987, US 9,876,042, US 2017/0148833, and US 9,818,788 (the last is expected to be post‑priority and unusable).
4. Confirm the disclosure content of US 2009/0242950 and US 2016/0020237 for a recessed/vertical transfer gate and its position relative to the photodiode.
5. Confirm the orientation convention assumed by the specification's own statements (row/column = <110>, diagonal = <100>) — this is the load‑bearing assumption in § 5.1.