US 9786510

Here is a concise summary of US patent 9786510:

US Patent 9786510 Summary

• Title: Fin-shaped structure and manufacturing method thereof
• Current Assignee: Marlin Semiconductor Ltd
• Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
• Filing Date: 2014-10-13
• Issue Date: 2017-10-10
• Abstract: The patent describes a fin-shaped structure that includes a substrate with a first fin-shaped structure in one area and a second fin-shaped structure in another area, where the second structure has a ladder-shaped cross-sectional profile. The invention also covers two methods for manufacturing this structure. One method involves modifying an external surface of the top of the second fin-shaped structure to form a modified part, then removing this modified part using a highly selective removal process to create the ladder-shaped profile.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a specific fin-shaped structure on a semiconductor substrate. It involves two types of fin arrangements: "first fin-shaped structures" and "second fin-shaped structures," each comprising at least two individual fins (first/second fin and third/fourth fin, respectively). The key distinction is in the spacing: the distance between the top corners of adjacent fins in the "first fin-shaped structures" is less than the distance between the top corners of adjacent fins in the "second fin-shaped structures." Crucially, the distance between the lower parts of adjacent fins is the same for both the first and second fin-shaped structures. This configuration means the second fin-shaped structures effectively have a wider top portion or a "ladder-shaped" profile compared to the first fin-shaped structures, while their bases maintain the same spacing. The top corners mentioned are directly opposite each other.

USPTO and CAFC 2026 Dockets:

A search for US patent 9786510 in the USPTO database indicates the patent is "Active" and expires on 2035-01-24. The patent information also notes that the "Family has litigation" and specifically mentions a "PTAB case IPR2025-01484 filed (Not Instituted - Procedural)".

As of April 26, 2026, a direct search of CAFC 2026 dockets for patent number 9786510 did not yield any specific case filings for 2026. While an Inter Partes Review (IPR) case (IPR2025-01484) was filed at the Patent Trial and Appeal Board (PTAB) in 2025, it was "Not Instituted - Procedural." This status suggests the case did not proceed to a full review, and therefore, it is unlikely to have led to an appeal at the CAFC in 2026.

As of April 26, 2026, there is one known litigation involving US patent 9786510:

• Case Number: IPR2025-01484.
• Filing Date: August 29, 2025.
• Plaintiff(s): Taiwan Semiconductor Manufacturing Company Ltd.
• Defendant(s): [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) (as the current assignee of US9786510B2).
• Jurisdiction: United States Patent and Trademark Office (USPTO), Patent Trial and Appeal Board (PTAB).
• Outcome/Current Status: Institution of inter partes review was denied. The petitioner, Taiwan Semiconductor Manufacturing Company Ltd., failed to show a reasonable likelihood of prevailing with respect to at least one of the challenged claims. This decision was issued on January 9, 2026.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 9,786,510, which resulted in a discretionary denial of institution. This means the patent claims were not substantively challenged and remain in force. For a defendant, this indicates that the patent has not been narrowed or invalidated by this PTAB proceeding, and any defensive posture would need to consider the full scope of the claims.

IPR2025-01484 — Taiwan Semiconductor Manufacturing Company Ltd. v. United Microelectronics Corp.

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Discretionary Denial - The PTAB declined to institute review.
• Judge panel: Not publicly available at this stage of the proceeding, as institution was denied.
• Petition grounds: Information regarding specific claims, prior art, and statutory bases (§ 102 / § 103 / § 112) is not publicly detailed for discretionary denials in the provided information.
• Institution decision: Denied (date: 2026-04-14). The status "Discretionary Denial" indicates that the PTAB exercised its discretion to deny institution, rather than making a decision on the merits of the patentability challenge.
• Final Written Decision (if issued): Not issued, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: Not applicable, as institution was denied and no Final Written Decision was issued.
• Defensive value: This proceeding does not impact the patentability of the claims of US 9,786,510. The patent owner prevailed on the procedural ground of discretionary denial, meaning the claims were not substantively reviewed. An IPR-based defense will need to be prepared from scratch, potentially raising different arguments or prior art, or seeking a different outcome at institution.

Strategic summary

All claims of US Patent 9,786,510 remain untested and sustained by virtue of the discretionary denial of institution in IPR2025-01484. The patent has not been narrowed or invalidated through this PTAB proceeding.

Regarding estoppel, since institution was denied on discretionary grounds, the petitioner (Taiwan Semiconductor Manufacturing Company Ltd.) may not be estopped from raising the same or similar grounds in future proceedings, depending on the specific reasoning for the discretionary denial and whether the merits were genuinely considered. However, the exact estoppel landscape would depend on the detailed reasoning provided in the institution denial decision, which is not fully available in the provided text. For a defendant currently being asserted against, all prior-art grounds remain potentially available.

There is no pattern of multiple IPRs on this patent or aggressive PTAB appeals by the patent owner based on the information provided. The petitioner in the single proceeding, Taiwan Semiconductor Manufacturing Company Ltd., is a known entity in the semiconductor industry and is not typically a defensive aggregator like Unified Patents.

Recommended next steps

Given the discretionary denial in IPR2025-01484, any defendant facing assertion of US 9,786,510 should be aware that the claims remain fully intact. A copy of the institution denial decision for IPR2025-01484 should be obtained to understand the precise reasons for the discretionary denial, as this could inform future PTAB strategy. The USPTO PTAB E2E system would provide the full decision. If considering a new IPR, a defendant would need to carefully assess whether to submit a petition with different grounds or arguments, addressing the potential concerns that led to the discretionary denial.

Inventors

• Wen-Jiun Shen (United Microelectronics Corp)
• Ssu-I Fu (United Microelectronics Corp)
• Yen-Liang Wu (United Microelectronics Corp)
• Chia-Jong Liu (United Microelectronics Corp)
• Yu-Hsiang Hung (United Microelectronics Corp)
• Chung-Fu Chang (United Microelectronics Corp)
• Man-Ling Lu (United Microelectronics Corp)
• Yi-Wei Chen (United Microelectronics Corp)

There are no unusual patterns indicating all inventors departing the original assignee within 12 months of filing.

Original assignee

The original assignee named on the issued patent is United Microelectronics Corp (UMC). UMC is a Taiwanese semiconductor foundry company that manufactures integrated circuits for other companies. They are an operating company and are currently active.

Assignment timeline

• 2014-10-13 (executed) / recorded 2014-10-13 — Reel 033934/0391

  • Conveyance: Assignment
  • Assignor: CHEN, YI-WEI; FU, SSU-I; HUNG, YU-HSIANG; LIU, CHIA-JONG; LU, MAN-LING; SHEN, WEN-JIUN; WU, YEN-LIANG; CHANG, CHUNG-FU (inventors)
  • Assignee: UNITED MICROELECTRONICS CORP.
  • Correspondent: Not specified in the provided data.
  • Context: Internal transfer from inventors to original corporate assignee.

• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292

  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED
  • Correspondent: J. C. PATENTS, 1F, NO. 40, SEC. 1, MINSHENG E. RD., TAIPEI, TAIWAN, (R.O.C.)
  • Context: Transfer to a new assignee.

Timeline diagram

timeline
    title Ownership of US 9786510
    2014 : Assigned to United Microelectronics Corp
    2017 : Issued
    2021 : Assigned to Marlin Semiconductor Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — present. The assignment from United Microelectronics Corporation to MARLIN SEMICONDUCTOR LIMITED (executed 2021-06-18 / recorded 2021-07-26, Reel 056991/0292) shows a transfer from an operating company to an entity with "Semiconductor Limited" in its name. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) is listed as the current assignee on Google Patents, and the Darts-IP litigation link suggests it is involved in global patent litigation, which is a common characteristic of licensing-only entities.
2. Known asserter in the chain — unclear. Marlin Semiconductor Ltd is not explicitly on the common public NPE lists (Acacia, Marathon, etc.). However, its name structure and the presence of litigation (as indicated by Google Patents) warrant further investigation.
3. Repeat correspondent across the chain — not present. The first assignment from inventors does not specify a correspondent. The correspondent for the second assignment is "J. C. PATENTS, 1F, NO. 40, SEC. 1, MINSHENG E. RD., TAIPEI, TAIWAN, (R.O.C.)" (Reel 056991/0292). Without additional information on other patents filed by this correspondent, it is not possible to determine if they are a repeat player.
4. Cascading transfers — not present. There is only one transfer recorded since the original assignment from inventors.
5. Pre-litigation transfer — unclear. The patent has litigation filed (PTAB case IPR2025-01484, and "First worldwide family litigation filed" by Darts-ip). However, the specific dates of the first infringement suit naming this patent are not provided, making it unclear if the assignment date (2021-06-18) falls within 6 months prior to any such suit.
6. Bankruptcy fire-sale — not present. There is no indication of United Microelectronics Corp filing for bankruptcy.
7. Privateering — unclear. While the patent transferred from an operating company (UMC) to what appears to be a licensing entity (Marlin Semiconductor Ltd), there is no explicit evidence (e.g., SEC filings or specific reports) to confirm if Marlin Semiconductor Ltd is asserting on UMC's behalf against competitors.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator.

Verdict

NPE — moderate confidence. The transfer from United Microelectronics Corp, a known operating company, to Marlin Semiconductor Limited (Reel 056991/0292) is a strong signal of a shell-entity transfer, especially given the "Limited" suffix and the indication of active litigation provided by Google Patents. While Marlin Semiconductor Ltd is not explicitly on widely published NPE lists, the transaction structure aligns with NPE behavior. Further, the existence of litigation activity (as noted in the Google Patents legal events section) supports the notion of assertion.

Verification: https://assignmentcenter.uspto.gov/

The USPTO provides a Patent Public Search tool to search for patents and patent application publications, which is the appropriate resource for identifying prior art.

Upon reviewing US Patent 9,786,510, the following prior art references are identified from the "Cited By" and "Citations" sections of the patent document itself. Please note that a full anticipation analysis under 35 U.S.C. § 102 would require a detailed claim-by-claim comparison and expert opinion, which is beyond the scope of this response. The descriptions below offer a brief overview of the cited art's relevance to the general subject matter of US9786510.

Cited Prior Art for US9786510:

1. US20100148234A1

   • Full Citation: US20100148234A1, "Subresolution silicon features and methods for forming the same"
   • Publication Date: June 17, 2010
   • Brief Description: This patent application describes methods for forming subresolution silicon features, which can include fins or similar structures, by using a hard mask layer and etching processes. It focuses on achieving fine feature sizes beyond the lithographic limit.
   • Potential Anticipation (General): This could potentially anticipate aspects of claims related to the formation of fin-shaped structures, particularly the initial steps of defining and etching fins in a semiconductor substrate. Given that US9786510 discusses forming first and second fin-shaped structures and various etching processes, general methods for fin formation are highly relevant.

2. US20080157225A1

   • Full Citation: US20080157225A1, "SRAM and logic transistors with variable height multi-gate transistor architecture"
   • Publication Date: July 3, 2008
   • Brief Description: This patent application discloses semiconductor devices with multi-gate transistor architectures, such as FinFETs, where fins may have variable heights to achieve different threshold voltages for various circuit blocks (e.g., SRAM and logic).
   • Potential Anticipation (General): This reference is highly relevant to US9786510's objective of forming fin-shaped structures of "different heights and critical dimensions" in "different areas" to meet "specific electrical demands" like high voltage threshold (HVT) and low voltage threshold (LVT) areas. Claims 5 and 6 of US9786510, which relate to different fin heights protruding from the isolation structure or substrate, could be particularly implicated.

3. US8373238B2

   • Full Citation: US8373238B2, "FinFETs with multiple Fin heights"
   • Publication Date: February 12, 2013
   • Brief Description: This patent describes FinFET devices having multiple fin heights. It details methods to achieve these varying heights, often involving selective etching processes and different masking steps, to optimize device performance for different circuit requirements.
   • Potential Anticipation (General): Similar to US20080157225A1, this patent directly addresses the concept of creating FinFETs with varying fin heights. The methods described could anticipate aspects of US9786510's processes for forming fin-shaped structures of different heights, and thus impact claims related to achieving such variations. Claims 5 and 6 of US9786510 are again particularly relevant.

4. US20130149826A1

   • Full Citation: US20130149826A1, "FinFETs with Multiple Fin Heights"
   • Publication Date: June 13, 2013
   • Brief Description: This is a patent application related to US8373238B2, disclosing FinFETs with multiple fin heights and methods for their fabrication. It aims to optimize FinFET performance by allowing for different fin heights across a single chip.
   • Potential Anticipation (General): As a related application, its relevance and potential anticipation are similar to US8373238B2, focusing on the formation of FinFETs with varying fin heights to meet specific electrical requirements, which is a core aspect of US9786510.

5. US20120313169A1

   • Full Citation: US20120313169A1, "Fin-FET device and method and integrated circuits using such"
   • Publication Date: December 13, 2012
   • Brief Description: This patent application describes FinFET devices and their fabrication methods, including integrated circuits utilizing such devices. It generally covers the structure and manufacturing of FinFETs.
   • Potential Anticipation (General): This reference provides general background on FinFET devices and their manufacturing. Depending on the specific details of its claims, it could broadly anticipate elements of the FinFET structure or basic manufacturing steps described in US9786510.

6. US8669167B1

   • Full Citation: US8669167B1, "Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices"
   • Publication Date: March 11, 2014
   • Brief Description: This patent focuses on techniques for engineering metal gates in FinFET devices to achieve multiple threshold voltages. While not directly about fin shape, the context is creating different electrical characteristics in FinFETs.
   • Potential Anticipation (General): While not directly related to the "ladder-shaped cross-sectional profile" of the fins in US9786510, this patent addresses the broader problem of achieving varied electrical demands in different areas of a chip using FinFETs, which is an explicit goal of US9786510. If the methods described in US9786510 are used in conjunction with metal gate work function engineering, there could be an indirect relevance.

7. US8669615B1

   • Full Citation: US8669615B1, "Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices"
   • Publication Date: March 11, 2014
   • Brief Description: This patent is a continuation or related to US8669167B1, also discussing metal gate workfunction engineering for multiple threshold voltage FinFETs.
   • Potential Anticipation (General): Similar to US8669167B1, its relevance lies in the context of achieving varied electrical characteristics in different areas of a chip using FinFETs, which is a stated advantage of the fin structures created by US9786510.

8. US20140191323A1

   • Full Citation: US20140191323A1, "Method of forming finfet of variable channel width"
   • Publication Date: July 10, 2014
   • Brief Description: This patent application describes a method for forming FinFETs with variable channel widths. The variation in channel width can influence the electrical characteristics of the transistor.
   • Potential Anticipation (General): US9786510 explicitly mentions forming "fin-shaped structures of different heights and critical dimensions (CD)" and that the "width w1 of the top part of each of the first fin-shaped structures... is larger than a width w3 of a top part of each of the second fin-shaped structures". This directly relates to the concept of variable channel width. Therefore, claims like Claim 2, which specifies the width difference, could be impacted.

9. US20140335673A1

   • Full Citation: US20140335673A1, "Methods of manufacturing finfet semiconductor devices using sacrificial gate patterns and selective oxidization of a fin"
   • Publication Date: November 13, 2014
   • Brief Description: This patent application details methods for manufacturing FinFET devices that involve sacrificial gate patterns and selective oxidation of fins. Selective oxidation can be used to modify fin dimensions or create insulating layers.
   • Potential Anticipation (General): US9786510's first embodiment involves a "treatment process Q2" which is "preferably an oxidation process" to form a "modified part 120" on the fin, which is then removed. This has strong similarities to the "selective oxidization of a fin" described in this prior art. Therefore, method claims of US9786510 related to the modification and removal of fin surfaces through oxidation could be anticipated.

10. US20150145048A1

    • Full Citation: US20150145048A1, "Structure and method for forming cmos with nfet and pfet having different channel materials"
    • Publication Date: May 28, 2015
    • Brief Description: This patent application describes methods for forming CMOS devices where n-type and p-type FinFETs have different channel materials. This addresses optimizing performance for different transistor types.
    • Potential Anticipation (General): While the primary focus is on different channel materials, the underlying FinFET structures and their formation processes would be relevant. If the methods described for forming the fins themselves overlap with US9786510, certain claims could be implicated. The filing date of 2013-11-22 is after the priority date of US9786510 (2014-09-09), making this a later-filed application if it relies on its own priority date. However, further analysis would be needed to determine if it could still be prior art under different 35 U.S.C. § 102 provisions (e.g., if it claims priority to an earlier application that predates US9786510). Given the 2015 publication, it is likely cited for its disclosure rather than necessarily anticipating the claims of US9786510 based solely on its publication date.

11. US20150311085A1

    • Full Citation: US20150311085A1, "Field effect transistor (finfet) device with a planar block area to enable varialble fin pitch and width"
    • Publication Date: October 29, 2015
    • Brief Description: This patent application describes a FinFET device with a planar block area that allows for variable fin pitch and width. This enables flexibility in FinFET layout and performance optimization.
    • Potential Anticipation (General): US9786510 discusses variations in fin width and the distances between fins (p1, p2, p3, p5, p6). Claim 1 of US9786510 specifically addresses the difference in distances between adjacent top corners of fins. Therefore, prior art disclosing variable fin pitch and width, like this reference, would be directly relevant to such claims. The filing date of 2014-04-23 is also before the priority date of US9786510 (2014-09-09).

Obviousness under 35 U.S.C. § 103 dictates that a patent claim cannot be obtained if the differences between the claimed invention and the prior art would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the invention. The analysis requires identifying the scope and content of the prior art, distinguishing the claimed invention from the prior art, and determining the level of ordinary skill in the art. A key component of an obviousness rejection is providing a clear articulation of the reasons why the claimed invention would have been obvious, including a motivation to combine prior art references. This motivation can stem from design needs, market pressure, common sense, or a reasonable expectation of success.

US patent 9786510 claims a fin-shaped structure and a method for manufacturing it, particularly focusing on forming fin-shaped structures with ladder-shaped cross-sectional profiles in different areas to achieve varying electrical demands for transistors. The patent emphasizes the ability to form fin-shaped structures of different heights and critical dimensions.

A PHOSITA in the field of FinFET technology at the time of the invention (priority date 2014-09-09) would have been aware of the challenges in scaling semiconductor devices and the advantages of multi-gate MOSFETs like FinFETs for better channel control, reduced short channel effects, and increased current. They would also understand that transistors in different areas (e.g., logic vs. input/output) have different purposes and electrical demands, necessitating tailored structures.

Here are potential combinations of prior art references that could render the claims of US9786510 obvious:

Combination 1: US20080157225A1 (Datta) + US8373238B2 (Taiwan Semiconductor Manufacturing Company, Ltd.) + General knowledge in the art

• US20080157225A1 (Datta): This reference discloses SRAM and logic transistors with variable height multi-gate transistor architecture. This directly addresses the concept of having different fin heights for different types of transistors, which is a core aspect of US9786510, particularly for meeting varying electrical demands (e.g., HVT and LVT areas).
• US8373238B2 (Taiwan Semiconductor Manufacturing Company, Ltd.): This patent explicitly teaches FinFETs with multiple fin heights. It details methods for achieving these different heights.
• Motivation to Combine: A PHOSITA would be motivated to combine the teachings of Datta and US8373238B2 to implement the variable fin heights proposed by Datta using the specific FinFET manufacturing techniques described in US8373238B2. The motivation would be to optimize transistor performance for different circuit areas (e.g., logic vs. I/O) by tailoring fin heights, a known design consideration in FinFET development. The ability to create FinFETs with different heights allows for better control of electrical characteristics such as threshold voltage, which is crucial for integrating different types of devices on a single substrate.

Combination 2: US20140191323A1 (International Business Machines Corporation) + US20140335673A1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)) + General knowledge in the art

• US20140191323A1 (International Business Machines Corporation): This reference describes a method of forming FinFETs of variable channel width. Variation in channel width directly relates to variation in critical dimensions (CDs) of the fins.
• US20140335673A1 (Samsung Electronics Co., Ltd.): This patent describes methods of manufacturing FinFET semiconductor devices using sacrificial gate patterns and selective oxidation of a fin. This aligns with the methods described in US9786510 for modifying fin structures. The patent details how to selectively oxidize a fin, which can lead to changes in its dimensions.
• Motivation to Combine: A PHOSITA would be motivated to combine the concept of variable channel width from US20140191323A1 with the selective modification techniques of US20140335673A1. The goal would be to create FinFETs with varied critical dimensions in different regions of a semiconductor device to meet diverse electrical performance requirements. For example, by selectively oxidizing a fin, its effective width and/or height can be altered, leading to different critical dimensions. This is a predictable outcome when seeking to customize FinFET characteristics for specific applications or areas on a chip. The ability to modify fin dimensions selectively allows for the tailoring of transistor properties such as drive current and leakage.

Combination 3: US20150311085A1 (Globalfoundries Inc.) + US20120313169A1 (Globalfoundries Inc.) + General knowledge in the art

• US20150311085A1 (Globalfoundries Inc.): This reference discloses a FinFET device with a planar block area to enable variable fin pitch and width. This directly addresses forming fins with different dimensions (including width, which impacts CD) in different areas.
• US20120313169A1 (Globalfoundries Inc.): This patent teaches FinFET devices and methods, and integrated circuits using such. It represents general knowledge regarding FinFET fabrication.
• Motivation to Combine: A PHOSITA would be motivated to use the methods described in US20120313169A1, which pertain to FinFET fabrication, to implement the variable fin pitch and width structures described in US20150311085A1. The motivation would be to create FinFETs with customized geometries (e.g., width) in different areas on a chip, which is a known approach to achieving desired electrical characteristics for various components (e.g., high-performance logic vs. low-power memory). The combination offers a direct path to the "fin-shaped structures of different heights and critical dimensions" mentioned in US9786510.

It's important to note that the above combinations are based on the information provided in the "Prior Art" section and the claims of US9786510. A complete obviousness analysis would require a deeper dive into the specific details of each cited prior art reference and a more thorough comparison with each claim element of US9786510, as well as a robust argument regarding the motivation to combine and the reasonable expectation of success for a PHOSITA.

To provide a comprehensive overview of US Patent 9,786,510 regarding its term adjustments, extensions, and related applications, I will extract information from the authoritative patent document and USPTO resources.

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE)

Patent Term Adjustments (PTA):
PTA is granted to compensate for delays caused by the USPTO during the prosecution of a patent application. It adds additional time to the standard 20-year patent term (from the earliest filing date) for utility or plant patents. These delays can be categorized as "A-delays" (USPTO failing to act within specific timeframes, e.g., issuing a first office action within 14 months), "B-delays" (patent not issuing within three years of filing), and "C-delays" (delays due to interferences, secrecy orders, or appeals). Any overlap between these delays and applicant-caused delays are subtracted.

The Google Patents record for US9786510 indicates an "Adjusted expiration" date of 2035-01-24. This suggests that PTA has been applied to this patent, as the expiration date is later than 20 years from its filing date of 2014-10-13 (which would typically be 2034-10-13). The specific calculation of PTA would be detailed in the Issue Notification Letter for the patent, which is issued by the USPTO.

Patent Term Extensions (PTE):
PTE is typically available for patents on certain human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products to restore time lost during premarket government approval from a regulatory agency.

Given the technical nature of US9786510, which relates to "fin-shaped structures and manufacturing methods thereof" for semiconductor devices, it is highly unlikely to be eligible for Patent Term Extension (PTE) under 35 U.S.C. § 156, as its subject matter does not fall within the categories of products requiring regulatory approval.

Continuation and Divisional Applications

• Continuation Applications: A continuation application allows an applicant to pursue additional claims based on an earlier-filed "parent" application, while retaining the benefit of the parent's filing date. It must be copending with the parent application (i.e., filed before the parent issues or is abandoned).
• Divisional Applications: A divisional application is filed when the USPTO determines that a patent application contains more than one invention (via a "restriction requirement"). The applicant can then pursue the non-elected inventions in separate divisional applications, also retaining the priority date of the original application.

US Patent 9,786,510 is identified as belonging to a "Family" with ID 55438222. The Google Patents information lists the following related applications:

• US15/688,885 (US10418251B2): This is listed as a "Priority" application with a filing date of 2017-08-29 and is also explicitly identified as a "Division" of US14/512,475 (the application for US9786510). Its title is "Method of forming fin-shaped structure having ladder-shaped cross-sectional profile".
• US16/532,477 (US10930517B2): This is also listed as a "Priority" application with a filing date of 2019-08-06. Its title is "Method of forming fin-shaped structure".

Based on this, US9786510 has at least one divisional application, US10418251B2, and another related family member, US10930517B2, which claims priority back to the original filing date of US9786510.

Related Family Members

The patent family for US9786510 (Family ID=55438222) includes:

• US14/512,475 (US9786510B2): The subject patent itself.
• US15/688,885 (US10418251B2): A divisional application.
• US16/532,477 (US10930517B2): Another related application claiming priority.
• CN201410454915.XA (CN105470295B): A Chinese application claiming priority.

These illustrate the global patent strategy for the invention, with both US and international counterparts.

Projected Expiration Date

The Google Patents record for US9786510 indicates an "Adjusted expiration" date of 2035-01-24. This date already accounts for any Patent Term Adjustments (PTA) applied to the patent. The typical term for a U.S. utility patent filed on or after June 8, 1995, is 20 years from the earliest filing date, with adjustments for USPTO delays. Since the original filing date was 2014-10-13, a 20-year term would normally end on 2034-10-13. The extended expiration date of 2035-01-24 confirms that PTA was granted.