US 9619601

US Patent 9619601 (US9619601B1) provides techniques for generating a control and data flow graph (CDFG) specifically adapted for hardware description languages (HDLs).

Here's a concise summary:

• Title: Control and data flow graph generation for hardware description languages
• Assignee: Xilinx Inc.
• Inventors: Jason Villarreal and Valeria Mihalache
• Filing Date: 2015-01-22
• Issue Date: 2017-04-11
• Abstract: The patent describes a method for generating a control and data flow graph for HDL code that defines a circuit design. This method involves examining an Abstract Syntax Tree (AST) of the HDL code, module by module. For each module that contains concurrent execution paths, an "execution unit" is added to the control and data flow graph. Within this execution unit, specific nodes are included: a "loopback sink" which merges the concurrent paths, and a "loopback source" which receives feedback from the loopback sink and then distributes this feedback back to the concurrent paths.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method): This claim outlines a computer-implemented method for creating a specialized control and data flow graph (CDFG) for hardware description language (HDL) code. The method involves analyzing the HDL code's structure, represented as an Abstract Syntax Tree (AST), one module at a time. For any module within the HDL code that has sections designed to execute simultaneously (concurrent paths), the method adds a specific construct called an "execution unit" to the CDFG. This execution unit is designed with special "loopback" nodes: a "loopback sink" that gathers all information from the concurrent paths, and a "loopback source" that then redistributes this information back to all concurrent paths, effectively modeling the simultaneous data exchange inherent in HDL.
• Claim 8 (System): This claim describes a physical system, such as a computer, that is capable of performing the method described in Claim 1. The system includes memory to store the necessary software instructions and the HDL's AST, and a processor that executes these instructions. The processor is configured to traverse the AST and construct the CDFG by adding execution units with their associated loopback sink and loopback source nodes for concurrent HDL modules, precisely as detailed in Claim 1.
• Claim 15 (Non-transitory Computer Readable Medium): This claim covers a non-temporary digital storage device (like a hard drive or flash memory) that contains software instructions. When a processor executes these instructions, it carries out the method of Claim 1. This means the processor will traverse an HDL AST and generate a control and data flow graph, including the unique execution units with loopback sinks and sources for concurrent HDL modules.

CAFC 2026 Dockets:
No specific docket entries for US patent 9619601 were found in the CAFC 2026 dockets.

I have searched for litigation involving US patent 9619601. My search focused on Unified Patents, CAFC, and PACER.

Based on the search results, I found no known litigation explicitly listing US patent 9619601. The Unified Patents search results provided examples of how to search for patent litigation but did not return any specific cases for US9619601. Similarly, the PACER and CAFC results describe how to find cases and their functionalities, but do not directly show any litigation for the specified patent number.

Therefore, as of April 26, 2026, there is no known litigation involving US patent 9619601 based on the conducted searches.

Proceedings overview

There are no AIA trial proceedings on file for US Patent 9619601. The USPTO Open Data Portal API indicates no PTAB activity, and targeted web searches for Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) proceedings related to this patent did not yield any results. This means the patent has not been challenged in an AIA trial.

Strategic summary

As of 2026-08-07, US Patent 9619601 has not been subjected to any AIA trial proceedings (IPR, PGR, or CBM). All 20 claims of the patent remain untested by the Patent Trial and Appeal Board (PTAB).

The absence of PTAB activity is a significant signal. While not definitive proof of validity, patents that are actively asserted in litigation or are considered valuable often become targets for IPRs or PGRs. The lack of such challenges for US9619601 suggests that it may not have been widely asserted or deemed a high-value target for invalidation efforts by third parties to date.

Without any PTAB proceedings, there is no estoppel landscape under 35 U.S.C. § 315(e)(2) for any petitioner or their privies. This means that if a defendant were to be asserted against, all prior-art grounds that could be raised in an IPR (based on patents and printed publications under §§ 102 or 103) or a PGR (any ground under § 282(b)(2) or (3), including §§ 101, 102, 103, and 112, for eligible patents) are still available for a future challenge.

Recommended next steps

Since no PTAB activity exists for US Patent 9619601, a potential defendant facing assertion of this patent should consider the following:

• Evaluate the patent's claims and prior art: Conduct a thorough prior art search and claim analysis to determine the strength of the patent's claims against potential invalidity arguments. This is particularly important because the patent has not been subjected to PTAB scrutiny.
• Consider filing an AIA petition: If the analysis reveals strong grounds for invalidity, filing an IPR (for challenges based on patents and printed publications under §§ 102 or 103) or a PGR (if the patent is eligible and within the 9-month window post-issuance, allowing for broader grounds) could be a viable defensive strategy. The patent was granted on 2017-04-11, so the window for a PGR has closed. An IPR remains an option.
• Monitor for future PTAB activity: While there are no current proceedings, this could change. Continuously monitor PTAB dockets (via P-TACTS, for example) for any newly filed petitions against US9619601.

Inventors

• Jason Villarreal: Employed by Xilinx Inc. at the time of filing.
• Valeria Mihalache: Employed by Xilinx Inc. at the time of filing.

No unusual patterns detected; the inventors assigned their interest to the original assignee on the filing date.

Original assignee

The entity named on the issued patent is Xilinx Inc..
Xilinx Inc. was a technology and semiconductor company that designed and developed programmable logic devices, including Field-Programmable Gate Arrays (FPGAs), System-on-Chips (SoCs), software design tools, and intellectual property (IP) cores. They shipped products embodying the claims, such as FPGAs, to various markets including communications, data processing, industrial, consumer, and automotive.

Current Status: Xilinx Inc. was acquired by Advanced Micro Devices, Inc. (AMD) in an all-stock transaction valued at approximately $60 billion, which was announced in October 2020 and completed on February 14, 2022. Xilinx Inc. now operates as a wholly owned subsidiary of AMD. While the Xilinx brand is being consolidated under AMD's branding since June 2023, the legal entity Xilinx Inc. (or its subsidiary forms) remains active.

Assignment timeline

• 2015-01-22 (executed) / recorded 2015-01-22 — Reel 034794/0546
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: VILLARREAL, JASON; MIHALACHE, VALERIA
  • Assignee: XILINX, INC.
  • Correspondent: VENABLE LLP, P.O. BOX 34385, WASHINGTON, DC 20043-4385
  • Context: Initial assignment from inventors to the corporate entity at the time of application filing.

Timeline diagram

timeline
    title Ownership of US 9619601
    2015 : Filed by Xilinx Inc
         : Inventors assigned to Xilinx
    2017 : Patent issued
    2022 : Xilinx acquired by AMD

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded assignment is from individual inventors to Xilinx Inc., a known operating company.
2. Known asserter in the chain — Not present. Xilinx Inc. (and subsequently AMD) is an operating company, not a known NPE.
3. Repeat correspondent across the chain — Not present. There is only one assignment record for this patent from the USPTO Assignment Center, handled by VENABLE LLP.
4. Cascading transfers — Not present. There is only one assignment record.
5. Pre-litigation transfer — Unclear. There is no information in the provided sources to determine if an assignment occurred within 6 months of the first infringement suit.
6. Bankruptcy fire-sale — Not present. Xilinx Inc. was acquired by AMD, not involved in a bankruptcy sale.
7. Privateering — Not present. The patent remains with AMD, which acquired Xilinx.
8. Defensive aggregator (anti-NPE) — Not present. The patent is held by AMD, an operating company.

Verdict

Insufficient data.
The only assignment recorded is the initial transfer from the inventors to the original assignee, Xilinx Inc., on the application filing date (Reel 034794/0546). While Xilinx was later acquired by AMD in 2022, this corporate acquisition does not typically register as a separate assignment of individual patent assets in the USPTO Assignment Center unless specifically recorded as such. The absence of subsequent assignments prevents the identification of NPE patterns.

USPTO Patent Assignment Search for US9619601

The following is an analysis of US Patent 9619601 and its most relevant prior art.

US Patent 9619601: Control and data flow graph generation for hardware description languages

• Publication Number: US9619601B1
• Filing Date: 2015-01-22
• Publication Date: 2017-04-11
• Assignee: Xilinx Inc.
• Inventors: Jason Villarreal, Valeria Mihalache

This patent describes a method, system, and non-transitory computer readable medium for generating a control and data flow graph (CDFG) for hardware description language (HDL) code. The method involves traversing an abstract syntax tree (AST) of the HDL code on a module-by-module basis and adding an execution unit to the CDFG for each module with concurrent paths. These execution units include a loopback sink to merge concurrent paths and a loopback source to propagate feedback to them. The patent aims to address the challenges of modeling concurrency, time, and hierarchical references in HDL designs within a CDFG, enabling more efficient compiler optimizations and simulation.

Most Relevant Prior Art Citations:

The patent US9619601B1 cites six prior art patents during its prosecution. These are analyzed below for their potential relevance.

1. USRE40925E1 (Methods for automatically pipelining loops)

   • Full Citation: USRE40925E1
   • Publication/Filing Date: Priority Date: 1995-05-12, Publication Date: 2009-09-29
   • Brief Description: This patent describes methods for automatically pipelining loops in a hardware description language. It focuses on techniques to improve the performance of hardware designs by optimizing loop execution.
   • Potential Anticipation (35 U.S.C. § 102): While USRE40925E1 deals with HDL optimization, its primary focus on pipelining loops might not directly anticipate the core method of generating a CDFG with specific constructs for concurrent paths, loopback sinks, and loopback sources as claimed in US9619601 (Claim 1). However, the general concept of optimizing HDL code for hardware could be seen as related. Depending on the level of abstraction of the underlying data structures used for pipelining, there could be an argument regarding anticipation if those structures implicitly or explicitly capture control and data flow in a manner similar to the CDFG described in US9619601. Without further detail on the internal representation in USRE40925E1, a direct anticipation of Claim 1 for the specific CDFG structure is not immediately clear.

2. US20020188923A1 (High-level synthesis apparatus, high-level synthesis method, method for producing logic circuit using the high-level synthesis method, and recording medium)

   • Full Citation: US20020188923A1
   • Publication/Filing Date: Priority Date: 2001-06-11, Publication Date: 2002-12-12
   • Brief Description: This publication relates to high-level synthesis, transforming a high-level description (e.g., in an HDL) into a register-transfer level (RTL) or logic circuit description. It generally involves generating data flow graphs or control data flow graphs as part of the synthesis process.
   • Potential Anticipation (35 U.S.C. § 102): US20020188923A1 is highly relevant as it explicitly mentions the generation and use of control data flow graphs (CDFG) in high-level synthesis of HDL code. Claim 1 of US9619601 broadly claims a method of generating a CDFG for HDL code by traversing an AST and adding execution units with loopback sinks and sources for concurrent paths. If US20020188923A1 details a method of CDFG generation for HDL that includes similar mechanisms for handling concurrency, especially with implicit feedback or merging of concurrent paths, it could potentially anticipate Claim 1. The specific "loopback sink" and "loopback source" nodes as distinct features for merging and propagating feedback in concurrent paths would need to be thoroughly compared. If US20020188923A1 uses a form of CDFG generation for HDL that inherently models concurrency and data flow between concurrent sections, then claims related to these foundational aspects could be anticipated.

3. US20030188299A1 (Method and apparatus for simulation system compiler)

   • Full Citation: US20030188299A1
   • Publication/Filing Date: Priority Date: 2001-08-17, Publication Date: 2003-10-02
   • Brief Description: This patent application describes a simulation system compiler, likely involving the compilation of hardware description languages for simulation purposes. Such compilers often involve some form of intermediate representation, which could include control and/or data flow graphs.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US20020188923A1, if this reference describes the generation of a CDFG or a similar graph representation from HDL code for simulation, it could be relevant to Claim 1 of US9619601. The key would be whether it teaches the specific "loopback sink" and "loopback source" nodes for merging and propagating feedback in concurrent paths, or an equivalent mechanism that achieves the same function in the context of HDL concurrency. If the simulation system compiler relies on an intermediate representation that functions as a CDFG and implicitly or explicitly handles concurrent paths in a manner that falls under the scope of Claim 1, then anticipation is possible.

4. US8863069B1 (Hardware definition language generation for data serialization from executable graphical models)

   • Full Citation: US8863069B1
   • Publication/Filing Date: Priority Date: 2006-09-11, Publication Date: 2014-10-14
   • Brief Description: This patent focuses on generating HDL from executable graphical models for data serialization. While it involves HDL, the primary inventive step appears to be the generation of HDL from graphical models rather than the analysis of existing HDL to generate a CDFG for compiler optimizations.
   • Potential Anticipation (35 U.S.C. § 102): This patent is likely less directly anticipatory of Claim 1 of US9619601. Its focus on generating HDL from graphical models for data serialization is different from analyzing existing HDL to create a CDFG for compiler optimizations. While it deals with HDL, the specific mechanism for generating a CDFG with loopback elements for concurrent paths is not immediately apparent from the description.

5. US8694947B1 (Resource sharing workflows within executable graphical models)

   • Full Citation: US8694947B1
   • Publication/Filing Date: Priority Date: 2009-12-09, Publication Date: 2014-04-08
   • Brief Description: This patent concerns resource sharing workflows within executable graphical models. It's related to design and optimization within graphical modeling environments, which may eventually lead to HDL, but does not explicitly detail the generation of a CDFG from HDL with the specific structures of US9619601.
   • Potential Anticipation (35 U.S.C. § 102): This patent is also likely less directly anticipatory. Its subject matter, resource sharing in graphical models, is a step removed from the core inventive concept of US9619601, which is the generation of a specialized CDFG from HDL code that specifically addresses concurrency using loopback mechanisms.

6. US20130198713A1 (Code generation for control design)

   • Full Citation: US20130198713A1
   • Publication/Filing Date: Priority Date: 2011-11-08, Publication Date: 2013-08-01
   • Brief Description: This publication discusses code generation for control design, which could involve generating HDL from a higher-level control specification. It may involve intermediate representations, but the specific CDFG structure for concurrent HDL as described in US9619601 is not its primary focus.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the previous two, this reference's focus on code generation for control design might not directly anticipate the specific CDFG generation method of US9619601. If the "code generation" process implicitly or explicitly creates an intermediate representation that functions identically to the CDFG and its loopback components as described in Claim 1 of US9619601, there could be an argument for anticipation. However, without explicit details on such a representation and its construction from HDL for concurrent paths, it is less likely to directly anticipate.

Conclusion on Most Relevant Prior Art:

Based on the brief descriptions, US20020188923A1 (High-level synthesis apparatus) and US20030188299A1 (Method and apparatus for simulation system compiler) appear to be the most relevant prior art. These references explicitly deal with the compilation and synthesis of HDL code and the use of graph representations, such as CDFGs, for this purpose. Their methods of handling control and data flow, particularly in the context of concurrency in HDL, would need careful examination to determine if they directly teach or render obvious the specific "loopback sink" and "loopback source" nodes for merging concurrent paths and propagating feedback, as claimed in US9619601. Claim 1 of US9619601, which defines the core method of generating the CDFG with these specific nodes for concurrent paths, would be the primary target for potential anticipation by these two references.

US patent 9619601 (hereinafter "the '601 patent") describes methods and systems for generating a control and data flow graph (CDFG) for hardware description language (HDL) code, which is designed to enable compiler optimizations for concurrent HDL. The critical date for this patent is its priority date, January 22, 2015.

The independent claim, Claim 1, recites:
"1. A method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design, comprising: traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis; and using a processor, generating the control and data flow graph by adding an execution unit to the control and data flow graph for each module having concurrent paths, each execution unit comprising nodes in the control and data flow graph, the nodes including a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths."

An analysis of obviousness under 35 U.S.C. § 103 requires identifying prior art that teaches or suggests the claimed invention, and providing a motivation for a person having ordinary skill in the art (POSA) to combine these references to arrive at the claimed invention with a reasonable expectation of success.

The following prior art references are considered for this analysis:

• US20020188923A1 (Ohnishi): Teaches a high-level synthesis apparatus and method that generates a logic circuit from a behavioral description written in an HDL, involving analysis and control flow graphs.
• US20030188299A1 (Broughton): Describes a method and apparatus for a simulation system compiler for HDL designs, which handles discrete event simulation.
• USRE40925E1 (Synopsys): Focuses on methods for automatically pipelining loops, involving control flow graph and data flow graph analyses.
• US8863069B1 (The Mathworks, Inc.): Concerns hardware definition language generation from executable graphical models, including extracting data dependencies.

Obviousness Analysis of Claim 1

Combination: US20020188923A1 (Ohnishi) in view of US20030188299A1 (Broughton) and general knowledge in compiler design for concurrent languages.

Rationale:

1. Generating CDFGs for HDL from AST traversal: Ohnishi explicitly teaches generating a control data flow graph from a behavioral description written in an HDL for high-level synthesis, implying the traversal of an intermediate representation like an AST. The '601 patent itself states that "Previous approaches in building graph representations for HDL designs are based on abstract syntax tree (AST) models" and that its HDL-CDFG "can be constructed from a traversal of an AST." This establishes the foundational steps of traversing an AST representation of HDL code on a module-by-module basis to generate a CDFG.

2. Addressing Concurrency in HDL: The '601 patent's background acknowledges that "For concurrent languages, such as a hardware description language (HDL), a traditional CDFG cannot adequately represent all the semantics of the language, such as the representation of statements executing concurrently, the notion of time, or hierarchical references." Broughton teaches a simulation system compiler for HDL designs that utilizes discrete event simulation. Discrete event simulation inherently deals with the concurrent nature of HDL statements and the propagation of values across simulation time steps.

3. Motivation to Combine: A person having ordinary skill in the art (POSA) in the field of EDA and compiler design for HDLs, seeking to improve the efficiency and accuracy of HDL compilation for optimization (as taught by Ohnishi) and simulation (as taught by Broughton), would be acutely aware of the challenges in statically modeling the dynamic, concurrent behavior of HDLs in a CDFG. The need to capture interdependencies between concurrently executing blocks, where data definitions in one concurrent section become accessible to others, is a fundamental problem in analyzing parallel and concurrent programs.

4. The Loopback Source/Sink Construct: To address this known problem, it would have been obvious for a POSA to employ a feedback mechanism within the CDFG to manage the iterative flow of data between concurrent paths. The concept of "loopback" structures, where outputs from a set of operations are collected and then fed back as inputs for subsequent iterations or "time steps," is a well-established pattern in graph theory, particularly in iterative data flow analysis and modeling of systems with cyclic dependencies (e.g., feedback loops in control systems, or fixed-point computations in program analysis).

   The '601 patent's "loopback sink that merges the concurrent paths" serves to collect all data modifications or effects from the concurrently executing sections within an execution unit. The "loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths" then effectively distributes this updated state back to the concurrent paths for their next logical execution cycle. This construct directly maps the temporal and data-dependent cycles inherent in concurrent HDL execution into a static graph structure, allowing for traditional compiler optimizations. The '601 patent itself reinforces this by describing specific constructs like the delta delay construct (FIG. 6) and event-driven constructs (FIG. 10) which utilize loopback source/sink mechanisms to model time-dependent and event-driven feedback, further demonstrating that such mechanisms are a recognized means for representing these HDL semantics in a graph.

Therefore, a POSA, motivated to enhance the analytical capabilities of HDL compilers (Ohnishi) to accurately represent and optimize for concurrent HDL behavior (inherent in Broughton's simulation), would find it obvious to integrate a graph-based feedback mechanism—specifically, loopback source and sink nodes—to model the cyclical data dependencies arising from concurrent paths within an HDL module's execution unit.

Obviousness Analysis of Dependent Claims (Claims 2-7)

Given the obviousness of the core method in Claim 1, the dependent claims would also be rendered obvious as they represent straightforward applications or specific implementations of well-known HDL semantics and compiler design patterns within this established CDFG framework.

• Claim 2 (Tracking New/Old Variables for Non-Blocking Assignments): Broughton's discrete event simulation for HDL implies the need to handle non-blocking assignments and delta delays, which fundamentally distinguish between current and future (old and new) values of signals. Explicitly tracking "new" and "old" versions of variables in a data flow graph is an obvious method for accurately modeling delta-delay semantics within the CDFG framework.
• Claim 3 (Initialization Sections with True Source/Sink): HDL modules frequently include initialization sections (e.g., 'initial' blocks in Verilog). The use of "true source" and "true sink" nodes to represent the absolute beginning and end of control and data flow for an HDL module, especially for initial sections that execute once, is a standard graph modeling technique.
• Claim 4 (HDL Functions with True Source/Sink and Initial Path): HDL functions are known to execute instantaneously without delays, similar to sequential programming language functions. Modeling such a function with a single, linear initial path between a true source and true sink is a direct and obvious representation in a CDFG.
• Claim 5 (HDL Tasks with Delay Block): HDL tasks can contain delays. Inserting a "delay block" to split an initial path and model a delay point, potentially leveraging the dual variable concept of Claim 2, is an obvious adaptation to represent task semantics within the CDFG.
• Claim 6 (Event-Driven Sections with Not-Taken Path): Event-driven constructs (e.g., VHDL processes, Verilog 'always' blocks) are fundamental to HDLs. When an event guards concurrent code, a POSA would understand that control flow analysis needs to consider both the "taken path" (event occurred) and the "not-taken path" (event did not occur) to correctly track data flow. Adding a node representing the "not-taken path" and providing fake definitions to maintain old variable values is an obvious technique in data flow analysis for conditional branches.
• Claim 7 (Adding Instructions for Ports): Ports define the interface of an HDL module. Representing these ports as explicit "instructions" within the CDFG at the module's entry and exit points (true source/sink) for accurate data flow analysis is a basic and obvious step for any compiler performing inter-module analysis.

In conclusion, the combination of Ohnishi and Broughton, together with the general knowledge of a POSA in the field of HDL compilation and concurrent system modeling, would have rendered the claims of US9619601B1 obvious. The motivation would be to overcome the known limitations of traditional CDFGs in accurately representing the concurrent and time-based semantics of HDLs for effective optimization and simulation.