US 9337193

US Patent 9337193, titled "Semiconductor device with epitaxial structures," was issued on May 10, 2016, from an application filed on March 4, 2015 [cite: The full patent text confirms the publication date as the issue date and the filing date.]. The patent was originally assigned to United Microelectronics Corp and is currently assigned to [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

Abstract:
The patent describes a semiconductor device featuring at least two fin-shaped structures on a substrate, covered by a gate structure. The device also includes at least two epitaxial structures, which are spaced apart and located on one side of the gate structure, directly contacting each fin-shaped structure. A key feature is the presence of at least two caps, each surrounding the epitaxial structures, with at least two adjacent caps merged together.

Independent Claim Overview:

Independent Claim 1:
A semiconductor device is described, which includes:

• At least two fin-shaped structures that are built on a substrate.
• A gate structure that covers these fin-shaped structures.
• At least two epitaxial structures, positioned on one side of the gate structure, each directly touching a fin-shaped structure. These epitaxial structures are kept separate from each other.
• At least two caps, with each cap surrounding an epitaxial structure. At least two of these adjacent caps are combined (merged) together.

As of April 26, 2026, a search of CAFC 2026 dockets for US patent 9337193 did not yield any specific results indicating litigation activity for this particular patent number.

As of April 26, 2026, there is one known litigation involving US Patent 9337193:

Case 1: Inter Partes Review (IPR)

• Plaintiff(s): Unified Patents (Petitioner)
• Defendant(s): Taiwan Semiconductor Manufacturing Company Limited (Patent Owner)
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Case Number: IPR2025-01054
• Filing Date: August 20, 2025 (Effective date)
• Outcome or Current Status: Not Instituted - Merits.

Proceedings overview

One AIA trial proceeding has been filed against US patent 9337193. The status is "Institution Denied", meaning all challenged claims were sustained. This gives a defendant a stronger defensive posture, as the patent has withstood an IPR challenge at the institution stage.

IPR2025-01054 — Taiwan Semiconductor Manufacturing Company Limited v. Chin-I Liao et al

• Type: Inter Partes Review
• Filed: 2025-08-20
• Status: Institution Denied. The PTAB declined to institute a trial.
• Judge panel: Not publicly available yet for this institution decision.
• Petition grounds: The exact claims and prior art challenged are not available from the provided data, but the petition was likely based on novelty (§ 102) and/or obviousness (§ 103) grounds.
• Institution decision: Denied (2026-04-13). The PTAB denied institution of the IPR, meaning the petitioner did not demonstrate a reasonable likelihood that at least one of the challenged claims is unpatentable.
• Final Written Decision (if issued): No Final Written Decision was issued as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: Not applicable, as institution was denied.
• Defensive value: The patent owner prevailed at the institution stage. This means that, for a potential defendant, an IPR-based defense using the same or substantially similar prior art grounds as IPR2025-01054 would be more difficult.

Strategic summary

The single AIA trial proceeding against US9337193, IPR2025-01054, resulted in a denial of institution on 2026-04-13. This means that all claims challenged in the petition remain patentable. As the institution was denied, no claims of US9337193 have been canceled or narrowed through IPR. All claims of the patent are currently sustained and untested by a final written decision.

Regarding the estoppel landscape, for the petitioner, Taiwan Semiconductor Manufacturing Company Limited, and its privies, § 315(e)(2) bars them from raising any ground they raised or reasonably could have raised in IPR2025-01054. For other defendants, prior art grounds are still available. However, the fact that the PTAB denied institution suggests that the particular arguments or prior art presented in IPR2025-01054 were not deemed strong enough to meet the institution threshold. There is no information to suggest a pattern of multiple IPRs by the same petitioner or aggressive PTAB appeals by the patent owner from the provided data. Unified Patents is noted as associated with the IPR.

Recommended next steps

If you are a defendant facing assertion of this patent, it is important to understand the specific prior art and arguments presented in IPR2025-01054 and why institution was denied. While the full institution decision is not available in the provided data, reviewing it would be crucial. The fact that institution was denied makes an IPR-based defense more challenging, but not impossible, especially if new and stronger prior art or different arguments can be presented. You should analyze whether your infringement theories rely on the claims that were challenged in IPR2025-01054.

Inventors

• Chin-I Liao (United Microelectronics Corp.)
• Chun-Yu Chen (United Microelectronics Corp.)

Original assignee

United Microelectronics Corp. (UMC) is a Taiwanese semiconductor foundry company. Their primary line of business is the manufacturing of integrated circuits for other companies. UMC ships a wide range of products embodying various semiconductor technologies, including FinFETs, which are the subject of this patent. UMC is currently operating.

Assignment timeline

• 2015-03-04 (executed) / recorded 2015-03-04 — Reel 035080/0575
  • Conveyance: Assignment
  • Assignor: Liao, Chin-I; Chen, Chun-Yu
  • Assignee: United Microelectronics Corp.
  • Correspondent: Patent Attorney, Morris Chang, No. 3, Li-Hsin Rd. II, Hsinchu Science Park, Hsinchu 300, Taiwan, R.O.C.
  • Context: Original assignment from inventors to their employer.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: United Microelectronics Corporation
  • Assignee: Marlin Semiconductor Limited
  • Correspondent: Brian M. Berliner, O'Melveny & Myers LLP, 400 South Hope Street, Los Angeles, CA 90071
  • Context: Transfer to a likely asserting entity.

Timeline diagram

timeline
    title Ownership of US 9337193
    2015 : Assigned to UMC
    2016 : Patent issued
    2021 : Assigned to Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — present. The assignment from United Microelectronics Corporation to Marlin Semiconductor Limited (Reel 056991/0292) is a strong signal. Marlin Semiconductor Limited does not appear to be an operating company, suggesting it is a licensing-only entity.
2. Known asserter in the chain — unclear. While Marlin Semiconductor Limited appears to be a shell entity, it is not listed on publicly available NPE lists from RPX or Unified Patents as of my last update.
3. Repeat correspondent across the chain — not present. Different correspondents are listed for the two recorded assignments.
4. Cascading transfers — not present. Only one assignment after the initial inventor-to-company transfer is recorded.
5. Pre-litigation transfer — unclear. There is no information provided regarding litigation history to determine if this transfer occurred within 6 months of a first infringement suit.
6. Bankruptcy fire-sale — not present. There is no indication of United Microelectronics Corp. filing for bankruptcy.
7. Privateering — unclear. While the transfer from UMC to Marlin Semiconductor could be a privateering arrangement, there is no public information or SEC filing data provided to confirm this.
8. Defensive aggregator (anti-NPE) — not present. The chain ends with Marlin Semiconductor Limited, which is not a known defensive aggregator.

Verdict

NPE — moderate confidence. The transfer of the patent from an operating company (United Microelectronics Corp.) to Marlin Semiconductor Limited (Reel 056991/0292), which strongly appears to be a shell entity, indicates a likely assertion play. There is no evidence of Marlin Semiconductor Limited being an operating company.

For verification, you can search the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ or https://assignment.uspto.gov/patent/index.html.

Here is an analysis of the most relevant prior art for US patent 9337193, based on the citations listed within the patent document. It is important to note that without access to the full text of each cited patent, the brief descriptions and anticipation assessments are inferred primarily from the titles and the context provided in US9337193 regarding prior art, and thus represent potential rather than definitive conclusions.

The core distinguishing features of US9337193, particularly in independent claim 1, revolve around a semiconductor device including:

• At least two fin-shaped structures on a substrate, covered by a gate structure.
• At least two epitaxial structures, spaced apart, at one side of the gate, and directly contacting each fin-shaped structure.
• At least two caps, each surrounding an epitaxial structure, where at least two adjacent caps are merged together.

The invention emphasizes the benefits of merged caps in addressing lattice defects and enhancing stresses in the channel region (Description, "SUMMARY OF THE INVENTION").

Here are the cited prior art references:

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1. US6043138A

• Full Citation: US6043138A, "Multi-step polysilicon deposition process for boron penetration inhibition", Advanced Micro Devices, Inc., published March 28, 2000.
• Publication/Filing Date: Priority Date: 1996-09-16, Publication Date: 2000-03-28.
• Brief Description: This patent appears to describe a method for depositing polysilicon in multiple steps to prevent boron penetration in semiconductor devices. This is generally related to gate electrode formation and doping.
• Potential Anticipation (35 U.S.C. § 102): This patent's title does not suggest the presence of fin-shaped structures, epitaxial structures, or merged caps as defined in claim 1 of US9337193. It primarily addresses a specific gate fabrication issue. Therefore, it is unlikely to anticipate claim 1 or its dependent claims that relate to the structural arrangement of fins, epitaxial structures, and merged caps.

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2. US7087477B2

• Full Citation: US7087477B2, "FinFET SRAM cell using low mobility plane for cell stability and method for forming", International Business Machines Corporation, published August 8, 2006.
• Publication/Filing Date: Priority Date: 2001-12-04, Publication Date: 2006-08-08.
• Brief Description: This patent focuses on FinFET (Fin Field Effect Transistor) technology, specifically in the context of SRAM cells, and mentions using a low mobility plane for stability. This indicates a general FinFET structure and possibly specific material or orientation considerations for performance.
• Potential Anticipation (35 U.S.C. § 102): This patent explicitly mentions "FinFET," indicating it likely includes "at least two fin-shaped structures" and a "gate structure, covering the fin-shaped structures" (Claim 1, US9337193). However, the title does not suggest "epitaxial structures spaced apart from each other" or "caps...merged together." While it's a FinFET, the specific epitaxial structure and merged cap arrangement of US9337193 appears novel relative to this title. It might anticipate the broader concepts of FinFETs (portions of claim 1 relating to fins and gate), but not the specific epitaxial and cap arrangement.

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3. US6492216B1

• Full Citation: US6492216B1, "Method of forming a transistor with a strained channel", Taiwan Semiconductor Manufacturing Company, published December 10, 2002.
• Publication/Filing Date: Priority Date: 2002-02-07, Publication Date: 2002-12-10.
• Brief Description: This patent describes methods for forming transistors with strained channels, a technique used to improve device performance. Strained silicon technology is generally achieved by incorporating epitaxial structures with different lattice constants.
• Potential Anticipation (35 U.S.C. § 102): This patent broadly covers "strained channel" transistors, which US9337193 acknowledges as a prior art concept for improving performance ("a strained-silicon technology has also been developed," Description, BACKGROUND OF THE INVENTION). It likely describes the use of epitaxial structures to induce strain (as stated in US9337193's background: "one main technology generally used in the strained-silicon technology is to dispose epitaxial structures with lattice constants different from that of the crystal silicon in the source/drain regions"). However, the title does not specify fin-shaped structures, nor the critical arrangement of spaced apart epitaxial structures with merged caps as defined in claim 1 of US9337193. It may anticipate the general concept of using epitaxial structures for strain (portions of claims 1 and 7), but not the specific structural novelty.

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4. US6921963B2

• Full Citation: US6921963B2, "Narrow fin FinFET", Advanced Micro Devices, Inc., published July 26, 2005.
• Publication/Filing Date: Priority Date: 2003-01-23, Publication Date: 2005-07-26.
• Brief Description: This patent describes a FinFET design with "narrow fins," likely addressing challenges related to scaling down transistor dimensions.
• Potential Anticipation (35 U.S.C. § 102): Similar to US7087477B2, this patent clearly relates to FinFETs, implying "fin-shaped structures" and a "gate structure" (Claim 1, US9337193). The emphasis on "narrow fin" points to device scaling. However, the title provides no indication of the "spaced apart epitaxial structures" or "merged caps" feature central to claim 1 of US9337193. It may anticipate generic FinFET elements but not the unique epitaxial/cap configuration.

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5. US20040195624A1

• Full Citation: US20040195624A1, "Strained silicon fin field effect transistor", National Taiwan University, published October 7, 2004.
• Publication/Filing Date: Priority Date: 2003-04-04, Publication Date: 2004-10-07.
• Brief Description: This publication describes a "strained silicon fin field effect transistor," combining both FinFET architecture and strained silicon technology.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant as it combines "FinFET" and "Strained silicon," directly touching upon the two primary technologies addressed by US9337193 (Description, BACKGROUND OF THE INVENTION). This likely discloses "fin-shaped structures," "gate structure," and "epitaxial structures" for strain (portions of claim 1). However, whether it discloses the specific arrangement of spaced apart epitaxial structures with merged caps is not evident from the title. US9337193 aims to solve the problem of "unwanted lattice defects on their interfaces" of adjacent epitaxial structures, which the merged cap structure helps to address. If this prior art does not teach the specific merged cap configuration, it would not anticipate claim 1 in its entirety. It is likely to anticipate aspects of claims 1 and 7 related to the combination of FinFET and strained epitaxial regions, but not the specific cap merging.

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6. US7250658B2

• Full Citation: US7250658B2, "Hybrid planar and FinFET CMOS devices", International Business Machines Corporation, published July 31, 2007.
• Publication/Filing Date: Priority Date: 2003-06-26, Publication Date: 2007-07-31.
• Brief Description: This patent describes integrating both planar and FinFET CMOS devices on a single substrate.
• Potential Anticipation (35 U.S.C. § 102): This patent covers FinFETs (as part of a hybrid device), so it would likely disclose "fin-shaped structures" and a "gate structure" (portions of claim 1). However, its focus is on the integration of different device types, not on the specific epitaxial and cap structures that distinguish US9337193. It is unlikely to anticipate claim 1's unique features.

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7. US20050051825A1

• Full Citation: US20050051825A1, "Semiconductor device and manufacturing method thereof", Makoto Fujiwara, published March 10, 2005.
• Publication/Filing Date: Priority Date: 2003-09-09, Publication Date: 2005-03-10.
• Brief Description: The title is very general, indicating a semiconductor device and its manufacturing method. Without further details, it's hard to ascertain its specific relevance.
• Potential Anticipation (35 U.S.C. § 102): With such a general title, it is difficult to determine if this patent anticipates any specific claims of US9337193, especially the distinct features of epitaxial structures and merged caps. It might broadly cover general semiconductor device components but not the specific claimed invention.

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8. US6888181B1

• Full Citation: US6888181B1, "Triple gate device having strained-silicon channel", United Microelectronics Corp., published May 3, 2005.
• Publication/Filing Date: Priority Date: 2004-03-18, Publication Date: 2005-05-03.
• Brief Description: This patent describes a "triple gate device" (which is a type of FinFET/multi-gate MOSFET, as explained in US9337193: "a tri-gate MOSFET... is another kind of multi-gate MOSFET") that incorporates a "strained-silicon channel."
• Potential Anticipation (35 U.S.C. § 102): This reference is also highly relevant, combining "triple gate device" (similar to FinFETs which have fin-shaped structures and a gate covering them) and "strained-silicon channel," implying the use of epitaxial structures (portions of claim 1, and claim 7). Similar to US20040195624A1, the crucial question for anticipation of claim 1 of US9337193 lies in whether it discloses the spaced apart epitaxial structures and, more importantly, the merged caps that "simultaneously surround the epitaxial structures." If it does not teach the merged cap structure, it would not anticipate claim 1 in its entirety.

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9. US7531437B2

• Full Citation: US7531437B2, "Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material", Intel Corporation, published May 12, 2009.
• Publication/Filing Date: Priority Date: 2004-09-30, Publication Date: 2009-05-12.
• Brief Description: This patent describes a method for fabricating metal gate electrodes using a "gate-last" or "replacement metal gate (RMG)" process, involving sacrificial materials. US9337193 also uses a "gate-last for high-k last process" (Description, DETAILED DESCRIPTION).
• Potential Anticipation (35 U.S.C. § 102): This patent's focus is on the manufacturing process of metal gates (relevant to the "RMG process" mentioned in US9337193, particularly steps leading to claim 11). It does not, from its title, appear to disclose the fin-shaped structures, epitaxial structures, or merged caps of claim 1. Thus, it is unlikely to anticipate claim 1 or its dependent claims focusing on the physical arrangement of fins, epitaxial structures, and caps, but it might be relevant to the manufacturing process disclosed in US9337193 for forming the gate structure.

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10. US20060099830A1

• Full Citation: US20060099830A1, "Plasma implantation using halogenated dopant species to limit deposition of surface layers", Varian Semiconductor Equipment Associates, Inc., published May 11, 2006.
• Publication/Filing Date: Priority Date: 2004-11-05, Publication Date: 2006-05-11.
• Brief Description: This publication concerns plasma implantation techniques using specific dopant species to control surface layer deposition. This relates to doping processes in semiconductor manufacturing.
• Potential Anticipation (35 U.S.C. § 102): The title suggests a process for doping, not a specific device structure. It does not appear to disclose fin-shaped structures, epitaxial structures, or merged caps, and thus is unlikely to anticipate claim 1 or its dependent claims relating to the device structure of US9337193.

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11. US7091551B1

• Full Citation: US7091551B1, "Four-bit FinFET NVRAM memory device", International Business Machines Corporation, published August 15, 2006.
• Publication/Filing Date: Priority Date: 2005-04-13, Publication Date: 2006-08-15.
• Brief Description: This patent describes a FinFET-based non-volatile RAM (NVRAM) memory device.
• Potential Anticipation (35 U.S.C. § 102): Similar to other FinFET-related prior art, this reference explicitly mentions "FinFET," indicating it would likely disclose "fin-shaped structures" and a "gate structure" (portions of claim 1). However, its specific application to NVRAM and the title itself do not suggest the presence of the unique "spaced apart epitaxial structures" with "merged caps" as claimed in US9337193. It anticipates generic FinFET elements but not the specific cap merging.

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12. US20060286729A1

• Full Citation: US20060286729A1, "Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate", Jack Kavalieros, published December 21, 2006.
• Publication/Filing Date: Priority Date: 2005-06-21, Publication Date: 2006-12-21.
• Brief Description: This publication describes a CMOS integrated circuit utilizing "raised source/drain" structures and a "replacement metal gate" (RMG) process. Raised source/drain structures often involve epitaxial growth.
• Potential Anticipation (35 U.S.C. § 102): This reference mentions "raised source drain" which is often achieved through epitaxial growth, making it potentially relevant to "epitaxial structures" (portions of claim 1 and claim 7). It also mentions "replacement metal gate," relevant to the process of US9337193 leading to claim 11. The term "Complementary metal oxide semiconductor integrated circuit" does not explicitly mention FinFETs, though raised source/drains are common in FinFETs. Even if it implicitly involves FinFETs and epitaxial source/drains, the title does not suggest the spaced apart nature of epitaxial structures or the merged caps that are central to claim 1 of US9337193.

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13. US7247887B2

• Full Citation: US7247887B2, "Segmented channel MOS transistor", Synopsys, Inc., published July 24, 2007.
• Publication/Filing Date: Priority Date: 2005-07-01, Publication Date: 2007-07-24.
• Brief Description: This patent describes a MOS transistor with a "segmented channel."
• Potential Anticipation (35 U.S.C. § 102): The title is quite general for a MOS transistor. It does not suggest the specific fin architecture, epitaxial structures, or merged caps of US9337193. Therefore, it is unlikely to anticipate claim 1 or its dependent claims.

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14. US7352034B2

• Full Citation: US7352034B2, "Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures", International Business Machines Corporation, published April 1, 2008.
• Publication/Filing Date: Priority Date: 2005-08-25, Publication Date: 2008-04-01.
• Brief Description: This patent describes semiconductor structures that integrate "damascene-body FinFETs" and planar devices on the same substrate.
• Potential Anticipation (35 U.S.C. § 102): This is another FinFET-related patent, suggesting "fin-shaped structures" and a "gate structure" (portions of claim 1). Its focus is on integrating different device types and a specific type of FinFET ("damascene-body"). The title does not imply the "spaced apart epitaxial structures" with "merged caps" feature of US9337193. It would anticipate generic FinFET elements but not the specific cap merging.

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15. US7309626B2

• Full Citation: US7309626B2, "Quasi self-aligned source/drain FinFET process", International Business Machines Corporation, published December 18, 2007.
• Publication/Filing Date: Priority Date: 2005-11-15, Publication Date: 2007-12-18.
• Brief Description: This patent describes a method for fabricating FinFETs with a "quasi self-aligned source/drain" process, which often involves epitaxial growth for source/drain regions.
• Potential Anticipation (35 U.S.C. § 102): This is a FinFET patent ("fin-shaped structures," "gate structure," portions of claim 1) and specifically addresses "source/drain" formation, which would typically involve "epitaxial structures" in advanced FinFETs (portions of claim 1, and potentially claims 2 and 3 regarding placement of epitaxial structures). The self-aligned nature might pertain to the interaction with the gate. However, the title does not suggest the spaced apart epitaxial structures or the crucial merged caps of claim 1. It might anticipate the use of epitaxial source/drains in FinFETs but not the specific cap merging element.

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16. US20070108528A1

• Full Citation: US20070108528A1, "Sram cell", International Business Machines Corporation, published May 17, 2007.
• Publication/Filing Date: Priority Date: 2005-11-15, Publication Date: 2007-05-17.
• Brief Description: This publication broadly describes an SRAM cell. Without further details, its specific relevance is unclear.
• Potential Anticipation (35 U.S.C. § 102): A very general title; it is unlikely to anticipate the specific structural features of US9337193.

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17. US20070158756A1

• Full Citation: US20070158756A1, "Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement", Lars Dreeskornfeld, published July 12, 2007.
• Publication/Filing Date: Priority Date: 2006-01-12, Publication Date: 2007-07-12.
• Brief Description: This publication details a production method for a FinFET transistor arrangement.
• Potential Anticipation (35 U.S.C. § 102): This patent directly addresses FinFETs and their fabrication (implying "fin-shaped structures" and "gate structure," portions of claim 1). However, the title does not specify the presence of epitaxial structures or the unique merged cap arrangement of US9337193. It anticipates generic FinFET elements and manufacturing but not the specific cap merging.

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18. US20090242964A1

• Full Citation: US20090242964A1, "Non-volatile memory device", Nxp B.V., published October 1, 2009.
• Publication/Filing Date: Priority Date: 2006-04-26, Publication Date: 2009-10-01.
• Brief Description: This publication describes a non-volatile memory device.
• Potential Anticipation (35 U.S.C. § 102): A general title, unlikely to anticipate the specific structural features of US9337193.

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19. US7569857B2

• Full Citation: US7569857B2, "Dual crystal orientation circuit devices on the same substrate", Intel Corporation, published August 4, 2009.
• Publication/Filing Date: Priority Date: 2006-09-29, Publication Date: 2009-08-04.
• Brief Description: This patent describes circuit devices that utilize different crystal orientations on the same substrate, a technique often used for optimizing performance of different transistor types (e.g., PMOS and NMOS). This can involve selective epitaxial growth on different crystal planes.
• Potential Anticipation (35 U.S.C. § 102): The use of "dual crystal orientation" suggests advanced semiconductor fabrication, potentially involving epitaxial growth for different device types. This could be related to the choice of epitaxial composition for P-type vs. N-type devices as discussed in US9337193 (Description, DETAILED DESCRIPTION, paragraph "composition of the epitaxial structure 66 may be correspondingly modified..."). However, the title does not mention fin-shaped structures or the specific arrangement of spaced apart epitaxial structures with merged caps as in claim 1. It may anticipate aspects of material engineering (e.g., portions of claim 7) but not the structural novelty.

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20. US7470570B2

• Full Citation: US7470570B2, "Process for fabrication of FinFETs", International Business Machines Corporation, published December 30, 2008.
• Publication/Filing Date: Priority Date: 2006-11-14, Publication Date: 2008-12-30.
• Brief Description: This patent explicitly focuses on the "process for fabrication of FinFETs."
• Potential Anticipation (35 U.S.C. § 102): This patent clearly pertains to FinFETs, so it would likely disclose "fin-shaped structures" and a "gate structure" (portions of claim 1). Its focus on the fabrication process implies it might cover aspects of forming the fins or gates. However, the title does not indicate the presence of the spaced apart epitaxial structures with merged caps of claim 1. It anticipates generic FinFET elements and their fabrication but not the specific cap merging.

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21. US20080157208A1

• Full Citation: US20080157208A1, "Stressed barrier plug slot contact structure for transistor performance enhancement", Fischer Kevin J, published July 3, 2008.
• Publication/Filing Date: Priority Date: 2006-12-29, Publication Date: 2008-07-03.
• Brief Description: This publication describes a "stressed barrier plug slot contact structure" aimed at enhancing transistor performance. Stress is a key theme, similar to US9337193.
• Potential Anticipation (35 U.S.C. § 102): This reference mentions "stressed" structures for performance enhancement, aligning with the "strained-silicon technology" mentioned in US9337193's background. It also mentions "contact structure" (related to claim 11 of US9337193). However, the specific structure described, "barrier plug slot contact," does not immediately map to the fin-shaped structures, epitaxial structures, and especially the merged caps of claim 1 of US9337193. It may anticipate the general concept of stress for performance or elements of contact structures (portions of claim 11) but not the defining features of claim 1.

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22. US20090124097A1

• Full Citation: US20090124097A1, "Method of forming narrow fins in finfet devices with reduced spacing therebetween", International Business Machines Corporation, published May 14, 2009.
• Publication/Filing Date: Priority Date: 2007-11-09, Publication Date: 2009-05-14.
• Brief Description: This publication describes a method for forming "narrow fins in FinFET devices with reduced spacing." This directly addresses scaling challenges in FinFETs.
• Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to the "fin-shaped structures" of claim 1 and the general scaling context of FinFETs. It explicitly mentions "FinFET devices" and "narrow fins with reduced spacing," which are characteristics of modern FinFETs (e.g., the pitch between fins mentioned in US9337193's description, "a pitch ranges from 10 nanometers (nm) to 14 nm between two adjacent fin-shaped structures 12"). However, the title does not indicate the presence of "epitaxial structures" (beyond perhaps the fin material itself) or the "merged caps" feature unique to claim 1 of US9337193. It anticipates the fin structure elements of claim 1 but not the specific epitaxial and cap arrangement.

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23. US20090269916A1

• Full Citation: US20090269916A1, "Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges", Inkuk Kang, published October 29, 2009.
• Publication/Filing Date: Priority Date: 2008-04-28, Publication Date: 2009-10-29.
• Brief Description: This publication describes fabrication methods for memory cells that include "fin structures with semicircular top surfaces and rounded top corners and edges," focusing on fin morphology.
• Potential Anticipation (35 U.S.C. § 102): This reference clearly teaches "fin structures" (part of claim 1). Its focus on specific fin shapes (semicircular top surfaces, rounded corners) suggests detailed fin engineering. However, the title provides no indication of epitaxial structures at the source/drain or the merged cap structure of US9337193. It anticipates the fin structure element of claim 1 but not the specific epitaxial and cap arrangement.

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24. US20100048027A1

• Full Citation: US20100048027A1, "Smooth and vertical semiconductor fin structure", International Business Machines Corporation, published February 25, 2010.
• Publication/Filing Date: Priority Date: 2008-08-21, Publication Date: 2010-02-25.
• Brief Description: This publication describes "smooth and vertical semiconductor fin structures," focusing on the morphology and quality of the fins.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous entry, this reference describes "fin structures" (part of claim 1) and focuses on their quality ("smooth and vertical"). The title, however, does not reveal the presence of the distinct epitaxial structures and merged caps of claim 1 of US9337193. It anticipates the fin structure element of claim 1 but not the specific epitaxial and cap arrangement.

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25. US20100072553A1

• Full Citation: US20100072553A1, "METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE", Taiwan Semiconductor Manufacturing Co., Ltd., published March 25, 2010.
• Publication/Filing Date: Priority Date: 2008-09-23, Publication Date: 2010-03-25.
• Brief Description: This publication describes using a "metal gate stress film" to enhance mobility in a FinFET device. This combines FinFET technology with stress engineering, similar to US9337193.
• Potential Anticipation (35 U.S.C. § 102): This is highly relevant as it involves "FinFET device" (implying "fin-shaped structures" and "gate structure," portions of claim 1) and "stress" for "mobility enhancement" (similar goal to US9337193). However, the source of the stress is described as a "metal gate stress film," which differs from the "epitaxial structures" in the source/drain regions as the primary stressor in US9337193 (claims 1 and 7). Also, the title does not suggest the spaced apart epitaxial structures or the merged caps. It anticipates the combination of FinFET and stress for performance, but not through the specific structural elements of claim 1 of US9337193.

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26. US20100144121A1

• Full Citation: US20100144121A1, "Germanium FinFETs Having Dielectric Punch-Through Stoppers", Cheng-Hung Chang, published June 10, 2010.
• Publication/Filing Date: Priority Date: 2008-12-05, Publication Date: 2010-06-10.
• Brief Description: This publication describes "Germanium FinFETs" with "dielectric punch-through stoppers." Germanium (Ge) is a common material in epitaxial structures for strain (as mentioned in US9337193: "silicon germanium (SiGe)").
• Potential Anticipation (35 U.S.C. § 102): This reference clearly teaches "FinFETs" (implying "fin-shaped structures" and "gate structure," portions of claim 1) and explicitly mentions "Germanium," which could be part of the "epitaxial structures" for strain (relevant to claim 7 and portions of claim 1). This is very close to the core aspects of US9337193. The critical question for anticipation of claim 1 lies in whether it discloses the spaced apart nature of these Ge structures (which would likely be epitaxial source/drains) and, crucially, the merged caps covering them. If the Ge structures are the epitaxial structures and are spaced apart, and if it also teaches merged caps, it would be highly anticipatory. Without the full text, it's a strong potential anticipator for many elements of claim 1, particularly those related to FinFETs and Ge-containing epitaxial structures for strain, but the merged cap feature is still the key differentiator.

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27. US20100167506A1

• Full Citation: US20100167506A1, "Inductive plasma doping", Taiwan Semiconductor Manufacturing Co., Ltd., published July 1, 2010.
• Publication/Filing Date: Priority Date: 2008-12-31, Publication Date: 2010-07-01.
• Brief Description: This publication describes a method of "inductive plasma doping." This is a doping process.
• Potential Anticipation (35 U.S.C. § 102): This relates to doping processes, not directly to the device structure of US9337193. It is unlikely to anticipate claim 1 or its dependent claims focusing on the structural arrangement of fins, epitaxial structures, and merged caps.

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28. US20110042744A1

• Full Citation: US20110042744A1, "Method of forming extremely thin semiconductor on insulator (etsoi) device without ion implantation", International Business Machines Corporation, published February 24, 2011.
• Publication/Filing Date: Priority Date: 2009-08-18, Publication Date: 2011-02-24.
• Brief Description: This publication describes a method for forming "extremely thin semiconductor on insulator (ETSOI)" devices without ion implantation. This relates to a specific substrate type (SOI) and a fabrication method.
• Potential Anticipation (35 U.S.C. § 102): US9337193 explicitly states its substrate "is not a silicon-on-insulator (SOI) substrate" (Description, DETAILED DESCRIPTION, paragraph related to substrate 10). Therefore, this reference describes a different type of substrate and device architecture from the bulk substrate of the primary embodiment of US9337193. It is unlikely to anticipate claim 1 or its dependent claims, especially given the differing substrate types.

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29. US8362575B2

• Full Citation: US8362575B2, "Controlling the shape of source/drain regions in FinFETs", Taiwan Semiconductor Manufacturing Company, Ltd., published January 29, 2013.
• Publication/Filing Date: Priority Date: 2009-09-29, Publication Date: 2013-01-29.
• Brief Description: This patent describes methods for "controlling the shape of source/drain regions in FinFETs." Epitaxial growth is a common way to control source/drain shape in FinFETs.
• Potential Anticipation (35 U.S.C. § 102): This is a highly relevant FinFET patent that focuses on "source/drain regions" and their "shape," directly relating to the "epitaxial structures" and their formation in US9337193 (claims 1, 2, 3). The control of shape implies detailed engineering of the epitaxial growth. It directly addresses forming source/drain regions within FinFETs, which are often epitaxial. It likely discloses "fin-shaped structures" and "gate structure" (portions of claim 1), and "epitaxial structures" forming source/drains. The critical missing piece for full anticipation of claim 1 of US9337193 would be the explicit teaching of spaced apart epitaxial structures and merged caps surrounding them. If it teaches fins, epitaxial source/drains, and the shape control inherently leads to spaced-apart structures, the merged cap would be the primary remaining differentiating feature of claim 1.

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30. US20110298058A1

• Full Citation: US20110298058A1, "Faceted epi shape and half-wrap around silicide in s/d merged finfet", Toshiba America Electronic Components, Inc., published December 8, 2011.
• Publication/Filing Date: Priority Date: 2010-06-04, Publication Date: 2011-12-08.
• Brief Description: This publication describes a FinFET with "faceted epi shape" and "half-wrap around silicide in s/d merged FinFET." The term "s/d merged FinFET" suggests that source/drain regions between fins are merged.
• Potential Anticipation (35 U.S.C. § 102): This is extremely relevant. It explicitly mentions "FinFET" (fin-shaped structures, gate structure, portions of claim 1), "epi shape" (epitaxial structures, portions of claim 1, 2, 3), and "s/d merged FinFET." The "s/d merged FinFET" could imply merged source/drain regions. While US9337193 describes spaced apart epitaxial structures with merged caps (claim 1), the "s/d merged FinFET" here refers to the merging of the source/drain regions themselves. This might be a point of distinction, where US9337193 ensures the epitaxial structures are spaced apart initially to control defects, then merges the caps. If "s/d merged FinFET" implies the epitaxial structures themselves are merged in this prior art, it would differ from the "epitaxial structures spaced apart from each other" clause of claim 1 of US9337193. However, the presence of "faceted epi shape" and "silicide" (relevant to salicide process in US9337193) makes it highly pertinent. Without the full text, it's hard to definitively say it anticipates claim 1's spaced apart epitaxial structures followed by merged caps if "s/d merged FinFET" means the epitaxial regions are merged directly.

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31. US8455313B1

• Full Citation: US8455313B1, "Method for fabricating finFET with merged fins and vertical silicide", International Business Machines Corporation, published June 4, 2013.
• Publication/Filing Date: Priority Date: 2011-12-27, Publication Date: 2013-06-04.
• Brief Description: This patent describes a method for fabricating a "FinFET with merged fins and vertical silicide." Merged fins refer to the fin-shaped structures themselves being merged, which is distinct from merged epitaxial source/drains or merged caps.
• Potential Anticipation (35 U.S.C. § 102): This reference teaches "FinFET" (fin-shaped structures, gate structure, portions of claim 1) and "merged fins." "Merged fins" is a structural feature of the fin itself, not necessarily the epitaxial regions or caps described in US9337193. The "vertical silicide" is related to contact formation (similar to claim 11 of US9337193). While it's a FinFET patent, its emphasis on "merged fins" differentiates it from the "spaced apart" epitaxial structures of claim 1 of US9337193, and it does not explicitly disclose the merged caps. Therefore, it is unlikely to anticipate claim 1 in its entirety.

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32. US20130200470A1

• Full Citation: US20130200470A1, "Semiconductor structure and method of fabricating the same", An-Chi Liu, published August 8, 2013.
• Publication/Filing Date: Priority Date: 2012-02-07, Publication Date: 2013-08-08.
• Brief Description: This publication describes a general "semiconductor structure and method of fabricating the same." The title is very broad.
• Potential Anticipation (35 U.S.C. § 102): A very general title; it is unlikely to anticipate the specific structural features of US9337193.

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33. US9006805B2

• Full Citation: US9006805B2, "Semiconductor device", United Microelectronics Corp., published April 14, 2015.
• Publication/Filing Date: Priority Date: 2013-08-07, Publication Date: 2015-04-14.
• Brief Description: This patent is explicitly identified as the parent application from which US9337193 claims continuation. It shares the same priority date as US9337193's parent application (August 7, 2013).
• Potential Anticipation (35 U.S.C. § 102): As US9337193 is a continuation of the application leading to US9006805B2, its disclosure is incorporated by reference, and it is not considered prior art for the purpose of anticipation under 35 U.S.C. § 102 for US9337193, assuming both patents cover the same inventive subject matter from the same priority date. It represents the same invention or a variation thereof from the same inventive lineage, not prior art in the sense of disclosing the invention before it was conceived.

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Most Relevant Prior Art Summary for Potential Anticipation of Claim 1:

Based purely on titles and the understanding of US9337193's novel elements, the most relevant prior art for potentially anticipating elements of US9337193's claims, particularly claim 1, would be those that combine FinFET structures with strained silicon and/or epitaxial source/drain regions. These include:

• US20040195624A1 ("Strained silicon fin field effect transistor"): Directly combines FinFET and strained silicon.
• US6888181B1 ("Triple gate device having strained-silicon channel"): Also combines a multi-gate device (FinFET type) with strained silicon.
• US20100144121A1 ("Germanium FinFETs Having Dielectric Punch-Through Stoppers"): Explicitly mentions FinFETs and Germanium, a common epitaxial strain material.
• US8362575B2 ("Controlling the shape of source/drain regions in FinFETs"): Focuses on FinFET source/drain shaping, which is often done via epitaxy.
• US20110298058A1 ("Faceted epi shape and half-wrap around silicide in s/d merged finfet"): This is perhaps the most relevant, as it describes "FinFET," "epi shape," and "s/d merged FinFET." The term "s/d merged FinFET" could imply a merging of source/drain regions, which would be a key point of comparison with US9337193's "epitaxial structures spaced apart from each other" followed by "at least two adjacent caps are merged together." The distinction would lie in what is merged and when it is merged, and specifically the presence of the separate "cap" layer that merges over spaced-apart epitaxial structures in US9337193.

These patents likely anticipate the broad concepts of FinFETs and the use of epitaxial structures for strain or source/drain formation (elements common to claims 1 and 7). However, the critical differentiating feature of "at least two epitaxial structures, disposed at one side of the gate structure and respectively directly contacting each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other; and at least two caps, respectively surrounding the epitaxial structures, wherein at least two adjacent caps are merged together" (Claim 1 of US9337193) appears to be the novel contribution that would need to be evaluated against the full disclosures of these prior art documents. Without the full text of the cited prior art, it is not possible to definitively state that any single reference anticipates this precise combination.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 9337193

This analysis identifies combinations of prior art references that would render the claims of US Patent 9337193 obvious to a person having ordinary skill in the art (PHOSITA), and explains the motivation for combining them.

Independent Claim 1 of US9337193

Independent Claim 1 defines a semiconductor device comprising:

1. At least two fin-shaped structures disposed on a substrate.
2. A gate structure covering the fin-shaped structures.
3. At least two epitaxial structures, disposed at one side of the gate structure and respectively directly contacting each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other.
4. At least two caps, respectively surrounding the epitaxial structures, wherein at least two adjacent caps are merged together.

The distinguishing features of Claim 1, particularly in combination, are the presence of spaced-apart epitaxial structures and merged adjacent caps that surround these epitaxial structures. The patent itself identifies a problem of "unwanted lattice defects on their interfaces" between adjacent epitaxial structures [cite: The full patent text, Description of the Prior Art]. The solution proposed is to have few lattice defects and enhanced stresses by using this specific configuration [cite: The full patent text, Summary of the Invention].

Prior Art References for Obviousness

The following prior art references are identified from the "Citations (33)" section of US9337193 as particularly relevant:

• US9006805B2 (Semiconductor device): This is the parent application of US9337193, filed on August 7, 2013, and its disclosure is incorporated by reference in its entirety [cite: The full patent text, CROSS REFERENCE TO RELATED APPLICATIONS]. As such, it is highly likely to disclose most, if not all, of the structural features of US9337193, including fin-shaped structures, gate structures, epitaxial source/drain regions, and possibly individual caps over these regions.
• US20040195624A1 (Strained silicon fin field effect transistor): This reference teaches the fundamental concept of FinFETs and the use of strained silicon for performance enhancement, which often involves epitaxial growth in source/drain regions.
• US20110298058A1 (Faceted epi shape and half-wrap around silicide in s/d merged finfet): The title of this reference explicitly mentions "s/d merged finfet" and "half-wrap around silicide," suggesting the concept of merging elements in the source/drain regions and using capping layers for silicide formation.

Obviousness Combination and Motivation

A person having ordinary skill in the art (PHOSITA) would have been motivated to combine the teachings of these references to achieve the claimed invention, particularly in light of known challenges in semiconductor device fabrication.

Combination: US9006805B2 in view of US20110298058A1 and general PHOSITA knowledge.

1. US9006805B2 (Primary Reference): As the parent application, US9006805B2 would teach the foundational elements of a FinFET device, including:

   • (a) At least two fin-shaped structures disposed on a substrate.
   • (b) A gate structure covering the fin-shaped structures.
   • (c) At least two epitaxial structures, disposed at one side of the gate structure and respectively directly contacting each fin-shaped structure. US9006805B2 would teach the formation of epitaxial source/drain regions for FinFETs, a common technique for introducing strain and enhancing performance, as also generally taught by US20040195624A1. US9006805B2 would likely show these epitaxial structures as distinct and potentially spaced apart to maintain individual fin integrity and crystalline quality. Furthermore, individual caps over these epitaxial structures would be a known technique for facilitating subsequent processing steps like silicide formation.

2. Motivation from PHOSITA Knowledge and US20110298058A1:

   • Problem Recognition: A PHOSITA, as explicitly noted in the background of US9337193, would be aware that "two adjacent epitaxial structures within the semiconductor device often generate unwanted lattice defects on their interfaces" when they are closely spaced or directly merged [cite: The full patent text, Description of the Prior Art]. This problem significantly impacts device performance.
   • Desire for Merged S/D: US20110298058A1 teaches the concept of "s/d merged finfet," which implies a desire for a larger or continuous source/drain region, likely to reduce resistance or improve contact area.
   • Combining Solution: A PHOSITA, seeking to achieve the benefits of a "merged S/D" configuration (as suggested by US20110298058A1) while simultaneously mitigating the known problem of lattice defects between directly merged epitaxial structures, would be motivated to:
     • Maintain the epitaxial structures spaced apart from each other (as likely shown or implied by US9006805B2) to preserve their crystalline quality and avoid interface defects.
     • Then, grow a subsequent capping layer (such as monocrystalline silicon, as described in US9337193 [cite: The full patent text, Detailed Description, FIG. 7]) over these spaced-apart epitaxial structures, allowing this capping layer to merge together between the adjacent epitaxial structures. This merged cap would provide the desired contiguous surface for subsequent contact formation (e.g., silicide, as implied by "half-wrap around silicide" in US20110298058A1), effectively creating a "merged S/D" contact region without compromising the quality of the underlying strained epitaxial structures.

This combination of maintaining spaced epitaxial structures to avoid defects, while merging a subsequent cap layer to create a larger, continuous contact region, represents an obvious design choice for a PHOSITA trying to optimize FinFET performance and address known manufacturing challenges. The structure and method disclosed in US9337193, where "the silicon cap 68 continuously grows on the surface of each of epitaxial structure 66 and gradually fills up the space between two adjacent epitaxial structures 66 until two adjacent silicon caps 68 merge together" [cite: The full patent text, Detailed Description, FIG. 7], directly implements this obvious solution.

Therefore, the combination of US9006805B2 (for the basic FinFET with epitaxial S/D and individual caps) with the motivation from US20110298058A1 (for merged S/D) and the general understanding of epitaxial defect challenges would render Claim 1 of US9337193 obvious.