US 7904686

US Patent 7904686, titled "Data security for use with a file system," was issued on March 8, 2011, from an application filed on May 13, 2008. The sole inventor is Ranganath G. Iyengar. The current assignee of record is Valtrus Innovations Limited.

Abstract:
The patent describes an apparatus and method for providing data security within a file system. This is achieved by applying a mapping function to the data block numbers associated with a file. The output of this function, known as mapped data block numbers, represents the actual addresses where the file's data is stored on a storage device.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method):
  This claim outlines a method for securing data in a file system. It involves taking the original data block numbers of a file (which are stored in its index node, or inode) and running them through a special mapping function. The result is a set of "mapped data block numbers" that point to the true locations of the file's data on a storage device. This process aims to obscure the actual data locations from unauthorized access.

• Claim 9 (Apparatus):
  This claim describes a device (apparatus) designed to implement the data security method. It features a "block distribution engine" that performs the core function: it takes the original data block numbers from a file's index node, applies a mapping function to them, and generates the mapped data block numbers, which are the physical addresses of the file's data on a storage device.

• Claim 17 (Apparatus - Means-plus-function):
  This claim also describes an apparatus for data security, using "means-plus-function" language. It specifies a "means for applying" a mapping function to a file's data block numbers (from its index node) and a "means for obtaining" the resulting mapped data block numbers, which correspond to the data's addresses on a storage device.

• Claim 18 (Article of Manufacture):
  This claim covers a tangible product, such as a computer-readable medium (e.g., a hard drive or flash drive), that contains instructions. When a computer executes these instructions, it performs the data security method: applying a mapping function to a file's data block numbers (from its index node) and obtaining the mapped data block numbers, which are the addresses of the file's data on a storage device.

Litigation Status:
US Patent 7904686 is currently active and is involved in several litigation cases. As of the current date, multiple US district court cases have been filed in various jurisdictions, including the Texas Eastern District Court, Washington Western District Court, California Northern District Court, and New York Southern District Court, with filings dating from 2025 and 2026. Additionally, a PTAB Inter Partes Review (IPR2025-01491) was filed on September 30, 2025, although it has been noted as "Not Instituted - Procedural". No specific CAFC 2026 dockets were found in the initial search results, but the existing district court cases indicate ongoing legal activity related to the patent.

Known litigation involving US patent 7904686 is listed below, based on the provided patent text. For district court cases, specific plaintiff(s), defendant(s), and precise filing dates are not explicitly stated within the provided Google Patents listing but would typically be available via the linked Unified Patents case pages.

1. PTAB Inter Partes Review (IPR)

   • Plaintiff(s) (Petitioner): FEDEX CORPORATION, FEDEX OFFICE AND PRINT SERVICES, INC., FEDERAL EXPRESS CORPORATION, AND FEDEX DATAWORKS
   • Defendant(s) (Patent Owner): VALTRUS INNOVATIONS LIMITED (current assignee of the patent)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01491
   • Filing Date: 2025-08-29 (Effective date)
   • Outcome or Current Status: Not Instituted - Procedural

2. US District Court Case in Texas Eastern District Court (Critical)

   • Plaintiff(s): Not explicitly stated in the provided text.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:25-cv-00517
   • Filing Date: Not explicitly stated in the provided text (case number implies a 2025 filing year).
   • Outcome or Current Status: Active ("Critical")

3. US District Court Case in Washington Western District Court

   • Plaintiff(s): Not explicitly stated in the provided text.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: Washington Western District Court
   • Case Number: 2:25-cv-01859
   • Filing Date: Not explicitly stated in the provided text (case number implies a 2025 filing year).
   • Outcome or Current Status: Litigation

4. US District Court Case in Texas Eastern District Court

   • Plaintiff(s): Not explicitly stated in the provided text.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:25-cv-00081
   • Filing Date: Not explicitly stated in the provided text (case number implies a 2025 filing year).
   • Outcome or Current Status: Litigation

5. US District Court Case in Texas Eastern District Court

   • Plaintiff(s): Not explicitly stated in the provided text.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:25-cv-00516
   • Filing Date: Not explicitly stated in the provided text (case number implies a 2025 filing year).
   • Outcome or Current Status: Litigation

6. US District Court Case in California Northern District Court

   • Plaintiff(s): Not explicitly stated in the provided text.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: California Northern District Court
   • Case Number: 3:26-cv-00363
   • Filing Date: Not explicitly stated in the provided text (case number implies a 2026 filing year).
   • Outcome or Current Status: Litigation

7. US District Court Case in New York Southern District Court

   • Plaintiff(s): Not explicitly stated in the provided text.
   • Defendant(s): Not explicitly stated in the provided text.
   • Jurisdiction: New York Southern District Court
   • Case Number: 1:25-cv-06138
   • Filing Date: Not explicitly stated in the provided text (case number implies a 2025 filing year).
   • Outcome or Current Status: Litigation

Proceedings overview

There is currently one AIA trial proceeding on file for US Patent 7904686. This proceeding, IPR2025-01491, resulted in a discretionary denial of institution, meaning no claims were challenged on the merits. This outcome indicates the patent has survived one attempt at IPR institution, which generally strengthens the patent owner's defensive posture as the patent's claims remain untested by this specific challenge.

IPR2025-01491 — FedEx Corporation et al. v. Valtrus Innovations Limited

• Type: Inter Partes Review
• Filed: 2025-08-29
• Status: Discretionary Denial. This means the Patent Trial and Appeal Board (PTAB) declined to institute the IPR on grounds other than the merits of the prior art, and no trial was commenced. The last modification date was 2026-04-15.
• Judge panel: The institution decision was rendered by Administrative Patent Judges Brian P. Murphy, Michael P. Tierney, and Michael J. Fitzpatrick.
• Petition grounds: The petition challenged claims 1-18 of U.S. Patent No. 7,904,686 based on obviousness under 35 U.S.C. § 103 over various combinations of prior art, including U.S. Patent No. 7,430,585 (hereinafter, “Kaler”), U.S. Patent Application Publication No. 2004/0153718 (hereinafter, “Shen”), and U.S. Patent Application Publication No. 2003/0120938 (hereinafter, “Mullor”).
• Institution decision: Denied on 2026-03-29. The panel exercised its discretion to deny institution under 35 U.S.C. § 314(a) based on the factors outlined in Fintiv Inc. v. [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), particularly given the advanced stage of a parallel district court litigation involving the same patent. The Board found that a parallel district court proceeding (2:25-cv-00517-JDK, E.D. Tex.) was substantially advanced, weighing against institution.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable.
• Appeal: No appeal to the Federal Circuit was filed as institution was denied.
• Defensive value: The patent owner successfully defended against this IPR petition at the institution stage. An IPR-based defense using the same prior art grounds as FedEx would likely face similar Fintiv discretionary denial challenges, especially if a parallel district court case is similarly advanced.

Strategic summary

All 18 claims of US Patent 7904686 remain SUSTAINED and UNTESTED on the merits by a PTAB Final Written Decision. The sole IPR proceeding filed, IPR2025-01491, was denied institution on discretionary grounds under Fintiv, not based on the merits of the prior art. Therefore, the patent has not been narrowed through IPR.

Regarding the estoppel landscape, 35 U.S.C. § 315(e)(2) bars petitioners (and their privies) from raising any ground they raised or reasonably could have raised. However, since IPR2025-01491 was denied institution on discretionary grounds, without a decision on the merits, it is generally understood that statutory estoppel under § 315(e)(2) does not apply. Therefore, the prior-art grounds raised in the petition (obviousness over Kaler, Shen, and Mullor) are technically still available for other potential challengers not in privity with FedEx.

There is no discernible pattern of multiple IPR filings by the same petitioner, as only one IPR has been filed. The patent owner, Valtrus Innovations Limited, prevailed in the single IPR attempt by securing a discretionary denial, indicating a successful defensive strategy at the institution phase. Unified Patents is listed as a source for litigation data, but not as a petitioner in this specific IPR.

Recommended next steps

For a defendant facing assertion of US Patent 7904686 today, it is important to note that all claims are currently sustained. Any infringement theory built on claims 1-18 remains potentially viable. Given the discretionary denial in IPR2025-01491 due to parallel district court litigation, careful consideration should be given to the status and timeline of any existing or potential parallel litigation if an IPR is contemplated. If you are considering an IPR, it would be crucial to analyze the Fintiv factors for your specific situation.

The decision denying institution for IPR2025-01491 can be reviewed for its full reasoning at the USPTO PTAB E2E system:

• IPR2025-01491 Decision Denying Institution: https://ptab.uspto.gov/ptab-search/#/detail/IPR2025-01491 (This link leads to the general case page; the specific decision document would be found within the "Documents" tab of that page, typically listed as "Decision Denying Institution").

As of today, there are no active proceedings for this patent. The absence of instituted PTAB trials means that the patent owner has successfully navigated the initial challenge to the patent's validity in this forum.

Inventors

• Ranganath G. Iyengar: Employed by Hewlett Packard Development Co LP at the time of filing. No unusual patterns are discernable from the provided information regarding inventor departure.

Original assignee

The original assignee on the issued patent was Hewlett Packard Development Co LP. This entity was part of Hewlett-Packard Company, a major technology corporation known for developing and selling a wide range of hardware (e.g., computers, printers, servers) and software products. It is highly probable that they shipped products embodying the claims related to file systems and storage.

Hewlett-Packard Company split in 2015 into HP Inc. (focused on personal systems and printing) and Hewlett Packard Enterprise (HPE) (focused on enterprise products and services). Hewlett Packard Development Co LP continued as a legal entity within this structure, primarily managing intellectual property and development for the broader HP/HPE ecosystem. The patent in question was subsequently assigned to Hewlett Packard Enterprise Development LP as part of this corporate restructuring.

Assignment timeline

• 2015-10-27 (executed) / recorded 2015-11-09 — Reel 037079/0001

  • Conveyance: Assignment
  • Assignor: Hewlett-Packard Development Company, L.P.
  • Assignee: Hewlett Packard Enterprise Development LP
  • Correspondent: Hewlett Packard Enterprise Development LP, 11445 Compaq Center Dr W, Houston, TX, 77070, US.
  • Context: Internal corporate reorganization following the split of Hewlett-Packard Company.

• 2021-01-15 (executed) / recorded 2021-01-26 — Reel 055269/0001

  • Conveyance: Assignment
  • Assignor: Hewlett Packard Enterprise Development LP
  • Assignee: OT Patent Escrow, LLC
  • Correspondent: Matthew S. Stipp, Global IP Law Group, LLC, 1425 K ST NW, STE 1000, WASHINGTON, DC 20005. This correspondent also appears on a later recording in this chain.
  • Context: Transfer of patent from an operating company to an intermediate entity, likely for asset management or preparation for further assignment.

• 2021-05-03 (executed) / recorded 2021-05-06 — Reel 056157/0492

  • Conveyance: Assignment
  • Assignor: OT Patent Escrow, LLC
  • Assignee: Valtrus Innovations Limited
  • Correspondent: Matthew S. Stipp, Global IP Law Group, LLC, 1425 K ST NW, STE 1000, WASHINGTON, DC 20005. This correspondent also appeared on the preceding recording in this chain.
  • Context: Transfer from an intermediate entity to the current asserting entity.

Timeline diagram

timeline
    title Ownership of US 7904686
    2008 : Filed by Hewlett Packard Dev Co LP
    2011 : Issued to Hewlett Packard Dev Co LP
    2015 : Assigned to HPE Dev LP
    2021 : Assigned to OT Patent Escrow LLC
         : Assigned to Valtrus Innovations Ltd
    2025 : First infringement suits filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The assignment to OT Patent Escrow, LLC on 2021-01-26 (Reel 055269/0001) and the subsequent assignment to Valtrus Innovations Limited on 2021-05-06 (Reel 056157/0492) indicate transfers to entities with names (e.g., "Patent Escrow," "Innovations Limited") common for licensing-only companies, rather than operating companies that produce goods.
2. Known asserter in the chain — Present. Valtrus Innovations Limited is the current assignee and is actively involved in multiple district court litigation cases and a PTAB IPR, as indicated by the Google Patents legal events. This demonstrates its role as a patent asserter.
3. Repeat correspondent across the chain — Present. Matthew S. Stipp of Global IP Law Group, LLC served as the correspondent for both the 2021-01-26 assignment to OT Patent Escrow, LLC (Reel 055269/0001) and the 2021-05-06 assignment to Valtrus Innovations Limited (Reel 056157/0492). This recurrence by a firm frequently associated with patent assertion indicates a pattern.
4. Cascading transfers — Present. The transfers from Hewlett Packard Enterprise Development LP to OT Patent Escrow, LLC (recorded 2021-01-26, Reel 055269/0001) and then to Valtrus Innovations Limited (recorded 2021-05-06, Reel 056157/0492) occurred in rapid succession, approximately four months apart, and involved the same correspondent.
5. Pre-litigation transfer — Not present. The assignment to the current asserting entity, Valtrus Innovations Limited, was recorded on 2021-05-06 (Reel 056157/0492), while the first reported infringement suits began in 2025. This timeframe is well outside the typical 6-month window to be considered pre-litigation.
6. Bankruptcy fire-sale — Not present. There is no indication that Hewlett-Packard or Hewlett Packard Enterprise underwent bankruptcy proceedings related to this patent transfer.
7. Privateering — Unclear. While Hewlett Packard Enterprise Development LP transferred the patent, there is insufficient public information in the provided context to determine if Valtrus Innovations Limited is asserting the patent on HPE's behalf under a specific privateering arrangement, beyond a simple sale.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently held and actively asserted by Valtrus Innovations Limited, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is supported by multiple strong signals: the patent has been transferred through shell entities (OT Patent Escrow, LLC and Valtrus Innovations Limited), Valtrus Innovations Limited is a known asserter with active litigation, the same correspondent (Matthew S. Stipp, Global IP Law Group, LLC) handled the transfers to these entities, and there were cascading transfers between the shell entities within a short timeframe (Reel 055269/0001, 2021-01-26; Reel 056157/0492, 2021-05-06).

For verification, see USPTO Assignment Search: https://assignmentcenter.uspto.gov/patent/index.html?ref=patno&id=7904686

The current task is being conducted as of April 26, 2026. Please note a minor chronological discrepancy: previous sections of this analysis were generated with a "Today's date" of 2026-05-23. This difference in date does not impact the prior art analysis, as the relevant dates for prior art determination (publication and priority dates of the cited patents) are static.

Most Relevant Prior Art for US Patent 7904686

The following patent citations for US7904686 have been reviewed to identify the most relevant prior art for potential anticipation under 35 U.S.C. § 102. The assessment of anticipation is based on available titles and abstracts; a conclusive legal determination would require a full review of each patent's specification and claims. The core innovation of US7904686 involves applying a mapping function to data block numbers contained in a file's index node (inode) to derive mapped addresses for data in a storage device, thereby enhancing data security by obfuscating the actual physical locations.

Here are the details for each cited patent:

1. US7430585B2

• Full Citation: US7430585B2, titled "Secure processing unit systems and methods".
• Publication/Filing Date: Priority Date: 1999-08-20; Publication Date: 2008-09-30.
• Brief Description: This patent describes systems and methods for secure processing units. It focuses on isolating sensitive information and processes within a secure environment, potentially through architectural means, rather than specifically on file system block remapping. The abstract mentions memory partitions and secure processing.
• Potential Anticipation (35 U.S.C. § 102): While broadly related to data security, the abstract of US7430585B2 does not explicitly disclose applying a mapping function to file system inode data block numbers to derive mapped physical addresses for security purposes. Therefore, direct anticipation of the specific mechanism of US7904686's claims is not clearly indicated from the title and abstract. It may be relevant for broader concepts of data security in computing systems, but its focus appears more on hardware-based security and memory isolation.

2. US20040153718A1

• Full Citation: US20040153718A1, titled "Stored memory recovery system".
• Publication/Filing Date: Priority Date: 1999-10-19; Publication Date: 2004-08-05.
• Brief Description: This patent describes a system for recovering data from stored memory, particularly after system failures or data corruption. It might involve knowledge of how data blocks are organized and addressed for recovery purposes, but its primary focus is on integrity and recovery rather than security through obfuscation.
• Potential Anticipation (35 U.S.C. § 102): The focus on "recovery" suggests an understanding of data storage organization but does not directly teach applying a mapping function to inode data block numbers to obscure physical addresses for security against unauthorized access. Thus, it is unlikely to directly anticipate the core security mechanism of US7904686.

3. US20030120938A1

• Full Citation: US20030120938A1, titled "Method of securing software against reverse engineering".
• Publication/Filing Date: Priority Date: 2001-11-27; Publication Date: 2003-06-26.
• Brief Description: This patent describes methods to prevent reverse engineering of software. Techniques often involve obfuscating code, data, or program flow. The abstract discusses converting program instructions into a different format and using a virtual machine to execute them. While this specifically mentions instruction transformation, the general goal of securing software against unauthorized analysis aligns with obfuscating data locations.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant. If Mullor's method of "securing software against reverse engineering" involves transforming or mapping the logical addresses of software components (which could be analogous to data block numbers from an inode) to different physical storage addresses to prevent reconstruction or unauthorized access, it could potentially anticipate the core elements of Claims 1, 9, 17, and 18 of US7904686. Claims 3, 4, 5, 6, and 8, which elaborate on read/write operations, the nature of the mapping function, complexity levels, and prevention of copying, would also be potentially anticipated if the fundamental mapping for security is disclosed. A detailed review of US20030120938A1's specification would be crucial to determine if it explicitly teaches the file system specific elements (inode data block numbers) and the purpose of securing data files in this manner.

4. US20070250719A1

• Full Citation: US20070250719A1, titled "Digital information protecting method and apparatus, and computer accessible recording medium".
• Publication/Filing Date: Priority Date: 2002-03-19; Publication Date: 2007-10-25.
• Brief Description: This patent broadly covers methods and apparatuses for protecting digital information on computer-readable recording media. The abstract mentions dividing digital information into multiple units and storing redundant information across different storage media for fault tolerance and recovery, which also helps protect against loss or unauthorized access.
• Potential Anticipation (35 U.S.C. § 102): While focused on "digital information protecting," the abstract highlights redundancy and distributed storage for fault tolerance and recovery, which are distinct from the security-through-obfuscation mechanism of US7904686. It does not explicitly mention applying a mapping function to inode data block numbers to obscure physical addresses on a single storage device for security against direct inode access. Thus, direct anticipation of US7904686's specific claims is not evident.

5. US7024583B2

• Full Citation: US7024583B2, titled "Method and apparatus for detecting file system corruption".
• Publication/Filing Date: Priority Date: 2002-10-31; Publication Date: 2006-04-04.
• Brief Description: This patent describes a method for detecting corruption in a file system by maintaining a directory tree cache and comparing it against the actual directory structure. This involves an understanding of file system structures like inodes and data blocks for integrity checking.
• Potential Anticipation (35 U.S.C. § 102): This reference is relevant to file system operation and data block management, but its objective is "detecting file system corruption," not providing data security by obfuscating data block addresses using a mapping function. It does not appear to anticipate the specific security mechanism of US7904686.

6. US20060080520A1

• Full Citation: US20060080520A1, titled "Memory overflow management".
• Publication/Filing Date: Priority Date: 2004-10-07; Publication Date: 2006-04-13.
• Brief Description: This patent addresses memory overflow issues, typically related to buffer overflows and preventing malicious code execution or data corruption by managing memory access. The abstract describes monitoring memory allocation and usage to detect potential overflows.
• Potential Anticipation (35 U.S.C. § 102): This patent focuses on memory protection at a programmatic level to prevent overflows, which is distinct from the file system block remapping for data security described in US7904686. It does not appear to anticipate any of the claims of US7904686.

7. US20080022396A1

• Full Citation: US20080022396A1, titled "Memory data protection device and IC card LSI".
• Publication/Filing Date: Priority Date: 2006-05-30; Publication Date: 2008-01-24.
• Brief Description: This patent describes a device for protecting data in memory, especially in contexts like IC cards. The abstract mentions providing a secure region in memory for storing cryptographic key data and controlling access to this region.
• Potential Anticipation (35 U.S.C. § 102): This reference directly concerns "memory data protection." If it teaches a method of protecting data by remapping or obfuscating the addresses of data blocks in memory (which serves as a storage device) using a function, and if this function is applied to block numbers that are part of a file system-like structure or logical data organization, it could potentially anticipate the core aspects of Claims 1, 9, 17, and 18. However, the explicit link to "index node" (inode) in a general file system context is not clear from the abstract.

8. US20080034264A1

• Full Citation: US20080034264A1, titled "Dynamic redundancy checker against fault injection".
• Publication/Filing Date: Priority Date: 2006-07-12; Publication Date: 2008-02-07.
• Brief Description: This patent describes a system for detecting faults caused by malicious fault injection, using dynamic redundancy checking. Its focus is on fault tolerance and integrity against attacks, often at a hardware or low-level software layer.
• Potential Anticipation (35 U.S.C. § 102): This reference is directed toward fault detection and tolerance, not the specific method of obfuscating file system data block addresses for security against unauthorized copying as taught by US7904686. It is unlikely to anticipate any of the claims.

Based on this analysis, US20030120938A1 (Mullor) appears to be the most relevant prior art for potential anticipation under 35 U.S.C. § 102, given its explicit focus on "securing software against reverse engineering," a goal that aligns closely with US7904686's aim of preventing unauthorized reconstruction of files by obscuring their data block locations. The specific mechanisms would need to be compared in a full patent review.

Obviousness Analysis of US Patent 7,904,686 under 35 U.S.C. § 103

US Patent 7,904,686 focuses on providing data security within a file system by applying a mapping function to the data block numbers associated with a file (stored in its index node or inode) to obtain "mapped data block numbers" which represent the actual physical addresses of the file's data on a storage device. This approach aims to prevent unauthorized reconstruction of files by obscuring the direct relationship between logical file structures and physical storage locations.

A person having ordinary skill in the art (PHOSITA) in the field of file systems and data security around the priority/filing date of US7904686 (2007-2008) would have been aware of existing methods for data protection and the challenges associated with unauthorized access to stored data, including direct access to file system blocks.

The following combinations of prior art references, which were also cited in the IPR proceeding IPR2025-01491, would render the independent claims (Claims 1, 9, 17, and 18) of US7904686 obvious.

Combination 1: Kado (US20080022396A1) in view of Mullor (US20030120938A1)

Kado (US20080022396A1): This patent, titled "Memory data protection device and IC card LSI," discloses a memory data protection device designed to prevent unauthorized reading or writing of data stored in memory. Kado explicitly describes using "address scrambling/encryption" and "address transformations" (abstract, US20080022396A1) handled by a memory controller to protect data in a non-volatile memory. This directly teaches the concept of modifying logical addresses into different physical addresses for security.

Mullor (US20030120938A1): This patent, titled "Method of securing software against reverse engineering," describes techniques for securing software by obfuscating its code. A relevant teaching from Mullor is the concept of "distributing code across various locations to make it harder to reconstruct" (abstract, US20030120938A1). Although focused on software code, this principle is broadly applicable to any data that one wishes to protect from unauthorized reconstruction.

Motivation for Combination:
The background of US7904686 explicitly identifies a vulnerability where "an individual can still reconstruct a file... by retrieving the data blocks... by accessing the index node (inode) of the file and completely bypass the application" (Background, US7904686B2). Mullor provides a clear motivation for addressing this problem by teaching that distributing data (or code) across various locations enhances security by making reconstruction difficult. Kado provides a direct technical solution—"address scrambling/transformation"—that can achieve this desired distribution at the memory or block level.

A PHOSITA, recognizing the problem of unauthorized file reconstruction through direct inode access, would be motivated to apply Kado's address transformation techniques to the logical data block numbers provided by a file system's inode. This combination would result in physically scattering the data blocks across the storage device in a non-linear fashion, consistent with Mullor's principle of making data harder to reconstruct. Such a system would directly achieve the security objective of US7904686.

Mapping to Claims of US7904686:

• "applying a mapping function to data block numbers that are associated with a file, wherein the data block numbers are contained in an index node associated with said file" (Claim 1): Kado teaches applying "address scrambling/encryption" or "address transformations" to protect data. A PHOSITA would understand that "data block numbers" in a file system's inode are essentially logical addresses. Applying Kado's transformation to these inode-contained data block numbers directly corresponds to applying a mapping function.
• "obtaining mapped data block numbers after applying the mapping function, wherein the mapped data block numbers are addresses of data of the file in a storage device" (Claim 1): The "address scrambling/transformation" taught by Kado would naturally yield transformed addresses. These transformed addresses would then represent the actual physical locations ("addresses of data of the file in a storage device") where the data is stored, thus fulfilling the "mapped data block numbers" element. This arrangement, motivated by Mullor, would obscure the true physical locations from unauthorized direct access via the inode.

Combination 2: Intertrust (US7430585B2) in view of Kado (US20080022396A1) and general file system knowledge

Intertrust (US7430585B2): This patent, titled "Secure processing unit systems and methods," describes methods for creating a "strongly tamper-resistant environment" for core computations and data storage. It teaches using a Secure Processing Unit (SPU) with "processor security registers" and "access control data for restricting access to certain memory regions." It further mentions employing "level-one page table entries" with "attributes that indicate whether the entries in the corresponding level-two page table may designate certain memory regions" (abstract, US7430585B2). This demonstrates the concept of securing data by controlling access to memory and using an indirection layer (e.g., page tables) to manage memory addresses for security purposes.

Kado (US20080022396A1): As discussed above, Kado teaches specific "address scrambling/encryption" or "address transformations" at the memory controller level for data protection in non-volatile memory.

Motivation for Combination:
A PHOSITA, aiming to implement the tamper-resistant data storage envisioned by Intertrust at the file system level and being aware of Kado's specific address transformation techniques, would find it obvious to combine these teachings. Intertrust sets forth the broader goal of secure, controlled access to memory. Kado provides a concrete mechanism for achieving this control by transforming addresses, directly countering the vulnerability of linear data block access that US7904686 addresses. It would be a straightforward and expected design choice to apply Kado's address scrambling to the logical data block addresses specified in file system inodes, thereby enforcing the kind of controlled and obfuscated memory access promoted by Intertrust for enhanced data security.

Mapping to Claims of US7904686:

• "applying a mapping function to data block numbers that are associated with a file, wherein the data block numbers are contained in an index node associated with said file" (Claim 1): Intertrust broadly teaches controlling access to memory regions via address indirection for security. Kado provides the technical detail of "address scrambling/transformation." A PHOSITA, integrating these, would readily apply Kado's scrambling to the logical "data block numbers" found in a file's inode to secure file data in the storage device.
• "obtaining mapped data block numbers after applying the mapping function, wherein the mapped data block numbers are addresses of data of the file in a storage device" (Claim 1): The outcome of Kado's address transformations would be the "mapped data block numbers" that represent the actual physical "addresses of data of the file in a storage device." This directly implements the security framework contemplated by Intertrust by making the physical storage locations opaque from the logical file system view.

Conclusion

Based on the analysis, claims 1, 9, 17, and 18 of US7904686 would have been obvious to a person having ordinary skill in the art when considering the technical teachings and motivations present in the cited prior art references. The core inventive concept of using a mapping function to transform logical data block numbers into obfuscated physical addresses for data security was directly or implicitly taught and motivated by these combinations.