US 7836244

I'll search for litigation and docket information on this specific patent number before summarizing.

Let me run additional targeted searches to confirm whether any 2026 litigation or CAFC docket cites this exact patent.

US Patent 7,836,244 — Summary

Source of record: The Google Patents full text you supplied (fetched 2026‑09‑30) is the authoritative source here; it agrees with the corroborating hits I found (PubChem patent record, patentimages PDF of the granted patent, and the JP family member JP2008117516A).

Bibliographic data

Abstract (verbatim)

"A method of providing block state information in a semiconductor memory device including a flash memory comprises storing block state information on at least one bad block of the flash memory and a plurality of reserved blocks which replace the at least one bad block, and providing the stored block state information to a user in response to a command provided by the user."

Plain-language overview of the independent claims

Claim 1 (method): In a flash‑memory device, store in the flash memory information about (i) bad block(s), (ii) the reserved blocks that replace them, specifically including the number of bad blocks, the number of reserved blocks present, and the number of available reserved blocks. Then, on a user‑issued command, report that block‑state information back to the user. Also, issue a warning when the count of available reserved blocks reaches a reference value, where that reference value is variably set by a vendor in a vendor‑specific area of a command having one of the register values, and that same command determines when the warning fires. The method runs during a read operation and/or a write operation of the flash memory.

Claim 7 (method): Similar storage of bad‑block/reserved‑block state information, but the reporting is tied specifically to the ATA 'SMART READ DATA' command, and the warning is delivered via the ATA 'SMART RETURN STATUS' command when the capacity or number of reserved blocks falls to a predetermined level. As in claim 1, that predetermined warning level is variably set by a vendor in a vendor‑specific area of a command having one of the register values, and that command determines the warning time point. Again, performed during a read and/or write operation of the flash memory.

Dependent claims: Claim 2 — store the block‑state info in the flash memory's meta blocks (which hold block and mapping information). Claim 3 — the command is the ATA 'SMART READ DATA' command. Claim 4 — the command is a vendor‑specific ATA command. Claim 5 — determine the warning time point using a vendor‑specific ATA command. Claim 6 — the device is an SSD using NAND flash memory. Claim 8 — determine the warning time point with a vendor‑specific ATA command.

The specification grounds these on the ATA/S.M.A.R.T. command set: 512‑byte 'SMART READ DATA' payload with vendor‑specific byte regions holding SMART data version (bytes 0–1), amount of useful information (2–3), number of reserved blocks (4–7), number of additional bad blocks (8–11), and number of initial bad blocks (12–15); and 'SMART RETURN STATUS' (feature register DAh) with Cylinder Low/High register pairs 4Fh/C2h vs. F4h/2Ch for the warning state. The vendor‑settable warning threshold is described via a sub‑command (feature register E0h) with the reference value in the Sector Count register.

Legal status — note the conflict in the record

The authoritative Google Patents data you supplied shows two inconsistent entries, which I am reporting literally rather than reconciling:

• A legal‑status label of "Expired – Fee Related" with an "Adjusted expiration" of 2028‑01‑13; and
• Legal Events showing a 2014 fee payment (4th year), then "Lapse for failure to pay maintenance fees" (2018‑12‑24) and "Expired due to failure to pay maintenance fee," effective 2018‑11‑16, followed by "Patent expired for failure to pay maintenance fees" (2019‑01‑15).

So the patent appears to have lapsed in November 2018 for non‑payment of maintenance fees, even though the nominal term (20 years from the Nov 1, 2007 filing, plus adjustment) would have run to January 2028. I flag this as a genuine discrepancy in the source rather than asserting one figure is correct.

Litigation / CAFC 2026 docket check

I found no evidence of any litigation, PTAB proceeding, or Federal Circuit appeal involving US 7,836,244 in 2026 (or at any time).

What my searches did return, and why none of it is an infringement suit on this patent:

1. A PTAB petition document (ptacts.uspto.gov) containing the string "7836244" inside a large table of patent numbers (alongside 7818489, 7861122, etc.) with a "US‑PGPUB; USPAT … 2021/09/27" query line. This looks like a prior‑art search‑strategy string within a petition exhibit, not a challenge to the '244 patent itself. I could not confirm from the snippet which petition or whether the patent was even material to it — treat this as unverified.
2. Justia "cited by" listings (e.g., US 11,288,203; US 9,652,376; US 11,275,695) which merely show later patents citing 7,836,244 as prior art — not litigation.
3. A false positive: French publication FR2413409B1 carries application number FR7836244A — a 1978 brominated‑polystyrene chemistry patent with no relationship to this US patent. Different identifier class entirely.

Samsung is heavily litigated in 2026 (e.g., IOENGINE LLC, E.D. Tex. case 2:26‑cv‑00866, asserting US 7,861,006 / 9,059,969 / 10,397,374 / 10,447,819 / 10,992,786; and Collision Communications), but none of those patents is 7,836,244, and I found nothing naming this patent.

Confidence and caveats

• Bibliographic data, abstract, and claims: high confidence — taken directly from the authoritative full text you provided and corroborated by independent sources.
• Legal‑status/expiration: medium confidence — the source is internally contradictory (see above).
• No‑litigation finding: medium confidence. I could not query USPTO PatentCenter/PTAB or CAFC docket systems directly, only general web search; the "7836244" hits above were indexed documents rather than live docket records. A negative can't be proven by search alone, so treat "no known litigation" as an absence of evidence rather than affirmative proof.

I'll run targeted searches across litigation-focused sources for this specific patent number.

Let me check the specialized litigation databases directly.

Litigation search: US Patent 7,836,244

Bottom line

I found no litigation — no district court case, no ITC investigation, no PTAB proceeding, no CAFC appeal — involving US 7,836,244 (US 7,836,244 B2), at any time, and none pending as of today.

To be precise about what that means: this is an absence of evidence, not affirmative proof of non-litigation. My searches hit indexed web documents and aggregator pages (Justia, PubChem, Google Patents/PTAB petition PDFs, Stanford NPE database snippets), not live PACER/CAFC/PTAB docket queries, which I could not execute directly in this session. Treat the finding as "no known litigation identified," with that limitation stated up front.

What the case list would look like

Because no case was identified, there is no plaintiff/defendant/jurisdiction/case-number/filing-date/status table to populate. I will not manufacture one. The only way to state it accurately is:

What the searches actually returned, and why none of it is a hit on '244

1. A PTAB prior-art search-strategy string containing "7836244." A petition exhibit in the PTAB document set lists patent numbers in a table — "7406563" | "7581078" | "7702846" ... "7818489" | "7836244" | "7861122" with the query line US-PGPUB; USPAT … OR … 2021/09/27 14:33. This is an examiner/petitioner search query string, not a challenge to the '244 patent. Nothing in the retrieved text ties the '244 patent to the petition's grounds. Consistent with the earlier-generated section, I could not confirm which petition this belongs to. Unverified and immaterial.

2. Justia "cited by" tables. Pages for US 11,288,203, US 9,652,376, US 10,884,915, etc., list "7836244 | November 16, 2010 | Kim et al." in their reference tables. That is US 7,836,244 appearing as prior art cited against later patents — which is the opposite of litigation involving it. It is, however, useful corroboration of the bibliographic data (Nov 16, 2010 grant; Kim et al.) already in the record you supplied.

3. API/aggregator pages (PubChem US-7836244-B2, a wiki mirror) — bibliographic echoes only, no litigation.

4. CPC classification hits — US 7,836,244 is classified in G06F 12/0246 (flash memory address translation) and G11C 16/0483. This places it in the flash-management art where the Radian Memory Systems family (which cites '244) litigates, but citing is not being asserted.

5. "7,836,244" / "7836244" as a case-number substring. A trademark record (quickcompany.in, notice no. 7836244) and unrelated dockets surface on bare-number queries. As flagged previously, the French publication FR2413409B1 (application FR7836244A, 1978 brominated-polystyrene chemistry) is a false-positive identifier class entirely and must not be confused with the US patent.

Cross-checks confirming the negative

• Samsung-specific flash litigation. The 2008 Spansion v. Samsung ITC/Delaware campaign (NAND flash patents) predates and does not name '244; those were Spansion charge-trapping patents, not Samsung's own '244.
• 2026 Samsung campaigns. The IOENGINE LLC suits (five patents: 7,861,006 / 9,059,969 / 10,397,374 / 10,447,819 / 10,992,786), Headwater Research (2:24-cv-00627), Staton Techiya, and Network-1 Technologies matters all name different patent numbers. None asserts 7,836,244. The identical trap here is US 9,270,244 (Samsung v. Staton Techiya, IPR2022-00281) — a different patent whose number shares the "244" suffix. I excluded it deliberately; do not let a "244" match pull it in.
• Enforcement incentives point the same way. US 7,836,244 was a Samsung-owned, Samsung-assigned patent (recorded Nov 1, 2007, effective Oct 31, 2007) never reassigned in the record. It never left a large operating company's portfolio into NPE hands, which is the usual precondition for assertion litigation. And its maintenance-fee lapse effective 2018-11-16 (reported in the prior section) removed any residual assertion prospect after that date.

Two discrepancies in the record you should be aware of

• Prior section's internal conflict between the "Expired – Fee Related / adjusted expiration 2028-01-13" label and the LAPS/STCH/FP events showing expiration effective 2018-11-16. This conflict is in the source; I did not reconcile it and neither should you without checking PatentCenter. It is relevant here because a lapsed patent cannot be asserted for post-lapse infringement — reinforcing the no-litigation finding, but only if the lapse date is right.
• Date inconsistency in my tooling environment. The task header states the current date as April 26, 2026, but a search result (sammyguru.com) is dated September 24, 2026 and describes an IOENGINE/Samsung suit filed September 22. I flag this rather than silently adopting either date; it does not change the no-litigation finding on '244.

Caveats and confidence

Recommended verification if you need a litigation-grade negative: query PACER (all districts, party = Samsung Electronics and patent = 7,836,244), the CAFC docket system, and the PTAB API/PatentCenter for the patent's "Litigation" and "Post-Grant" tabs. Those are authoritative and I could not reach them in this session.

One drafting note in case this is for an infringement/validity opinion or an FTO clearance: given the patent's apparent 2018 lapse and January 2028 nominal term figure in conflict, do not represent to a client that '244 is expired — represent that the record is contradictory and must be verified against USPTO fee records.

I'll verify the "no PTAB activity" default with targeted searches before writing up.

Let me confirm with a few more targeted queries.

One search hit mentioned a "'244 patent" asserted by Valtrus Innovations. I need to check whether that's this Samsung patent.

PTAB / AIA Trial Proceedings — US 7,836,244

Canonical source used: the structured "PTAB proceedings on file" block (USPTO Open Data Portal ingest) supplied in this prompt. Web search was used only to look for activity the ODP has not indexed. No proceeding numbers are invented below.

Proceedings overview

There are zero (0) AIA trial proceedings on file against US 7,836,244 — no IPR, no PGR, no CBM — and therefore no claims invalidated, none sustained, none settled, and no institution decisions; the defensive posture for a defendant is that this is an untested patent whose operative threat is not PTAB precedent but its own legal status: it lapsed for non-payment of maintenance fees effective 2018-11-16 and no party has ever challenged its claims at the Board.

Two caveats that matter more than the PTAB count:

• The absence of PTAB activity is not evidence the claims are strong. It is consistent with the patent having died on the maintenance-fee docket in 2018, which removes the usual commercial incentive to file.
• A patent-expiration posture is not a substitute for an invalidity position if the patent is ever revived or if a demand letter is pending — see "Recommended next steps."

No proceedings to report

Because the structured data returns an empty AIA-trial set, I cannot populate the per-proceeding template (type / filed date / status / panel / grounds / institution / FWD / settlement / appeal) — doing so would mean fabricating proceeding numbers, which the task expressly forbids. Instead, here is what the search actually surfaced, so you can see the negative was checked rather than assumed:

Strategic summary

Claim status. All 8 claims of US 7,836,244 — independent claims 1 and 7 and dependent claims 2–6 and 8 — are UNTESTED at the PTAB. None is canceled, none is confirmed, and no estoppel has attached to anyone. That is a genuinely unusual posture: independent claim 1 carries a fairly narrow, machine-particular limitation set (specific enumerated counts of bad/reserved/available-reserved blocks; a vendor-settable reference value in a vendor-specific area of a command having one of the register values; execution during a read and/or write operation). Those are exactly the kind of "receiver-side / protocol-register" limitations that have historically been vulnerable to § 103 combinations of the ATA/SSD-health art cited on the face of the patent — e.g., US 2004/0080998 A1 (SanDisk, unusable block management in a non-volatile memory system, published 2004-04-29) and US 7,464,306 B1 (Lexar Media, "Status of overall health of nonvolatile memory," filed 2004-08-27) — but no panel has ever ruled on that, and I am not going to imply it has.

Estoppel landscape. With no IPR/PGR/CBM on file, § 315(e)(2) estoppel is empty. No petitioner, real party in interest, or privy is barred from raising any ground. Any defendant who has not yet been served with a complaint alleging infringement of this patent faces no § 315(b) one-year bar on filing, and could raise the full field of § 102/§ 103 art, plus § 112. The strategic point runs the other way from a typical analysis: the clean estoppel slate is only valuable if there is something left to defend against — and here the gating issue is the patent's lapse, not the art.

Pattern signals. No repeated petitioner (there is no petitioner). No patent-owner PTAB appeal history (there is no FWD to appeal), so the Samsung-as-aggressive-appellant pattern seen in the Netlist v. Samsung/Micron family — e.g., CAFC 2023-2133, 2024-1707, 2024-2304 — has no application here. No defensive aggregator (Unified Patents, RPX, etc.) appears anywhere in the chain for this patent, which is consistent with a 2010-issued Samsung flash-management patent that was never monetized and lapsed quietly.

One nuance worth recording: the patent is heavily forward-cited (the Google Patents record lists 91 "cited by" entries, largely the Radian Memory Systems family and SanDisk Technologies' US 8,719,660 / US 2013/0159797 on removable-storage health reporting). High forward citation with zero assertion and zero PTAB activity is the signature of a reference-grade patent, not a litigation asset. That supports the "never asserted, lapsed in 2018" reading.

Flagged discrepancy from the earlier sections (carried forward, unresolved). The bibliographic summary already noted that the Google Patents record is internally contradictory on status: it labels the patent "Expired – Fee Related" with an "adjusted expiration" of 2028-01-13, while the Legal Events show a 2014 fee payment, then "Lapse for failure to pay maintenance fees" (2018-12-24), "Expired due to failure to pay maintenance fee" effective 2018-11-16, and "Patent expired for failure to pay maintenance fees" (2019-01-15). I do not reconcile these; I report both. For PTAB purposes the practical consequence is the same either way: there is no live AIA trial and no live Federal Circuit appeal touching this patent.

Recommended next steps

If there is no PTAB activity, say so plainly — done. There is none, and I found no FWD, no institution decision, no termination, and no CAFC appeal to link to. I am therefore not linking to a Final Written Decision, because none exists; inventing one would be the single worst thing I could do in this memo.

1. Lead with the lapse, not with the art. The strongest fact in this file is the 2018-11-16 expiration for maintenance-fee non-payment. If you are a defendant holding a demand letter on US 7,836,244:

• Confirm current status in USPTO PatentCenter (https://patentcenter.uspto.gov/) rather than relying on Google Patents' contradictory label, and pull the Fee(s) / maintenance-fee transaction history for application 11/933,564.
• Check whether any petition to revive under 35 U.S.C. § 41(c) / 37 C.F.R. § 1.378 was ever filed. Reinstatement for unintentional delay required a petition within 24 months of the lapse (i.e., by roughly 2020-11-16); beyond that window only an unavoidable-delay showing can revive it. As of 2026-09-30 that window is long closed, so revival is improbable — but this is my inference from the statute and the recorded dates, not a verified fact, and it should be checked against the official file wrapper.
• If the patent is confirmed lapsed and unrevived, damages for post-lapse infringement are effectively unavailable and the demand is answerable on status alone. Note also that an expired patent can still be the subject of an IPR (the Board has taken expired-patent reviews, subject to arguments that no meaningful relief is available) — but filing one is almost certainly a waste of money here.

2. If the patent turns out to be alive (revived, or contradicting the above), then and only then does the art matter. The most likely § 103 attack on claim 1 would combine the ATA/S.M.A.R.T. self-monitoring infrastructure admitted as prior art in the specification itself (the nine standardized SMART commands; 'SMART READ DATA' D0h; 'SMART RETURN STATUS' DAh) with a flash bad-block-management reference such as US 2004/0080998 A1 (Sandisk) or US 7,464,306 B1 (Lexar), plus a vendor-specific-threshold teaching. Independent claim 7 is narrower in that it ties reporting and warning to named ATA commands, so the art would need to disclose or render obvious the specific command-level reporting/warning pairing. I emphasize: no panel has evaluated any of this. It is a petition*-shaped* hypothesis, not a ruling.

3. Watch the docket only if a case appears. There is no PTAB trial calendar to track — no institution deadline, no oral hearing, no statutory 1-year FWD date. If an assertion ever materializes, docket it via PTAB E2E (https://e2e.uspto.gov/) for any new petition and CourtListener (https://www.courtlistener.com/) for the district case and any CAFC appeal.

Confidence: no-PTAB-activity finding — medium-high. The ODP structured set is empty, and targeted searches for proceedings, FWDs, and appeals returned nothing but a false-positive Valtrus US 6,889,244 and a prior-art search string inside an unrelated petition exhibit. Because I could only query general web search (not PTAB E2E or the CAFC docket system directly), treat this as absence of evidence rather than proof of absence — but there is no affirmative hint of any proceeding, and none has surfaced from any independent angle.

I'll verify the assignment record for this patent before writing up the ownership chain.

Inventors

Both names appear as assignors on the only recorded assignment (reel 020058/0837), which conveys their rights to Samsung Electronics — the standard inventor-to-employer instrument. The same two inventors appear on the co-filed German counterpart DE 102007006307 A8 with Samsung as applicant, corroborating common employment.

Unusual-pattern check: Not present. There is no evidence that either inventor departed Samsung around the filing. Third-party inventor-index data (Patent Leaderboard) shows Jung-Been Im with 14 granted US patents assigned to Samsung, the earliest granted 2010 and the most recent in October 2016 — i.e., roughly a decade of continued Samsung filing activity after this 2006 priority date. That is the opposite of the "inventors leave within 12 months, portfolio gets sold" precursor.

Original assignee

Samsung Electronics Co., Ltd. (Suwon, Gyeonggi-do, Republic of Korea) — named on the issued patent and the sole assignee of record.

• Primary line of business: consumer electronics and semiconductor manufacturing; Samsung is one of the world's largest NAND flash memory producers.
• Product embodying the claims: Yes, plausibly. The claims are directed to reporting flash bad-block / reserved-block state via the ATA S.M.A.R.T. command set in an SSD with NAND flash (claim 6). Samsung shipped such SSDs and flash controllers in the relevant period. Note, however, that I could not locate a specific product manual or datasheet tying a named Samsung SSD model to these exact register values (feature register D0h/DAh/E0h, Cylinder Low/High 4Fh/C2h vs. F4h/2Ch), so treat "embodied in a product" as high-likelihood but not documentary-confirmed.
• Current status: Operating. No bankruptcy, dissolution, or acquisition of Samsung Electronics relevant to this patent. (Samsung is, unrelatedly, a frequent litigation party in 2026, but see the prior section — none of those cases names US 7,836,244.)

Assignment timeline

The USPTO Assignment Center record for this patent contains exactly one recorded assignment — the original inventor-to-employer conveyance. There are no subsequent transfers, no security agreements, no change-of-name or merger recordings, and no assignments to any third party or LLC.

• 2007-10-31 (executed) / recorded 2007-11-01 — Reel 020058/0837
  • Conveyance: Assignment of assignors' interest
  • Assignor: HYE-YOUNG KIM; JUNG-BEEN IM (individually)
  • Assignee: SAMSUNG ELECTRONICS CO., LTD. (Korea, Republic of)
  • Correspondent: Not determinable from the sources I could access. The correspondent-of-record field was not retrievable through the search tools available to me, and the Google Patents legal-event row does not surface it. I am flagging this as a gap rather than supplying a name. If you can open the Assignment Center record directly at the reel/frame above, the correspondent will be on the face of the recorded document.
  • Context: Ordinary internal ownership capture — inventors assign to their employer at filing (effective date is one day before the US filing date of 2007-11-01). Single link; no fire-sale, securitization, or transfer-to-asserter character.

Because the chain has only the original assignment, the assignment record is complete as a negative finding: ownership has never left Samsung Electronics. The patent then died by fee lapse rather than by transfer (see below).

Note on status conflict (carried forward, unresolved): Google Patents lists a nominal "Adjusted expiration" of 2028-01-13, but the Legal Events show a lapse for non-payment effective 2018-11-16, "Expired due to failure to pay maintenance fee" (recorded 2018-12-24), and "Patent expired for failure to pay maintenance fees" (2019-01-15). A lapsed patent is not a transferable litigation asset, which is directly relevant to the NPE analysis below.

Timeline diagram

timeline
    title Ownership of US 7836244
    2006 : KR priority application filed
    2007 : US application filed
         : Inventors assign to Samsung
    2010 : US patent issued
    2018 : Lapsed for unpaid maintenance fee

NPE / troll-pattern signals

Verdict

Insufficient data — in the specific sense the rubric allows: "only the original assignment." The Assignment Center record for US 7,836,244 contains a single entry, the inventor-to-Samsung conveyance executed 2007-10-31 and recorded 2007-11-01 at reel 020058/0837, with no post-issuance transfers of any kind.

That thin record nonetheless supports a negative conclusion with reasonable confidence: there is no NPE activity in this chain. The patent was never assigned to an LLC or aggregator, was never asserted (no suit found), and lapsed effective 2018-11-16 for non-payment of a maintenance fee — the mirror image of a troll's acquisition profile. The one unavailable datapoint is the correspondent-of-record name on reel 020058/0837, which I could not retrieve and will not guess; that gap is the honest reason the verdict is "insufficient data" rather than an affirmative non-NPE classification.

Verify at: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 7836244 or application 11/933,564) and the mirrored legacy search at https://assignment.uspto.gov/patent/index.html.

I'll research this systematically, starting with the USPTO record for 7836244 and then pulling details on each cited reference.

Let me pull details on the most relevant examiner-cited references.

Prior-Art Analysis — US 7,836,244 B2 ("Method of providing block state information in semiconductor memory device including flash memory")

Method and provenance note (read first)

• The authoritative source I worked from is the full Google Patents text you supplied (fetched 2026‑09‑30), specifically its "Patent Citations (24)" table — this is the record of references cited against the '244 application. I cross-checked individual references against Google Patents, patentimages PDFs, FreePatentsOnline, uspto.report and Patents-Review pages.
• Limitation I must flag: I was not able to query USPTO PatentCenter or the USPTO "Patent Full-Text" examiner citation record directly — the USPTO web tools returned redirect/JS-blocker pages to the search tool, and my later searches hit a step cap. So the citation list below is reproduced from the granted patent's own front-page citation table (authoritative for what was cited) rather than from a live PAP/PatentCenter "References Cited" screen. Where I could not retrieve a reference's substance, I say so rather than inventing it.
• The Google Patents citation table marks some rows with * / † ("cited by examiner" vs "cited by third party"). In the fetched text the asterisk placement is internally inconsistent (asterisks appear in odd places across the two citation blocks), so I do not rely on the marks to assert which references the examiner substantively relied on. I treat all 24 as "cited references."
• Nothing below should be read as an auto-correction of any patent number. All numbers are taken literally as given.

Part 1 — The 24 cited references (full citation, date, brief description, relevance)

Dates are the filing / priority date shown in the citation table and, where I could retrieve it, the publication/grant date. "Relevance" is my assessment of what the reference could teach relative to the '244 claims.

Part 2 — The genuinely relevant prior art (short list)

Ranked by closeness to the '244 independent claims:

1. US7464306B1 (Lexar / Furuhjelm), filed 2004‑08‑27, granted 2008‑12‑09 — the closest art.
2. US20090077434A1 (Lexar, continuation of the above), pub. 2009‑03‑19.
3. US20040080998A1 (SanDisk), pub. 2004‑04‑29.
4. US20060023524A1 (NEC Electronics), pub. 2006‑02‑02 (granted counterpart: US 7,453,727).
5. KR20060083336A (Samsung), pub. 2006‑07‑20; US6956769B2 (Samsung), granted 2005‑10‑18; US6161195A (Toshiba), granted 2000‑12‑12; US5349558A (AMD), granted 1994‑09‑20 — redundancy/bad-block substitution family.

The remainder are largely background/architecture references (Japanese disk/card/camera items) or peripheral (US6003135, US20080211638, US20030095439, US7009889).

Part 3 — Claim-by-claim §102 analysis

Important framing: the '244 independent claims require, in combination, (a) storing bad-block and reserved-block state including counts of bad blocks, reserved blocks, and available reserved blocks; (b) reporting that state to a user in response to a user command; (c) firing a warning when available reserved blocks reach a reference value where (d) that reference value is variably set by a vendor in a vendor-specific area of a command having one of the register values, and the same command determines the warning time point; and (e) the method runs during a read and/or write operation. Claim 7 pins the reporting to the ATA 'SMART READ DATA' command and the warning to ATA 'SMART RETURN STATUS'.

No single cited reference discloses all of (a)–(e). My honest assessment is that independent claims 1 and 7 are not anticipated by any reference in the list, because every cited reference is a memory-internal defect/redundancy scheme, whereas the '244 claims are defined by the ATA/S.M.A.R.T. command interface and the vendor-settable threshold in a vendor-specific register.

Per-reference findings

US7464306B1 (Lexar) — potentially anticipates elements of claim 1's preamble/step (a) and the general "report to user / warning" concept, but not the full claim.

• Discloses: nonvolatile memory organized into blocks; spare blocks; blocks defective at manufacture and growing defects; controller keeps a list of spare blocks and a mapping of defective blocks to spare blocks; host sends an inquiry and the device reports health status; a display shows a "Warning!" that the memory "may not be usable much longer."
• Gap: no ATA/SMART command, no register-value-based reference threshold, no vendor-specific command area, and no express "executed during read/write operation" limitation as claimed. → §102 anticipation of claims 1/7 is unlikely; it is instead the leading §103 obviousness reference.
• Claim 2 (meta blocks) — not squarely met; Lexar uses a controller-maintained list/mapping, not necessarily flash meta blocks. Partial relevance.

US20090077434A1 (Lexar continuation) — same disclosure as US7464306B1; same conclusion. Also a potential §102(e) reference (filing 2004‑08‑27 predates the '244 priority date of 2006‑11‑02).

US20040080998A1 (SanDisk) — potentially anticipates only the "storing block state information on bad blocks and reserved/spare blocks" portion of claim 1's preamble.

• Discloses tracking defective blocks, maintaining a pool of spare blocks, and storing a defect "signature" in a data structure (erase-count block).
• Gap: no user-command reporting of counts, no warning threshold, no ATA/SMART. → Anticipates none of claims 1–8 as a whole; relevant only to the storage sub-step. Its 2004‑04‑29 publication predates the priority date by >1 year (§102(b) posture).

US20060023524A1 (NEC Electronics) — potentially anticipates the "storing block state information … reserved blocks" sub-step.

• Discloses a replacement data cell array storing replacement confirmation data and address data identifying which main array is replaced by which redundancy array.
• Gap: same as above — no user-command reporting, warning, or ATA/SMART. → Anticipates none of the claims as a whole.

US6956769B2 (Samsung) / US6161195A (Toshiba) / US5349558A (AMD) / KR20060083336A (Samsung) — redundancy and bad-block substitution architecture. These map to the pre-characterization ("reserved blocks which replace bad blocks") and, at most, to a broad reading of claim 1's storing step. None discloses the user-command reporting or vendor-threshold warning. → No full-claim anticipation; at most §103 fodder.

Phison US20070276978A1, Micron US20070285981A1, Micron US20060034136A1, TI US20030095439A1, SanDisk US7009889B2, Spyrus US6003135A, Fujitsu US20080211638A1 — for the ones I could not fully retrieve, I will not assert specific anticipation. On their titles/known subject matter they are defect-handling, erase, or peripheral-system references and do not appear to disclose the ATA/SMART vendor-register reporting/threshold combination at the heart of claims 1 and 7. Confidence: low-to-medium (full texts not all retrieved before the step cap).

Net §102 conclusion

Bottom line under §102: the cited prior art establishes that storing bad-block/reserved-block information and warning a user that memory is wearing out were known (principally US7464306B1). But the distinguishing limitations of US 7,836,244 — reporting via the ATA S.M.A.R.T. command set and a vendor-settable reference value located in a vendor-specific area of a command having one of the register values, with the warning time point set by that command, performed during read/write — appear to be absent from every cited reference, including the Lexar art. That is consistent with the patent having issued over this art.

Caveats (per operating rules)

• Do not treat the above as a legal conclusion. Anticipation is a claim-by-claim, element-by-element inquiry, and I have assessed it from the full text of the challenged patent and the cited references' abstracts/descriptions, not from USPTO PatentCenter's full examiner-citation and Image File Wrapper record, which I could not access.
• Unverified items: the substance of US20070285981A1 (Micron) and US20070276978A1 (Phison) was not retrieved; my descriptions of them are title/subject-based and flagged as such. US20080211638A1 (Fujitsu electronic tag) and US6003135A (Spyrus) appear peripheral on their face; I could not confirm why the examiner cited them.
• Citation-marking uncertainty: the */† "examiner vs third-party" markers in the source text are internally inconsistent, so I did not treat any marker as dispositive of examiner reliance.
• Cross-reference to the earlier section: the earlier summary's finding that the '244 patent appears to have lapsed 2018‑11‑16 for non‑payment of maintenance fees (despite a nominal 2028‑01‑13 expiration) does not affect the prior-art analysis — the references remain prior art regardless of the patent's current status. No contradiction with the earlier section is introduced here.
• If you want a definitive §102/§103 position, the next step is a PRPS/PatentCenter pull of the actual "References Cited" and examiner's search notes, plus full texts of references #22 and #24, which I flagged as not retrieved.

I'll ground the analysis in the actual prior-art references listed on the patent page before building the §103 combinations.

Obviousness Analysis of US 7,836,244 B2 under 35 U.S.C. § 103

Note on my evidence base. Per the instruction, I am working from the Prior Art section of the Google Patents page for US 7,836,244 (the "Citations (23)/(24)" list at https://patents.google.com/patent/US7836244/en), and from search results I retrieved for individual references. I ran additional verification searches on the Lexar, SanDisk, Micron and NEC references (results quoted below) and hit the tool step limit before I could verify JP2002269992A (Funai), JPH09198884A (Toshiba), JPH11250675A (Canon), JP2004227723A (Renesas), JP20070276978A1 (Phison) and the ATA SMART command standard. Where I lack the reference text I say so explicitly rather than inventing content. This ties to the earlier section's caveat that "no known litigation" and similar negatives are absences of evidence — the same applies to reference content I could not open.

1. The claim to be invalidated, decomposed

Claim 1 requires, in combination:

Claim 7 swaps 1e's generic command for specific ATA commands: reporting via 'SMART READ DATA'; warning via 'SMART RETURN STATUS' when the capacity or number of reserved blocks reaches a predetermined level; with the same vendor-settable register area limitation and the same read/write context.

Dependents: cl. 2 (store in meta blocks that hold block + mapping info), cl. 3 ('SMART READ DATA' command), cl. 4 (vendor-specific ATA command), cl. 5 (vendor-specific ATA command sets warning time point), cl. 6 (SSD with NAND flash), cl. 8 (vendor-specific ATA command sets warning time point).

Key structural observation: limitation 1e is the only limitation in the entire patent that is not squarely about flash bad-block management. Everything else is block-defect bookkeeping plus host reporting of that bookkeeping — a field saturated by the cited art.

2. Person of ordinary skill in the art (POSA)

A POSA here would hold a B.S. in electrical engineering or computer science and have ~2–3 years of experience in flash storage controllers, FTL firmware, and NAND bad-block/redundancy management, including familiarity with the ATA/ATAPI command set (which the '244 specification itself treats as common knowledge) and with the routine practice of making a flash device appear to a host as a hard disk drive via a flash translation layer. The patent's own specification supports this level: it states the SMART commands "are well known to those skilled in the art" and describes the meta block / user block / reserved block architecture as "general flash memory."

3. The primary combination

3.1 Lexar Media US 7,464,306 B1 (and its continuation publication US 2009/0077434 A1) — the closest reference

US 7,464,306 B1 (Furuhjelm et al., Lexar Media), filed Aug. 27, 2004 — before the '244 priority date of Nov. 2, 2006 — is directly on the problem the '244 patent claims to solve. From the granted text (https://patents.google.com/patent/[US7464306B1](/patent/US7464306B1) and the PDF at http://patentimages.storage.googleapis.com/35/3c/e9/327b3fe47b3cd3/US7464306B1.pdf):

• It expressly identifies the same deficiency the '244 background identifies: "while the controller device is aware of the number of defective blocks and the number of spare blocks and the number of blocks being employed for storage, or in essence, status of the health of a nonvolatile memory device, the user of the latter and the host remain ignorant of such information."
• It describes the identical replacement mechanism: "defects within the devices are managed by replacing use of the detected defective blocks with blocks from a list of spare blocks… the controller device must maintain a list of spare blocks and a mapping of the defective blocks, if any, to spare blocks."
• It quantifies exactly the three counts of limitation 1b, with named variables: MD = number of manufacturing defects (number of bad blocks), SBfw = "the total number of spare blocks… initially reserved" (number of reserved blocks present in the device), and SBrem = "the total number of spare blocks remaining at the time of the measurement" (number of available reserved blocks). Claim 1 of '306 recites the controller is "configured to output a signal indicative of a total number of spare blocks at the time of the measurement of the health status"; claim 7 recites outputting that to a host; claim 8 recites "the controller is configured to receive a signal from a host requesting the health status" — which is limitation 1c.
• It discloses the periodic/operational context of limitation 1f: "the controller device 20 is coupled to the host 12… which initiate a read or write operation through the controller device 20", and defect growth is tracked on an on-going basis as blocks are written and erased.
• It discloses the warning of limitation 1d, though keyed to a computed health percentage rather than a spare-block count: "SBrem is zero… HS is 0% indicating that the information stored in the nonvolatile memory is reliable but should not be used any further. This would perhaps invoke the 'Warning!' message on the monitor 18", and "the monitor 18 is caused to display a 'Warning!' regarding the health of the nonvolatile memory."

In short, '306 discloses 1a–1d and 1f, and the pre-warning concept, differing from claim 1 mainly in (i) storing the counts in a controller-maintained structure rather than expressly "in the flash memory," and (ii) the trigger formulation (ratio HS ≤ threshold vs. spare count ≤ reference value) — which is a mathematically trivial restatement, since HS = SBrem/(SBfw − MD).

3.2 SanDisk US 2004/0080998 A1 (Chang et al.) — supplies "store in the flash memory" and the factory/growing defect split

US 2004/0080998 A1 (https://patents.google.com/patent/US20040080998 and https://patentimages.storage.googleapis.com/22/ea/70/e53cbb7b40cf3b/EP1418502A3.pdf) discloses:

• Distinguishing factory defects from growing defects arising during use, and handling them with different data structures: "a data structure may be an erase count block", and "storing a first signature into a data structure in the non-volatile memory that identifies the first physical storage element as being defective" — that is limitation 1a's "storing in the flash memory," and the exact informational split the '244 FIG. 6 declares for bytes 8–11 ("number of additional bad blocks") and 12–15 ("number of initial bad blocks").
• The spare-block pool with reclaim: "identifying the defective physical block as a first spare block, and adding the first spare block to a pool of spare blocks associated with the non-volatile memory."
• The exhaustion trigger that motivates the '244 warning: "during the course of using a memory system which includes a flash memory component, it may be determined that the memory system does not have enough spare blocks available for use in storing data."

3.3 Samsung US 6,956,769 B2 — reserved blocks for NAND bad blocks, and exhaustion

US 6,956,769 B2 (https://patents.google.com/patent/US6956769, PDF https://patentimages.storage.googleapis.com/f8/d2/0d/8366bfe56abc8d/US6956769.pdf), filed from a Mar. 4, 2002 Korean priority, discloses a NAND flash array of main blocks and redundant cell blocks in which "the first memory cell block is assigned to substitute for at least one defective memory cell block", and expressly addresses the exhaustion scenario: "it may occur that the number of bad blocks is greater than the number of redundant cell blocks embedded therein… after all redundant cell blocks have already been exhausted by substitution for other bad blocks." This supports limitation 1a's bad-block→reserved-block substitution and claim 6's NAND context, and supplies a reason to track and expose bad/reserved counts (bad-block mapping information is needed to address the device correctly).

3.4 The combination and the motivation

Proposed ground: Lexar '306 in view of SanDisk '998, further in view of Samsung '769.

• Same field, same problem, same solution mechanism. All three are flash memory systems in which defective erase blocks are replaced from a finite reserve, and all three are concerned with knowing how much reserve remains. The '244 patent's own background (FIGS. 1–2) is a paraphrase of this art.
• The motivation is expressly stated in the art itself. '306 frames the invention as curing the ignorance of host and user about the number of defective and spare blocks. A POSA reading '306 and asked to implement it on a NAND device would naturally adopt '998's nonvolatile in-memory defect data structure (because '306 requires the host and controller to be able to measure health after power cycles, and a controller-RAM-only count would be lost), and would naturally read out the three counts '306 already computes (MD, SBfw, SBrem) — three values that '998's bookkeeping already makes available.
• Predictable result, no new mechanism. Nothing in the combination requires re-architecting anything: reading a counter from a flash data structure and returning it in response to a host inquiry is the routine use of known elements for their known purposes (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)). '306 already outputs the values; '998 already stores them in the flash; '769 confirms the NAND/reserved-block setting.
• Claim 2 is met by the same combination. Storing the counts in the meta block (claim 2) is the natural placement, since the '244 specification itself concedes that "block state information for the reserved blocks or bad blocks may be already stored in the 'FTL'… or in the meta blocks of the flash memory" — an applicant admission that this placement was known. '998's "data structure in the non-volatile memory" (erase count block) is that structure.

4. The ATA/S.M.A.R.T. limitations (claims 3, 4, 5, 7, 8, and the 1e vendor-register limitation)

Here the cited-art list is a genuine gap that I must flag.

The "Citations" list on the page contains no ATA, S.M.A.R.T., ATA-8, or disk-drive-health reference that I can identify from the titles. The command-set content the '244 patent relies on is instead supplied by the patent's own specification as admitted prior art:

• "the SMART commands shown in FIG. 4 are well known to those skilled in the art, thus its detailed description will be omitted."
• "In these SMART commands, nine commands, 'SMART READ DATA(D0h)', 'SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE(D2h)', … and 'SMART RETURN STATUS', are standardized."
• The 512-byte 'SMART READ DATA' payload with "vendor-specific data areas (0th to 361st bytes and 386th to 510th bytes)".

Under § 103, an Applicant Admitted Prior Art statement of this kind can be relied on for what it concedes (In re Nomiya, 509 F.2d 566 (CCPA 1975); MPEP § 2129). So the ground would be:

Proposed ground: Lexar '306 (or '306 + SanDisk '998 + Samsung '769) in view of the ATA S.M.A.R.T. command set as admitted known art, optionally in further view of a drive-health/status-reporting reference.

Motivation: The '244 specification supplies it in its own words — the device is used "as an SSD (Solid State Disk) or hard disk," and via the FTL "a host can recognize the flash memory 30 as a hard disk driver, and can access the flash memory device by the same method as the host would access a hard disk driver." Once a flash device identifies itself as an ATA hard disk drive, the host-visible, standardized channel for reporting drive health is S.M.A.R.T. Choosing S.M.A.R.T. over a proprietary side-channel is the selection of a known, standardized technique for the very purpose for which it is standardized — i.e., predictable, and arguably the obvious choice for anyone wanting broad host support without custom drivers. This also explains the SMART attribute list the '244 spec recites (head flying height, spin-up time, re-allocated sector count, etc.), all of which are standard drive-health attributes.

Mapping for claim 7: 'SMART READ DATA' (D0h) is the standardized command whose 512-byte response already contains vendor-specific regions — the natural place to report spare-block counts (and the '244 spec admits vendor-specific bytes 0–361 and 386–510 exist in the standard). 'SMART RETURN STATUS' (DAh) is the standardized mechanism by which an ATA drive signals an imminent-failure condition to the host via the Cylinder Low/High register pair (4Fh/C2h vs. F4h/2Ch) — precisely claim 7's "warning… when a capacity or a number of the reserved blocks reaches a predetermined level." Lexar '306 supplies the threshold logic and the underlying data; the ATA standard supplies the transport.

Caveat (I will not overstate this): I could not confirm from the page whether the examiner considered an ATA/S.M.A.R.T. document of record; the list as presented shows none. I also could not retrieve the Phison reference US 2007/0276978 A1 ("Universal Serial Bus (USB) memory system and control method thereof," cited in the list and marked as examiner-cited), and that reference — being a USB mass-storage flash device with a host interface — is a plausible candidate for a host-command interface teaching. Its content is unverified here.

5. Secondary combinations worth noting

I do not rely on the Konica JPH09163293A (digital still camera) or Fujitsu US 2008/0211638 A1 (electronic tag) references; from their titles alone they appear to be § 102(b)/obviousness background only, and I could not verify their content. Treating a reference as prior art for § 103 purposes on the basis of its title would be exactly the kind of auto-correction I have been told to avoid.

6. Where the obviousness case is weakest — and the strongest non-obviousness argument

The weak link is limitation 1e, and it is weak in a way that explains why the patent issued on Nov. 16, 2010 over art that otherwise looks fatal.

• None of the cited references appears to disclose "the reference value is variably set by a vendor in a vendor-specific area of a command having one of the register values, and… a warning time point… is determined by the command having the one of the register values." The '244 spec locates this in the ATA Feature Register sub-command E0h with the threshold in the Sector Count register, inside the vendor-usable E0h–FFh range — a host-to-device configuration command that both carries the user's threshold and sets when the warning fires.
• The closest cited art ('306) has the device/controller compute a health ratio and display a warning; the user does not push a threshold into a drive register. If the ATA/S.M.A.R.T. admission is treated as prior art, this limitation collapses into "use the standard's vendor-specific register bytes for your own parameter" — but a patentee would argue that (a) the cited references are directed to controller-side health display rather than host-programmable device-side warning thresholds, and (b) no cited reference teaches or suggests the two-way configuration channel at all, so the combination would be supported only by the AAPA concession plus ATA general knowledge — a thinner evidentiary footing than the element-by-element mapping available for 1a–1d and 1f.
• A secondary argument: '306's health metric is a ratio (SBrem/(SBfw − MD)), not a count compared to a reference value; a patentee could argue the trigger formulation differs. This is a weak argument (algebraically equivalent), but it may matter if the examiner treats the counts as the inventive core.

No objective indicia (secondary considerations) were found on the page: no evidence of commercial success, long-felt-but-unmet need, failure of others, copying, or industry praise. Absent such evidence, KSR's "predictable use of prior art elements according to their established functions" controls.

7. Bottom line

1. Claims 1, 2, 6 (and, if the ATA admission is credited, 3, 4, 5, 7, 8) are strong § 103 candidates over Lexar US 7,464,306 B1 in view of SanDisk US 2004/0080998 A1, further in view of Samsung US 6,956,769 B2 — with Lexar supplying the three counts (MD / SBfw / SBrem), the host-inquiry reporting (claim 8 of '306) and the warning, SanDisk supplying the in-flash nonvolatile defect/bad-block data structure and the factory-vs-growing-defect distinction, and Samsung supplying the NAND reserved-block substitution and the exhaustion motivation.
2. Claim 7's ATA-specific limitations hinge on treating the S.M.A.R.T. command set as Applicant Admitted Prior Art (the '244 spec's "well known to those skilled in the art" statement about FIG. 4 and the "nine standardized" SMART commands). This is a legally usable ground but rests on an admission plus general knowledge rather than a cited document containing the command set.
3. Limitation 1e (vendor-settable reference value in a vendor-specific register area, which also defines the warning time point) is the most defensible limitation and the likely reason the claims survived prosecution. A § 103 challenge that does not produce a document teaching a host-programmable device-side warning threshold, as distinct from device-side health computation and display, will be incomplete.
4. Verification gaps I am flagging rather than papering over: the full texts of JP2002269992A (Funai), JPH09198884A (Toshiba), JPH11250675A (Canon), JP2004227723A (Renesas), and US 2007/0276978 A1 (Phison) were not retrievable within my search budget; the Funai reference in particular ("Non-volatile memory device and system") and the Phison reference (USB memory system with a host interface and control method) are the most likely to contain additional host-command/status-reporting teachings, and my analysis would need revision if they do. Consistent with the earlier section of this analysis, note also the internal contradiction in the source's legal-status data (a nominal 2028-01-13 adjusted expiration versus a recorded lapse for non-payment effective 2018-11-16) — for an invalidity opinion the patent is treated as expired and unenforceable, which affects the practical value, not the merits, of the § 103 analysis above.