US 7693002

I'll verify the patent details and check for any litigation/docket activity before summarizing.

Let me check for any CAFC 2026 appellate docket activity specifically tied to this patent.

Verification result: this is the correct patent

US 7,693,002 B2 is a real, granted, still-active US patent, and it matches the number you gave. I found no evidence of a different patent at or near this number in any of the sources checked (the only near-miss hits were unrelated — e.g., a De Dietrich heat-pump model "Alezio S 16 MR/H V200 (7693002)," which is an EU declaration-of-conformity part number, not a patent).

1. Bibliographic data — US 7,693,002 B2

Foreign family (same priority): EP 2076904 B1, JP 5362575 B2, JP 5631906 B2, KR 101002565 B1, CN 101523501 B, TW 200832441 A, WO 2008/045966 A2.

Source: https://patents.google.com/patent/US7693002/en ; https://patents.justia.com/patent/7693002 ; https://patexia.com/us/patent/07693002

2. Abstract (verbatim)

"In a particular illustrative embodiment, a circuit device that includes first logic and second logic is disclosed. The first logic receives a clock signal and a first portion of a memory address of a memory array, decodes the first portion of the memory address, and selectively applies the clock signal to a selected group of wordline drivers associated with the memory array. The second logic decodes a second portion of the memory address and selectively activates a particular wordline driver of the selected group of wordline drivers according to the second portion of the memory address."

3. Plain-language overview of the independent claims

This patent describes a split/decoded clocking scheme for SRAM-style wordline drivers, plus a layout trick to cancel capacitive coupling between adjacent wordline data lines. There are eleven independent claims (1, 7, 11, 17, 21, 23, 24, 25, 26, 27, 29). Claims 21, 23, 24, 25 are essentially claim 1 with a dependent-claim limitation folded up into the independent claim; 26 folds up claim 10; 27 folds up claim 13; 29 folds up claim 18.

Selected dependent claims worth flagging: claim 6 (four drivers sharing a common address input); claim 8 (receiving the clock and selectively applying to one of several clock outputs); claim 9 (determining the clock output via a conditional clock generator); claim 14 (applying the second address portion to a shared address line); claim 15/16 (the device is an integrated circuit, and the IC includes the memory array); claim 28 (decoder applies the second portion to a shared address line); claim 37 (active-evaluation vs. static-precharge states, plus logic = conditional clock generator).

Drafting anomalies (reported literally, not corrected):

• Claim 35 reads "The method of claim 1…" — but claim 1 is a circuit device, not a method. Read literally this is a malformed dependency; it appears intended to depend on claim 7.
• Claim 38 contains the typo "wheren" for "wherein."
• The independent-claim set is unusually duplicative (21/23/24/25 largely restate claim 1 plus one dependent limitation each), which is consistent with claims being added or amended post-grant.

4. Litigation / PTAB posture relevant to this patent

Important caveat: my search returned strong, consistent evidence of the patent's litigation history, but I could not find any 2026 CAFC docket entry naming 7,693,002. I also could not verify which individual claims survived the IPR. Treat the following as sourced but incomplete.

• IPR2018-01249, [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Qualcomm Incorporated (PTAB) — Petition filed 2018-06-18; Final Written Decision 2020-01-06; panel: Judges Daniel Galligan, Scott Howard, Trevor Jefferson; TC 2800 / AU 2827. An inter partes review certificate (kind code K1) issued 2021-09-20 for Trial No. IPR2018-01249. A K1 certificate generally accompanies cancellation/termination outcomes, but I could not confirm from the sources retrieved exactly which of claims 1–38 were cancelled versus upheld — verify at the USPTO PTAB/PatentCenter record. Source: https://www.docketalarm.com/cases/PTAB/IPR2018-01249/Apple_Inc._v._Qualcomm_Incorporated/
• District court: Qualcomm Incorporated v. Apple Incorporated, No. 3:17-cv-02398 (S.D. Cal., filed 2017-11-29; Judge Dana M. Sabraw). The '002 patent was one of five Qualcomm patents asserted there, directed to "dynamic drivers and memory array decoding," particularly SRAM memory cell logic, and tied in press coverage to Apple's A10 processor (iPhone 7/7 Plus). The case was later consolidated into the related San Diego Qualcomm v. Apple DMS case line (3:17-cv-0108 / 3:17-cv-1375). Source: https://www.docketalarm.com/search/?q=patent:(7693002) ; contemporaneous coverage describing the five-patent assertion, e.g. https://www.jiemian.com/article/[1785756](/patent/1785756).html
• ITC: Investigation 337-TA-1093 involving this patent family (Qualcomm v. Apple), per the Google Patents litigation record.
• CAFC: My searches surfaced 2026 Federal Circuit activity between Qualcomm and Apple, but not on this patent — e.g., Federal Express Corp. v. Qualcomm Inc., No. 2024-1236 (Fed. Cir. Apr. 29, 2026) (unrelated FedEx patent), ParkerVision v. Qualcomm (M.D. Fla., expedited appeal, oral argument set June 1, 2026), and Apple Inc. v. Squires, No. 2024-1864 (Fed. Cir. Feb. 13, 2026). The Qualcomm/Apple Federal Circuit line involving applicant-admitted prior art concerned U.S. Patent 8,063,674, not the '002 patent (Qualcomm Inc. v. Apple Inc., No. 23-1208 (Fed. Cir. 2025); earlier Apple Inc. v. Qualcomm Inc., No. 20-1560 (Fed. Cir. Feb. 9, 2021), which affirmed PTAB rulings).

5. Explicit uncertainties

1. No CAFC 2026 docket for 7,693,002 was found. I cannot confirm one exists or that it definitively does not; a PACER/CAFC docket-by-patent search and the USPTO IPR certificate would be needed to close this out.
2. Claim survival after IPR2018-01249 is unverified. The K1 certificate's effect on individual claims of the '002 patent was not retrievable from the sources I searched.
3. The technical/claim summaries above are drawn from the patent text itself (authoritative per my instructions); the litigation summary relies on third-party aggregators (Google Patents litigation metadata, Docket Alarm, press coverage) and should be confirmed against primary records before being relied on.

I'll search for litigation involving US patent 7693002 across patent litigation databases.

Let me search for more specific case details.

Let me get more detail on the IPR outcome and CAFC appeal, and confirm the district court case status.

Litigation Involving U.S. Patent No. 7,693,002

Based on the patent record (Google Patents family/litigation data for US 7,693,002 and the PTAB/IPR certificates) and litigation-database searches (Docket Alarm, CourtListener, Justia, ITC records), I identified three proceedings in which US 7,693,002 ("Dynamic word line drivers and decoders for memory arrays," Qualcomm, inventor Jentsung Lin) was asserted or challenged. All three arose out of the Qualcomm–Apple dispute and involve the same parties.

1. District Court — Qualcomm Incorporated v. Apple Incorporated

• The '002 patent was one of five patents asserted in this complaint (the others being U.S. 9,154,356; 9,473,336; 8,063,674; and 9,552,633). Qualcomm accused Apple's iPhone 7, iPhone 8, and iPhone X — specifically the A10 processor's SRAM memory control logic — of infringing the '002 patent.
• The docket reflects active litigation through claim construction and discovery (e.g., Joint Claim Construction Chart, invalidity-contentions orders) during 2018–2019 before the global settlement.

Note: Do not confuse this with Qualcomm's separately-numbered S.D. Cal. case 3:17-cv-01375-DMS-MDD (same judges), which asserted a different set of patents ('936, '558, '949, '490, '675). That case also settled in 2019.

2. International Trade Commission — Certain Mobile Electronic Devices and RF/Processing Components Thereof (II)

• The '002 patent was among the asserted patents; its claim terms (e.g., "second logic to selectively activate a particular wordline driver of the selected group of wordline drivers according to the second portion of the memory address" and "selected group of [a plurality of] wordline drivers") appear in the Joint Claim Construction Chart dated May 15, 2018 (Investigation No. 337-TA-1093).
• ALJ McNamara's March 26, 2019 Initial Determination found a Section 337 violation based on one asserted claim and recommended tailored remedial orders; the parties then filed a joint motion to terminate the investigation on settlement.

3. PTAB — Apple Inc. v. Qualcomm Incorporated (Inter Partes Review)

I could not, within the available search results, retrieve the claim-by-claim disposition of the Final Written Decision (i.e., exactly which of claims 1–38 were held unpatentable versus upheld). The issuance of an IPR certificate for the '002 patent indicates at least some claims were cancelled or confirmed through this proceeding.

Summary of Litigation History

The '002 patent was litigated only in the Qualcomm v. Apple campaign (2017–2019), across three fora:

1. Qualcomm Inc. v. Apple Inc., No. 3:17-cv-02398 (S.D. Cal., filed Nov. 29, 2017) — patent infringement action; resolved by the 2019 global settlement.
2. ITC Inv. No. 337-TA-1093 — Section 337 investigation; violation found in ALJ Initial Determination (Mar. 26, 2019); terminated on settlement.
3. Apple Inc. v. Qualcomm Inc., IPR2018-01249 (PTAB, filed June 18, 2018) — inter partes review; Final Written Decision and IPR Certificate issued (2020–2021).

I found no other litigation (no additional district court, ITC, or PTAB matters) asserting or challenging US 7,693,002, and no current/live litigation — the patent is now owned by Qualcomm, its anticipated expiration is October 10, 2026, and the family data lists the litigations above as historical events.

Caveats

• Patent numbers and case numbers are reproduced literally from the sources; I did not normalize or "correct" any identifier.
• Specific outcome details I could not verify from primary documents (e.g., the exact claims held unpatentable in the IPR Final Written Decision, precise dismissal dates, and settlement terms) are flagged as such rather than asserted. If you need these confirmed, the authoritative sources are the PTAB Final Written Decision in IPR2018-01249 and the S.D. Cal. docket in 3:17-cv-02398 via PACER.

I'll research the PTAB proceedings on US 7,693,002, starting with the case referenced in the patent record.

Good — I found the IPR. Let me get claim-level detail and check for related proceedings and appeals.

Now let me pin down the appeal outcome and the IPR certificate, and check for any other petitions.

AIA Trial Proceedings — U.S. Patent No. 7,693,002 B2 ("Dynamic word line drivers and decoders for memory arrays")

Data-integrity flag (read first). The "PTAB proceedings on file" block in this prompt states that the USPTO ODP API returns no AIA trial proceedings. That is wrong or stale. The patent's own Google Patents record carries a litigation entry — "PTAB case IPR2018-01249 filed (Final Written Decision)" — and public PTAB records confirm a full trial through Final Written Decision, a Federal Circuit appeal, and an issued IPR certificate. I have therefore sourced the proceedings list from the patent record plus public PTAB/CAFC dockets rather than the ODP block, and I flag below every inference I could not verify directly.

Proceedings overview

There is exactly one (1) AIA trial proceeding on the '002 patent: IPR2018-01249, [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Qualcomm Incorporated, which ran to a Final Written Decision on 2020-01-06 holding all challenged claims unpatentable and resulted in an IPR certificate issued 2021-09-20 — meaning the breakdown is 1 invalidated / 0 sustained / 0 settled / 0 institution-denied / 0 active. The bottom line for a defendant: the patent has been gutted — claims 1–28 and 31–37 are canceled, including every asserted independent claim (claims 1, 7, 11, 17, 21, 23, 24, 25, 26, 27). If a demand letter cites any of those claims, it is citing dead paper. Only claims 29, 30, and 38 were never challenged and remain formally untested — and the patent's anticipated expiration is 2026-10-10, roughly two weeks from today.

IPR2018-01249 — Apple Inc. v. Qualcomm Incorporated

Type: Inter Partes Review (35 U.S.C. §§ 311–319)
Filed: 2018-06-18
Patent: 7,693,002 B2 | Art Unit 2827 | Tech Center 2800
Status: Terminated 2020-01-06 — "Final Written Decision Determining All Challenged Claims Unpatentable; Granting Petitioner's Motion to Exclude, 35 U.S.C. § 318(a)" (Paper 27). Docket Alarm status field: "Final Written Decision."

Judge panel: Trevor M. Jefferson, Daniel J. Galligan, and Scott B. Howard, Administrative Patent Judges. Judge Galligan authored the Final Written Decision.

Petition grounds (pre-AIA § 103(a); the Board applied pre-AIA §§ 103/112 because the '002 application predates the AIA):

No § 102 anticipation and no § 112 grounds were presented. Claims 29, 30, and 38 were not challenged.

Institution decision: Instituted 2019-01-15 (Paper 6) — on all grounds. Patent Owner filed no Preliminary Response, so the Board's § 314(a) analysis went unrebutted.

Final Written Decision — 2020-01-06 (Paper 27):

• Verdict at claim level: claims 1–28 and 31–37 — all challenged claims — unpatentable as obvious. The Board's disposition line is quoted verbatim above: "we determine that Petitioner has proven by a preponderance of the evidence that claims 1–28 and 31–37 of the '002 patent are unpatentable."
• No challenged claim was sustained. There is no partial win for Qualcomm in this FWD.
• Petitioner's Motion to Exclude Exhibit 2004 was granted (Papers 19, 21, 23).
• Oral hearing held 2019-10-10 per the FWD text (Paper 26, "Tr."); the hearing transcript is docketed at 2019-11-06 in third-party dockets — treat 2019-10-10 as the substantive hearing date of record.
• Full FWD PDF: https://www.docketalarm.com/cases/PTAB/IPR2018-01249/Inter_Partes_Review_of_U.S._Pat._7693002/docs/01-06-2020-Board/Termination_Decision_Document-27-JUDGMENTFinal_Written_DecisionDetermining_All_Challenged_Claims_UnpatentableGranting_Petitioners_Motion_to_Exclude35_USC_sec_318a.pdf
• Case docket: https://www.docketalarm.com/cases/PTAB/IPR2018-01249/Apple_Inc._v._Qualcomm_Incorporated/

Settlement / termination: The IPR was not settled or terminated on settlement; it ran the full statutory course to FWD. Separately, the underlying district court litigation settled — Qualcomm and Apple entered a global settlement/license in April 2019 (six-year portfolio license with an extension option), which mooted the parallel S.D. Cal. case (Qualcomm Inc. v. Apple Inc., No. 3:17-cv-02398) and the ITC action. The PTAB trial continued regardless and Apple won it on the merits. Terms of the Apple–Qualcomm license are public only in outline; the financials are confidential.

Appeal: Patent Owner Qualcomm appealed. Notice of Appeal filed 2020-03-04 under 37 C.F.R. § 90.2(a), expressly appealing the FWD and the 2019-01-15 institution decision. The stated issues were:

1. the constitutionality of the appointment of the Administrative Patent Judges (the Arthrex Appointments Clause challenge); and
2. the § 103(a) unpatentability determination as to claims 1–28 and 31–37.

Notice of appeal: https://insight.rpxcorp.com/federal_circuit/[829974](/patent/829974)/rpx-ptab/IPR2018-01249/IPR2018_01249___Notice_of_Appeal_b1e8b369d46e7332c9d07d2ab5e87e8e.pdf

Appeal disposition — flagged as inference. A nonprecedential Fed. Cir. R. 36 affirmance issued in Qualcomm Incorporated v. Apple Inc., No. 20-1560 (Fed. Cir. 2021-02-09) (per curiam: Reyna, Taranto, Stoll), on appeal from a PTAB IPR involving Apple, with Qualcomm's Jones Day appellate team arguing for the appellant (the same Jones Day attorneys, incl. Joshua R. Nightingale, who signed the IPR2018-01249 notice of appeal) and the USPTO Solicitor as intervenor. The CourtListener source truncates the underlying trial number ("Appeal from … PTAB in No. IPR2018-…"), and I could not confirm from the retrieved text that the underlying proceeding was IPR2018-01249 specifically — Qualcomm lost several Apple-initiated IPRs in that window and appealed more than one. What is objectively established is the IPR certificate issued 2021-09-20 (below), which under § 318(b) can only issue after the appeal window closes or the appeal terminates without disturbing the FWD.

https://www.courtlistener.com/opinion/[4854953](/patent/4854953)/qualcomm-incorporated-v-apple-inc/

Certificate: USPTO legal event IPRC / kind code K1 — "INTER PARTES REVIEW CERTIFICATE … FOR PATENT 7,693,002, ISSUED APR. 6, 2010, APPL. NO. 11/548,132 … TRIAL NO. IPR2018-01249 … ISSUED SEP. 20, 2021." A § 318(b) certificate issues to give effect to the FWD; given that the FWD held claims 1–28 and 31–37 unpatentable and the affirmance stands, the certificate cancels those claims. (I have not seen the certificate's face and cannot independently confirm the claim-by-claim listing — verify on PatentCenter before relying on it in a filing.)

Defensive value: Claims 1–28 and 31–37 are canceled. Every independent claim that Qualcomm actually asserted against Apple's A10/SRAM logic (claims 1, 7, 11, 17, 21, 23, 24, 25, 26, 27) is dead. An infringement theory built on any of them is not merely weak — it is a Rule 11 exposure. The only live exposure is claims 29 and 30 (and, awkwardly, claim 38, addressed below).

Strategic summary

Claim status of the '002 patent today.

Two practitioner caveats on the survivors:

• Claim 38 is a trap, not a lifeline. It reads "The circuit device of claim 17, where[n] the second logic selects the particular wordline driver…" — it depends from claim 17, which was canceled. A dependent claim cannot stand on a canceled base claim; absent certificate-style rewriting into independent form, claim 38 is inoperative. Its fate depends entirely on how the certificate handled the dependency — confirm on PatentCenter.
• Claim 29 is the only structurally independent survivor. It claims an apparatus with an address input, a plurality of clock outputs, a group of wordline drivers, and first/second logic — i.e., the same architecture in reworded form. It is untested art-wise, but note the patent's anticipated expiration of 2026-10-10; the practical runway for any assertion is essentially zero.

Estoppel landscape. Because a FWD issued, Apple Inc. and its privies are estopped under 35 U.S.C. § 315(e)(2) from asserting in district court or the ITC that any of claims 1–28 / 31–37 is invalid on any ground Apple raised or reasonably could have raised — which sweeps in Sato (U.S. 4,951,259), the Asano/Itoh combination, and any other patents or printed publications a skilled searcher could have found in 2018. That estoppel is largely academic now that the claims are canceled. For a different defendant being asserted today, there is no estoppel at all (§ 315(e)(2) runs against the petitioner and its privies, not the world). A new challenger has the full § 102/§ 103 universe available — but only against claims 29, 30, and 38, because a canceled claim cannot be infringed and needs no defense.

Pattern signals. Qualcomm is a single-patent, single-petition target here: one petitioner (Apple), one IPR, no joinders, no second petition by the same party, and no defensive aggregator in the chain. Unified Patents appears in the record only as the data source for the "Family has litigation" link on the Google Patents page — Unified did not petition. The patent owner's posture was, however, aggressive: Qualcomm did appeal the loss, and it argued the Arthrex Appointments Clause issue on appeal — a mirror-image of the posture Qualcomm faced from Intel in the '949 patent litigation. That appeal failed.

Assertion history (context, not PTAB). The '002 patent was asserted by Qualcomm against Apple over the A10 processor's SRAM control logic in Qualcomm Inc. v. Apple Inc., No. 3:17-cv-02398 (S.D. Cal., filed 2017-11-29), and in ITC Inv. No. 337-TA-1093, where the parties briefed '002 claim terms including "second logic to selectively activate a particular wordline driver of the selected group of wordline drivers according to the second portion of the memory address" and "selected group of [a plurality of] wordline drivers." Apple petitioned for IPR in response and won outright.

Recommended next steps

1. If a demand letter cites any of claims 1–28 or 31–37, reject on the merits, not on settlement value. Point to the FWD (Paper 27, 2020-01-06) — "Final Written Decision Determining All Challenged Claims Unpatentable" — and to the IPR certificate issued 2021-09-20 canceling those claims. Link: FWD PDF.
2. Pull the certificate and the current claim set from USPTO PatentCenter / PTAB E2E before filing anything. Specifically confirm (a) the exact list of canceled claims, and (b) whether claim 38 was rewritten in independent form notwithstanding the cancellation of its base claim 17. E2E: https://e2e.uspto.gov/ · PTAB API/portal record: https://portal.unifiedpatents.com/ptab/case/IPR2018-01249
3. If the assertion targets claims 29/30, you are in a genuinely open fight: no PTAB FWD has construed those claims, no estoppel binds you, and the PTAB's own record on the '002 disclosure (Sato; Asano + Itoh) is a ready-made roadmap for a § 103 attack in district court. But first check the 2026-10-10 anticipated expiration — an expired or imminently-expiring claim may end the dispute without any validity work.
4. Do not over-read the ODP "no proceedings" result. Where a patent has been asserted in three venues (S.D. Cal., the ITC, and the PTAB) and litigated to a certificate, an empty ODP response is an ingest gap, not evidence of a clean patent. Confirm docket state manually.
5. No pending trial milestones to track. The proceeding is terminated, the appeal is resolved, and no new AIA petition is on file. There is no institution deadline, no hearing, and no FWD date outstanding.

Verification caveats, stated plainly: (i) the ODP-supplied "no AIA proceedings" block is contradicted by public records and should be corrected; (ii) the mapping of Federal Circuit No. 20-1560 to IPR2018-01249 is an inference from counsel, timing, panel, and the Rule 36 affirmance — the underlying trial number was truncated in the source I could retrieve; and (iii) the certificate's claim-by-claim cancellation list is inferred from the FWD's disposition, not read from the certificate itself.

I'll start by attempting to ground the assignment record and litigation context via web search, since the Assignment Center itself isn't directly queryable from here.

Assignment Reconstruction — US 7,693,002 B2

Patent: Dynamic word line drivers and decoders for memory arrays
App.: 11/548,132 · Filed: 2006-10-10 · Issued: 2010-04-06 · Assignee of record: Qualcomm Incorporated

Source note / limitation. USPTO Assignment Center (https://assignmentcenter.uspto.gov/) is a JavaScript application and could not be queried directly from this environment; the USPTO assignment record is reproduced below from the Google Patents legal-events mirror of the Assignment Search database (which surfaces the same reel/frame records), corroborated against PTAB and ITC filings that name the patent owner. The single recorded assignment entry is Reel/Frame 019233/0141. I found no evidence of any assignment after that one. Verify at: https://assignment.uspto.gov/patent/index.html#/patent/search?q=[7693002](/patent/7693002)

Inventors

• Jentsung Lin — sole named inventor. Employer at filing: Qualcomm Incorporated (San Diego, CA). Confirmable from the recorded assignment, in which "LIN, JENTSUNG" is the assignor conveying rights to Qualcomm Incorporated (Reel/Frame 019233/0141), and from the PTAB caption in IPR2018-01249, which lists inventor "Jentsung Lin" and Qualcomm as Patent Owner.

Unusual-pattern check: None observed. The inventor→company assignment was executed 2007-03-22 (recorded 2007-05-01), roughly 5.5 months after the 2006-10-10 filing — a routine employment/invention assignment timing, not a fire-sale precursor. There is no evidence in the record of the inventor departing Qualcomm within 12 months of filing, and no co-inventor group that fragmented.

Original assignee

Qualcomm Incorporated (5775 Morehouse Drive, San Diego, CA 92121) — named on the issued patent and still the owner of record.

• Primary business: fabless semiconductor design and wireless-technology licensing (Snapdragon mobile processors, modem/baseband chipsets, RF, and memory/SoC IP). Qualcomm's S.D. Cal. complaint describes it as an operating technology company founded in 1985 with a portfolio of "more than 130,000 issued patents and patent applications worldwide."
• Product embodying the claims: Yes — the claims cover wordline drivers/decoders for memory arrays, i.e., SRAM memory subsystems within Qualcomm's own SoC/chipset products. The ITC and district-court records describe Qualcomm products practicing the asserted power-reduction/memory technologies.
• Current status: Operating, publicly traded (NASDAQ: QCOM). No bankruptcy, dissolution, or acquisition. The '002 patent remains Active with anticipated expiration 2026-10-10.

Assignment timeline

Chronological list of every recorded assignment:

• 2007-03-22 (executed) / recorded 2007-05-01 — Reel 019233/0141
  • Conveyance: Assignment of assignors' interest (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: Jentsung Lin (individual inventor)
  • Assignee: Qualcomm Incorporated (California corporation)
  • Correspondent: Not disclosed in the available record. The Assignment Search mirror shows the reel/frame, parties, and conveyance, but not the recording attorney/correspondent of record for this entry. I will not fabricate a correspondent. (For completeness — and explicitly not an assignment correspondent — Qualcomm's litigation counsel on this patent were Quinn Emanuel (ITC 337-TA-1093) and Jones Day (Federal Circuit App. No. 20-1560); these are litigation, not recording, counsel.)
  • Context: Initial inventor-to-employer assignment — routine conveyance of the inventor's rights to his employer; no commercialization, sale, or third-party transfer implied.

No other assignments are recorded. There is no post-issuance assignment, no security interest, no merger, no change-of-name, and no transfer to any licensing entity. The only USPTO post-grant events on this patent are a Certificate of Correction (2011-07-05), maintenance-fee payments (4th yr 2013, 8th yr 2017, 12th yr 2021), and the IPR certificate (2021-09-28) — none of which is an assignment.

Per the instructions: because the Assignment Center record contains only the original assignment, the "no further assignments" finding means the original assignee (Qualcomm) still owns the patent. I continue below because the additional context (litigation) is material to the NPE/verdict analysis, but the ownership chain itself terminates at Qualcomm.

Related legal events (not assignments — context only):

• 2017-11-29 — Qualcomm Inc. v. [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), S.D. Cal. 3:17-cv-02398 (patent infringement; '002 among asserted patents). Terminated 2019-04-23.
• 2018-01-18 — ITC Inv. No. 337-TA-1093 instituted (Qualcomm v. Apple); '002 asserted claims 1-4, 7-9, 11, 17, 20-23, 31-33, 36.
• 2018-06-18 — Apple Inc. v. Qualcomm Inc., IPR2018-01249 filed challenging claims 1-28, 31-37.
• 2019-04 — Qualcomm/Apple global settlement; ITC and district-court matters terminated.
• 2020-01-06 — PTAB Final Written Decision: all challenged claims (1-28, 31-37) unpatentable.
• 2021-02-09 — Fed. Cir. App. No. 20-1560 affirmed (Rule 36).
• 2021-09-28 — IPR certificate K1 issued (claims cancelled per IPR2018-01249).

Timeline diagram

timeline
    title Ownership of US 7693002
    2006 : Filed by Qualcomm
         : Inventor Jentsung Lin
    2007 : Assignment to Qualcomm
         : Reel 019233 frame 0141
    2010 : Patent issued
    2017 : Qualcomm sues Apple
         : Southern District of California
    2018 : ITC case vs Apple
         : Apple files IPR against claims
    2020 : Claims held unpatentable
    2021 : Federal Circuit affirmed
         : IPR certificate issued

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded transfer is the inventor→Qualcomm assignment (Reel 019233/0141, exec. 2007-03-22). The assignee is a large publicly traded operating company at a corporate headquarters address, not a registered-agent service or single-purpose LLC. No "IP / Holdings / Ventures" entity appears anywhere in the chain.

2. Known asserter in the chain — Not present. Qualcomm Incorporated is an operating semiconductor company, not a listed NPE/PAE. It is absent from the RPX/Unified Patents high-frequency-plaintiff directories in the sense used for troll tracking. Qualcomm is a prolific patent plaintiff and licensor, but it sells the accused-technology-bearing silicon itself; the PTAB caption names Qualcomm as "Patent Owner" (IPR2018-01249) and the ITC names Qualcomm as "Complainant" in its own name — no assertion proxy exists.

3. Repeat correspondent across the chain — Not present / unclear. With only one recorded assignment, there is no recurrence to detect, and the recording correspondent for Reel 019233/0141 is not exposed in the available data. No finding can be made; I decline to speculate.

4. Cascading transfers — Not present. There is no sequence of chained assignments; the record contains exactly one conveyance, and it occurred in 2007, long before any assertion activity.

5. Pre-litigation transfer — Not present. The nearest assertion (S.D. Cal. 3:17-cv-02398, filed 2017-11-29) is ~10.5 years after the sole assignment (2007-03-22). No assignment was executed within 6 months before suit. The chain was not rearranged for standing or venue.

6. Bankruptcy fire-sale — Not present. Qualcomm has not filed for bankruptcy; the patent was never sold out of an insolvency estate.

7. Privateering — Not present. Qualcomm asserted the '002 patent in its own name against Apple (ITC 337-TA-1093 and S.D. Cal. 3:17-cv-02398). There is no operating-company-to-NPE transfer and no assertion-on-behalf proxy.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. (Note: Unified Patents is not a neutral party here — a Unified Patents-linked source appears as a data provider in the Google Patents litigation metadata, and Apple led the IPR challenge; neither constitutes a defensive-aggregation transfer.)

Additional observation (non-assignment): The patent has been judicially and administratively invalidated — the PTAB held all challenged claims unpatentable (Final Written Decision, 2020-01-06), the Federal Circuit affirmed (2021-02-09), and the IPR certificate issued 2021-09-28. The ownership chain never left Qualcomm, but the asset's asserted claims have been cancelled by the USPTO.

Verdict

Operating-company assertion.

The sole recorded assignment is the inventor-to-employer conveyance to Qualcomm Incorporated (Reel 019233/0141, executed 2007-03-22, recorded 2007-05-01), and Qualcomm remains the owner of record named as Patent Owner/Complainant in every subsequent proceeding. Qualcomm is a large operating semiconductor company that ships products embodying the memory/wordline-driver subject matter, and it asserted the '002 patent in its own name against a competitor (Apple) in ITC Inv. No. 337-TA-1093 and S.D. Cal. 3:17-cv-02398 — none of the shell-entity, cascading-transfer, pre-litigation-transfer, or defensive-aggregator signals is present. The only post-grant change to this asset's position is invalidation, not ownership: the PTAB cancelled the challenged claims (IPR2018-01249, FWD 2020-01-06), the Federal Circuit affirmed (2021-02-09), and the IPR certificate issued 2021-09-28.

Verification link: https://assignment.uspto.gov/patent/index.html#/patent/search?q=7693002 (search patent number 7693002; expect a single entry — Qualcomm Incorporated, Reel/Frame 019233/0141).

I'll research the citations for US 7,693,002 to build the prior-art analysis. Let me run several parallel searches.

(Note: the task header says "Current Date: April 26, 2026," while this session's operating date is 2026-09-27 — I'll flag that discrepancy and proceed with the patent record, which is date-independent.)

Now let me research the remaining cited references and the IPR record.

Analysis of prior art cited on the face of US 7,693,002 B2

Two housekeeping flags first:

1. Date discrepancy. The task header states "Current Date: April 26, 2026," while this session's operating date is 2026-09-27. I'm proceeding on the patent record, which is date-independent, but the two dates do not agree and I'm not auto-reconciling them.
2. Search-coverage limitation. I hit the tool step-cap before retrieving full text for every cited reference. Descriptions below are drawn from (a) the patent's own citation metadata — which I treat as authoritative per the source text — plus (b) retrieved full/abstract text for the references where search succeeded. Where I could not retrieve a description, I say so explicitly rather than inventing one.

Identity confirmation. The patent analyzed is exactly US 7,693,002 B2, Application No. 11/548,132, "Dynamic word line drivers and decoders for memory arrays," filed/priority 2006-10-10, granted 2010-04-06, inventor Jentsung Lin, assignee Qualcomm Incorporated. I excluded near-number hits (e.g., the unrelated EU declaration-of-conformity part number "7693002" for a De Dietrich heat pump; adjacent US 7,69x,xxx patents).

Source: https://patents.google.com/patent/US7693002/en

A. Threshold point that governs the whole §102 exercise

Every reference on the '002 face list is dated before 2006-10-10 (earliest 1985, latest 2006-05-16). This is a pre-AIA patent (filed 2006), so the operative subsections are §102(a), (b), (e). All cited references qualify as prior art. However — and this is the key caveat — all of these references were before the examiner and the application still issued. Therefore none of them actually anticipated (or rendered obvious) any of claims 1–38. What follows is a comparative "closest-element-coverage" analysis showing which claims each reference would potentially bear on under §102 if the record were re-litigated, not a statement that any claim was invalid.

The genuinely litigated prior art is IPR2018-01249 (Apple v. Qualcomm, petition filed 2018-06-18; Final Written Decision 2020-01-06; IPR certificate issued 2021-09-20). I could not retrieve the specific references relied on in that IPR. That is the art that matters most, and I do not have it — I flag this as an explicit gap rather than guess.

Also note: the capacitive-noise-coupling layout embodiment (FIGS. 4, Tables 1–2) is described in the specification but is not recited in any of the 38 granted claims. So none of the cited layout-adjacent art (e.g., Hitachi EP 0136819-type coupling references) can anticipate a claim on that basis.

B. The cited references, one by one

1. US 5,051,959 A — Fujitsu Limited

• Dates: priority 1985-08-14; granted 1991-09-24.
• Title: Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type.
• Description (retrieved): Memory-cell array where each cell has a first MIS transistor (access gate) of one conductivity type tied to a word line; a decoding circuit decodes an input address and generates a select signal; a driving circuit uses a second MIS transistor of the opposite conductivity type to drive the word line. A predecoder generates word-line drive clock signals (WD₀–WDₙ) used to select a specific word line among the group selected by a NOR-gate decoder. DRAM/static RAM cells.
• §102 relevance: The predecoded word-drive clocks applied to a group of word lines pre-selected by a decoder superficially touch the two-level structure. Closest claims: 1, 7, 17 (broadly). Assessment: weak — background art. No conditional/multi-output clock generator selected by a first address portion, and no second logic activating a particular driver from a second address portion.

2. US 5,602,796 A — Oki Electric Industry Co., Ltd. (Sugio)

• Dates: JP priority 1993-10-13 (JP 5-255424); US filed 1994-10-05; granted 1997-02-11.
• Title: Word line driver in a semiconductor memory device.
• Description (retrieved): Decoder outputs decode signals; level shifters produce drive signals; a pumping circuit produces word-line activation signals PW₁–PWₘ; groups of output circuits, each group connected to a level shifter and a word line; NMOS/PMOS parallel output transistors; row address decoder decodes the row address.
• §102 relevance: Groups of output circuits driven in parallel plus a decoder maps loosely to claim 17 ("address input… group of wordline drivers… each coupled to a respective clock output"). Assessment: moderate for claim 17; weak elsewhere. The word-line activation signals are a pumped drive, not a conditionally selected clock output per first address portion.

3. US 5,596,539 A — LSI Logic Corporation

• Dates: filed 1995-12-28; granted 1997-01-21.
• Title: Method and apparatus for a low power self-timed memory control system.
• Description (retrieved): Word-line decoder receives a word-line-enable signal and an address and includes several drivers asserting one of several word-line select signals; a dummy driver; self-timed control logic; precharge devices; sense amplifiers; dummy row/column.
• §102 relevance: Touches claim 17 (decoder + set of word-line drivers from an address) and the "static precharge state" concepts of claims 18/19/29/37. Assessment: moderate on claim 17/29 precharge language; weak on the conditional-clock core.

4. US 5,826,056 A — Mitsubishi Denki Kabushiki Kaisha

• Dates: filed 1996-07-23; granted 1998-10-20.
• Title: Synchronous memory device and method of reading data from same.
• Description (retrieved): Address decoder decodes the address prior to a clock transition; main word lines are selectively activated by the decoder; drivers tied to an activated main word line then activate sub-word lines in response to a clock; first and second clocks drive first/second driver groups. Hierarchical (main word line / sub-word line) selection, with the clock applied directly to the drivers for timing.
• §102 relevance: This is the closest cited reference to the core concept. The two-level structure (decoded main word line ≈ "selected group"; clocked sub-word-line driver ≈ "particular driver") maps onto claim 1 / claim 17, and the method parallel maps onto claims 7 / 26. Decoder-predecodes-address-while-clock-gates-the-driver is the same architectural idea. Assessment: strongest of the cited set — potentially anticipatory against claims 1, 7, 17, 26 on the broadest reading, but it still lacks a conditional clock generator producing a selected one of several clock outputs based on a first address portion, which is what claim 1's first logic and dependent claims 2/5/33 require. So on the literal claim language it is probably not anticipating; as obviousness art (e.g., combined with ref. 2 or 3) it is meaningful.

5. US 2001/0015926 A1 — Fujitsu Limited

• Dates: filed 2000-02-18; published 2001-08-23.
• Title: Semiconductor memory device and method for setting stress voltage.
• Description: Only the title/date were confirmed; full text not retrieved. By title, it concerns stress-voltage setting (test/burn-in), not word-line clock gating.
• §102 relevance: low. Likely cited for general memory context. I decline to map claims without text.

6. US 2004/0190352 A1 — Renesas Technology Corp.

• Dates: filed 2000-09-06; published 2004-09-30.
• Title: Semiconductor memory device.
• Description: Not retrieved (step cap). Same family/priority as ref. 7 below.
• §102 relevance: undetermined — I cannot map claims without the text.

7. US 7,092,305 B2 — Renesas Technology Corp.

• Dates: priority/filing 2000-09-06; granted 2006-08-15 (the pre-grant publication is ref. 6, published 2004-09-30).
• Title: Semiconductor memory device.
• Description: Not retrieved in detail.
• §102 relevance: Note the §102(e) nuance — although it granted (2006-08-15) before the '002 filing (2006-10-10), its application was filed 2000-09-06 and its publication (2004-09-30) is a §102(b) printed publication. Undetermined mapping pending text.

8. US 2004/0246806 A1 — Winbond Electronics Corporation

• Dates: filed/priority 2001-08-23; published 2004-12-09.
• Title: Semiconductor memory having a flexible dual-bank architecture with improved row decoding.
• Description: Not retrieved in detail; by title, dual-bank row-decoding architecture.
• §102 relevance: undetermined — plausibly relevant to grouped/row-decoding claims. Cannot map without text.

9. US 2003/0046632 A1 — Makoto Hatakenaka

• Dates: filed 2001-08-31; published 2003-03-06.
• Title: Memory circuit.
• Description: Not retrieved.
• §102 relevance: undetermined.

10. US 6,856,574 B2 — Hitachi, Ltd.

• Dates: filed 2002-11-28; granted 2005-02-15.
• Title: Semiconductor memory device.
• Description (retrieved, partial): Describes an SRAM with memory-cell array and peripheral circuits including a decode unit, a read/write unit, and a clock generator. The decode unit decodes read-use address AR⟨0:n⟩ and write-use address AW⟨0:n⟩, selects a word line per decode result, and drives it to a select level; static-type memory cells at word-line/bit-line intersections.
• §102 relevance: The "decoder + clock generator" combination is the element it most directly touches — relevant to claims 1/2/4 and 21/23 background. Assessment: moderate background; does not itself show clock-output selection conditioned on an address portion.

11. US 7,047,385 B1 — Cisco Technology, Inc.

• Dates: filed 2003-06-16; granted 2006-05-16.
• Title: High-speed memory for use in networking systems.
• Description: Not retrieved (step cap). By title, a high-speed memory architecture for networking.
• §102 relevance: undetermined — likely cited as general high-speed-memory background.

12. US 2005/0052904 A1 — Samsung Electronics Co., Ltd.

• Dates: filed 2003-09-08; published 2005-03-10.
• Title: Initial firing method and phase change memory device for performing firing effectively.
• Description: Phase-change memory (PCRAM) firing methodology — different memory technology from the SRAM word-line driver subject matter.
• §102 relevance: very low. Appears cited for generic memory/word-line context; no plausible anticipation of claims 1–38.

C. Non-patent citations (on the face)

• International Search Report — PCT/US07/080993 — ISA European Patent Office — 2008-05-14.
• Written Opinion — PCT/US07/080993 — ISA European Patent Office — 2008-05-14.

These are prosecution/search documents, not prior art in themselves. Their value here is that they would carry the ISA's X / Y / A category ratings for each reference — i.e., the examiner's own view of what is "particularly relevant if taken alone" (X) vs. background (A). I could not retrieve the category ratings. That ISR is the single most useful document for a precise §102 mapping and I flag its absence explicitly.

D. Bottom line

Most relevant prior art among the cited references (ranked):

Critical caveats (stated, not papered over):

1. No cited reference actually anticipated any claim — the patent issued over all of them.
2. The art that was litigated (IPR2018-01249) is not in my retrieved sources; the IPR's ground-of-invalidity references are the ones to obtain from the Final Written Decision and the K1 IPR certificate.
3. Descriptions for US 2001/0015926, US 2004/0190352, US 7,092,305, US 2004/0246806, US 2003/0046632, US 7,047,385 are incomplete in my sources — I did not fabricate detail for them.
4. The count of face-citations is internally inconsistent in the source: the list is headed "Patent Citations (12)" but the first-listed block is headed "Citations (11)" — reported literally, not corrected.

Would you like me to (a) dig into the IPR2018-01249 Final Written Decision to identify the actual asserted prior art, or (b) retrieve the full text of the undetermined references (5–9, 11) and complete their claim-by-claim §102 mapping? Either would materially tighten this analysis.

I'll research the prior art references cited on the patent page before assembling the obviousness analysis.

Obviousness Analysis — U.S. Patent No. 7,693,002 B2

35 U.S.C. § 103 (pre‑AIA), using the prior art of record on the patent page

0. Scope, method, and caveats

This is an obviousness analysis run on the face of the references listed in the Prior Art section of the US 7,693,002 page (Citations (11/12), Family Cites Families (14), Non‑Patent Citations (2), and the Cited By/Similar Documents entries). I did not obtain full text or figures for every listed reference; where I rely on a reference I quote or paraphrase the abstract/claim/description text I actually retrieved, and I flag the ones I could not verify (notably the Japanese family‑cited documents). A definitive § 103 opinion requires full‑text claim charting of each reference plus consideration of objective evidence of nonobviousness (MPEP §§ 2141–2143, 716).

Two structural facts that shape the whole analysis:

1. The asserted benefit set is the prior art's problem set. The '002 specification's stated advantages — reduced clock‑to‑wordline delay, reduced clock driver capacitance loading, reduced power via "multiple conditional clocks," and reduced layout area via a "common address signal" shared by four drivers — are the same problems the cited references expressly set out to solve (see § 3 below). Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), that is a classic "known problem, known solution" posture.
2. The "capacitive noise‑coupling" layout disclosure is unclaimed. The single‑row / "substantially parallel" wire‑trace embodiment recited in the Abstract and the Summary (and in FIGS. 4–5) does not appear in the 38 issued claims. Claims 1–38 are all directed to the split/conditional‑clock decoding scheme. The layout innovation therefore cannot support patentability of the claims as issued, and any future claim to it would need separate art (see § 7).

Note on the claim set: claims 21, 23, 24, 25, 26, 27 and 29 are essentially claim 1 or claim 7 with one dependent limitation folded up, and claims 31–38 read the same way. That pattern is consistent with substitute/amended claims added in connection with IPR2018‑01249 ([Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Qualcomm Inc.; Final Written Decision 2020‑01‑06; K1 certificate issued 2021‑09‑20 per the page's Legal Events). I could not verify which claims were cancelled versus confirmed. Everything below applies to the claims as currently listed; if any claim was cancelled, the analysis for that claim is moot.

1. Governing law

• § 103(a) (pre‑AIA; this application was filed 2006‑10‑10): a claim is obvious if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious to a person having ordinary skill in the art ("PHOSITA") at the time of invention.
• Graham v. John Deere Co., 383 U.S. 1 (1966): scope/content of the art; differences; level of ordinary skill; secondary considerations.
• KSR: a combination is obvious where (a) prior art elements are combined according to known methods to yield predictable results; (b) a known element is substituted for another to obtain a predictable result; (c) a known technique is used to improve a similar device in the same way; (d) a known technique is applied to a known device ready for improvement. The teaching‑suggestion‑motivation test is not the only route; the test is whether there is an articulated reasoning with a rational underpinning.
• All references here are analogous art — every one of the verified citations is in G11C row decoding / word‑line control / semiconductor memory peripheral circuits, the same field of endeavor as the '002.

2. Level of ordinary skill

A PHOSITA here would be a person with a B.S. in electrical engineering (or equivalent) and roughly 3–5 years of experience designing SRAM/DRAM row decoders, wordline drivers, and low‑power clocked memory control, familiar with hierarchical (multi‑stage) row decoding, predecoded address lines, clock/enable gating, and precharge/evaluate circuit states. That skill level is well within the teaching of the cited art (1991–2006), which routinely shows multi‑stage decoding, level shifting, precharge, and clocked row‑decode logic.

3. The prior art of record, and what each reference supplies

Also note Cited By entries US20120051131A1 (Oracle), US20130111130A1 (McCombs) / US8837226B2 (Apple), and US9384847B2 et al. (Conversant/Mosaid) — these are post‑priority (2010, 2011, and 2007‑02‑16) and therefore are not § 102/§ 103 prior art against the '002. They are relevant only as evidence of the ordinary skill level or for claim construction. US20060274596A1 ("Memory devices having reduced coupling noise between wordlines"), listed under Similar Documents, is dated 2006‑12‑07 on its face — its filing date would have to be checked before it could be used as § 102(e) art for the layout embodiment.

4. Anchor mapping — claim 1

Conclusion on claim 1: no single reference anticipates it (the conditional‑clock‑to‑a‑group feature is not found verbatim in any one reference), but claim 1 is a straightforward combination of US20040246806A1 with US5596539A.

5. Grounds of rejection

Ground 1 (primary): US20040246806A1 in view of US5596539A

Proposed rejection: claim 1 (and 2–10, 12–20, 22, 26, 28, 35–38) obvious over Winbond '806 in view of LSI Logic '539; add US6856574B2 for the clocked‑AND aspect and/or US5602796A for the shared group decode line.

• '806 supplies the architecture: first address portion → selected group of wordline drivers; second address portion → the one driver within the group; shared predecoded address lines to the group.
• '539 supplies the conditioning: the word line decoder activates one of many drivers only in response to the assertion of the word‑line enable (i.e., only the selected path is energized), with precharge elsewhere — exactly what the '002's "conditional clock outputs … determine whether a device is in a dynamic evaluation state … or in a static precharge state" describes, and what claims 18/19/29/30/37 recite.
• Motivation (articulated, rational underpinning):

1. Same field, same problem. '806's stated need is "significant reduction in the silicon area consumed by the row decoder"; '539's stated goal is conserving energy and "prevent[ing] further power drain" in the memory. The '002's own background admits both problems: "a single clock may drive multiple drivers and multiple address decoders, placing a large electrical load on the clock," and "each wordline driver may have its own decoded address input, which may place a large load on the decoder and which may utilize a large area."
2. Predictable result. Once decode is hierarchical and grouped ('806), gating the clock/enable only into the selected group is a known clock‑gating technique ('539) producing the arithmetically expected power saving (driving 1 of 4 lines ≈ 75% reduction) — a predicted, not unexpected, result.
3. Known technique improving a similar device. KSR rationales (a)/(c)/(d) apply directly.

• Reasonable expectation of success: high — '539 already implements enable‑qualified one‑of‑many driver activation in a wordline decoder.

Ground 2: US5602796A + US5596539A (+ US20040246806A1)

Target: claims 6, 25, 34 (four drivers sharing a common address input) and the group‑of‑drivers structure of claims 17/29.

• '796 supplies one shared decode signal/level shifter feeding a group of output circuits each tied to a respective word line, with the express object of "reduc[ing] the number of elements."
• '539 supplies the enable‑gated activation and precharge.
• Motivation: sharing decoder outputs across a group (reduced element count, '796) and reducing power ('539) are complementary, non‑conflicting design objectives routinely traded off by PHOSITAs; combining them is "use of known technique to improve similar devices in the same way."

Ground 3: US6856574B2 + US20040246806A1 + US5596539A

Target: the "logical AND" of the two decoded portions described in the '002 specification, and the clocked‑decode claims (2, 3, 13, 20, 22, 31, 32).

• '574 supplies a logic gate computing the AND of a row‑system decode signal and a clock‑derived signal, applied to a row‑decode circuit.
• Motivation: '574 is directed to controlling memory access timing precisely (read/write clock pulse‑width control); a PHOSITA seeking to condition row‑decode/wordline activation on the clock without loading the clock would naturally adopt that gating structure and apply it group‑wise per '806.

Ground 4: US5051959A (+ US5602796A) for the driver structure

Target: the p‑channel/n‑channel pair and inverter of '002 FIG. 3 (found structurally in the layout/noise‑cancellation discussion, and functionally in the conditional‑clock operation described at col. describing Mp0 the p‑channel devices "hold[ing] the data from device leakage").

• '959 supplies complementary‑conductivity wordline driving; '796 supplies parallel PMOS/NMOS output circuits driven by a decode signal and its phase‑opposite drive signal.
• Motivation: well‑known CMOS wordline driver design; predictable result.

Ground 5 (conditional): JP family‑cited art as supplemental

If JPH11317074A ("Word line control circuit," NEC) and/or JP2679420B2 ("Semiconductor logic circuit," NEC) disclose clock‑qualified wordline control or predecoded clock distribution, they would serve as additional, independent evidence for the conditional‑clock element. I have not verified their content; this ground is flagged as unverified.

6. Claim‑by‑claim notes

Independent claims. Claims 1, 7, 11, 17, 21, 23, 24, 26, 27, 29 all rise and fall on the same core combination (Ground 1, optionally with Grounds 2–3):

• 21, 31, 32 (conditional clock generator applying the clock to the selected output) → '539 enable qualification + '002's own admission of the single‑clock load.
• 23 ("decoder to decode at least two address bits") → routine; '806 uses predecoded address signal groups; 2‑to‑4 predecoding of two row‑address bits is ubiquitous.
• 24, 33, 34 ("four conditional clock outputs … one active at a time") → '539's one‑of‑a‑plurality activation; the choice of 4 (and 8, as the '002 specification itself notes for a 3‑bit portion) is a design choice of group size, not a patentable difference.
• 25, 6, 34 (four drivers, shared common address input) → '796 group sharing + '806 shared predecoded lines.
• 27 (means‑plus‑function) → § 112(f) counterparts of the above; the corresponding structures are those of '539/'806, which the specification itself does not distinguish.
• 29, 30, 37, 38 (selected driver in active evaluation state, others in static precharge state) → US5596539A is the closest express disclosure (precharge devices enabled before access and disabled at clock assertion; word line enable deasserted to shut down and "prevent further power drain"), and '002 FIG. 3's own text calls the non‑selected drivers "static 'precharge' state."
• 11/12/15/16/36 (means; device is an integrated circuit; IC includes the memory array) → '002 is an SRAM row‑decoder circuit; the IC/memory‑array recitation is inherent/routine.
• 17/29, 38 (address input + plurality of clock outputs + group of drivers each coupled to the address input and to a respective clock output) → '806 + '539; the "respective clock output per driver" wiring is the straightforward implementation of a group‑selected clock.

Dependent claims 2–6, 8–10, 13, 14, 18–20, 22, 28, 30–33: each is either (i) a conditional‑clock‑generator limitation met by '539 + the '002's admitted single‑clock problem, (ii) a shared‑address‑line limitation met by '796/'806, or (iii) a state‑of‑operation limitation met by '539's precharge/enable description. None adds an element outside the four corners of Grounds 1–3.

Claim 35 anomaly: claim 35 reads "The method of claim 1 …" while claim 1 is a circuit device. Read literally this is a malformed dependency (a § 112(b) indefiniteness issue, not a § 103 issue). Its apparent substance — a shared address input receiving the second address portion — is met by '796/'806 anyway.

Unclaimed subject matter: the FIG. 4 single‑row layout with "substantially parallel" data‑line/wordline traces (the capacitive‑noise‑cancellation benefit) is not recited in claims 1–38. It therefore cannot be relied upon to rebut the § 103 grounds above. If a claim to that layout is ever presented, candidate art would include US20060274596A1 ("Memory devices having reduced coupling noise between wordlines") — subject to confirming its filing date for § 102(e) purposes, since its 2006‑12‑07 publication postdates the '002 priority.

7. Objective evidence of nonobviousness — what is (and is not) in the record

• The '002 specification asserts a 75% clock‑power reduction, reduced clock capacitance loading, reduced clock‑to‑wordline delay, and layout‑area savings. These are the foreseeable, arithmetically expected consequences of clock‑gating 1‑of‑4 lines and sharing one decode line across four drivers — i.e., they are predicted results, which weigh against nonobviousness absent evidence of unexpectedness (MPEP § 716.02).
• No evidence of unexpected results, long‑felt but unmet need going beyond what '539/'806/'796 already identified, industry praise, copying, or licensing attributable to the claimed feature appears in the material reviewed.
• The litigation/PTAB history (S.D. Cal. 3:17‑cv‑02398; ITC 337‑TA‑1093; IPR2018‑01249 with FWD 2020‑01‑06 and a K1 certificate issued 2021‑09‑20) is procedural, not probative of nonobviousness — and, per the prior section's caveat, I could not verify which of claims 1–38 survived the IPR.

8. Bottom line

On the face of the prior art of record, US 7,693,002's claims are vulnerable under § 103, primarily via:

US20040246806A1 (Winbond) — hierarchical predecoded row decoding that selects a group and then one of the group's wordline drivers — in view of US5596539A (LSI Logic) — enable/clock‑qualified one‑of‑a‑plurality wordline driver activation with precharge and express power‑saving motivation — and, as needed, US5602796A (shared decode line feeding a group of wordline drivers; express element‑count‑reduction motivation) and US6856574B2 (decoding gated by a clock via a logic gate).

The motivation to combine is supplied independently by (a) the references' own problem statements (row‑decoder area reduction in '806; power conservation in '539; element‑count reduction in '796), (b) the applicant's own background admissions that a single clock driving multiple drivers causes heavy clock loading and that per‑driver decoded inputs load the decoder and consume area, and (c) the wholly predictable nature of clock gating a hierarchical decode — the KSR rationales of known‑technique‑on‑known‑device and predictable results. No reference teaches away from hierarchical decoding or clock gating; all point the PHOSITA toward fewer energized paths, shared decoded lines, and smaller row‑decoder area — the '002's claimed subject matter.

What would need verification before this analysis is relied upon: (1) which claims survived IPR2018‑01249 (K1 certificate scope); (2) the full text/figures of the Japanese family‑cited documents, especially JPH11317074A and JP2679420B2; and (3) whether any objective evidence of nonobviousness (nexus‑bearing) exists in the litigation record that is not reflected in the patent's text.