US 7446515

I'll search for authoritative information on this patent number.

The searches returned no relevant results. Let me try more targeted queries.

Let me run a couple more targeted searches to confirm litigation status.

Summary: US Patent 7,446,515 (US7446515B2)

Important threshold note: I searched for this specific number (7446515) and found no CAFC 2026 docket, no PTAB proceeding, and no district-court litigation in which this patent appears. The results returned were either the patent itself or unrelated documents containing the digit string "7446515" (e.g., a Japanese patent JP7446515B1 for a humidifier, a Brazilian company registration "7446515 MODULAR TRANSPORTES LTDA," and a maize gene ID "Gl-7446515"). I therefore cannot report any litigation activity, and I am not asserting that none exists — my tools may not cover every docket. Everything below is drawn from the authoritative patent text (Google Patents / FreePatentsOnline / Justia), which agree with one another.

Bibliographic data

Source: https://patents.google.com/patent/[US7446515](/patent/US7446515)/en

Abstract (as issued)

An LDO regulator including a pass transistor having a first electrode coupled to produce an output voltage, a control electrode, and a second electrode coupled to receive an input voltage. An error amplifier has a first input coupled to a first reference voltage and an output coupled to the control electrode of the pass transistor. A first feedback circuit produces a first feedback voltage coupled to a second input of the error amplifier. An auxiliary amplifier has a first input coupled to a second reference voltage and an output coupled to the output of the error amplifier. A second feedback circuit has an input coupled to the output of the auxiliary amplifier and an output producing a second feedback voltage coupled to a second input of the auxiliary amplifier. The auxiliary feedback loop takes over control of the feedback in the LDO regulator at high frequencies.

Plain-language overview of the independent claims

The patent has three independent claims — 1, 16, and 20 (20 claims total).

Claim 1 — the LDO regulator (apparatus). A low-dropout regulator built from five elements:

• (a) a pass transistor whose first electrode provides the regulated output (Vout), whose control electrode is driven, and whose second electrode receives the unregulated input (Vin);
• (b) an error amplifier that compares a first reference voltage (Vref) against feedback and drives the pass transistor's control electrode;
• (c) a first feedback circuit (in the figures, a resistor divider 9/10) that senses the regulator output and returns a first feedback voltage to the error amplifier's second input;
• (d) an auxiliary amplifier whose first input sits at a second reference voltage (ground) and whose output is tied to the error amplifier's output node; and
• (e) a second feedback circuit that takes the auxiliary amplifier's output as its input and returns a second feedback voltage to the auxiliary amplifier's second input — expressly "for taking over control of the feedback in the LDO regulator at high frequencies."

The gist: a second, auxiliary feedback loop runs in parallel with the conventional main loop and assumes loop control at high frequency, so that a zero tracks the load-capacitance pole and the regulator stays stable across wide ranges of load current and output capacitance.

Claim 16 — the method. Steps for operating such an LDO: (a) apply input voltage to the pass transistor's second electrode; (b) apply a second reference voltage to the auxiliary amplifier's first input; (c) couple the auxiliary amplifier output to the error amplifier output; (d) generate a second feedback voltage with a second feedback circuit taken from the auxiliary amplifier output and fed to the auxiliary amplifier's second input; and (e) operate that second feedback circuit to control overall feedback operation above a predetermined frequency.

Claim 20 — the LDO regulator (means-plus-function form). Recites the same pass transistor / error amplifier / first feedback circuit environment and the input and second-reference voltages, then claims: means for coupling the auxiliary amplifier output to the error amplifier output; means for producing a second feedback voltage responsive to the auxiliary amplifier output plus means for coupling that voltage to the auxiliary amplifier's second input; and means for operating the second feedback circuit to control overall feedback above a predetermined frequency.

Notable dependent claims (context for scope)

• Claim 2: error amplifier output may be directly coupled to the pass transistor gate.
• Claim 3/4: the second feedback circuit includes a feedback transistor (gate at auxiliary amplifier output, one electrode to the output, other to the high-pass filter), realized as FETs (gates/sources/drains).
• Claim 5/6: N-channel MOS pass transistor; PMOS differential input stage plus folded-cascode stage, with the auxiliary amplifier's second CMOS differential input stage feeding the same folded-cascode stage.
• Claim 7/8: error-amplifier transconductance (g_mi) "substantially greater" than auxiliary-amplifier transconductance (g_ma); claim 8 quantifies this as approximately 10×.
• Claims 9–11: high-pass filter (R_f, C_f) in the second feedback circuit; variable resistor settable by a control voltage representative of load current, e.g., an N-channel MOS transistor.
• Claims 12–13: second feedback circuit takes over at frequencies above g_mo/C_L.
• Claim 14–15: AC feedback path tracks the load-capacitance pole to hold a minimum phase margin; claim 15 states the phase-margin expression as 90° − (180°/π){tan⁻¹[(g_mi/g_ma)^1/2] + tan⁻¹[(g_ma/g_mi)^1/2]}.

Points of uncertainty / anomalies I will not silently correct

• Formula inconsistency: Claim 15 and the Summary of the Invention use a "+" between the two arctangent terms, whereas Equation (8) in the Detailed Description uses a "−" and states a simplified form. I am reporting both as they literally appear rather than harmonizing them.
• Figure/description typo: In the FIG. 2 narrative the error amplifier's "output Vout" is said to be coupled by conductor 3 to the gate — presumably meant to be the gate drive voltage V_g, not Vout. I have not corrected the identifier.
• PMOS/bipolar scope: The specification states the technique is conceptually applicable to PMOS and bipolar implementations, though the claims are directed to the described (NMOS/FET) regulator.
• No litigation found: As noted above, my searches for a CAFC 2026 docket, PTAB proceeding, or infringement suit involving this exact patent returned nothing. Treat any assertion that this patent has been litigated in 2026 as unverified unless confirmed in PACER/CAFC dockets directly.

I'll search for litigation records involving US patent 7446515.

Initial searches surfaced nothing relevant. Let me check the specialized litigation portals directly.

Let me try a few more targeted sources, including litigation dockets and the patent's appellate history.

Search Results: Litigation Involving U.S. Patent No. 7,446,515

Conclusion: I found no litigation involving U.S. Patent No. 7,446,515.

I was unable to locate any district court action, Court of Appeals for the Federal Circuit appeal, ITC Section 337 investigation, or PTAB post-grant proceeding (IPR/PGR/CBM) in which U.S. 7,446,515 was asserted, challenged, or otherwise at issue.

What I searched and what I found

I ran multiple searches targeting patent-litigation-specific sources (Unified Patents litigation/PTAB portal references, PTAB petition documents, court dockets, CourtListener, and general web/case-law indices), using both the plain number 7446515 and the patent-title terms ("compensating NMOS LDO regulator," "auxiliary amplifier," Texas Instruments LDO).

Every "hit" for the numeral 7446515 fell into one of the following unrelated categories, none of which involves U.S. 7,446,515:

I want to be transparent about the limits of this search: I do not have direct, authenticated query access to PACER's full docket database or to commercial dockets such as Docket Navigator or Lex Machina through the tools available to me. My "no litigation found" statement is therefore based on the public sources that were reachable, not on an exhaustive PACER full-text verification. The fact that the Google Patents record for US 7,446,515 (fetched 2026-09-24) lists no litigation, no PTAB proceedings, and no reassignment (only an assignment to TI and maintenance-fee payments) is consistent with — but not conclusive of — the absence of litigation.

Why an absence of litigation is plausible for this patent

The intrinsic record supports the "no litigation" conclusion rather than suggesting my search simply missed something:

• Owner/assignee: Texas Instruments Incorporated (original and current assignee; no reassignment beyond the inventor-to-TI assignment recorded 2007-01-17). TI is an operating company that does not typically assert its internal analog-IP patents offensively, and no NPE ever acquired this patent per the record.
• No PTAB challenges of record: The USPTO feed for this patent shows only prosecution and maintenance-fee events (fees paid at 4, 8, and 12 years; 12th-year fee paid 2020-04-15, large entity). There are no IPR/PGR petitions, no reexamination certificates, and no litigation-driven stays or transfer orders.
• Status: Active, with anticipated expiration 2027-01-17 (20 years from the 2007-01-17 filing date; the 2006-08-31 provisional priority date does not extend the term itself).
• The patent's forward citations (e.g., Qualcomm US 9,684,325; US 10,175,706; Intel US 11,921,529; Samsung US 11,429,127; TI US 9,577,508) reflect technical citation activity in LDO/PSRR designs, not adversarial proceedings against the '515 patent.

Recommended verification steps (for a definitive answer)

Because a negative result cannot be verified by web search alone, if you need a litigation-grade clearance, confirm against:

1. Unified Patents Portal — litigation case list: https://portal.unifiedpatents.com/litigation/caselist (filter by patent number 7446515)
2. Unified Patents Portal — PTAB case list: https://portal.unifiedpatents.com/ptab/caselist
3. PACER and CourtListener/RECAP full-text docket search for "7,446,515" / "'515 patent"
4. Docket Navigator / Lex Machina patent case searches
5. USITC EDIS (for any Section 337 complaint listing the patent)

If none of those returns a case, you can state with reasonable confidence that U.S. 7,446,515 has never been litigated — which is the conclusion my search supports.

I'll verify the structured data against live sources before writing the analysis.

PTAB / AIA Trial Analysis — U.S. Patent 7,446,515

Patent: US7446515B2 — "Compensating NMOS LDO regulator using auxiliary amplifier"
Patent owner: Texas Instruments Incorporated (original assignee; sole recorded assignee per the 2007-01-17 assignment, Reel/Frame 018801/0564)
Inventor: Jianbao Wang
Priority: 2006-08-31 (provisional 60/824,208) · Filed: 2007-01-17 · Granted: 2008-11-04
Listed anticipated expiration: 2027-01-17

Proceedings overview

There are zero AIA trial proceedings on this patent. The USPTO Open Data Portal (ODP) structured feed supplied for this analysis reports no IPR, PGR, or CBM proceeding for US 7,446,515 as of the most recent ingest, and independent web searching (PTAB filings coverage, PTAB E2E references, Unified Patents docket pages, and general IPR/PGR/CBM coverage) surfaced no petition — filed, instituted, denied, or terminated — naming this patent. There is accordingly no institution decision, no Final Written Decision, no settlement, and no Federal Circuit appeal to report, and no proceeding-by-proceeding entries follow because inventing proceeding numbers or outcomes is not permissible.

Defensive posture: This is a "no PTAB record" patent, not a "hardened by IPR" patent and not a "claims canceled" patent. For a defendant, that means two things simultaneously: (i) you have no free kill — no FWD canceling claims that a demand letter might rest on — and (ii) you are subject to no § 315(e)(2) estoppel, so the entire prior-art universe remains available to you. The absence of IPRs is not a signal of patent strength here; it is almost certainly a function of who owns the patent (Texas Instruments, a large operating company that does not assert patents as a monetization strategy) and the fact that the term is nearly run (see below).

Important context that reframes the standard "defendant vs. troll" analysis:

Proceedings

None. No IPR, PGR, or CBM proceeding exists on US 7,446,515 in the ODP structured data or in any public source located.

For completeness, the following sources were checked and returned nothing specific to this patent:

• USPTO ODP AIA-trial feed (canonical, per the supplied structured block): no proceedings
• PTAB E2E / PTAB Decisions public records coverage: no proceeding referencing US 7,446,515
• Unified Patents docket/proceeding pages: no entry
• General press and docket-coverage searches for IPR/PGR/CBM petitions citing "7,446,515" / "7446515": no relevant hits (results were the patent itself, a Japanese humidifier patent JP7446515B1, a Brazilian transport-company registration, and a maize gene identifier — all false positives on the digit string)

Strategic summary

Claim status: all untested. Claims 1–20 of US 7,446,515 are untested before the PTAB. Nothing is canceled; nothing is sustained by an administrative adjudication. Independent claims 1 (apparatus), 16 (method), and 20 (means-plus-function apparatus) — and all fifteen dependent claims — stand exactly as they issued on 2008-11-04. The dependent-claim architecture matters if you are mapping a product: claim 8 (g_mi ≈ 10 × g_ma), claim 11 (N-channel MOS variable resistor), and claim 13 (auxiliary loop dominance above g_mo/C_L) supply the narrowest, most concrete fallbacks, while claim 15's phase-margin formula is arguably the most difficult limitation in the patent to meet literally — note the previously flagged "+" vs. "−" discrepancy between claim 15 / Summary and Equation (8) in the Detailed Description, which is a live indefiniteness-adjacent issue (§ 112(b)) that no tribunal has yet construed.

Estoppel landscape: nothing is barred. Because no IPR was ever instituted, § 315(e)(2) estoppel does not attach to anyone. Any defendant today may raise, in district court or in a fresh IPR, every prior-art ground it can find — including art cumulative of the three references cited on the face of the patent: US5982226A (TI, "Optimized frequency shaping circuit topologies for LDOs"), US6861827B1 (System General, adaptive frequency compensation), and US7015680B2 (Micrel, current-limiting circuitry). Conversely, because no IPR exists, there is also no Shaw-type dispute to exploit and no institution decision to mine for the Board's claim constructions. A challenger would be litigating this patent's claim scope from a blank slate — which cuts both ways: no adverse construction against you, but no helpful one either.

Pattern signals: none. No petitioner has filed once, let alone serially. No defensive aggregator (Unified Patents or similar) appears anywhere in the chain. Texas Instruments has never taken this patent into an AIA trial as patent owner, and — per the prior section's search — has not asserted it in the litigation located. There is no appeal history to the Federal Circuit. The single most salient "pattern" is the owner profile: a large operating company holding a component-level LDO regulator patent that it uses defensively, not assertively. Combined with ~3.5 months of nominal term remaining, the practical assertion risk from this patent today is very low, and the economics of a defensive IPR (hundreds of thousands of dollars against a patent expiring in the next quarter) are prohibitive.

Recommended next steps

If you are a defendant being asserted against under US 7,446,515:

1. Do not file an IPR reflexively. There is no FWD to link to and no proceeding to point at, because none exists. The statutory clock under § 316(a)(11) means an FWD would be due roughly a year after institution — well past the listed 2027-01-17 expiration. Confirm the expiration date and any patent-term adjustment in Patent Center first; if the patent expires in Q1 2027, the IPR is almost certainly value-destroying.
2. Lead with § 112(b) on claim 15 and on the "substantially greater" language of claim 7, not with prior art. The internal "+" vs. "−" inconsistency between claim 15 / Summary of the Invention and Equation (8) is a documented, unresolved claim-scope defect that no tribunal has addressed. Similarly, "substantially greater" in claim 7 and "at least a predetermined phase margin" in claim 14 are relative terms with no objective boundary in the intrinsic record.
3. Verify in-force status. The most recent maintenance-fee event in the source record is the 12th-year payment on 2020-04-15. Check USPTO Patent Center for the subsequent fee and for any lapse, reinstatement, or petition under 37 C.F.R. § 1.378. If the patent lapsed, the case ends there and none of the above matters.
4. Confirm the litigation predicate. The prior section found no suit or CAFC docket for this patent. Before investing in any defense, verify the demand-letter basis — it is possible the patent number is being cited in error or as part of a broader portfolio demand in which the operative asserted patent is a different one (TI holds many LDO patents; e.g., US9,577,508, "NMOS LDO PSRR improvement using power supply noise cancellation," appears in this patent's citing-family list).
5. If you nonetheless need prior art, there is no estoppel and no § 315(b) bar unless you have already been served with a complaint on this patent more than one year ago — if served within the last 12 months, an IPR remains timely, but weigh it against point 1.

If no PTAB activity is the question being asked: the answer is plainly there is none. This patent has never been before the Board. The absence is itself informative — combined with an operating-company owner, zero located litigation, and a term expiring in the next quarter — but it should be read as low assertion pressure, not as adjudicated strength.

Reliability note: I found no PTAB proceeding, and I am not asserting that none exists in any forum my tools cannot reach. The canonical ODP structured feed says none exists, and every independent search I ran corroborates that. If a proceeding surfaces that this analysis missed, it should be treated as controlling over the "zero proceedings" conclusion above.

I'll research the assignment record for this patent. Let me run targeted searches.

Let me cross-reference the asserter directories and check for any post-issuance transfers.

Let me look for the specific recorded assignment cover sheet and any correspondent of record.

I've reached my search-step limit, but I have what I need from the authoritative patent text (which embeds the full Google Patents legal-events register) plus the cross-reference searches. Below is the ownership-chain reconstruction.

Inventors

Pattern note — no fire-sale precursor. Wang is the sole named inventor. He is a repeat TI inventor (also on TI's later application US20100052635A1, "Compensation of LDO regulator using parallel signal path with fractional frequency response," filed 2008-08-26 and granted as US 8,115,463), and later appears on Apple filings as well. That is ordinary engineer career mobility out of a large operating company, not the "all inventors gone within 12 months" cluster that precedes a portfolio sale. No red flag here.

Original assignee

Texas Instruments Incorporated (Dallas, TX). Confirmed as the assignee of record on the issued patent and on the recorded assignment.

• Primary line of business: Analog and embedded semiconductor design and manufacturing. This patent sits squarely in TI's analog/LDO product line — the specification itself references the assignee's TPS731 NMOS LDO product as prior art, which is direct evidence TI practices in this exact technology space.
• Product embodying the claims: TI's LDO regulator family (TPS73xxx and successors) is the relevant commercial line; the spec's own discussion of the TPS731 establishes that TI ships regulators in this area. I cannot confirm from the sources I reached that a specific shipping die reads on the issued claims (that would require a teardown/claim chart), so treat "ships an embodying product" as likely but not verified to claim level.
• Current status: Operating. Per TI's own Rule 7.1 corporate disclosure statement filed in Texas litigation, TI is publicly traded, has no parent corporation, and no entity owns >10% of its stock.

Assignment timeline

The USPTO assignment register, as indexed in the Google Patents legal-events record, contains exactly one conveyance, and it is the original inventor→company assignment. All post-issue events are maintenance-fee payments, not transfers.

• 2007-01-15 (executed) / recorded 2007-01-17 — Reel 018801/0564
  • Conveyance: Assignment (Assignment of Assignors' Interest)
  • Assignor: Wang, Jianbao
  • Assignee: Texas Instruments Incorporated (Texas, USA)
  • Correspondent: Not exposed in the indexed legal-events record. The Google Patents register returns only code "AS," owner name, free-form text "ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WANG, JIANBAO;REEL/FRAME:018801/0564," and the effective date. I did not independently retrieve the Assignment Center cover sheet for reel 018801/0564, so I will not name a correspondent or firm — I cannot verify it, and TI assignment cover sheets are typically filed by TI's own internal patent-assignment desk rather than an outside firm. No correspondent-recurrence finding can be made on one unverified data point anyway.
  • Context: Standard employment/inventor assignment — the inventor's pre-filing title transfer to his employer; not a sale, spin-out, or securitization.

No further recorded assignments exist. There is no post-issuance transfer of any kind — no change of name, no security agreement, no LLC assignment, no defensive-aggregator acquisition. Per the task instruction, this is itself the finding: TI still owns the patent.

Supporting non-transfer events (fee payments, not ownership changes):

Expected expiration: 2027-01-17 (per the register's "anticipated expiration").

Timeline diagram

timeline
    title Ownership of US 7446515
    2006 : Provisional application filed by TI
    2007 : Utility application filed
         : Assignment executed to Texas Instruments
         : Assignment recorded reel 018801 frame 0564
    2008 : Patent US7446515B2 issued
    2012 : Maintenance fee paid year 4
    2020 : Maintenance fee paid year 12

NPE / troll-pattern signals

Verdict

Insufficient data — specifically, the "only the original assignment" case named in the rubric.

Justification: The complete ownership chain is a single recorded conveyance — reel 018801/0564, executed 2007-01-15 and recorded 2007-01-17, assigning from inventor Jianbao Wang to Texas Instruments Incorporated — with no post-issuance transfers of any kind, only routine maintenance-fee payments through 2020. There is no second assignee, no shell LLC, no known asserter, and no pre-suit transfer, so not a single NPE signal is present; but because the chain contains only the original assignment, the rubric directs the "Insufficient data" label rather than "Operating-company assertion" (I could not verify TI is suing competitors on this patent — in fact I found no litigation naming it at all). The practical read is the benign one: this is a Texas Instruments captive portfolio patent, still owned by TI and remaining in force until the 2027-01-17 expiration.

Verify at: https://assignmentcenter.uspto.gov/ (search application 11/654,049 or patent 7,446,515) — and note that the correspondent field for reel 018801/0564 is the one detail I could not confirm and would want pulled directly from the cover sheet before making any correspondent-based finding.

Caveat on scope: the Google Patents legal-events register is normally a faithful mirror of the Assignment Center, but it can lag on very recent recordings. My searches surfaced no activity later than the 2020-04-15 fee payment; if you need current-as-of-today assurance, pull the Assignment Center abstract directly for application 11/654,049. I found no evidence of any such later recording.

I'll search for the specific patent and its cited prior art.

Prior Art Analysis — US 7,446,515 B2 ("Compensating NMOS LDO regulator using auxiliary amplifier")

Threshold: identifying the actual prior art on the face of the patent

US 7,446,515 has exactly three references cited against it in the "Patent Citations (3)" table on Google Patents (all marked "cited by examiner"). Everything else on the page (the "Cited By (16)/(23)" and "Families Citing this family (29)" tables) is forward citation material — later patents that cite '515 — and is therefore not prior art to it. The three backward citations are the universe I analyze below.

All three predate the earliest priority date carried by '515 (provisional 60/824,208, filed 2006-08-31), so all three are available as prior art. D1 and D2 are "printed publications" more than one year before that date (§102(b)); D3 published within the one-year grace window but is still prior art under §102(a), and its earlier-published US 2005/0275394 A1 (2005-12-15) is §102(e)/(a) art as well.

D1 — US 5,982,226 A

Full citation: Rinćon-Mora, G. A. & Allen, P. E., "Optimized frequency shaping circuit topologies for LDOs," U.S. Patent 5,982,226, issued Nov. 9, 1999; assignee Texas Instruments Incorporated; priority to provisional 60/042,751 (Apr. 7, 1997). https://patents.google.com/patent/US5982226

Description: An LDO regulator in which the error amplifier is given an added pole/zero pair to boost DC open-loop gain without sacrificing unity-gain bandwidth. FIG. 4a shows the disclosure's core: two amplifiers connected in parallel (a high-gain, narrow-band amplifier 18 and a lower-gain, wider-band amplifier 20) whose outputs are tied together at node A, which drives the gate of PMOS pass element 22. A resistor divider 24/26 senses Vout and returns a feedback node B to the non-inverting inputs of both amplifiers; both inverting inputs receive Vref. The lower-gain parallel amplifier 20 "feed-forwards" the AC signal through a bypass path to generate the zero Zx that shapes the response. Alternate embodiments use a feed-forward capacitor in a folded topology (FIG. 6a) or a frequency-shaping amplifier (FIGS. 8–9). (Derived from the patent's own abstract/summary and the Espacenet description text.)

§102 analysis: D1 discloses several environment elements of claim 1 — an error amplifier (18), a pass element (22) with a control terminal at the error-amplifier output and a current path between Vin and Vout, and a resistive divider feedback circuit (24, 26) returning a feedback voltage to a second amplifier input. That maps to claim 1 elements (a)–(c). It does not disclose claim 1 element (d) or (e) as claimed: the auxiliary amplifier's output in '515 is coupled to the error-amplifier output with its first input tied to a second reference voltage (ground), and the second feedback circuit takes the auxiliary amplifier's output as its input and returns a second feedback voltage to the auxiliary amplifier's second input. In D1's parallel-amplifier topology the two amplifiers share the same two inputs (Vref and divider node B); there is no feedback path from amplifier 20's own output back to a second input of amplifier 20. Consequently D1 does not anticipate claim 1, 16, or 20, and it cannot anticipate any dependent claim (each depends from an independent claim whose (d)/(e) limitations are unmet).

Value: It is, however, the most pertinent §103 reference — the "parallel/auxiliary amplifier that shapes the loop" concept is the closest prior art to the claimed auxiliary loop, and its sharing of Vref/feedback inputs vs. '515's separate second-loop inputs is precisely the point of novelty the '515 examiner appears to have relied on for allowance.

D2 — US 6,861,827 B1

Full citation: "Low drop-out voltage regulator and an adaptive frequency compensation," U.S. Patent 6,861,827 B1, issued Mar. 1, 2005; assignee System General Corp.; priority 2003-09-17. https://patents.google.com/patent/US6861827 (also uspto.report/patent/grant/6861827)

Description: An LDO that generates its own ESR instead of relying on the output capacitor's ESR. The feedback-control circuit splits feedback into a DC feedback terminal V_FBDC (via resistor 44 from Vout to the error amplifier) and an AC feedback terminal V_FBAC. The AC path is taken from the source of a transistor 45 whose gate is driven by the gate-signal terminal V_GATE, and is AC-coupled into the error amplifier's positive input through a capacitor 43. A current-controlled resistor 100 (an N-channel/MOS resistor responsive to output current) is inserted between Vout and V_FBAC, generating a controllable zero whose frequency follows the output pole as load current varies. This yields stability with a low-ESR (ceramic) output capacitor and improves light-load transient response.

§102 analysis: D2 is highly analogous to the '515 FIG. 1B prior-art topology (transistor 14 driven by V_g, AC-coupled by C_f through conductor 6A to the error-amplifier inverting input) and to the current-adaptive resistor 18 taught in the '515 specification. It therefore discloses: an error amplifier, an NMOS-type pass device with divider feedback (claim 1 (a)–(c)), a second, AC feedback path derived from a gate-driven transistor that tracks the load pole (overlapping claim 3 and claim 14 in substance), and an adaptive resistor set by load current (overlapping claims 10–11 and claim 19). What it lacks is the auxiliary amplifier: D2's AC path is fed back to the error amplifier's own input, there is no separate auxiliary amplifier whose output is tied to the error-amplifier output, and hence no second feedback voltage returned to a second input of an auxiliary amplifier. Claim 1 element (d) and the recursive "auxiliary output → second feedback circuit → auxiliary second input" structure of element (e) are absent, so D2 does not anticipate claim 1, 16, or 20. Its disclosure is squarely §103 material against the second-feedback-circuit / adaptive-resistor dependent claims (3, 9–11, 14, 19) and against the FIG. 1B starting point the '515 specification itself disparages.

D3 — US 7,015,680 B2

Full citation: "Current-limiting circuitry," U.S. Patent 7,015,680 B2, issued Mar. 21, 2006; assignee Micrel, Incorporated; inventors Moraveji & Mohtashemi; priority 2004-06-10; also published as US 2005/0275394 A1 (2005-12-15). https://patents.google.com/patent/US7015680

Description: A FET driver circuit for an LDO (NMOS power transistor Q282) with overcurrent protection. It includes an error amplifier 110 driving the FET, a bandgap-derived reference (through a buffer) to the error amplifier, a feedback loop from the FET output to the error-amplifier input, a sense resistor RS in the FET current path, and a current-limiting amplifier 120 that compares the sense-resistor drop against a reference drop. On overcurrent, the current-limiting amplifier pulls down the error amplifier's output node (via control transistor Q102) and simultaneously reduces the reference fed to the error amplifier, "coordinated" to prevent the error amplifier and current-limiting amplifier from fighting each other and causing output oscillation.

§102 analysis: D3 is the least relevant of the three to the '515 claims. It discloses only the generic LDO environment of claim 1: an error amplifier (110) with a pass device (Q282) and an output-sensing feedback loop. The second amplifier it contains (120) is a current-limit comparator, not a frequency-compensation auxiliary amplifier: its first input is not tied to a second reference voltage in the sense claimed, its output does not drive the pass-transistor gate node as the claimed auxiliary amplifier does, and there is no second feedback circuit returning a feedback voltage to a second input of that amplifier. It therefore does not anticipate claim 1, 16, or 20, nor any dependent claim. It is at most background §103 art — and only marginally so, because its concern (current limit / loop contention during overcurrent) is orthogonal to the load-pole compensation problem '515 addresses. It likely entered the file as a §102(a)-dated, same-field LDO reference.

Bottom line

No cited reference anticipates any claim of US 7,446,515 under §102. For every independent claim (1, 16, 20) at least one limitation is missing from each reference:

• Claim 1 (d)/(e): an auxiliary amplifier with a first input at a second reference voltage whose output is coupled to the error-amplifier output, plus a second feedback circuit feeding a second feedback voltage back to the auxiliary amplifier's second input.
  • D1 — amplifiers share both inputs; no second feedback loop → missing (d)/(e).
  • D2 — AC path returns to the error amplifier input; no auxiliary amplifier → missing (d)/(e).
  • D3 — its second amplifier is a current-limit comparator, not a compensation auxiliary amplifier → missing (d)/(e).
• Claim 16 and claim 20 inherit the same missing structure (method steps (c)–(e); the means-plus-function "auxiliary amplifier / second feedback voltage" elements).

Accordingly, the references are §103 obviousness art, ranked by pertinence: D1 (parallel/auxiliary amplifier frequency-shaping) > D2 (adaptive AC feedback path and load-tracking resistor) > D3 (LDO error-amplifier/current-limit environment only). D2 independently maps onto the specification's own FIG. 1B/adaptive-resistor admissions, so it is the strongest reference against the dependent claims (3, 9–11, 14, 19), while D1 is the strongest against the core independent-claim concept of an auxiliary gain loop.

Caveats and points I will not silently resolve

• I report the citation set exactly as printed: only D1–D3 appear under "Patent Citations (3)." If the file history contains non-patent literature (e.g., the Rinćon-Mora & Allen IEEE TCAS-II paper that underlies D1) or §102(e) art not surfaced by Google Patents, my list is incomplete; PACER/PatentCenter would be needed to confirm the full examiner citation record.
• I could not independently confirm the D1/D2/D3 final §102 rejections actually entered during prosecution from the sources retrieved; my §102 conclusions above are element-by-element comparisons against the claims as issued, not a report of the examiner's rejections.
• The two anomalies flagged in the prior summary remain: the "+" vs "−" discrepancy between claim 15 / the Summary and Equation (8), and the "output Vout coupled to the gate" typo in the FIG. 2 narrative. Neither affects this §102 analysis.

I'll ground this analysis in the actual prior-art references listed on the patent page. Let me pull details on each of the three examiner-cited references.

Obviousness Analysis — US 7,446,515 B2 ("Compensating NMOS LDO Regulator Using Auxiliary Amplifier")

Legal framework applied: This patent has a filing date of 2007‑01‑17 and priority to provisional 60/824,208 (2006‑08‑31), so it is governed by pre‑AIA 35 U.S.C. § 103(a). The analysis below applies the Graham v. John Deere, 383 U.S. 1 (1966) factors as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), and MPEP §§ 2141–2143.

Prior-art universe used: Per instruction, I rely on the "Patent Citations (3)" section of the patent page — the three examiner-cited references — plus the admitted prior art in the specification (FIGS. 1A and 1B).

Threshold caution on the "Cited By" list. The page's "Cited By" and "Families Citing this family" entries (e.g., US 9,686,325; US 10,175,706; CN 114,610,107) are not § 103 prior art — they post‑date the 2006 priority date. They are useful only to show the field's evolution, not for a validity attack. Likewise, REFERENCE C (Micrel) is directed to overcurrent protection and adds little to the compensation question; it is best characterized as a background reference for the NMOS/LDO environment, not as part of the core prima facie case. I flag this because one of the three examiner citations is essentially non-substantive on the point at issue.

1. The references

Reference A — US 5,982,226 (Rincón-Mora / Allen, TI)

This is the most on-point reference, and it is a TI-internal family member of the same technical lineage as the patent.

• It addresses the identical problem: an LDO whose pole/zero locations "are functions of the output capacitance, the electronic series resistance (ESR) of the output capacitor, and the load current," making "proper compensation a laborious endeavor."
• Its express solution is to add a pole/zero pair to the error-amplifier response by connecting two amplifiers in parallel: "Amplifiers 18 and 20 are connected in parallel with inverting inputs coupled to Vref and outputs coupled to node A," where node A is the gate-drive node of the pass device (PMOS 22). (Google Patents US5982226)
• It expressly attributes different functions to the two parallel amplifiers: "Amplifier 18 has high gain and its bandwidth determines the location of Px[,] while amplifier 20 has lower gain (whose magnitude determines the location of Zx) and higher bandwidth."
• Crucially for motivation, it states: "The amplifier thus serves to shape the frequency behavior of the system as well as provide gain," and "[t]he regulator 16 operates by feed-forwarding the ac signal through a bypass path constituted by the amplifier 20."

Why this matters: Reference A discloses, in substance, elements (a)–(d) of claim 1 — a pass transistor, a main error amplifier driving its gate, a resistor-divider first feedback circuit, and a second, lower-gain, higher-bandwidth amplifier whose output is coupled to the same node as the error amplifier's output. It also supplies the claimed transconductance hierarchy of claims 7–8 (one amp "high gain," the other "lower gain") and the functional concept of a second path "taking over" at high frequency (its low-gain/high-bandwidth bypass path introduces Zx near the unity-gain frequency).

Reference B — US 6,861,827 B1 (System General / Fairchild Taiwan)

• It teaches a generally conventional LDO (pass transistor 10, error amplifier 40, divider 31/32 for DC feedback) — i.e., AP‑1.
• It then adds a parallel AC feedback path: "A source of a transistor 45 is connected to the unregulated DC input port V_IN. A gate of the transistor 45 is connected to the gate signal terminal V_GATE. A drain of the transistor 45 is connected to the AC feedback terminal V_FBAC. The AC feedback terminal V_FBAC is connected to a positive input of the error amplifier 40 via a capacitor 43." (uspto.report/patent/grant/6861827)
• It then adds a current-controlled resistor 100 between V_OUT and V_FBAC, and expressly explains the adaptive‑zero advantage: "the resistance of the current-controlled resistor can be varied in response to the output current, so that the frequency of the zero will follow the frequency of the output pole," and "it is no longer necessary to depend on the parasitic ESR 22 for the stability."

Why this matters: Reference B discloses (i) the feedback transistor + high-pass capacitor AC path (gate driven by the gate‑drive node V_GATE, one electrode at V_IN) = claim 3; and (ii) the load‑current‑controlled variable resistor that makes the compensating zero track the output pole = claims 10–11 and the adaptive‑R_f feature. Reference B is essentially a patent‑of‑record embodiment of the specification's own admitted FIG. 1B, with the added adaptive zero.

Reference C — US 7,015,680 B2 (Micrel)

Discloses an NMOS‑pass LDO (Q282) with an error amplifier, a resistive feedback loop, and a current‑limiting amplifier that interacts with the error‑amplifier output node. It is useful only to confirm that an NMOS pass device, an error amplifier, a feedback loop, and a second amplifier whose output is coupled to the error amplifier's output node were all well‑known in LDO design at the relevant time. (Google Patents US7015680)

Admitted prior art in the '515 specification

The specification itself concedes the key pieces:

• FIG. 1A = conventional NMOS LDO = claim 1 elements (a)–(c).
• FIG. 1B = an NMOS LDO with "the signal V_g … AC‑coupled by feedback capacitor C_f and conductor 6A to the (−) input of the error amplifier 2," where "[t]ransistor 14 provides another feedback path in which the signal is not affected by the load capacitance C_L," and the specification concludes: "the idea of a parallel AC‑coupled feedback path is very valuable for LDO loop compensation design" (emphasis added).

This sentence is a self-supplied motivation statement that operates heavily against the patent under § 103. An applicant's admission that a disclosed architecture is "very valuable" is strong evidence that a POSITA would have been motivated to build on it.

2. Level of ordinary skill

A POSITA here would hold a B.S. in electrical engineering plus roughly 3–5 years of analog/IC design experience (or an M.S. with ~2 years), with working knowledge of: LDO loop analysis, Bode/phase-margin analysis, pole‑zero compensation, Miller effects, differential pairs and folded‑cascode stages, and MOS resistor design. This is the level at which References A and B were written and would have been read.

3. Claim 1 — element mapping and the obviousness case

Claim 1 requires, in substance: (a) pass transistor; (b) error amp (Vref input, output to the control electrode); (c) first feedback circuit (divider) to the error amp's second input; (d) auxiliary amplifier with a first input at a second reference and an output coupled to the error amp output; and (e) a second feedback circuit whose input is the auxiliary amp's output and whose output is a second feedback voltage returned to the auxiliary amp's second input, "for taking over control of the feedback … at high frequencies."

Primary combination: Reference A in view of Reference B.

The only structural gap is that in A the parallel amplifier's inputs come from the reference node/divider (a feed‑forward parallel amplifier), and in B/AP‑2 the AC feedback signal returns to the main error amplifier's input. Neither reference, taken alone, places the AC high‑pass feedback network around a dedicated auxiliary amplifier whose output is summed at the error‑amp output node.

Motivation to close that gap (why the combination is proper):

1. Same field, same problem, same solution category. All three references and the admitted art address frequency compensation of linear/LDO regulators across varying load and output‑capacitance/ESR conditions. KSR holds that the field of endeavor itself and the known problem supply a reason to combine. Here the "known problem" — restoring phase margin when the load pole (g_mo/C_L) slides with load current and the low‑ESR output cap cannot supply a compensating zero — is expressly recited as the problem in both Reference A and the '515 specification.

2. Reference A expressly directs the auxiliary amplifier to carry the high‑frequency compensation. A POSITA reading "amplifier 20 has lower gain … and higher bandwidth" and "the magnitude [of amp 20] determines the location of Zx" is being taught that the second, parallel amplifier is the vehicle for introducing the zero. Placing the AC feedback path on that amplifier rather than on the main amplifier is therefore the natural, disclosed use of the auxiliary amplifier — a predictable rearrangement, not a new principle.

3. Reference B supplies the return‑path hardware and the express design goal. B's transistor 45 (gate at the gate‑drive node), capacitor 43, and current‑controlled resistor 100 are exactly the "second feedback circuit" hardware, and B explains that the purpose is to make the zero "follow the frequency of the output pole."

4. The admitted FIG. 1B shortcoming supplies a specific reason to add gain in the AC path. The '515 specification states the FIG. 1B architecture "was found to be impractical because C_f and R_f need to be large and therefore require too much die area," and that "R_f can not be too large because that would result in too much noise." Inserting an amplifier into the AC feedback path is the classic, well‑known remedy: amplifier gain multiplies the effective input impedance (Miller/charge‑amplifier effect), so a smaller C_f and R_f achieve the same high‑pass corner and same feedback voltage. A POSITA seeking to preserve the "very valuable … parallel AC‑coupled feedback path" while curing its admitted C‑area/noise drawback would be motivated to do precisely this, with a reasonable expectation of success.

5. Predictable result. The claimed benefit (a zero that tracks the load pole, and a bounded worst‑case phase margin, expressly 35° at g_mi/g_ma = 10 per the '515 FIG. 4) is exactly the predicted consequence of a low‑gain/high‑bandwidth parallel path (Reference A) plus a load‑tracking zero (Reference B). Nothing about the combination yields an unexpected or synergistic new property beyond the arithmetic of the two known compensations.

Conclusion on claim 1: A prima facie case of obviousness exists over US 5,982,226 in view of US 6,861,827, further supported by the applicant's own admission regarding FIG. 1B. Claim 1 is the broadest claim (it does not require NMOS, the folded‑cascode sharing, the g_mi/g_ma hierarchy, the adaptive resistor, or the specific high‑pass filter), and is therefore the most vulnerable.

4. Dependent and independent claims

5. Alternative and secondary combinations

• B as primary + A as secondary. B discloses the environment (LDO, error amp, divider) plus the feedback transistor/high‑pass‑capacitor AC path and the adaptive resistor. The only missing piece is the auxiliary amplifier at the summing node, which A supplies ("dual amplifiers connected in parallel … outputs coupled to node A," low‑gain/high‑bandwidth amp 20 introducing Zx). A POSITA would consult A because B's stated goal ("a faster transient response under light‑load conditions," adaptive zero) and A's stated goal (avoid restricting the ESR range; extend stability to low‑ESR caps) are the same goal. This combination is arguably as strong as the primary one.
• Either of the above + C. C adds nothing material except corroboration that an NMOS pass device, an error amplifier, a feedback loop, and a second amplifier tied to the error‑amp output node were routine. It is best used for the "general knowledge / predictable variation" prong of KSR, not as an essential reference.
• A + admitted FIG. 1B alone. Because FIG. 1B is admitted prior art and the specification labels its concept "very valuable for LDO loop compensation design," A (parallel auxiliary amplifier providing a zero at the gate node) in view of the admitted FIG. 1B AC path is itself a viable two‑reference‑equivalent combination. The applicant's own admission supplies the motivation.

6. Anticipated counter‑arguments and my assessment

1. "No single reference discloses routing the AC feedback into a local loop around a dedicated auxiliary amplifier." — Correct, and this is the applicant's strongest point. The gap is real: A uses a feed‑forward parallel amplifier (inputs shared with the main amp); B/AP‑2 returns the AC signal to the main amp. The § 103 case therefore stands or falls on the motivation to reroute, which rests on (i) A's express assignment of high‑frequency/zero‑forming duty to the low‑gain/high‑bandwidth amplifier, (ii) B's express goal of tracking the load pole, and (iii) the admitted FIG. 1B C‑area/noise drawback. I assess this motivation as strong but not airtight; a well‑argued rebuttal could survive at the margin, particularly on claim 6.

2. "Reference A teaches away because it warns the second amplifier's bandwidth is a parasitic pole." — Weak. A identifies it as a design consideration, not a discouragement, and still implements the parallel amplifier.

3. "The specification explains a counter‑intuitive trade‑off (equal gains would slow transient response, so the auxiliary gain must be kept low)." — Partially persuasive for claims 7–14 as to the magnitude of g_ma, but claim 7 only requires "substantially greater" and claim 8's 10× is a result‑effective optimization. And Reference A already discloses the "high gain / lower gain" pair, which is the same teaching.

4. Secondary considerations. No evidence of unexpected results, commercial success with nexus, long‑felt need, or failure of others appears in the record. The specification itself notes the FIG. 1B topology here "was not implemented in … the TPS731 product," which undercuts any commercial‑success/nexus argument for the commercial embodiment. Absent objective evidence, the Graham factor 4 is neutral-to-unfavorable.

7. Bottom line

• Claim 1 is the most likely to be held obvious: US 5,982,226 in view of US 6,861,827 (with the applicant's FIG. 1B admission supplying express motivation, and US 7,015,680 for the NMOS‑LDO environment). Confidence: moderate‑to‑high.
• Claims 3–4, 7, 9–11, 12–13 are squarely met by References A and B and would likely fall with claim 1. Confidence: high.
• Claims 5, 8, 14–15 are likely obvious as known elements/optimizations/mathematical results. Confidence: moderate‑high, with claim 8 the most debatable.
• Claim 2 is obvious over AP‑1/A. Confidence: high.
• Claim 6 (shared folded‑cascode summing of the two differential input stages) is the weakest link in the invalidity case and the best candidate for a non‑obviousness argument, though I would still expect an examiner or litigator to press it as a routine implementation choice.
• Claims 16–19 (method) and 20 (means‑plus‑function) rise and fall with the apparatus claims; the method steps introduce no independent inventive concept.

Caveats I am not silently resolving:

• I did not verify the references' internal figure/label numbers beyond what the retrieved text states; the mappings above should be re‑confirmed against the full reference PDFs before being relied upon in a filing.
• The "+" vs. "−" discrepancy in the claim‑15 phase‑margin expression (as flagged in the earlier summary) remains unresolved and is carried forward here; it does not change the § 103 outcome because the claim's patentability rides on the underlying circuit, not on the arithmetic.
• The earlier summary's note that no litigation involving this exact patent was found still stands; nothing in these prior‑art searches changes that, and no court/PTAB holding on obviousness is asserted here.
• Reference C (Micrel) is, in my view, substantively peripheral to the compensation issue; treating it as a core part of a § 103 combination would be an overstatement of its teaching.