US 7155716

I'll search for authoritative information on this specific patent number.

Let me search more specifically for any litigation or PTAB proceedings and verify the USPTO record.

Let me run a few more targeted searches to confirm the litigation/PTAB/CAFC record and the current status.

US Patent 7,155,716 B2 — Analyst Summary

Sourcing note: The authoritative full text of this patent was supplied in the prompt (fetched from Google Patents, US7155716B2, on 2026‑10‑01). My live searches for this specific number returned the patent record and third‑party mirrors, but no CAFC 2026 docket, PTAB/IPR proceeding, or district‑court case naming 7,155,716. Searches for "7155716" litigation predictably surfaced other numbers (e.g., 7,155,241; 7,119,716; 5,615,716; 12,337,716) — those are different patents and I have not conflated them.

Bibliographic Data

Uncertainty flag on status: The Google Patents page shows both a "2024‑01‑30 Adjusted expiration" entry and legal events recording a lapse for failure to pay maintenance fees (FEPP reminder 2018‑08‑06; LAPS 2019‑01‑28; FP 2019‑02‑19, effective 2018‑12‑26). These entries are internally inconsistent, and I could not resolve them from the record available. Treat the exact expiration date as uncertain; the record does clearly show a lapse for non‑payment of the (12‑year) maintenance fee, with only the 4‑year (2010‑06‑28) and 8‑year (2014‑05‑28) fees shown as paid.

Abstract (verbatim)

"In one embodiment, a method, system, and apparatus provide prioritized, fair, and weighted task scheduling for a shared execution queue. New tasks are prioritized according to their processing requirements and held in one or more queues according to their priority levels. Tasks are retrieved from each queue in a fair and weighted manner according to the priority level of each queue. In one embodiment, tasks of approximately equal total processing requirements/time are retrieved from each storage queue in a given task retrieval cycle."

Plain‑Language Overview of the Independent Claims

Claim 1 — Device (apparatus)

A device that receives data streams made of data frames. A task scheduler creates a task identifier for every frame. There are at least two priority queues (first priority type, second priority type). A switch pulls task identifiers out of both queues "in a fair manner" and loads them into a third queue (a shared execution queue) that feeds a processing unit in the order the switch placed them. A classifier assigns/assigns-and-reassigns priorities and, critically, monitors the first queue for an overflow condition; if overflow is detected, it reassigns frames from the first priority type to the second to prevent the first queue from overflowing. A task router receives the identifier from the task scheduler and the priority from the classifier and routes the identifier to the correct queue.

Key limitation to note: the classifier's overflow-monitoring + priority-reassignment function is affirmatively recited in claim 1 — it is not merely a disclosed embodiment.

Claim 8 — Method

A method that: (1) receives data streams of frames, each frame type having a processing‑time requirement; (2) determines a task priority level per frame; (3) routes each frame to a storage queue based on priority; (4) retrieves frames during a task retrieval cycle under a fair and weighted scheme in which frames of approximately equal total processing‑time restrictions are taken from each storage queue per cycle; (5) reassigns the priority level before routing if an overflow condition is detected in a first storage queue and the original priority would have landed the frame there (reassign to a level that routes it elsewhere); and (6) places retrieved frames into an execution queue for a processing unit.

Claim 12 — Method (task‑identifier variant)

Substantively the same pipeline as claim 8, but explicitly adds assigning a unique task identifier to each received frame and storing/retrieving task identifiers rather than frames themselves; it also omits claim 8's "fair and" qualifier, reciting a weighted processing scheme. Same overflow‑reassignment limitation.

Claim 14 — Machine‑readable medium (independent)

Instructions that, when executed, cause a processor to perform the claim‑8‑type operations (fair and weighted retrieval, approximately equal total processing time per queue per retrieval cycle, overflow‑based priority reassignment before routing, and placement into an execution queue).

Dependent claims (2–7, 9–11, 13, 15–16) add: a look‑up table mapping data streams to priority types (2); pre‑assigned priority (3); dynamic configuration of priority conversions based on queue usage (4); a task retrieval cycle retrieving at least one identifier from each of the first and second queues so that third‑queue space is allotted equally per processing‑time restrictions (5); retrieving first‑type identifiers until their cumulative processing time is substantially equal to the second type's processing time, then retrieving a second‑type identifier (6); the third queue as a shared execution queue serviced by one or more processing units (7); priority determined from frame size, echo‑canceller tail length, codec type, or frame processing requirements (9, 13, 15); pre‑configured priority per frame type (10); each queue holding a distinct priority level (11, 16).

Supporting Disclosure Highlights

• Motivating problem: shared FIFO execution queues servicing mixed frame rates (5 ms vs. 30 ms) cause bottlenecks (Figs. 1–2).
• Architecture: demultiplexer/task router (304) → High/Medium/Low priority queues (306/308/310) → switch (316) → shared execution queue (318); classifier (314) provides dynamic reassignment and load balancing; lookup table (312) provides default mapping (Fig. 3).
• Scheduling granularity: a "task retrieval cycle" is the period in which at least one task is retrieved from every priority queue, assuming availability. The 5 ms / 10 ms / 30 ms example yields a 6:3:1 weighting (H1–H6, M1–M3, L1) so each queue contributes ~30 ms of processing per cycle (Fig. 5).
• Ordering flexibility: tasks may be grouped, evenly interleaved, reverse‑priority, chunked, or randomized within a cycle so long as the weighted ratio is preserved (Fig. 6).
• Under‑supply handling: fill from the next lower‑priority queue (Fig. 7), next higher‑priority queue (Fig. 8), or simply skip the empty queue (Fig. 9).
• Priority bases: frame size, echo canceller tail length, codec type, frame processing requirements; pre‑assigned and/or dynamically reassigned.

Litigation / Post‑Grant Activity

• CAFC 2026 dockets: No record found tying 7,155,716 to any Federal Circuit appeal in 2026 (or any year) in the sources searched. The 2026 CAFC materials returned by search involved unrelated patents (e.g., 10,894,503; 12,337,715/716) and cases.
• PTAB: No IPR/PGR identified for 7,155,716.
• District court: No infringement action identified. The closest "7155716" hits were for different patents and are expressly excluded here.
• Prosecution/ownership: Two assignment recordations to Intel Corporation (application stage). Maintenance fees shown paid at years 4 and 8, with a lapse recorded in 2019.

Confidence: Bibliographic data, abstract, and claim substance are high‑confidence (grounded in the authoritative full text). The "no litigation" finding is a negative search result from limited tooling — it should be treated as "none found," not as proof of none existing. Status dates are recorded as listed but internally inconsistent and unresolved.

I'll search for litigation involving US patent 7155716.

Let me search more specific litigation databases.

Let me try a few more targeted searches.

Litigation Search Report — U.S. Patent No. 7,155,716

Conclusion: No litigation found

Based on my searches of litigation-oriented sources (Google Patents' litigation/citation data for the patent, Unified Patents portal references, PTAB/PTActs documents, CAFC opinions, Justia, CourtListener, and general web search), I found no known litigation involving U.S. Patent No. 7,155,716. I found no district court complaint, no PTAB proceeding (IPR/PGR/CBM), and no CAFC appeal in which this patent is the asserted or challenged patent.

What the sources affirmatively show

1. Google Patents record for US7155716B2 (https://patents.google.com/patent/[US7155716](/patent/US7155716)/en) contains no litigation section at all. The only "related case"-type data on that page are:

• Cited By and Families Citing entries — these are citation records, not litigation (they are other patents that cite or are related by family, e.g., US7178146 "Pizza Scheduler," US8797329, etc.).
• Patent Citations (8) — prior art cited by the examiner, not lawsuits.
• Legal Events — only prosecution/assignment/maintenance-fee events.

No "Litigation" or "PTAB" tab content is present for this patent.

2. Legal status / maintenance: The patent lapsed. Per the Google Patents legal events, the owner (Intel Corporation) failed to pay the maintenance fee; the entry "LAPS – Lapse for failure to pay maintenance fees," effective 2018-12-26 (docketed 2019-01-28), and the patent is listed as "Expired – Fee Related, expires 2024-01-30." An expired, lapsed patent is unlikely to have been recently asserted.

3. False positives I ruled out (per the strict identifier rule, these are different patents, not this one):

• U.S. Patent No. 5,615,716 — asserted in Akira Akazawa v. Link New Tech Int'l (C.D. Cal.), about cooling-system technology. Different patent.
• U.S. Patent No. 7,426,715 — asserted in multiple Sound View Innovations, LLC v. Walmart/Delta/Cigna/Vudu cases (D. Del.). Different patent.
• U.S. Patent No. 7,454,002, 9,069,648, etc. — unrelated Unified Patents matters.
• Various Brazilian corporate registration numbers ("7155716") in JUCE Ceará/JUCIS RS filings — not patents at all.

Important caveats

• No litigation "known" ≠ no litigation ever existed. My search is limited to publicly indexed web sources. A short-lived or sealed suit, or one not captured by the indexed databases I could reach, would not appear.
• I was unable to directly query PACER (paywalled) or the Unified Patents Litigation caselist for a per-patent "casedump" of this specific number, so my negative finding rests on secondary aggregators (Google Patents, Justia, CourtListener, Docket Alarm/PTActs excerpts) plus targeted keyword searches.
• To confirm with higher confidence, the definitive check would be a PACER "Patent Litigation Docket Report" by patent number and a PTAB caselist / Docket Alarm query on 7,155,716 directly.

Summary table

Bottom line: No litigation involving U.S. Patent 7,155,716 was identified. The patent appears to have been a non-asserted Intel portfolio patent that expired for non-payment of maintenance fees in December 2018.

If you can provide PACER access or a Docket Alarm/litigation-database export, I can run a definitive per-patent docket check to corroborate this negative result.

I'll start by checking the structured PTAB data against live sources.

Let me run a few more targeted checks before concluding.

Proceedings overview

Total AIA trial proceedings on US 7,155,716: 0 (0 active / 0 with claims invalidated / 0 with claims sustained / 0 settled / 0 institution denials) — the USPTO Open Data Portal returns no AIA trial proceedings for this patent, and targeted web searching (Google Patents, FreePatentsOnline, PTAB petition documents, and general IPR/CBM/PGR query strings) surfaced no IPR, PGR, or CBM number naming US 7,155,716. The bottom-line defensive posture is therefore not "the patent has survived two IPRs and is hardened" and not "claims 1–5 have been canceled." It is: the claims were never tested at the PTAB, and the patent is expired and unenforceable for failure to pay maintenance fees — which is a materially better defense than any IPR outcome, because there is no live patent to infringe going forward and no IPR estoppel was ever triggered.

Proceedings

No proceeding entries exist to report. Per the operating rules, I will not invent proceeding numbers. What follows is the evidence of absence plus the enforcement-relevant status of the patent.

No PTAB proceeding on file — US 7,155,716 B2

• Canonical source: the structured "PTAB proceedings on file" block states the ODP API returns no AIA trial proceedings for this patent as of the most recent ingest. I treat that as the controlling list.
• Independent verification (2026-10-01): web searches for US7155716 IPR, "IPR2013"/"IPR2014"/"IPR2015" "7155716", and petitioner-style queries ({Petitioner} v. Intel, "weighted and prioritized task scheduler" + IPR/CBM/PGR) returned no PTAB case number. The only "Cited By" / "Families Citing" hits on the Google Patents page are ordinary patent-to-patent citation relationships (e.g., JP5088145B2 citing the '716 patent, and the '716 patent's own citation of US4642756, US4942569, US5220653, US6058114, US6182120, US6341303, US6791990, US6816494) — those are prior-art citations, not AIA trials.
• Why the absence is plausible rather than a data gap: the patent is a 2002-filed, 2006-granted Intel Corporation patent covering DSP task-scheduling. It is a defensive industrial patent, not an NPE assertion vehicle. As of the latest legal-events data the current assignee is still Intel Corp (original assignee: Intel Corp); there is no recorded assignment to a monetization entity. Well-asserted troll patents attract IPRs; a dormant Intel scheduling patent does not.

Because there is no proceeding, the following fields are inapplicable and are not filled with speculation: Type, Judge panel, Petition grounds, Institution decision, Final Written Decision, Settlement / termination, Appeal.

Patent status that actually governs the defense (the part defendants care about)

Even with zero PTAB history, two recorded events dominate any analysis of this patent today. Both are drawn from the Google Patents legal-events table fetched 2026-10-01:

• Legal status as listed: Expired - Fee Related. Google Patents separately shows an "Adjusted expiration" of 2024-01-30, but that field is a terminal-date calculation, not an enforceability determination. The recorded lapse effective 2018-12-26 for nonpayment of the 12-year maintenance fee controls: the patent is not in force. Reviving it would require a USPTO petition to accept late payment (37 C.F.R. § 1.378) showing unintentional delay — and any such revival would implicate intervening-rights defenses under 35 U.S.C. § 252 for conduct during the lapse.
• Consequence for a defendant: no injunction is available for post-2018-12-26 conduct (there is nothing to enjoin — the patent term ended). Money exposure, if any, is past damages only, and 35 U.S.C. § 286 caps recovery at six years before suit, which for any 2026 filing would reach back only to 2020-10-01 — after the lapse date. In practice that means a demand letter citing claims 1–16 of this patent is asserting a patent on which damages may be entirely time-barred. Verify the exact lapse/revival status on USPTO Patent Center before relying on it in correspondence.

Strategic summary

Claim status: UNTESTED — but the patent is expired, which makes claim status largely academic. No claim of US 7,155,716 has been canceled, confirmed, or construed by the Board. The full set — independent claims 1, 8, and 12 and their dependents (2–7, 9–11, 13–16, 16 total) — is exactly as issued on 2006-12-26. There is no narrowing certificate, no certificate of correction on record in the fetched data, and no IPR-driven amendment (amendment isn't available in IPR anyway). The enforced scope is defined only by the issued claims and their prosecution history, which a defendant would litigate in district court or the ITC, not at the PTAB.

Estoppel landscape: clean. Because no IPR was instituted, 35 U.S.C. § 315(e)(2) estoppel never attached to any party. No petitioner, real party in interest, or privy is barred from raising any § 102/§ 103 ground in district court or a later IPR. Conversely, if a new petitioner files an IPR now, there is no prior-institution baggage, no Fintiv history, and no § 315(b) one-year bar unless the petitioner was itself served with a complaint more than a year ago. The full prior-art universe remains open — including the eight references already cited on the face of the patent (US4642756, US4942569, US5220653, US6058114, US6182120, US6341303, US6791990, US6816494) and the broader weighted-fair-queuing art that was already mature in 2002 (the Similar Documents list on the Google Patents page is dominated by fair/weighted queueing patents from the same era, e.g. US6687781 "Fair weighted queuing bandwidth allocation system for network switch port" and US6810426 "Methods and systems providing fair queuing and priority scheduling"). Claims 5 and 6 are the natural § 103 targets: they explicitly recite the "space in the third queue is allotted equally according to processing time restrictions" and "accumulated processing time equalization" limitations that read squarely on pre-2002 deficit-round-robin / weighted-fair-queuing literature.

Pattern signals: none. No serial petitioner behavior (there is no first petitioner). No patent-owner appeal activity (no FWD to appeal, so no Federal Circuit docket). No defensive aggregator — no Unified Patents, RPX, or other third-party challenger appears anywhere in the record. The only "challenger-adjacent" pattern is that Intel has been a frequent IPR petitioner and Fintiv litigant elsewhere (see the Intel v. VLSI § 315/§ 314(d) line of appeals described in Intel's 2021 cert petition, https://www.supremecourt.gov/DocketPDF/21/21-888/[204845](/patent/204845)/20211213134400635_21-xxxx%20-%20Intel%20Corp.%20v.%20VLSI%20Technology%20LLC%20-%20Petition%20for%20a%20Writ%20of%20Certiorari.pdf), but Intel is the owner here, not a challenger — that history is irrelevant to this patent except as background on how Intel litigates validity.

Recommended next steps

1. If you are a defendant and received a demand citing this patent, lead with expiration, not invalidity. Confirm the lapse and whether any § 1.378 revival petition was granted via USPTO Patent Center for application 09/683,993 and via the PTAB E2E / Patent Trial and Appeal Board portal for any AIA case tied to it. If the patent is confirmed lapsed, the demand is time-barred under § 286 for any suit filed in 2026 or later.
2. There is no FWD to quote and no claims-invalidated disposition to lean on. Do not draft a letter representing that any claim of the '716 patent has been canceled by the Board — no such decision exists. If the asserting party claims otherwise, demand the proceeding number; there is none.
3. If you nonetheless want an invalidity vehicle (e.g., to defeat a resurrected or revived patent, or a co-pending case on a related Intel family member), an IPR on claims 1–16 remains fully available — no § 315(e)(2) estoppel and no prosecution-driven disclaimer. Grounds would target the equalized-processing-time limitations of claims 5 and 6 against pre-2002 weighted-fair-queuing art, with § 112 support challenges limited to district court (IPR is § 102/§ 103 only). Because the patent is expired, IPR would be a past-damages defense play, and the Board will still institute against expired claims — but weigh that against the cost.
4. Trial-stage milestones: not applicable. No institution decision, oral hearing, or FWD deadline exists for this patent, so there is no statutory one-year clock running.
5. Caveat on the record I could not verify: I did not retrieve the certified prosecution history to confirm whether the granted claim 1 matched the as-published claim 1 in US2003/0172104 A1. The published application version of claim 1 (as reproduced on Justia, https://patents.justia.com/patent/20030172104) omits the classifier and task-router limitations that appear in granted claim 1 on Google Patents — that is typical of pre-grant amendment, but if claim scope matters to your dispute, pull the file wrapper rather than relying on either text source.

Links used: US 7,155,716 B2 on Google Patents · US 2003/0172104 A1 · FreePatentsOnline record · PTAB E2E portal · CourtListener (no Federal Circuit opinion naming this patent was found).

I'll verify the assignment record and look for correspondent-of-record details before writing the analysis.

Let me attempt to retrieve the recorded assignment cover-sheet details and corresponding attorney.

Assignment & Ownership Analysis — U.S. Patent No. 7,155,716

"Weighted and prioritized task scheduler" · App. 09/683,993 · filed 2002-03-08 · issued 2006-12-26 · Intel Corporation

Source note: The authoritative assignment data below comes from the Google Patents legal-events record for US7155716B2 (which mirrors the USPTO Assignment Center / EPAS reel-frame data), cross-checked against inventor and assignee profiles (Justia, PatentLeaderboard, patents-review, Radaris). The USPTO Assignment Center cover sheets were not directly retrievable with the tools available for this analysis (see the correspondent caveat under the timeline). No assignment is invented below; where a field is unknown it is marked as such.

Inventors

Employer determination. Both inventors list Orange County, California addresses. Inventor Honary's own professional biography states he was "one of the early engineers in the startup VxTel focused on developing a high-capacity VoIP chipset that was acquired by Intel in 2001." Steiger co-invented several other Intel voice-over-packet patents out of the same Irvine group (e.g., "System and method for controlling signal processing in a voice over packet (VoP) environment"). The application was filed in March 2002 — after the VxTel acquisition closed — and was assigned straight to Intel. The correct characterization is therefore that the inventors were Intel employees at filing, their work originating from the acquired VxTel business unit. Caveat: the employment relationship itself is not stated in the recorded assignment; it is inferred from the VxTel/Intel corporate history and the inventors' co-filed Intel portfolio.

Unusual patterns. None of the classic "inventors bolt within 12 months pre-fire-sale" pattern. This is the inverse: an acquisition-harvest — Intel absorbed VxTel (2001), the inventors' continuing work was filed and assigned to Intel (2002), and the same pair filed a companion Intel application, US 7,242,687 "Method and system for distribution of session scheduling," on 2002-05-24. Honary later moved on to Broadcom (11+ later patents) — a normal career move, not a distress signal. No inventor departure coincides with any transfer because no transfer ever occurred.

Original assignee

• Entity on the issued patent: Intel Corporation, Santa Clara, California (2200 Mission College Blvd., Santa Clara, CA 95054).
• Primary line of business: semiconductor design and manufacturing (microprocessors, chipsets, networking/communications silicon).
• Product embodying the claims: The specification is directed at a DSP task scheduler in a voice gateway handling concurrent five-, ten-, and thirty-millisecond frame streams. Intel was, through the VxTel acquisition, actively commercializing voice-over-packet / media-gateway silicon and reference platforms in this exact period, and this patent sits in that product line. I assess it as materially likely that Intel shipped voice-gateway/DSP products practicing the claims, but I did not locate a specific Intel datasheet or product manual tying a shipped SKU to these claims — so treat "shipped embodying product" as probable, not confirmed.
• Current status: Operating, publicly traded (NASDAQ: INTC). No bankruptcy, no dissolution, no acquisition. Intel remains the current assignee of record — there is no recorded post-issuance transfer away from Intel.

Assignment timeline

Two recorded assignments, both to Intel, both from the same two inventors. The second is a corrective re-recording of the first (it fixes the garbled assignor name "HOOMAN, HONARY" → "HONARY, HOOMAN"), not a change of ownership.

• 2002-03-05 (executed) / recorded 2002-03-08 — Reel 012461 / Frame 0904

  • Conveyance: Assignment ("Assignment of assignor's interest")
  • Assignor: Hooman Honary and Dianne L. Steiger (individuals)
  • Assignee: Intel Corporation (California)
  • Correspondent: Not surfaced in the accessible records (see caveat below). No recurrence can be established.
  • Context: Employee/inventor-to-employer assignment — initial recording of the inventors' rights to Intel for the application filed the same day.

• 2003-05-09 (executed) / recorded 2003-05-09 — Reel 013642 / Frame 0497

  • Conveyance: Assignment (same "Assignment of assignor's interest")
  • Assignor: Hooman Honary and Dianne L. Steiger
  • Assignee: Intel Corporation (California)
  • Correspondent: Not surfaced in the accessible records.
  • Context: Corrective re-recordation — same parties and same interest re-filed to correct the assignor's name/order in the earlier record. No new consideration, no new owner.

• No further records. There is no post-issuance assignment, security agreement, merger, change-of-name, license, or release recorded against this patent. The chain terminates at Intel.

Correspondent caveat (important). The most diagnostic field you asked for — the attorney/agent of record who filed each cover sheet — is not exposed in the Google Patents legal-event feed, and the USPTO Assignment Center cover sheets could not be pulled with the tools available here. I therefore cannot name the correspondent for either reel/frame, and I explicitly decline to infer one. This does not weaken the conclusion, because the chain has no NPE link whose correspondent would need to be matched — but if you have Assignment Center access, the definitive fields to pull are the correspondent name/firm on Reels 012461/0904 and 013642/0497.

Timeline diagram

timeline
    title Ownership of US 7155716
    2001 : Intel acquires VxTel
    2002 : Application filed 8 March
         : Inventors assign rights to Intel
         : Recorded reel 012461 frame 0904
    2003 : Corrective re-recording 013642 0497
    2006 : Patent issues to Intel
    2018 : Lapses for unpaid maintenance fees

NPE / troll-pattern signals

Verdict

Insufficient data (no records, or only the original assignment).

Justification. The only assignments on record are the original inventor-to-employer assignments to Intel Corporation, recorded at Reel 012461/Frame 0904 (2002-03-08) and its corrective re-recording at Reel 013642/Frame 0497 (2003-05-09); there is no post-issuance transfer, no NPE link, and no litigation. Substantively this is the cleanest possible anti-NPE fact pattern — a genuine operating-company employee invention (VxTel → Intel) that was never sold and never asserted, then allowed to lapse for unpaid maintenance fees (2018-12-26) — but because the file contains only the original assignments, it maps to the "Insufficient data / original assignment only" category rather than to an affirmative NPE or defensive-aggregator finding. The one field that could refine this — the correspondent of record — is not retrievable here and is flagged above.

Verify at:

• USPTO Assignment Center search — https://assignment.uspto.gov/patent/index.html (search property number 7,155,716 / app 09/683,993; the newer portal is https://assignmentcenter.uspto.gov/)
• Google Patents legal events — https://patents.google.com/patent/[US7155716](/patent/US7155716)/en
• USPTO Patent Center for the application — https://patentcenter.uspto.gov/

Contradiction check vs. prior sections. None material. The earlier litigation section correctly reported no litigation and an 2018 maintenance-fee lapse; that is fully consistent with the assignment record, which shows no transfers before or after issuance. Note only the cosmetic tension between Google Patents' header ("Expired – Fee Related, expires 2024-01-30" — the nominal/adjusted statutory term) and the actual 2018-12-26 lapse event; the lapse date, not the term-end date, governs ownership status.

I'll verify each of the eight examiner-cited references and assess their bearing on the claims. Let me search for authoritative records on each.

I have four references. Let me retrieve the remaining four.

Prior-Art Analysis — U.S. Patent No. 7,155,716 ("Weighted and prioritized task scheduler")

Scope note / sourcing. The task asked for "each patent citation for 7155716." The authoritative full text (Google Patents, US7155716B2, fetched 2026‑10‑01) lists eight references under "Patent Citations (8)" — i.e., the references the examiner actually cited against this application. Those eight are the subject of this report. The separate "Cited By / Families Citing" listings are later patents (they cite 7,155,716); they are not prior art to it and are excluded per the strict‑identifier and chronology rules. I verified five of the eight against primary/patent images and secondary records; I was unable to retrieve the full text of three (US 6,341,303; US 6,791,990; US 6,816,494) within the tool budget — for those I rely on the authoritative citation data in the patent text plus the titles, and I flag my confidence as lower.

Anticipation framework (pre‑AIA, since this is a March 2002 application). All eight predate the 2002‑03‑08 priority date and qualify as prior art — six under §102(b) (published/granted more than one year before filing) and the two 2004‑granted patents under §102(e) (U.S. patents granted on applications filed before 2002). For §102, a single reference must disclose every limitation of a claim; for §103, references may be combined. My bottom line, stated up front: none of the eight anticipates any independent claim (1, 8, 12, 14), which is consistent with the patent having issued with all 16 claims intact. Several are meaningful §103 references and several bear on specific dependent claims.

Summary table of the eight examiner citations

Date discrepancies flagged (record vs. front page):

• US 4,942,569 — the record lists priority 1988‑02‑29, but the patent front page shows Filed Feb. 24, 1989 (Appl. No. 314,865). The 1988 date is therefore the foreign (JP) priority, not the U.S. filing date. (Source: US4942569 PDF front page.)
• US 6,182,120 — the record lists priority 1997‑09‑30, but the front page shows Filed Sep. 11, 1998 (Appl. No. 09/152,144). The 1997 date is a foreign priority (inventors in Saint‑Jeannet, FR). (Source: US6182120 PDF front page.)

Neither discrepancy changes prior‑art status, but both matter if you are computing effective dates.

Reference-by-reference analysis

1. US 4,642,756 A — "Method and apparatus for scheduling the execution of multiple processing tasks in a computer system"

• Full citation: U.S. Patent 4,642,756, filed 1985‑03‑15, issued 1987‑02‑10, S & H Computer Systems, Inc. (https://patents.google.com/patent/US4642756).
• Description: A priority‑based task scheduler for a multitasking CPU. Each task carries two priority values — an internal priority derived from task state and an external priority set by the operator/task. Tasks are held in an ordered run list sorted by descending internal priority (ties broken by external priority/FIFO) and executed for fixed time quanta (QUAN0/QUAN3), with a round‑robin among equal‑priority tasks. Fixed‑high, fixed‑low, and interactive priority groups are defined.
• Potentially relevant claims (§102): Conceptually touches claim 1's "first/second priority type" queues and claim 3 ("priority type … pre‑assigned to the data stream" — the external priority here is pre‑assigned). It does not disclose a switch feeding a shared execution queue, a task‑identifier router, fair‑and‑weighted apportionment by processing‑time requirement, or any overflow‑based priority reassignment. Not anticipatory of any independent claim; at most a §103 reference on the "assign priorities to tasks" concept.

2. US 4,942,569 A — "Congestion control method for packet switching apparatus"

• Full citation: U.S. Patent 4,942,569, JP priority 1988‑02‑29, U.S. filed 1989‑02‑24, issued 1990‑07‑17, Kabushiki Kaisha Toshiba (inventor Junichi Maeno) (https://patents.google.com/patent/[US4942569A](/patent/US4942569A)/en).
• Description: Two priority fields per packet — a first "immediateness" priority and a second "necessity" priority. On queue congestion/overflow, the apparatus rearranges packets so high‑immediateness packets move to the front and discards high‑immediateness/low‑necessity packets (e.g., voice) before terminal data.
• Potentially relevant claims (§102): This is the reference most on‑point for the "monitor the first queue for an overflow condition" element of claim 1 and the overflow element of claims 8/12/14, and for the two‑priority concept. However, the claimed response to overflow is reassigning data‑frame priority types to route frames to a different queue; Toshiba instead discards or reorders within a queue. That is a material difference, so no independent claim is anticipated. Strong §103/§102‑comparison reference for the "priority + congestion" pairing.

3. US 5,220,653 A — "Scheduling input/output operations in multitasking systems"

• Full citation: U.S. Patent 5,220,653, filed 1990‑10‑26, issued 1993‑06‑15, International Business Machines Corp. (https://patents.google.com/patent/[US5220653A](/patent/US5220653A)).
• Description: Disk I/O requests are staged in multiple holding queues prioritized per task base priority, then transferred to a service queue serviced FIFO by the device driver. Notably, a "starvation advancement" process promotes the oldest enqueued requests to higher‑priority holding queues, and a per‑drive selection picks the next request by head proximity ("elevator" ordering).
• Potentially relevant claims (§102): Closest to claim 1's two‑tier architecture (priority queues → service queue) and, via starvation boosting, to the spirit of the classifier's reassignment to avoid an adverse condition; also arguably relevant to claim 7 (the service queue as the "shared execution queue"). But the service queue is served by a disk drive, not "processing units"; there is no task‑identifier generation from data frames, no fair‑and‑weighted equal‑processing‑time apportionment, and the boost is driven by starvation, not overflow. Not anticipatory; a credible §103 reference especially if combined with #5.

4. US 6,058,114 A — "Unified network cell scheduler and flow controller"

• Full citation: U.S. Patent 6,058,114, filed 1996‑05‑20, issued 2000‑05‑02, Cisco Systems, Inc. (https://patents.google.com/patent/US6058114).
• Description: An ATM cell scheduler for fixed‑length cells over multiple virtual channels. A rewritable store holds scheduled times and channel parameters (cell‑delay‑variation tolerance, allowed cell period); a sorter orders scheduled times and selects the highest‑priority cell; a microcontroller computes next scheduled times and adjusts rates. Priority can be pinned to an expiration time.
• Potentially relevant claims (§102): Bears on the general notion of fair/rate‑based, prioritized scheduling and priority ordering — useful for §103 arguments against the "fair" and "weighted" limitations of claims 1/5/8/12/14. It is a network‑cell scheduler, not a data‑frame task scheduler feeding DSP processing units, and it lacks the claimed task router, classifier overflow‑reassignment, and the equal‑processing‑time retrieval cycle. Not anticipatory.

5. US 6,182,120 B1 — "Method and system for scheduling queued messages based on queue delay and queue priority"

• Full citation: U.S. Patent 6,182,120 B1, priority 1997‑09‑30, U.S. filed 1998‑09‑11, issued 2001‑01‑30, IBM (inventors Beaulieu & Dispensa) (https://patents.google.com/patent/US6182120).
• Description: Up to 16 prioritized message queues ("MIQs"). A scheduler dequeues the highest‑priority non‑empty MIQ, serves it until a static weight (Stat.Ni) is reached, then moves to the next queue — defining a "scheduling cycle." A critical state is entered when a queue's dormant time exceeds its max delay (Delay.Maxi), at which point critical queues are served by critical weights, then the scheduler returns to the normal state.
• Potentially relevant claims (§102): This is the closest reference to the claimed scheduling mechanics. Its static‑weight, per‑queue, then‑advance "scheduling cycle" maps onto the patent's "task retrieval cycle" and onto claim 5 (retrieve from each queue per cycle) and is arguably near claim 6 (retrieve from one queue up to a threshold, then the next). Its "critical state" (delay‑triggered) is analogous to, but not the same as, the claimed overflow‑triggered priority reassignment — IBM adjusts service weights/state, it does not re‑route messages to a different priority queue. It also does not disclose data‑frame task identifiers, a switch placing identifiers into a shared execution queue in order, DSP processing units, or "approximately equal total processing time" apportionment. Not anticipatory of 1, 8, 12, or 14, but a serious §103 reference (particularly for dependent claims 5 and 6).

6. US 6,341,303 B1 — "System and method for scheduling a resource according to a preconfigured plan"

• Full citation: U.S. Patent 6,341,303 B1, priority 1998‑08‑28, issued 2002‑01‑22, Oracle Corp. (citation data from US7155716B2 "Patent Citations" table).
• Description (confidence: moderate — full text not retrieved): Per the title and Oracle's line of work at that period, this concerns scheduling/allocating a shared resource in accordance with a pre‑configured plan/schedule.
• Potentially relevant claims (§102): Its "pre‑configured plan" concept is on point for the pre‑assigned / pre‑configured priority limitations of claim 3 and claim 10, and loosely for the look‑up‑table feature of claim 2. It does not disclose the claimed multi‑queue + switch + shared‑execution‑queue + overflow‑reassignment pipeline. Not anticipatory. Flagged: I did not verify the disclosure beyond the citation record; treat as lower confidence.

7. US 6,791,990 B1 — "Priority selection means for data transmission apparatus"

• Full citation: U.S. Patent 6,791,990 B1, priority 1997‑09‑12, issued 2004‑09‑14, Xyratex Technology Ltd. (citation data from US7155716B2 "Patent Citations" table).
• Description (confidence: moderate — full text not retrieved): Concerns selecting among data units by priority in a data‑transmission apparatus.
• Potentially relevant claims (§102): General relevance to priority‑based selection/queuing (claim 1's priority queues; the "retrieve … in a fair manner" element as a §103 teaching). It is a §102(e) reference (application filed 1997, granted 2004). No disclosure of the claimed task‑identifier router, shared execution queue, or classifier overflow‑reassignment. Not anticipatory. Flagged: disclosure not verified beyond the citation record.

8. US 6,816,494 B1 — "Method and apparatus for distributed fairness algorithm for dynamic bandwidth allocation on a ring"

• Full citation: U.S. Patent 6,816,494 B1, filed 2000‑07‑20, issued 2004‑11‑09, Nortel Networks Ltd. (citation data from US7155716B2 "Patent Citations" table).
• Description (confidence: moderate — full text not retrieved): A distributed fairness algorithm for dynamic bandwidth allocation on a ring network.
• Potentially relevant claims (§102): Relevant only to the generic "fair" scheduling notion (claims 1, 8, 14 recite fairness). It is a network bandwidth‑allocation reference with no task/frame scheduler, no multi‑priority storage queues feeding a shared execution queue, and no overflow‑driven priority reassignment. Not anticipatory. Flagged: disclosure not verified beyond the citation record.

Synthesized §102 exposure by claim

Key gap common to all eight: none discloses the distinctive combination this patent claims — (a) task identifiers generated per data frame, (b) routed to multiple priority storage queues, (c) drained by a switch in a fair‑and‑weighted task retrieval cycle that equalizes ~total processing time per queue, (d) into a shared execution queue serviced by processing units, with (e) a classifier that reassigns a frame's priority type specifically upon detecting queue overflow. Element (e) — an explicit limitation of independent claims 1, 8, 12 and 14 — is where the art is thinnest: #2 discards, #3 boosts on starvation, #5 re‑weights on delay. That limitation is the strongest basis for the claims' validity over these citations.

Caveats

• Negative/limited results: Anticipation assessments above are based on the citation record plus verified full text for references 1–5. For references 6–8 I could not retrieve full disclosures within the tool budget; those three are assessed at moderate confidence from their titles and citation data and should be re‑checked against the actual specifications before being relied upon.
• Not re‑searched beyond the examiner set: The task specified "each patent citation for 7155716." Other prior art (e.g., non‑patent literature or references cited only in the 2003‑09‑11 pre‑grant publication US 2003/0172104 A1) is outside this report. If a broader §102/§103 landscape is wanted, the next step is the full "References Cited" list from the published application and the file wrapper (USPTO PatentCenter) for the examiner's actual rejection grounds.
• Status reminder (from prior section, unchanged): The patent is recorded as Expired – Fee Related with a maintenance‑fee lapse effective 2018‑12‑26; the "2024‑01‑30 adjusted expiration" entry remains inconsistent with the lapse events and is unresolved. This does not affect the prior‑art analysis but is relevant to any freedom‑to‑operate use of these references.

I'll ground my analysis by pulling the actual disclosures of the eight examiner-cited references (the "Prior Art" section of the page), since an element-by-element §103 analysis depends on what those references actually teach.

Obviousness Analysis — U.S. Patent No. 7,155,716 B2 (35 U.S.C. § 103)

Note on scope and sourcing. Per the task instruction I used the Prior Art section of the patent page — i.e., the eight examiner-cited references in the "Patent Citations (8)" table and the "Prior art keywords" field (task / queue / priority / data frame / data). I retrieved substantive disclosure text for five of the eight. For three (US 6,341,303; US 4,942,569; US 6,816,494) my searches were truncated by tool limits, so those are treated below on the basis of their titles/assignees only, and I flag that limitation explicitly rather than fabricating content. Nothing in this section repeats the bibliographic/claim-summary material already generated; it builds on it.

1. The §103 reference set and its critical dates

⚠️ Trap flagged. Two of these cite-table entries are listed by their U.S. grant dates, which post‑date the '716 filing date of 2002‑03‑08 — US 6,791,990 B1 (granted 2004‑09‑14) and US 6,816,494 B1 (granted 2004‑11‑09). Treated literally as printed, those grant dates would make them non-prior art. They remain available only through their pre‑2002 priority/filing/publication events (for the Xyratex reference, the GB priority of 1997‑09‑12 and the WO 1999/014916 publication of 1999‑03‑25). Any §103 theory built on US 6,791,990 B1 must be anchored to those earlier dates, not the U.S. grant date. This is a genuine analytical hazard, not a formality.

All eight references otherwise pre‑date the 2002‑03‑08 priority date and are therefore available as prior art.

Level of ordinary skill in the art (POSITA): a B.S. in electrical engineering or computer science (or equivalent) with ~2–3 years of experience in real-time embedded task scheduling and/or DSP/voice-gateway data-path software, familiar with priority/multi-level feedback queueing, weighted round-robin and fair queueing.

2. Claim 1 (device) — element mapping

Claim 1 assessment: obvious. Every element is disclosed, and the only element that is not disclosed in a single reference — overflow-triggered reassignment of priority type — is squarely taught by US 6,791,990's overflow-threshold override of the priority symbol, reinforced by US 6,182,120's critical-state priority change. See §4 for the one colorable counter-argument.

Claim 7 (third queue = shared execution queue serviced by one or more processing units) is met directly by US 5,220,653's shared service queue feeding the disk drive, and by US 6,182,120's dispatch of dequeued messages to processing tasks.

3. Claims 8, 12 and 14 — element mapping

Claims 8/12/14 assessment: obvious. The only feature requiring more than one reference is the quantitative "approximately equal total processing time per queue per cycle." US 6,182,120 already frames the queue-weighting choice as a weight-vs-time selection (its own Background lists "the principle based on time"), and US 6,058,114 demonstrates time-parameterized weighted apportionment in the same scheduling art. Setting the weights to equalize per-queue processing time is a predictable design choice among a finite number of identified options — the classic KSR rationale. Claim 12's substitution of task identifiers for frames is met by US 4,642,756 / US 6,182,120, which queue and dispatch task/message descriptors, not payloads; claim 14 is the same method recited on a medium.

4. Dependent claims

5. Combinations and the motivation to combine

Combination A — for claim 1 (and 7, 11, 16)

US 5,220,653 (IBM) as primary + US 6,791,990 (Xyratex) + US 6,182,120 (IBM).

• Same field / analogous art: all three concern scheduling queued work items across multiple priority queues feeding a single service resource. US 5,220,653 and US 6,182,120 share an assignee (IBM) and even the same architectural vocabulary (holding queues → service queue; MIQs → task dispatch). US 6,791,990 is a data-switching scheduler — the very environment the '716 specification describes (voice gateway / DSP data path).
• Same problem: head-of-line blocking, starvation of low-priority work, and buffer overflow. US 5,220,653 states the goal is that "low priority tasks are not unduly 'service starved'"; US 6,791,990 defines overflow and override thresholds for exactly this reason.
• Predictable result: composing a multi-queue→service-queue scheduler with an overflow-threshold priority override yields nothing more than the expected sum of each reference's function. In re Keller: the test is not whether one reference's features can be "bodily incorporated" into another, but whether the claimed subject matter as a whole would have been obvious from the combined teachings.

Combination B — for claims 8, 12, 14 (and 5, 6)

US 6,182,120 (IBM) as primary + US 6,058,114 (Cisco) + US 4,642,756 (S&H).

• US 6,182,120 supplies the complete method skeleton: a scheduling cycle, per-queue weights, a critical/aging state, and an express discussion of time-based versus weight-based queue service.
• US 6,058,114 supplies the time-parameterized weighting and per-channel scheduling parameters, and even a first partition / second partition of channels by priority (claim 14 of '114) — directly parallel to the claimed first/second storage queues.
• US 4,642,756 supplies apportioning time quanta across priority groups in a task scheduler.
• Motivation: the frame-rate-mismatch problem recited in the '716 Background (5 ms vs. 30 ms streams in one FIFO queue) is precisely the problem each of these references addresses. A POSITA seeking to prevent a long 30 ms task from delaying a 5 ms task would naturally weight service by processing-time requirement — the express teaching of US 6,182,120's Background and the express mechanism of US 6,058,114.

Combination C — for claims 2, 4, 9, 10

US 6,791,990's proportioned lookup table + US 6,058,114's time parameters + US 6,182,120's dynamic critical state, for the pre-assigned/dynamic priority and lookup-table claims.

6. The strongest non-obviousness arguments (and why they likely fail)

(a) The Xyratex reference selects, it does not reclassify. US 6,791,990's overflow override "change[s] the priority symbol" so the selector picks the overflowing buffer now; it does not, on its face, re-route future, not-yet-received frames to a different queue. Claim 1, however, requires the classifier to "reassign data frame priority types from the first priority type to the second priority type to prevent overflow." A patentee could argue this is a predictive, closed-loop classification function absent from the art. Rebuttal: US 6,182,120's critical-state mechanism does modify the effective priority of queues based on measured occupancy/aging and then continues in that modified state — i.e., queue conditions feed back into the scheduling classification. Combined with Xyratex's own statement that the priority proportions "may be continuously varied in accordance with traffic patterns," the resulting control loop is merely the combination of two known feedback techniques, with a predictable result (KSR).

(b) Quantitative precision of "approximately equal total processing time." No single reference recites 6:3:1 weighting keyed to 5/10/30 ms. Rebuttal: US 6,182,120 identifies time-based queue weighting as a known alternative principle, and US 6,058,114 implements exactly that. Choosing the weights is an optimization of a disclosed parameter, not a new principle.

(c) Echo-canceller tail length (claims 9, 13, 15). Genuinely absent from the cited art. But these claims are in the alternative, and the remaining alternatives (frame size, codec type, frame processing requirements) find support in US 6,058,114.

(d) Objective indicia (§103 Graham factor 4). Per the earlier sections of this analysis, the patent lapsed for non‑payment of the 12‑year maintenance fee (effective 2018‑12‑26), and no litigation, PTAB proceeding, or CAFC appeal involving 7,155,716 was found. There is therefore no evidence in the record of commercial success, licensing, copying, or long-felt-but-unmet need — and no nexus evidence to invoke. Nothing rebuts the prima facie case.

Terms are broad enough to capture the art. The specification defines "frame" as "any block or arrangement of data or information" and "task identifier" as "any representation corresponding to a unique data frame," while stating the components "may be implemented as hardware, software, and/or a combination thereof." That breadth makes the structural claim language (port, scheduler, switch, router, classifier) functional, and functional labels do not distinguish over references performing the same functions.

7. Conclusion

Overall: the claimed subject matter would have been obvious to a POSITA at the 2002‑03‑08 priority date. The '716 patent's contribution is best characterized as the systematic composition of three well‑known scheduling techniques — multi-priority holding queues feeding one service queue (US 5,220,653), weighted/cyclical dequeueing with an aging-based critical state (US 6,182,120), and overflow-threshold priority override plus proportioned priority lookup (US 6,791,990) — with time-proportional weighting (US 6,058,114; US 4,642,756) substituted for message-count weighting as a predictable design choice.

Confidence: High for claims 1, 5–8, 11–14, 16 (grounded in full disclosure text of five references, with quotes above). Moderate for claims 2, 3, 4, 9, 10, 15 (dependent on three references I could only verify by title — US 6,341,303, US 4,942,569, US 6,816,494 — and on the voice-gateway-specific "echo canceller tail length" alternative). Recommended next step: pull the full texts of US 4,942,569 (Toshiba congestion control — likely to add explicit overflow-triggered rerouting) and US 6,816,494 (Nortel fairness algorithm) to firm up the claim‑1 overflow-reassignment and weighted-fairness showings, and confirm the pre-2002 publication dates for US 6,791,990 and US 6,816,494 as discussed in §1.