US 6810334

I'll run searches against public patent databases and litigation docket sources for this specific number.

Let me check litigation/PTAB history and confirm bibliographic data from additional sources.

Search coverage and what I found

I ran targeted queries against Google Patents, FreePatentsOnline, and general docket/web results for the exact strings 6810334, 6,810,334, and US6810334B2 combined with "CAFC 2026 docket," "litigation," "lawsuit," "Dongbu," and "infringement."

Bottom line on the litigation/docket request: I found no CAFC 2026 docket activity — and none is plausible. Zero 2026 Federal Circuit, district-court, or PTAB hits surfaced for this number. This is consistent with the record: the patent lapsed for failure to pay maintenance fees on 2012-10-26 and is listed "Expired – Fee Related" (Google Patents, FPO). A patent that lapsed in 2012 is not a realistic candidate for 2026 appellate enforcement activity. I state this as a negative search result, not proof that no filing exists — I have not queried PACER or the CAFC docket system directly, only public web indexes.

⚠️ Identifier collision warning: JP Patent No. 6810334 (特許第6810334号, registered 2020-12-15) is an unrelated Fujitsu patent on profile-data distribution control (P2016-120401). Do not conflate it with US 6,810,334. I interpret each literally and did not cross-map them.

Bibliographic summary — US 6,810,334 B2

Assignee chain-of-title note: recorded events run Dongbu Electronics → Dongbuanam Semiconductor, Inc. (merger, 2005-05-31) → Dongbu Electronics Co., Ltd. (change of name, 2006-06-06); Google Patents lists the current assignee as DB HiTek Co Ltd.

Data-quality anomaly I want to flag explicitly: the Google Patents legal-events table contains a 2004-03-11 entry for "LANZA TECHVENTURE, COLLATERAL AGENT … SECURITY AGREEMENT; ASSIGNOR: IREADY CORPORATION." That assignor (a different California entity) has no apparent connection to this wafer-inspection patent or to Dongbu. I treat that entry as a record artifact / mis-indexed reassignment, not as evidence of a real ownership transfer. I could not confirm it independently; treat it as uncertain.

Abstract (verbatim, from the record)

Disclosed is a method for inspecting defects of a wafer of a semiconductor device, wherein the wafer is set up with reference coordinates for a respective die so that inspection time is reduced and the defects are classified by the respective die. The method may be carried out by a defect analysis system comprising an inspection station for inspecting defects of the wafer and a review station for precisely re-inspecting defects. The method includes the steps of: providing the respective die with a serial number, the plural dies being formed on the wafer; and setting up coordinates for a plane of the respective die based on one edge of the die as reference point.

Plain-language overview of the independent claims

The patent has six claims, of which three (1, 3 and 5) are independent. All are method claims implemented on a defect-analysis system comprising an inspection station, a review station, and (in claims 1 and 5) a data analysis station.

Claim 1 — the core inspection method. A wafer-defect inspection method where you (a) give every individual die on the wafer its own serial number; (b) establish a coordinate system for each die's own plane, using one edge of that die as the origin/reference point — rather than a single wafer-wide coordinate system pinned to one reference die; and (c) send the defects to the review station for precise re-inspection whenever precise re-inspection is required. The practical point is per-die localization: a defect is addressed as "die #N, coordinate (x, y) within that die," which the specification says cuts inspection time and avoids re-inspecting dies already known to be bad from earlier processes (see the Table 2 result, where positions are small per-die values such as 10 µm, 5 µm — versus Table 1's wafer-wide values in the thousands of µm). Note that the claim literally says "inspecting defects of the wafers" (plural) in its preamble, while the body refers to "the wafer"; I'm reading that as drafting inconsistency, but taking it literally.

Claim 2 (dependent). Adds the step of sorting/classifying each die by the size and kind of defect found on it.

Claim 3 — defect-position determination. Same two per-die setup steps (serial number per die; per-die coordinates with a die edge as reference), but the characterizing step is output/notation: a detected defect is specified by the serial number of the die it sits on combined with the coordinate value of that defect within that die's own coordinate system. This is essentially the "addressing scheme" claim — the mechanism that makes a defect uniquely locatable across the wafer.

Claim 4 (dependent). Same classification-by-size-and-kind limitation as claim 2, appended to claim 3.

Claim 5 — multi-die variant (narrowest framing of the concept, expressed with two dies). Give a first die a first serial number and a second die a second serial number; establish a first coordinate system for the first die based on one edge of that die, and a second, separate coordinate system for the second die based on one edge of that die; then inspect both dies for defects. The claim's hook is that the coordinate origin is anchored to each die independently, not shared between them.

Claim 6 (dependent). Adds classification of the first die by size and kind of defect.

Points of uncertainty

1. No CAFC 2026 (or any) docket activity located for US 6,810,334. Searches returned nothing. Given the 2012 lapse, this is expected. I did not query PACER/CAFC systems natively.
2. The Lanza TechVenture / iReady Corporation security-agreement entry appears in the reassignment history for this patent but is inconsistent with the Dongbu chain of title. I could not verify it; flagging as likely mis-indexed.
3. "Current assignee = DB HiTek Co Ltd" comes from the Google Patents record; I did not independently confirm it via the USPTO assignment database.
4. I did not independently re-derive the KR 100472776 B1 family member's claims; the priority relationship (KR10-2002-0032613, 2002-06-11) is taken from the record as fetched.

I'll search for litigation involving US patent 6810334 across patent litigation databases.

Let me search more specific litigation databases.

Let me try a few more targeted databases and searches.

Search Results: Litigation Involving US Patent 6,810,334

No litigation involving US Patent 6,810,334 was found.

I searched patent‑litigation‑oriented sources (including Google Patents' "Litigation"‑adjacent data and general litigation coverage, CourtListener/PACER‑style docket coverage, and Unified Patents–style sources) using the exact number 6810334 and its formatted variants. None returned any case, docket, complaint, or judgment naming US 6,810,334 as an asserted patent.

Important disambiguation note

• Searches for the bare string "6810334" returned an unrelated Japanese patent (JP 6810334 B2, Fujitsu, profile‑data distribution) — this is not the US patent and is excluded per your instruction not to return results for similar numbers.
• Other hits were unrelated (a Turkish academic publication number, a 2004 security‑agreement filing referencing iReady Corporation, etc.). None are litigation over US 6,810,334.

Patent identification (for the record)

Why the absence of litigation is plausible (not asserted as fact)

• The patent lapsed in 2012 for failure to pay maintenance fees, and its anticipated expiration was 2023‑06‑11; an abandoned/expired process patent of this type would have little value as an assertion vehicle.
• The subject matter (wafer defect‑inspection workflow using per‑die serial numbers and per‑die coordinate reference points) is a process/method claim tied to fab inspection equipment and software — a class of patents less frequently asserted in high‑volume campaigns.

Caveats / limitations

• I could not confirm a negative with certainty. My searches were limited in number (tool step limit reached), and free litigation databases do not capture every district‑court complaint, especially older or quickly‑dismissed suits (2024–2026 filings, ITC §337 actions, or state‑court actions).
• To verify definitively, the reliable next steps would be: (1) query Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist) directly for "6810334"; (2) run a PACER/RECAP docket search on CourtListener; (3) check RPX Insight or Docket Navigator; and (4) confirm via the USPTO Patent Assignment / litigation records.

Bottom line: Based on the available sources searched, there is no known litigation involving US Patent 6,810,334. If you require a certified negative, I recommend the direct database queries listed above.

I'll verify the structured "no proceedings" block against public sources before writing up. Let me run targeted searches.

Let me run a final verification pass on Federal Circuit / CourtListener and the PTAB portal.

Proceedings overview

Zero AIA trial proceedings — no IPR, PGR, or CBM petition has ever been filed against US 6,810,334 B2, per the structured "PTAB proceedings on file" block (USPTO Open Data Portal) and confirmed by my independent web searches (which returned nothing on PTAB/PTAB E2E, Unified Patents, or CourtListener for this patent number). There is therefore no breakdown to give: 0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denials. Claims 1–6 stand exactly as granted and are entirely UNTESTED at the Board. The bottom-line defensive posture is not "hardened patent" — it is "the patent is dead for a different reason": the '334 patent expired on 2012-10-26 for failure to pay maintenance fees under 37 CFR 1.362 (USPTO legal-events record: "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES"), so it is unavailable as an assertion vehicle today regardless of claim validity.

Proceedings

No proceeding numbers can be listed. The structured PTAB block returns an empty set, and I will not invent proceeding numbers. For completeness, here is the negative finding in the same format a defendant would expect:

None found — no petitioner identified

• Type: n/a (no IPR / PGR / CBM on file)
• Filed: n/a
• Status: n/a — the structured ODP block reports no AIA trial proceedings; independent searches corroborate
• Judge panel: n/a
• Petition grounds: n/a — no § 102 / § 103 / § 112 challenge has ever been lodged at the PTAB
• Institution decision: n/a
• Final Written Decision: n/a — because no FWD issued, there is no claim-level verdict to report; claims 1, 2, 3, 4, 5, and 6 are all unadjudicated
• Settlement / termination: n/a
• Appeal: n/a — with no FWD, there is nothing appealable to the Federal Circuit; no CAFC docket number exists for this patent
• Defensive value: An IPR-based defense is unnecessary. The patent lapsed in 2012, so there is nothing left to invalidate and — critically — nothing left to infringe.

Disambiguation notes (avoiding false positives)

• The bare string "6810334" surfaces an unrelated Japanese patent, JP 6810334 B2 (Fujitsu, profile-data distribution control, registered 2020-12-15). It is a different jurisdiction and a different invention and has no PTAB relevance.
• The Google Patents page for US 6,810,334 lists "Cited By" / "Families Citing this family" entries (e.g., US 2007/0266570 A1 Boeing; KR 102459337 B1; KR 102834256 B1). These are citation relationships during prosecution of other applications, not AIA trial proceedings, and must not be read as PTAB filings.
• KR 100472776 B1 is the Korean priority counterpart (same 2002-06-11 priority). Any Korean IPTAB/KIPO trial activity would not be a US AIA proceeding, and none surfaced in my searches.

Strategic summary

Claim status. Claims 1–6 of US 6,810,334 are all SUSTAINED by default and none are CANCELED — not because the Board validated them, but because no one ever challenged them. There are three independent claims (claim 1, claim 3, claim 5) plus three dependent claims (2, 4, 6), and every one is UNTESTED. A defendant should be careful not to describe any claim as "invalidated," "confirmed," or "held patentable" by the PTAB: none of those things happened.

Estoppel landscape. There is no § 315(e)(2) estoppel to map, because there has never been a petitioner. No real party in interest, no privy, and no defensive aggregator has been bound by any PTAB ground. Consequently, in the purely hypothetical world where this patent were assertable, all prior-art grounds would remain available — § 102 and § 103 challenges on the three examiner-cited references (US 5,539,752 AMD; US 6,259,960 Joel Ltd.; US 6,334,097 Hitachi) and the four family-cited documents (JP 57-45919; KR 960011254; US 5,913,105 AMD; KR 970053273) would be untouched by estoppel. In practice this is moot for the reason below.

Pattern signals. No petitioner has filed even once, so there is no serial-filer pattern. The patent owner (Dongbu Electronics → DongbuAnam → Dongbu Electronics → now listed as DB HiTek Co., Ltd.) never appealed anything to the Federal Circuit, because there was never an adverse FWD to appeal. No Unified Patents or RPX-style challenge exists in the chain. This is fully consistent with the earlier litigation section of this analysis, which found no litigation — an expired, fee-lapsed process patent for fab inspection workflow (per-die serial numbers + per-die coordinate reference points) is not a commercially rational assertion target. The absence of PTAB activity here is not the usual "the patent is too strong to attack" signal; it is the "nobody bothered, and the patent then died on the vine" signal.

The dispositive point for a defendant. Even a clean bill of health at the PTAB would not help you, and neither does the absence of one. Because the patent expired 2012-10-26, a demand letter citing claims 1–6 today is defective on its face: infringement under 35 U.S.C. § 271 requires practicing the claimed method during the patent's enforceable term, and any pre-expiration recovery window has long since been foreclosed by the § 286 six-year damages look-back. A suit filed in 2026 could reach back only to 2020 — eight years after expiration. The correct response to any assertion is therefore a term/expiration defense and a Rule 11 / § 285 posture, not an IPR.

Recommended next steps

1. Treat "no PTAB activity" as the finding, and state it plainly. There is no FWD to link to, no disposition to quote, and no proceeding number to cite. Do not manufacture one to fill this template.
2. Verify the negative directly if a certified answer is required, since free databases do not capture everything:
   • PTAB E2E / PTAB Center: https://ptab.uspto.gov/ (search patent number 6810334)
   • PTAB Data & Statistics / Open Data Portal (the source block for this task)
   • CourtListener / RECAP for any CAFC appeal: https://www.courtlistener.com/ (search "6810334")
   • Unified Patents litigation & PTAB portal: https://portal.unifiedpatents.com/litigation/caselist
3. Pivot the defense to expiration, not validity. Confirm the lapse from the USPTO Patent Center record ("Expired – Fee Related," event dated 2012-10-26) and the anticipated-expiration entry (2023-06-11, 20 years from the 2003-06-11 filing). Note that the actual controlling date is the earlier 2012 lapse.
4. If you nevertheless want an invalidity theory on file (e.g., for a declaratory-judgment or § 285 narrative), note that with no petitioner of record, no estoppel attaches and the full prior-art set — including the three cited references above — remains available. But lead with expiration; an IPR against a fee-lapsed patent is the wrong instrument.

Caveat on certainty: I could not prove the universal negative in the strict logical sense — my searches were bounded, and free sources may lag on very old, quickly-terminated, or non-indexed filings. But the two independent lines of evidence here (the structured ODP block plus web search) agree, and the practical conclusion is reinforced by the 2012 fee lapse. If your matter turns on this point, run the four direct queries in item 2 before filing.

I'll verify the assignment record against USPTO Assignment Center-indexed data and cross-check the anomalous security-agreement entry before writing up.

Good — I have the prosecution firm and the corporate history. Now let me probe the anomalous security-agreement entry and try to pin down the recorded correspondent.

Data provenance note before the tables

I could not load assignmentcenter.uspto.gov directly (tool step limit reached before the portal would render — it is a JS app that doesn't return useful content to a plain fetch anyway). The reel/frame numbers below therefore come from the USPTO assignment records as mirrored in the Google Patents legal-events table for US 6,810,334, which is populated from the same assignment.uspto.gov/Assignment Center dataset. I have the reel/frame, conveyance, assignor, assignee and dates, but not the "correspondent of record" field — that field is only visible on the portal's detail view. Where I substitute the patent's attorney/agent of record (from the FPO record) for the recording correspondent, I say so explicitly and mark it as unverified. I flag this rather than guess.

Inventors

Pattern note — departure signal: not present / not determinable. All three inventors executed a single assignment of their rights one day before the US filing date (executed 2003-06-10; US application 10/458,871 filed 2003-06-11; recorded 2003-08-25). That is the ordinary pre-filing employee-assignment pattern for a corporate-origin Korean filing (priority KR 10-2002-0032613, 2002-06-11), not the "inventors leave within 12 months" pattern that precedes a portfolio fire-sale. The patent record contains no employment-termination data, so the departure signal cannot be affirmatively assessed from these sources — I am not inferring it from silence.

Original assignee

Dongbu Electronics Co., Ltd. (Republic of Korea) — the assignee printed on the face of the patent at issuance (2004-10-26) and confirmed by the FPO record.

• Line of business: semiconductor manufacturing — founded 1997 as a memory maker, converted to a foundry in 2001, and in 2002 acquired Anam Semiconductor's foundry operation from Amkor (≈KRW 114 bn). It is a pure-play foundry, not an inspection-tool vendor.
• Did it ship a product embodying the claims? Not in the conventional sense. Claims 1–6 are fab-process methods (per-die serial numbering, per-die coordinate setup, review-station re-inspection, defect classification). The natural reading is that Dongbu practiced the method internally in its wafer-fab defect-inspection flow; there is no evidence it sold a commercial inspection tool or software embodying the claims. The specification itself frames the invention as internal process control ("process establishment of manufacturing equipment").
• Current status: operating — but under a different name, through a merger chain (see timeline). Dongbu Electronics → merged into Dongbuanam Semiconductor (2004) → renamed back to Dongbu Electronics (2006) → Dongbu HiTek (2007) → DB HiTek (2017, when Dongbu Group rebranded as DB Group). DB HiTek remains an operating Korean foundry (KOSPI-listed) headquartered in Bucheon. Dongbu Group suffered financial distress around 2013 and put Dongbu HiTek up for sale, but the semiconductor unit continued operating; it was not dissolved or liquidated, and no bankruptcy sale of this patent is recorded.

Assignment timeline

Four assignment-type records exist (plus fee-payment/lapse administrative events, which are not conveyances). Chronological by execution date:

• 2003-06-10 (executed) / recorded 2003-08-25 — Reel 014418/0681

  • Conveyance: Assignment
  • Assignor: Lee, Hyun Bae; Choi, Jung Hwan; Kim, Jeong Hun (the three inventors, individually)
  • Assignee: Dongbu Electronics Co., Ltd.
  • Correspondent: not retrieved from the reel. The patent's attorney/agent of record per FPO is Saliwanchik, Lloyd & Eisenschenk (Gainesville, FL) — the firm that prosecuted the application, and therefore the likely recording correspondent for this pre-issuance assignment. Marked unverified; I did not view reel 014418/0681's correspondent field. No recurrence across the chain can be established because subsequent records are corporate self-filings.
  • Context: initial assignment of inventors' rights to their employer (pre-filing, standard).

• 2004-03-11 (executed) / recorded 2004-03-11 — Reel 014409/0910

  • Conveyance: Security Agreement (grant of security interest)
  • Assignor: iReady Corporation (California)
  • Assignee: Lanza TechVenture, Collateral Agent (California)
  • Correspondent: not retrieved.
  • Context: anomalous — recorded on this patent but inconsistent with its chain of title. iReady Corporation was an unrelated San Jose–area consumer-electronics/internet-connectivity chip company (its name surfaces in the prior-art record of US 6,751,665), not a Dongbu entity and not an owner or pledgor of a Dongbu wafer-inspection patent. Two plausible explanations, neither confirmed: (a) a reel digit transposition/mis-index — note the Dongbu reel 014418/0681 and this reel 014409/0910 are one digit-group apart and both from early 2004; or (b) an erroneous collateral schedule. I treat this entry as a record artifact, not a real encumbrance on US 6,810,334. No corresponding release is recorded, which is itself consistent with the artifact theory.

• 2004-12-21 (executed) / recorded 2005-05-31 — Reel 016593/0667

  • Conveyance: Merger
  • Assignor: Dongbu Semiconductor Inc.
  • Assignee: Dongbuanam Semiconductor, Inc. (later styled "Dongbu Anam Semiconductor")
  • Correspondent: not retrieved (corporate merger filing; no outside IP counsel identifiable from the record).
  • Context: internal reorganization — the 2004 merger of Dongbu's semiconductor unit with Anam Semiconductor, corroborated by contemporaneous Korean press ("2004년에는 동부전자와 아남반도체가 합병해 동부아남반도체로 새롭게 출범").
  • ⚠️ Chain gap: the original assignment (2003) ran to Dongbu Electronics Co., Ltd., but the merger assignor here is "Dongbu Semiconductor Inc." The intervening name change (Dongbu Electronics → Dongbu Semiconductor) is not recorded on this patent's reel history. The corporate identity is consistent with press history, but the recorded chain has a one-link break.

• 2006-04-10 (executed) / recorded 2006-06-06 — Reel 017718/0964

  • Conveyance: Change of Name
  • Assignor: Dongbuanam Semiconductors, Inc.
  • Assignee: Dongbu Electronics Co., Ltd.
  • Correspondent: not retrieved (name-change filing).
  • Context: change of name only — dropping the "Anam" brand, corroborated by press ("동부아남반도체 … 동부일렉트로닉스로 사명을 변경").

No further assignments are recorded after 2006. There is no transfer to any LLC, trust, or licensing entity; no license recordation; no security-interest release; and no recorded post-lapse transfer. Subsequent name changes (→ Dongbu HiTek 2007 → DB HiTek 2017) are not separately recorded on this patent's reel history — Google Patents' "current assignee: DB HiTek Co Ltd" reflects the corporate-continuity mapping, not a recorded assignment on this docket. The last recorded event of substance is the 2012-10-26 lapse for non-payment of maintenance fees (37 CFR 1.362), followed by the 2012-11-26 discontinuation notice.

Timeline diagram

timeline
    title Ownership of US 6810334
    2002 : Korean priority application filed
    2003 : US application filed
         : Inventors assign to Dongbu Electronics
    2004 : Merger into Dongbuanam Semiconductor
         : Unrelated security agreement entry
    2006 : Renamed Dongbu Electronics
    2007 : Renamed Dongbu HiTek
    2012 : Lapsed for unpaid maintenance fee
    2017 : Renamed DB HiTek

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. Every recorded assignee is an operating semiconductor entity (Dongbu Electronics, Dongbuanam/Dongbu Anam, Dongbu Semiconductor). No "IP / Holdings / Ventures / Licensing" suffix appears as an assignee on any reel (014418/0681; 016593/0667; 017718/0964). The only "Ventures"-style name in the entire record — Lanza TechVenture, Collateral Agent (reel 014409/0910) — is on the anomalous iReady entry, is a collateral agent (secured lender) not a purchaser, and is unrelated to the Dongbu chain. Not a finding.

2. Known asserter in the chain — Not present. None of the chain entities (Dongbu Electronics, Dongbuanam, Dongbu HiTek, DB HiTek) appears on NPE/asserter directories maintained by RPX or Unified Patents or in the lists named in the task. The current listed owner, DB HiTek Co., Ltd., is an operating foundry, not an assertion vehicle. No Acacia / Marathon / IV / Wi-LAN / Conversant / Pendrell / Spangenberg entity appears anywhere in the record.

3. Repeat correspondent across the chain — Unclear / not verifiable. I could not retrieve the correspondent-of-record field for any reel (portal not directly queryable within this session). The single identifiable IP firm touching this patent is Saliwanchik, Lloyd & Eisenschenk (prosecution counsel of record per FPO), which is an ordinary operating-company prosecution firm; a single appearance is expressly not a signal under the task's own rule. No recurrence to report.

4. Cascading transfers — Not present. Only three conveyance-type events occur after filing, spanning ~3 years (2003 → 2004 → 2006), all of them intra-group corporate steps (assignment from employees, merger, name change). There is no chain of successive LLC-to-LLC assignments within 24 months, and no shared registered-agent address pattern (no agents appear at all).

5. Pre-litigation transfer — Not present. No litigation naming US 6,810,334 was located (consistent with the previously generated litigation section and the 2012 lapse). With no suit, there is no assignment dated within 6 months of a first suit. The nearest-dated conveyance to the patent's end-of-life is the 2006 name change — six years before lapse and with no assertion following.

6. Bankruptcy fire-sale — Not present as to this patent. Dongbu Group's group-level financial distress (2013 asset-sale plan, Dongbu HiTek put up for sale; Korean press coverage) is a corporate-level event, not a recorded patent assignment, and falls after the patent lapsed (2012-10-26). No Chapter 7/11 sale of this patent is recorded. Not a finding.

7. Privateering — Not present. No transfer from the operating company to an NPE that then asserts on its behalf. The chain simply ends at the operating entity.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at an operating foundry, and then the patent lapsed for non-payment.

Verdict

Insufficient data — but read precisely: there is insufficient data to support any NPE finding, and the affirmative evidence points the other way. The entire recorded chain is operating-company internal: inventors → Dongbu Electronics (reel 014418/0681, 2003), merger into Dongbuanam (reel 016593/0667, 2004), name change back to Dongbu Electronics (reel 017718/0964, 2006), with zero transfers to licensing entities and zero asserted litigation before the 2012-10-26 lapse. Of the five enumerated verdicts, none of the NPE categories fits, and "Operating-company assertion" fails because there is no suit; so the honest label is Insufficient data rather than a fabricated NPE call. Two record defects are the reason I stop short of a clean "operating/non-asserting" classification: the unexplained iReady/Lanza security-agreement entry on reel 014409/0910 and the unrecorded Dongbu Electronics → Dongbu Semiconductor name change between the 2003 assignment and the 2004 merger — both of which I flagged rather than papered over.

Verify directly at: USPTO Assignment Center — search by patent number 6810334 (fallback index: assignment.uspto.gov/patent/index.html). When you open reel 014418/0681 and reel 014409/0910 in the detail view, the two things worth capturing that I could not are (i) the correspondent of record on each, to test signal 3, and (ii) the property list on reel 014409/0910, to settle whether the iReady/Lanza entry is a genuine encumbrance or a cross-indexing artifact.

I'll research the cited prior art for US 6,810,334. Let me search the USPTO and patent databases for each reference.

Let me search for the remaining cited references.

Let me search for the remaining foreign-cited references and the pre-grant publication details.

I've now retrieved the cited references. Below is the prior-art analysis for US 6,810,334 B2, grounded in the patent record you provided (authoritative) plus the retrieved bibliographic/abstract data. I've reached my tool-step limit, so I flag what remains unverified.

Scope and method (what I actually searched)

• I queried Google Patents (which serves USPTO-derived bibliographic, citation, and family data for US 6,810,334) and FreePatentsOnline / uspto.report for each cited reference by number and title.
• ⚠️ I did not complete a native run through USPTO Patent Public Search or PatentCenter's file-wrapper/office-action view because I hit the tool-step cap. That means I cannot state which of these references were applied under §102 vs. §103, or whether any rejection was actually made. Google Patents lists them only as "cited by examiner" references; that is not the same as "applied as an anticipatory reference." Treat the §102 labels below as my analytic assessment, not a recitation of an examiner's rejection.
• Per the operating rule, I interpret 6810334 = US 6,810,334 B2 literally. The unrelated JP 6810334 (Fujitsu) is excluded, consistent with the earlier section.

Two categories of "citation" in this record — don't conflate them

The Google Patents record contains three different lists. Only the first is prior art:

The forward-citing items (Boeing US 20070266570/US 7353609, Hitachi US 20100128970→US 8090190, Lifetime Brands US 10127523, SK Siltron KR 102834256, Etamax KR 102459337) are not prior art and are excluded from the §102 analysis.

Prior art of record — the three examiner citations

All three pre-date the 2002-06-11 priority date, so each qualifies as prior art under pre-AIA §102 (this application was filed 2003-06-11, before the AIA first-inventor-to-file regime took effect 2013-03-16).

1. US 5,539,752 A — Advanced Micro Devices, Inc.

Brief description (from the retrieved text). An in-line, spatially-aware wafer-defect analysis system. A scan tool (14) feeds a defect analysis system (16) running three programs: a decluster program, a preclassify program (auto-identifies statistically meaningful sample defects for manual review), and an analysis program that extrapolates classification codes to the unclassified defects and flags yield-detracting operations. Defect records are stored by coordinates and estimated size. The patent expressly works at the die level — claim 33 recites "a die is first selected from amongst all die … and then a defect is randomly selected from within said randomly selected die," and subpopulations are defined by "defect size ranges" and "defect locations." A review station is used for manual classification (claim 36).

§102 potential (my assessment).

• Claims 1, 3, 5 — NOT anticipated. The reference's coordinate regime is a wafer-level map (defects recorded by wafer coordinates); it discloses no per-die serial number and no coordinate system anchored to an edge of each individual die. Both are indispensable to every independent claim. Claim 33's "die is selected" is a randomization construct for extrapolation, not per-die addressing, and does not supply a per-die origin.
• Claims 2, 4, 6 — NOT anticipated under §102. These depend from 1/3/5 and therefore incorporate the missing per-die limitations. The reference's classification-by-defect-type-and-size teaching is materially relevant, but only as §103 subject matter. It cannot anticipate a claim it does not fully disclose, and it cannot anticipate a dependent claim that carries the independent claim's unmet limitations.

2. US 6,259,960 B1 — Joel Ltd. (JEOL)

Brief description. A two-stage wafer/part inspection system: a preliminary optical inspection writes preliminary-inspection information files containing "product serial numbers, lot numbers, wafer identification numbers or codes, data about process steps, data about the fabrication equipment, and date," plus "the number of foreign materials, the number of defects, their positions on the wafer, their sizes." A review stage (review SEM / optical review) then re-inspects selected defects by reference to the preliminary data, and results are written back to the database. Selection of which defects to review is operator-driven.

§102 potential (my assessment).

• Claims 1 and 5 — NOT anticipated. This is the closest reference to the preamble ("inspection station … and a review station for precisely re-inspecting defects"), and it does disclose storing defect position and size and re-inspecting selected defects. But it fails the two limitations that define the invention: it assigns serial numbers to wafers/lots, not to each die, and it stores defect positions in a wafer-level frame — no per-die coordinate system referenced to a die edge. It also lacks the claim-5 "first die / second die" paired serial-number-plus-coordinate structure.
• Claim 3 — NOT anticipated. The claim's characterizing step requires specifying a defect by the serial number of the die it sits on combined with the coordinate of the defect within that die's own coordinate system. US 6,259,960 keys defects to wafer ID and wafer-frame positions, not die serial + intra-die coordinate. No anticipation.
• Claims 2, 4, 6 — NOT anticipated (dependent; inherit the unmet limitations). The reference does sort/store defects with sort codes representing kinds of defects and size-feature values, which is §103-relevant to the "size and kind" classification, but it is not anticipatory of any claim as a whole.

3. US 6,334,097 B1 — Hitachi, Ltd.

Brief description. Determines defect lethality/severity from defect coordinate data without manual review, then selects which defects to review in descending severity order. It segments circuit patterns into areas each defined by an explicit coordinate box "AREA NO | x1 | y1 | x2 | y2 | CLASS," associates each defect to its area from the defect coordinates, and compares defect sizes to rules per area. Critically for this case, it recites a step that "compares coordinate data of the defects … in a previous process to a process where the review is being executed at present with coordinate data of the defects … in the concerned process … and selects only the defects having non-coincident coordinate data … as candidate defects of the review object." It also classifies defects into cluster vs. random types.

§102 potential (my assessment).

• Claims 1, 3, 5 — NOT anticipated. The "compare previous-process vs. current-process coordinates and review only non-coincident defects" teaching is conceptually close to this patent's stated benefit (avoid re-inspecting dies already flagged from a prior process). But the reference operates in a wafer/pattern coordinate frame (area boxes x1,y1–x2,y2), with no per-die serial numbers and no per-die origin at a die edge. The independent claims are not met.
• Claims 2, 4, 6 — NOT anticipated (dependent). Its severity/size and cluster/random classification are §103-relevant to "size and kind," nothing more.
• This is the best of the three references for a §103 motivation-to-combine narrative (kill-the-redundant-reinspection goal), but it is not an anticipation reference.

Family-cited references (cited against KR 100472776 B1, not necessarily in the US record)

These four appear under "Family Cites Families." I include them because you asked for each citation in the 6810334 record, but I flag that their US-case status is unverified.

4. JP S57-45919 A — NEC Corp.

• Citation: JP S57-45919 A, "Applying method for chip recognition information onto semiconductor substrate"; NEC Corp.
• Dates: priority/publication 1980-09-02 → published 1982-03-16.
• Description: Method for applying chip-recognition information (chip identifiers/marks) onto a semiconductor substrate — i.e., marking individual chips with identifying information.
• §102: Not anticipatory. It concerns marking/recognizing chips, not defect inspection, and discloses no inspection/review workflow or per-die defect-coordinate system. Its subject matter — putting an identifier on each chip — is at most §103-relevant background to the "serial number per die" element. (Published 1982, so it is pre-AIA §102(b) art as to the 2002 priority.)

5. US 5,913,105 A — Advanced Micro Devices, Inc.

• Citation: US 5,913,105 A, "Method and system for recognizing scratch patterns on semiconductor wafers"; Advanced Micro Devices Inc.
• Dates: priority 1995-11-29 → granted 1999-06-15.
• Description: Automatically recognizes scratch-type defects from wafer scan data by declustering defects, fitting a best-fit line to each cluster, and classifying clusters as scratches. Records defects as location data (x, y) and size data (x_s, y_s); a review station with a microscope is used for manual classification. Directly maps to this patent's discussion of "scratch-type defects such as B and C" in FIG. 2.
• §102: Not anticipatory. Highly §103-relevant to the scratch/liquid defect problem and to defect coordinates + review station, but again wafer-level coordinates with no per-die serial number or per-die origin. Fails all independent claims.

6. KR 960011254 B1 — Hyundai Electronics Industries

• Citation: KR 960011254 B1, "Repair confirming method"; Hyundai Electronics Industries Co.
• Dates: priority 1993-02-05 → published/registered 1996-08-21.
• Description: A repair-confirmation method (repair verification) for semiconductor devices/wafer repair.
• §102: Not anticipatory on the retrieved information; unrelated to per-die defect-coordinate inspection. At most general fab-QA background. ⚠️ I could not retrieve a full-text abstract (tool limit), so this assessment rests on the title/classification only.

7. KR 970053273 A — inventor 김주용 (Kim Ju-yong)

• Citation: KR 970053273 A, "Wafer defect inspection method"; published 1997-07-31 (priority 1995-12-30).
• Description: A wafer defect-inspection method.
• §102: ⚠️ I could not retrieve a substantive abstract or claims (tool-step limit reached). By title it is in-field, but I have no basis to assert it discloses per-die serial numbers or per-die coordinate systems, and therefore no basis to assert anticipation. Flagged as unverified.

Bottom line

1. No cited reference anticipates any claim of US 6,810,334 under §102. The three examiner references (US 5,539,752; US 6,259,960; US 6,334,097) — and the family-cited US 5,913,105 — all operate on a wafer-level coordinate frame and none assigns a serial number to each die nor establishes a coordinate system anchored to an edge of each individual die. Those two features are common to all three independent claims (1, 3, 5); because dependent claims 2, 4, 6 incorporate them, no dependent claim is anticipated either.

2. The citations are best characterized as §103 (obviousness) art, not §102 art:

   • US 5,539,752 → defect classification by type/size, die-level defect enumeration, review station.
   • US 6,259,960 → two-stage preliminary-inspection + review workflow; storing defect position and size.
   • US 6,334,097 → automatic review-object selection; comparing previous-process vs. current-process defect coordinates to skip redundant review; size/severity classification.
   • US 5,913,105 → scratch-pattern recognition; defect coordinates + size + review station.

3. The apparent point of novelty — per-die serial numbering plus per-die coordinate frames with a die edge as origin (yielding the small intra-die values of Table 2, e.g. 10 µm/5 µm, vs. the wafer-scale values of Table 1) — is the limitation absent from every retrieved reference, which is why none is anticipatory.

Caveats

• I could not verify the examiner's actual rejection basis (office actions / file wrapper) for US 6,810,334; the §102 vs. §103 attribution above is analytical. Native USPTO Patent Public Search / PatentCenter review is the correct next step.
• Two family-cited references (KR 960011254 B1 and KR 970053273 A) could not be substantively retrieved within the tool budget; their entries above are title-level only and are expressly not asserted as anticipatory.
• Source of the citation lists is the Google Patents record for US 6,810,334 (USPTO-derived); I did not independently re-derive the KR family's examination citations.

I'll pull the substance of the cited prior-art references so the §103 analysis is grounded in actual disclosures rather than titles alone.

Now the remaining cited references, including the foreign-language family citations.

Now the foreign family citations and any additional art locating defects per-die.

Obviousness Analysis — US 6,810,334 B2 under 35 U.S.C. § 103

Scope note: the prior sections established the bibliographic record, claim architecture, litigation history (none found), and the 2012 lapse. This section does not repeat those. It builds directly on the claim-mapping already performed and the "Prior Art" module (examiner-cited references plus family citations shown on the Google Patents page).

1. Threshold framing: this is an academic § 103 exercise

Because the patent lapsed for non-payment of maintenance fees effective 2012-10-26, there is no live IPR, no district-court invalidity contention, and no Federal Circuit appeal in which a § 103 holding could issue. What follows is therefore a hypothetical merits analysis — the kind of rejection a USPTO examiner would have written, or the kind of invalidity position a defendant would have pleaded, had the patent been asserted while in force. This matters because it changes the standard: no presumption of validity burdens the analysis, but also no commercial-evidence record (secondary considerations) exists to weigh.

Governing law: Pre-AIA § 103(a) (application filed 2003-06-11; priority 2002-06-11 KR 10-2002-0032613). The Graham v. John Deere, 383 U.S. 1 (1966), factors and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), motivation standard apply.

2. The prior-art record actually available

All dates below are from the record as fetched. Every reference listed is a printed publication or patent published before the 2002-06-11 priority date, so each is available under pre-AIA § 102(b) unless noted.

Caveats I must state plainly:

• I retrieved abstracts, summaries-of-invention and partial claim text for the three examiner-cited US references and US 5,913,105 from Google Patents, FreePatentsOnline, EveryPatent and uspto.report. I did not read the full specifications. My characterization of each reference's disclosure is therefore reliable at the level of what the reference claims and summarizes, but I would not certify a verbatim quote from a column/line I have not read.
• I could not retrieve substantive disclosure for KR 970053273 A or KR 960011254 B1. My searches for those numbers returned irrelevant Japanese-language results and no usable text. I rely on their titles only and treat them as corroborating, not primary, art.
• Likewise, I could not retrieve the text of JP S57-45919; the title and the Google Patents listing are all I have. I flag this because the NEC reference is potentially important on the "serial number per chip" element, and my support for it is title-level only.
• Additional art not considered by the examiner that I encountered and that bears directly on the claims (each flagged for date verification below) should be treated as leads, not established § 102(b) art:
  • US 6,045,083 (issued 2000-04-04) — pattern inspection with a table reporting defects against CHIP NUMBER (e.g., "A II," "A III," "B II") and defect size classes. Appears to be solid § 102(b) art on the "identify defect by die/chip identifier + size class" concept.
  • US 5,801,067 (issued 1998-09-01) — "Method for recording and identifying integrated circuit chips and the like"; per-chip identification marking. Solid § 102(b) art on the serial-number element.
  • US 6,456,951 (issued 2002-09-24) — flowchart shows "WRITE AREA COORDINATES DATA IN CHIP" and repeated "CHIP NUMBER" tabulations. ⚠️ Its issuance postdates the 2002-06-11 priority date. Its availability turns entirely on whether its US filing date predates that date (§ 102(e)) — I did not verify its filing or priority date, so I treat it as unusable until verified. If its filing does predate, it is a strong secondary reference.
  • JP 2006294680 A (published 2006) — teaches recording both wafer identification information (ウェハ識別情報) and element-position identification information (素子位置識別情報) on the wafer. ⚠️ Post-dates the priority date by four years and is NOT prior art. I mention it only to note that the practice nonetheless became conventional; it cannot support a rejection.

3. Where the actual dispute lies: admitted prior art vs. the two contested limitations

This is the single most important structural point for the § 103 analysis, and it makes the claims much weaker than their face suggests.

The specification's FIG. 1 system is described in the specification as "a conventional system for analyzing defects of wafer" — inspection station 10, data analysis station 20, review station 30, host computer 40 — and the specification states the conventional system "adapts an inspecting way that the inspection station 10 and the review station 30 set up coordinates of wafer for its entire area based on a specific die in the wafer."

That is an applicant-admitted prior art (AAPA) statement. It concedes:

1. The entire three/four-station defect-analysis architecture recited in the preambles of claims 1, 3 and 5;
2. The conventional review-station re-inspection step; and
3. The conventional practice of wafer-wide coordinates referenced to one reference die.

AAPA cannot be used for anticipation (§ 102) but is fully usable for § 103 — In re Fout, 675 F.2d 297 (CCPA 1982); In re Nomiya, 509 F.2d 566 (CCPA 1975); MPEP § 2129. Once the preamble architecture and the re-inspection step are conceded, the only limitations left in genuine dispute across all six claims are two:

• (L1) giving each respective die its own serial number; and
• (L2) establishing a separate coordinate system for the plane of each die, anchored at an edge of that die (rather than one wafer-level system).

Everything else in the claims is either admitted art or a conventional data-processing step. Claims 2, 4 and 6 add only a classifying step. That collapses the case to a two-element obviousness question.

4. Limitation-by-limitation mapping

5. Grounds of rejection

Ground I (primary): US 6,259,960 in view of JP S57-45919, further in view of US 6,334,097

This is the cleanest ground and the one I would lead with.

What 6,259,960 already supplies. Joel's system is arguably 80% of claims 1 and 3 on its face: a preliminary optical inspection apparatus detects and stores defect positions and sizes; an inspected-part information database stores the data with part serial numbers and wafer identification numbers/codes; a review apparatus (review SEM with an XY table) re-inspects a selected defect by reference to that data; and the system detects and corrects coordinate deviations between the preliminary tool and the review tool via a part position reference point with a target coordinate correcting means (claim 8). Claim 11 goes further and locates those reference points on chips of a wafer patterned into identical chips.

What JP S57-45919 supplies. The element Joel does not clearly supply — a per-die identification — is supplied by the NEC reference's stated purpose of "applying chip recognition information onto a semiconductor substrate." Combined with 6,259,960's "part search information … helpful in identifying defects on an already preliminarily inspected part," the two together read on claim 1's "(a) per-die serial number; (b) per-die coordinate plane; (c) review-station re-inspection."

What US 6,334,097 supplies. The motivation, expressly and technically: Hitachi teaches comparing the coordinate data of defects detected in a previous process against coordinate data from the current process and selecting only the defects with non-coincident coordinates as review candidates. That is precisely the efficiency problem the patent's specification identifies (re-inspecting dies already known bad from earlier processes) and precisely the problem the patent claims to solve.

Motivation to combine — articulated as a POSITA would. A person of ordinary skill in the art in 2002 (a fab yield/inspection engineer or equipment-software developer) had several concrete, technical reasons to move from wafer-level to die-level coordinates:

1. Coordinate-drift correction. Joel itself teaches that preliminary-tool coordinates and review-tool coordinates deviate and must be corrected relative to a reference point. Drift accumulates with distance from the reference origin. Anchoring the coordinate frame at the local die edge — a short distance from the defect — mathematically reduces the lever arm over which stage-positioning and wafer-rotation errors accumulate. This is a mechanistic motivation, not a hindsight one.
2. Cross-process defect matching. Hitachi's cross-process comparison works only if "the same defect" can be reliably recognized in two data sets. Absolute wafer-level coordinates for a 200–300 mm wafer are sensitive to stage rotation and to which tool did the measuring; die-relative coordinates are rotation-tolerant and directly comparable. Thus the die-level frame improves the operability of the Hitachi comparison — a classic "improvement of the primary reference's own function" motivation (MPEP § 2144.04).
3. Die-level yield binning already required die identity. US 5,539,752 evaluates the number of die of a wafer rendered inoperative by the specified defect type and compares against a per-die threshold — the system must therefore already know, per defect, which die it belongs to. Die-relative addressing is the ordinary way to store that.
4. Fabrication tooling reality. The art already numbered and marked die/chips (JP S57-45919; US 5,801,067), and defect wafer maps were routinely organized in a row/column die grid (US 5,539,752's subpopulations "defined by defect locations"; US 5,913,105's wafer maps and "scanned dice" statistics). Adding a serial number to a grid cell that is already indexed is not an inventive act; it is data-schema bookkeeping.

Reasonable expectation of success. The combination requires no new hardware and no new physical principle — literally no more than changing the origin of a coordinate system and adding an index field to an existing defect record. KSR: "the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results." The patent's own asserted benefits (per-die identification of defective dies; reduced inspection time) follow necessarily from the change, and cannot constitute unexpected results.

Ground I would therefore reject claims 1, 2, 3 and 4.

Ground II (alternative): US 5,539,752 in view of US 6,259,960 and US 5,913,105

• US 5,539,752 provides the defect-analysis architecture, the review station (claim 36), the manual classification of defects, subpopulations defined by defect size ranges and by defect locations (claims 34–35), and per-die thresholds on the number of die rendered inoperative.
• US 5,913,105 provides the coordinate-based wafer-map framework — defect records with location (x, y) and size (x_s, y_s) and classification codes distinguishing size/cluster categories — plus per-die statistic tracking ("scanned dice," scratch density). AMD's two references are siblings; combining them requires no motivation beyond the fact that one is the defect-analysis engine and the other is a pattern-recognition utility for the same engine (the '105 patent's own FIG. 1 shows the same system topology).
• US 6,259,960 supplies the per-part/per-chip reference-point coordinate frame.

Ground II reaches claims 1–4 as well, and gives an independent route to claims 5 and 6 (see § 7).

Ground III: the honest fallback on the two disputed elements — obvious-to-try

If a patentee were to argue that neither Joel nor NEC actually discloses a coordinate origin at every die's own edge, the response is the KSR "obvious to try" branch: the field presented only two known coordinate-frame options for wafer inspection (wafer-level, as the specification concedes was conventional; and part/chip-level, as Joel claim 11 expresses). Where "a finite number of identified, predictable solutions" exists, § 103 is satisfied. The choice has a predictable effect on accuracy and on data volume, and nothing in the art taught away from the chip-level option.

6. The patentee's best counterargument — and why it fails

The strongest defense is narrow but real: US 6,259,960's claim 11 speaks of "part position reference pointS" established on "certain chips" — it is ambiguous whether that means a single wafer-level reference point that happens to be located at a chip landmark (which is what coordinate-deviation correction ordinarily needs) or an independent coordinate origin for each and every die. If read the former way, no reference in the record expressly teaches the "each respective die has its own reference point" limitation, and claims 1, 3 and 5 turn on exactly that.

Why it fails:

1. Claim 5 is written to defeat this argument. Claim 5 recites only a first die and a second die, each with its own serial number and its own origin. It does not require "every die." Two dies — adjacent dies that any wafer-level scheme would handle trivially — satisfy the literal claim. There is no plausible world in which using two die-local origins instead of one is nonobvious when one is conceded to be conventional.
2. Claim 1 is broader than its own specification. "Setting up coordinates for a plane of each respective die based on one edge of each respective die as reference point" specifies only one edge. One edge does not even fully define an origin; under the broadest reasonable interpretation, the claim reads on any scheme that uses a die-edge point as an anchor — which is routine alignment practice and is what Joel's reference-point mechanism already does.
3. No teaching away. Nothing in the art discourages the die-local frame. The only arguable "cost" (more reference frames to manage, more stored data) is a straightforward engineering trade-off, not a technical prejudice.
4. The problem was already recognized. The specification itself concedes the wafer-wide scheme was conventional and problematic, and the record's own Table 1 (wafer-level coordinates in the thousands of µm) versus Table 2 (die-level coordinates like 10 µm, 5 µm) shows the fix is definitional, not inventive.

7. Dependent and multiple-die claims

Claims 2 and 4 (classify by size and kind). These are the easiest claims in the patent to invalidate. US 5,539,752 expressly claims classification codes indicative of defect type and subpopulations defined by defect size ranges (claim 34), and US 6,334,097 determines lethality by comparing defect size and selects review objects by severity. US 5,913,105's classification codes "might classify defects in terms of defect size, i.e., whether it is part of a big cluster or small cluster." Three independent references teach the exact limitation. Claims 2 and 4 fall under any of Grounds I–III.

Claim 5 (two dies, two serial numbers, two origins). Beyond the Ground I–III analysis, claim 5 is vulnerable as an obvious duplication / repetition of parts. The Federal Circuit and its predecessor have long held that mere duplication of a known element to a known number of instances is obvious absent a new and unexpected result — In re Harza, 274 F.2d 669 (CCPA 1960); In re Geiger, 815 F.2d 686 (Fed. Cir. 1987). Stepping from one die-local origin (Joel claim 11, "certain chips") to two die-local origins adds nothing but a second instance of the same operation, and the specification identifies no result peculiar to the number two. Note also that claim 1 already recites "each respective die" — claim 5 is in substance a narrower restatement of claim 1 limited to two dies; anything that invalidates claim 1 a fortiori invalidates claim 5.

Claim 6 (classify the first die). Slightly narrower than claim 5 because it requires classification of only the first die — but the classification limitation is squarely met by US 5,539,752 and US 6,334,097 as above. It falls with claim 5.

8. Claim-drafting defects that materially assist the § 103 case

These are worth recording because they broaden the claims beyond what the patentee probably intended, and broad claims are easier to invalidate.

1. Claims 1 and 3 recite a purely conditional step. Claim 1's final step is "re-inspecting the defects at the review station, if precise re-inspection is required." Under Ex parte Schulhauser (PTAB 2016), where a method claim's final step is conditional and the condition need not be met, the broadest reasonable interpretation covers performance of the method without that step. So the review-station limitation adds essentially nothing to the prior-art analysis — and in any event the specification admits the review station was conventional. Claim 3's characterizing step ("specifying the position of a defect … with the serial number … and coordinate value") is a data-notation/output step, not a physical transformation, which further lowers the bar for showing that any system already storing defects against a die index meets it.
2. The preamble of claim 1 says "defects of the wafers" (plural) while the body recites "the wafer." I flagged this as a drafting inconsistency in the earlier claim overview and carry the same reading here: I take the preamble literally, but it is a § 112 clarity problem that a challenger would exploit to argue the preamble is non-limiting, thereby stripping claim 1 of even its system context.
3. "One edge … as reference point" is under-specified (see § 6.2), which broadens rather than narrows the claim.

9. Secondary considerations — none present, and none available

• No commercial-evidence record exists. The earlier litigation search found no litigation, no IPR, and no assertion involving US 6,810,334; there is therefore no licensee/adversity record, no industry-praise evidence, and no nexus evidence. My prior section flagged this as a negative search result rather than a certified negative, and I maintain that qualification.
• No unexpected results are disclosed. The specification's asserted benefits — the defective die is "easily identified," inspection time is reduced, yield rate increased — are the direct and expected consequences of die-level indexing. Anticipation of a benefit that follows necessarily from the structural change is not an unexpected result.
• Long-felt need cuts against the patentee here. The specification itself frames wafer-wide referencing as a longstanding, recognized problem ("The reason why the problems during above-mentioned inspection are generated is that the entire wafer is inspected based on a specific reference die"). Recognizing the problem is not the invention; the art (Joel claim 11; Hitachi's area-identification step) already pointed at the solution.

10. Bottom line

The claims' entire inventive contribution reduces to two administrative changes to a defect-record schema — an index field and a coordinate origin — applied to an inspection architecture the applicant itself conceded was conventional. Every element is disclosed or suggested by examiner-cited art, and the art supplies a specific technical motivation (reducing reference-point coordinate deviation; enabling reliable cross-process defect matching) plus an express statement of the efficiency problem. I would expect all six claims to be held obvious, with claim 1 the closest question and claims 2, 4 and 6 the easiest.

Confidence and limits, stated explicitly:

• High confidence in the § 103 conclusion as to claims 2, 4 and 6 (three independent references teach classification by size and kind).
• High-to-moderate as to claims 1, 3 and 5; the outcome turns on whether a tribunal reads Joel's claim 11 chip-level reference points as per-die origins, and on whether the AAPA concession in the specification's FIG. 1 discussion is given full weight.
• Not verified: the full specifications of US 5,539,752, US 6,259,960, US 6,334,097 and US 5,913,105 (I read abstracts, summaries and partial claims); the substantive disclosures of KR 970053273 A and KR 960011254 B1 and JP S57-45919 (title-level only); and the filing/priority dates of US 6,045,083 and US 6,456,951, the latter of which is not usable as prior art pending date verification. A rigorous rejection would quote the primary references at column/line, which I have not done.