US 6365917

I'll search for this specific patent number and check for any litigation activity.

Let me search for the specific claims and any litigation records.

Let me try to obtain the actual claim text for this patent.

I could not retrieve one piece of the record — the literal granted claim text — so I flag that explicitly below rather than reconstructing it.

US 6,365,917 B1 — Verified Bibliographic Data

Later applications claiming priority from this patent (per Google Patents "Priority to" entries): US 10/079,512 → US 6,949,767 B2; US 11/234,382 → US 7,564,059 B2; US 12/505,640 → US 2009/0315085 A1; US 13/298,469 → US 2012/0074418 A1. These are separate documents and I am not treating them as this patent.

Abstract (verbatim)

In order to realize a higher reliability TFT and a high reliability semiconductor device, an NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate should have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.

(The "potion" typo is in the source document; I have not corrected it.)

⚠️ Uncertainty flag on the claims

I do not have authoritative claim text for this patent. The full patent text supplied to me is truncated mid-sentence in Embodiment Mode 1 ("Anisotropic etching of the first conduct…"), and my searches of Google Patents, Justia, and USPTO/PTAB document repositories did not return the literal "What is claimed is" section. Google Patents' algorithmically extracted "Definitions" and "Prior art keywords" (impurity region; gate electrode; NTFT; impurity; circuit) are not a substitute for the claims.

Accordingly, the overview below is derived from the specification and abstract, which describe the invention's contemplated scope. Treat it as a faithful description of the disclosed invention, not as verified claim language. Anyone needing the actual claims should pull the grant from USPTO PatentCenter or the Google Patents "Claims" tab directly.

Plain-language overview of the disclosed inventive subject matter

Core device (NTFT). An n-channel thin-film transistor in a semiconductor layer has three doped regions between/adjacent to the channel:

• First impurity region (n⁺) — the source/drain; high concentration (~1×10¹⁹–1×10²¹ atoms/cm³), low resistance.
• Second impurity region (n⁻) — a lightly doped, high-resistance "LDD" region that overlaps the gate electrode through the gate insulating film (the so-called GOLD structure). Because it is doped through a tapered sidewall of the gate electrode, its impurity concentration increases gradually from the channel toward the first region — a concentration gradient that mirrors the gate's taper profile. This is what gives hot-carrier resistance.
• Third impurity region (n⁻) — a lightly doped region that does not overlap the gate electrode (an offset region). This is the stated point of novelty over conventional GOLD, and the specification says it dramatically reduces off-current.

The "most important characteristic." Two (or more) NTFTs on the same substrate have different second-impurity-region lengths, chosen according to their operating voltages: the higher-voltage device gets the longer second impurity region. This lets a shift register (low voltage, speed-critical) and a buffer/level-shifter (high voltage, ruggedness-critical) be co-fabricated with individually optimized LDD overlap.

Gate electrode structure. Either (a) a laminate of a lower first gate electrode in contact with the gate insulating film — which carries the tapered sidewall, taper angle θ between 3° and 40° (preferably 5°–35°, best 8°–20°) — plus an overlying second gate electrode that is narrower in the channel-length direction; or (b) a single-layer tapered gate electrode. The taper is the process knob that sets the second-impurity-region length.

Manufacturing aspects. Sequential doping steps (ion doping / ion implantation): a first, high-acceleration (80–160 keV) phosphorous dose through the tapered gate forms the graded n⁻ second region; a resist mask then defines the third region and a second dose forms the n⁺ first regions. The resist mask can be positioned so the third impurity region appears only on the drain side (source-side LDD is described as a needless resistance penalty). Taper angle is controlled by ICP etch bias power density and CF₄/Cl₂ flow ratio (per the '917 figures 13–15).

Broader coverage. The specification expressly extends the disclosure to AM-LCDs with on-substrate driver and signal-processing circuits, to electroluminescence (EL) display panels (several embodiments), to CMOS circuits pairing the NTFT with a PTFT, to microprocessors/ASICs/D-A converters and portable-device high-frequency circuits, and to electronic equipment (FIGS. 11A–11F, 22A–22D, 23A–23B). It also mentions applicability to SOI structures (SIMOX, Smart-Cut, ELTRAN).

Litigation / CAFC 2026 check — no results

Searches targeting this patent number against Federal Circuit and PTAB material returned no case, docket, IPR, or appeal involving US 6,365,917. Consistent with that, the patent's record shows Expired – Lifetime with anticipated expiration 2019-11-16, so active 2026 enforcement litigation would be unexpected.

One caution on the search results: a Chinese-language litigation summary in my results prominently displays the figure "6,616,397" — that is a jury damages dollar amount in Orange Electronics v. Shenzhen Autel concerning a different US patent (8,031,064 C3). I am deliberately not treating that as US 6,365,917, and I have not auto-corrected any identifier.

I also could not locate an authoritative statement of the underlying priority document (e.g., a Japanese application number) or of the examiner/art unit for this patent in the material retrieved; those are genuinely unknown to me here rather than being facts I omitted.

I'll research litigation involving US patent 6365917.

Let me search more targeted litigation databases.

Result: No litigation found involving U.S. Patent No. 6,365,917

After searching litigation-focused sources (Justia federal dockets, CourtListener/Harvard CAP, PTAB/USPTO petition filings, Law360, and Federal Circuit opinions surfaced via search), I found no civil action, ITC investigation, or PTAB proceeding that names U.S. Patent No. 6,365,917 ("Semiconductor device," Yamazaki, Semiconductor Energy Laboratory Co., Ltd., filed Nov. 16, 1999; issued Apr. 2, 2002) as a patent-in-suit.

Because I found no case, I cannot provide plaintiff/defendant/jurisdiction/case number/filing date/outcome for any case — there is nothing to report on that template.

Important caution — do not conflate similarly numbered patents

My searches repeatedly returned SEL litigation that is not this patent. Per the strict rule, I am reporting these identifiers literally and explicitly distinguishing them:

None of the above is U.S. 6,365,917, so none should be reported as litigation of this patent.

Caveats on my confidence

• I could not directly query the Unified Patents litigation caselist portal in this session; I relied on web-indexed results from docket aggregators and court/agency documents. Unified Patents' own record for 6,365,917 is not confirmed here.
• Absence of evidence is not proof of absence. License negotiations, unasserted licensing campaigns, foreign (non-U.S.) proceedings, and settled/very old district-court suits that are poorly indexed could exist and not appear in these results.
• I have no high-confidence knowledge of any specific case asserting 6,365,917. I am stating that explicitly rather than inferring or constructing one.

Contextual notes (not litigation)

• 6,365,917 is a Semiconductor Energy Laboratory continuation-family member (its progeny includes US 6,949,767, US 7,564,059, and later applications per the Google Patents family listing), and its disclosure is cited as prior art in later patents (e.g., US 7,486,344; US 7,666,718; US 7,115,434) — citation as prior art is not litigation.
• Google Patents lists its legal status as "Expired – Lifetime," with anticipated expiration Nov. 16, 2019. Note that the PTAB/IDS document mentioning "U.S. Patent No. 7,139,591" and the "'591 patent" reexamination concerns 7,139,591, another different patent — not 6,365,917.

Bottom line: Based on the searches performed, no litigation is known involving U.S. Patent No. 6,365,917. If you need certainty, the authoritative confirmations would be (a) a direct Unified Patents caselist lookup filtered to 6365917, (b) PACER/RECAP docket searches, and (c) the USPTO Patent Center " litigation " / assignment records for that patent number.

I'll verify the structured PTAB block against live sources before finalizing.

Let me run a few more targeted checks before concluding.

PTAB / AIA Trial Proceedings — U.S. Patent No. 6,365,917

Canonical source used: the structured "PTAB proceedings on file" block in this prompt (USPTO Open Data Portal ingest). I re-verified against live sources because the block itself invites flagging proceedings ODP may not have indexed. No new proceedings surfaced. Details and near-misses below.

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Proceedings overview

Total AIA trial proceedings on U.S. 6,365,917: ZERO. There is no IPR, no PGR, and no CBM naming this patent — so there is no breakdown by status to give (no active proceedings, no claims invalidated, no claims sustained in a trial, no settlements, no institution denials). The defensive posture this produces for a defendant is the mirror image of "hardened": the patent was never tested at the Board, and it never needed to be, because it expired before any AIA trial became worthwhile. Per the record carried forward from the prior section, legal status is Expired – Lifetime with an anticipated expiration of 2019-11-16. It issued 2002-04-02, meaning the PGR window (9 months post-grant) closed in 2002-2003, long before PGR existed in practice, and CBM review (sunset for new petitions 2020-09-16) never applied to a TFT device patent. Inter partes review was the only live AIA tool, and no one used it.

The practical bottom line for a defendant today: this is not a "claims are canceled, ignore the demand" situation, and it is not a "hardened survivor" situation either. It is an expired-patent situation, which is a materially different and generally stronger defense than either.

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Proceeding-by-proceeding

There are no proceedings to report. I am not going to populate the per-proceeding template with invented docket numbers, panels, grounds, or FWDs.

Per the prior section's instruction to flag rather than fabricate: I could not find any proceeding number to report, and the structured data lists none. Every template field (Filed / Judge panel / Petition grounds / Institution decision / FWD / Settlement / Appeal) is therefore unknown to me because it does not exist, not because it was omitted.

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What I actually searched, and what it turned up instead

Searching PTAB-facing sources for this patent number returns Semiconductor Energy Laboratory proceedings on other patents and digitally adjacent-but-different patent numbers. Reporting these literally, per the no-auto-correction rule:

Absence-of-evidence caveat, stated plainly: ODP ingest lag, and imperfect indexing of PTAB filings for patents that expired in 2019, are both real. I did not directly query the P-TACTS/PTAB-E2E case-lookup UI by patent number in this session — I relied on the ODP block plus web-indexed PTAB documents. I have no high-confidence knowledge of any AIA trial on 6,365,917. Authoritative confirmation would be a P-TACTS case search on patent number 6365917 (the "Enter appearance as patent owner/respondent" flow accepts a patent number, per the P-TACTS filing documentation at https://ptacts.uspto.gov/ptacts/ui/home), and the ODP API trials endpoint.

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Strategic summary

Claim status. There is no claim-level PTAB adjudication of 6,365,917. No claim is canceled by the Board; no claim is sustained by the Board. Every claim is UNTESTED at the PTAB — which is a different thing from "valid," and different again from "invalid." For the claims themselves, the prior section's uncertainty flag stands and compounds here: I still do not have authoritative claim text. So I cannot even tell you which claim numbers a demand letter is likely to cite, let alone that any of them are dead.

Estoppel landscape. § 315(e)(2) estoppel is not triggered for anyone, because no IPR was instituted that could ripen into a final written decision. This cuts in the defendant's favor in one specific way: no prior-art ground has been "used up." Any § 102/§ 103 ground the defendant can find is still fully available to raise — in an IPR (if one were even viable, which it is not here) and in district court. There is no General Plastic multi-petition problem, no § 325(d) "same or substantially the same art" problem, and no SAS-era joinder complexity. The entire IPR toolkit is unspent.

Pattern signals. SEL is a prolific and sophisticated PTAB participant — the record above shows it on the receiving end of IPRs and inter partes reexams on its TFT/display families (7,923,311; 6,756,258) and it litigated those families hard (SEL v. Chi Mei Optoelectronics, N.D. Cal.; SEL v. Chimei Innolux, SACV12-0021-JST, C.D. Cal.), including on stay/estoppel questions. So the absence of an IPR on 6,365,917 is best read as disinterest, not as immunity. Candidly: a patent family this actively litigated, owned by a patent owner this experienced at the Board, would very likely have drawn an IPR if it had been worth asserting while it had any life left. It expired 2019-11-16. No defensive aggregator (Unified Patents or similar) appears anywhere in this chain — consistent with the prior section's finding that the Unified Patents caselist for this number could not be confirmed.

The bigger point. The single most important strategic fact is not a PTAB fact at all: the patent expired on 2019-11-16, and the Board itself has acknowledged that expired patents can be subject to IPR (https://ptacts.uspto.gov/ptacts/public-informations/petitions/1460091/download-documents?artifactId=NkDZDKdFC1TpulB674DeWTzf5IBo8wT1P-5dQq2e-ulqfG4XoekAJi0, discussing claim construction for expired patents subject to IPR). Expiration does not automatically bar an IPR petition — but it does eliminate the reason to file one, which is exactly the pattern the docket shows.

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Recommended next steps

If you are a defendant receiving a demand citing 6,365,917:

1. Lead with expiration, not with PTAB. Do not build a defense around IPR outcomes; there are none. Build it around the fact that the patent expired 2019-11-16 and that the ODP record carries the status "Expired – Lifetime." Consequence worth checking with your litigation counsel: a complaint filed today (2026-10-01) reaches back only six years under 35 U.S.C. § 286 — to 2020-10-01 — which is entirely after the expiration date. Practical upshot: there is no recoverable period of infringement to sue over. I flag that as a legal-analysis point for counsel, not as advice.
2. Verify the number on the face of the demand. Given that my searches repeatedly returned 7,923,311, 6,756,258, 6,327,617, and an unrelated "'917 patent," confirm that the demand letter is not citing a different SEL patent — a transposed or mis-typed number is a real risk in this family.
3. If the demand cites a live sibling, the analysis changes entirely. The prior section identified the same-family progeny as US 6,949,767 (from US 10/079,512) and US 7,564,059 (from US 11/234,382), plus applications 12/505,640 (US 2009/0315085 A1) and 13/298,469 (US 2012/0074418 A1). Those have different (and, for some, later) expiration and priority dates and would each need their own PTAB check — this memo covers only 6,365,917.
4. Document the absence. If the demand letter implies a "validated" or "litigated" patent, note that it was never before the Board and that no § 315(e)(2) estoppel attaches to it. Separately, the prior section found no district court or ITC action naming this patent either, so the whole assertion record for 6,365,917 is, as far as I can verify, empty.

If no PTAB activity exists, say so plainly — which is what I am doing. There is no FWD to link to and quote, because none was ever issued. I have deliberately not linked to the 7,923,311 or 6,756,258 petitions as if they were this patent's record; those are other patents by the same assignee and are included above only as evidence of what I searched and what I found instead.

Confidence: High that ODP lists no proceedings. Moderate-to-high that no AIA trial exists at all, subject to the P-TACTS/ODP indexing caveat stated above. Zero fabrication of proceeding numbers, panels, grounds, or dispositions.

I'll research the assignment record for US 6,365,917.

Note on a contradiction with the prior sections (flagged per instructions)

The prior summary and PTAB sections state, twice, that no authoritative claim text could be found. In the searches run for this assignment analysis, claim text for US 6,365,917 did surface — FreePatentsOnline's page for the patent returned the claim set (claims 1–32, including claim 19 reciting a first NTFT in a pixel region and a second NTFT in at least one of a level shifter, buffer, sampling, or pre-charge circuit). I am flagging this rather than silently correcting the record; the prior sections' uncertainty flag should be treated as superseded on that point. It does not change anything in the ownership analysis below.

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Inventors

Unusual-pattern check — no signal. There is exactly one inventor, and no co-inventor departures to track. The application was filed 1999-11-16 and the inventor→employer assignment was recorded 2000-02-09 — roughly three months post-filing, which is ordinary practice for a Japanese corporate filer recording an employee invention assignment during pendency, not a distress or fire-sale precursor. There is no evidence of inventor departure, and none should be inferred from a single-inventor, single-assignment record.

Caveat: I could not confirm the execution date of the assignment (only the recording date, 2000-02-09, is in the material I retrieved), so I cannot state a precise execution→recording lag. See the correspondence caveat in the timeline section.

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Original assignee

Semiconductor Energy Laboratory Co., Ltd. (SEL) — Atsugi-shi, Kanagawa-ken, Japan. Named as assignee on the face of the issued patent and named in the sole recorded assignment.

• Primary line of business: semiconductor/display R&D and intellectual-property licensing — TFT, active-matrix LCD, EL/OLED, and (later) oxide-semiconductor technologies. SEL is a research-and-licensing house with a very large patent estate, not a panel or consumer-device manufacturer.
• Did they ship a product embodying the claims? Not in the mass-market sense. SEL's TFT/AM-LCD technology is embodied in products built by its licensees (e.g., display makers such as Sharp and Samsung), and SEL has historically monetized this estate through licensing plus litigation. This distinction matters for the verdict below: SEL is an operating technology company and licensor, not a consumer-product vendor and not an NPE.
• Current status: Operating. SEL remains an active, publicly traded Japanese company (Tokyo Stock Exchange) with a continuing, high-volume patent filing program into the 2020s — evidence of that activity appears throughout the searches above (e.g., recent SEL-published applications and later SEL patents). No bankruptcy, dissolution, or acquisition of SEL was found in any source consulted.
• Litigation posture (context, not this patent): SEL is a known and aggressive enforcer of other patents in its portfolio — SEL v. Samsung Electronics, No. 96-1460-A (E.D. Va.), aff'd 204 F.3d 1368 (Fed. Cir. 2000), and SEL v. Chi Mei Optoelectronics, No. C 04-4675 MHP (N.D. Cal.). This is consistent with the prior sections: an operating-company/licensor enforcement model, and importantly it is not an NPE model, because SEL actually develops the technology it licenses.

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Assignment timeline

The Assignment Center / USPTO assignment record for US 6,365,917 contains exactly one recorded assignment — the original inventor-to-employer transfer. That is a finding in itself: there are no post-issuance assignments, no security interests, no mergers, no name changes, and no transfers to a third party. SEL still owns the patent.

• Executed: not confirmed / recorded 2000-02-09 — Reel/Frame: NOT RETRIEVED (see caveat below)
  • Conveyance: Assignment of assignors' interest ("ASSIGNMENT OF ASSIGNORS' INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: YAMAZAKI, SHUNPEI (sole inventor)
  • Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
  • Correspondent: not retrieved — I have no verifiable correspondent name, firm, or address for this reel/frame, and I will not invent one. Recurrence flag: cannot be assessed with a single-link chain and an unretrieved correspondent.
  • Context: Routine employee-inventor assignment to the employer during pendency. Not an acquisition, fire-sale, internal reorg, securitization, transfer-to-asserter, or defensive aggregation.

Caveat on the reel/frame — stated plainly

I could not confirm the reel/frame number, execution date, or recording correspondent for this patent within this session. I am not fabricating them. Two points of context that I deliberately do not treat as this patent's data:

• Espacenet INPADOC for US 6,492,659 ("Semiconductor device having single crystal grains with hydrogen and tapered gate insulation layer") shows an SEL assignment recorded 2000-10-04, effective 2000-09-11, assigning Yamazaki and Arai, REEL/FRAME 011215/0607. Different patent — the same inventor and same assignee, but not 6,365,917. Do not use that reel/frame here.
• Espacenet INPADOC for US 2010/0253902 A1 shows an SEL assignment, effective 2010-03-08, recorded 2010-03-25, REEL/FRAME 024137/0168. Also a different document.

What those two entries do evidence is the mechanics of SEL's recording practice: inventor→SEL assignments executed and recorded close together, indexed under "ASSIGNMENT OF ASSIGNORS INTEREST." That is consistent with, but not proof of, the reel/frame for 6,365,917. To get the actual reel/frame and correspondent, the authoritative lookup is the USPTO Assignment Center by patent number — https://assignmentcenter.uspto.gov/ (mirror index: https://assignment.uspto.gov/patent/index.html).

Note on the priority-link events in the Google Patents record (2002-02-22 "Priority to US 10/079,512"; 2005-09-26 "Priority to US 11/234,382"; 2009-07-20 "Priority to US 12/505,640"; 2011-11-17 "Priority to US 13/298,469"): these are continuation/divisional family lineage events, not assignments. A continuation does not transfer ownership. All four remain within the SEL chain as filings, and none should be read as a change of assignee.

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Timeline diagram

timeline
    title Ownership of US 6365917
    1998 : Priority date
    1999 : Application filed by Yamazaki
    2000 : Assigned to Semiconductor Energy Laboratory
    2002 : Patent issued to SEL
    2002 : Continuation family filings
    2019 : Patent expired lifetime

Every post-2000 node is an SEL-owned event. No third party ever appears in this chain.

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NPE / troll-pattern signals

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Verdict

Insufficient data (only the original assignment).

This is the verdict the evidence compels, and it is a clean version of it: the USPTO/Google Patents record for US 6,365,917 shows exactly one recorded transfer — the original inventor-to-employer assignment to Semiconductor Energy Laboratory Co., Ltd., recorded 2000-02-09 — and nothing after it. There is no shell entity, no known asserter, no cascade, no fire-sale, no privateering, and no defensive aggregator in the chain; the patent issued 2002-04-02 and expired 2019-11-16 with the original corporate assignee still on title. I could not retrieve the reel/frame or correspondent for that single record, so I state the finding at the level the evidence supports rather than dressing it with a fabricated frame number.

One residual caveat: the assignment data available to me was drawn from Google Patents legal events and indexed assignment material, not a direct USPTO Assignment Center query on patent number 6365917 (the tooling in this session did not return the Center's record page). Reel/frame and correspondent should be confirmed there. A zero-NPE-signal result plus a known litigious family owner is, on the prior sections' reasoning, better read as "the family was monetized on other members (7,923,311; 6,756,258) while this one expired quietly," not as a dormant assertion threat.

Verify at: https://assignmentcenter.uspto.gov/ — search patent number 6365917 (mirror: https://assignment.uspto.gov/patent/index.html).

I'll research the prior art citations for US 6,365,917. Let me start with several searches.

I need the front-page "References Cited" of US 6,365,917 specifically (not patents that cite it). Let me search further.

I found citation lists, but I need US 6,365,917's own front-page references. Let me dig deeper.

I was unable to complete additional searches (step limit reached), so I'll report exactly what the searches did and did not establish. Per the strict rule, I am not going to fabricate a front-page reference list I could not retrieve.

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Prior art analysis — US 6,365,917 B1 ("Semiconductor device," Yamazaki, SEL)

⚠️ Critical retrieval limitation (read first)

I could NOT retrieve the authoritative front-page "References Cited" (U.S. Patent Documents / Foreign Patent Documents) list of US 6,365,917 itself. This is the same class of gap flagged in the previously generated sections for the claims. Specifically:

• Searches for "US6365917 references cited / prior art" returned forward citations (patents that cite 6,365,917) and family-level citation lists, not 6,365,917's own front page.
• I also still do not have authoritative claim text, so I cannot key a § 102 analysis to specific claim numbers. Doing so would be fabrication. I therefore analyze against the disclosed inventive elements and state plainly where a claim mapping is unknown.
• I did not obtain an examiner/art-unit record or the cited NPL (non-patent literature) list for this patent.

Any reference list below is therefore provisional and provenance-labeled. The authoritative source is the grant PDF / PatentCenter "References Cited," or the Google Patents "Patent Citations" tab for US6365917 directly.

Legal frame used: priority 1998-11-25, filing 1999-11-16, grant 2002-04-02. Section 102 art must predate those dates (or qualify as § 102(e) art with an earlier effective filing).

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What the searches actually returned, and what each list really is

Bottom line on provenance: every 6,365,917-attributed item I found points at the patent (forward citation), not from it. I could not convert any of this into a verified "references cited by 6,365,917" list.

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Most relevant prior art I can actually support (candidates, not confirmed front-page citations)

Below are the references whose citations and dates I retrieved, each with a § 102 read keyed to the disclosed invention elements (not to fabricated claim numbers). Treat the "Cited by '917?" column honestly.

Group A — Seiko Epson TFT/LDD art (highest technical relevance)

A1. WO 1994/000882 A1 — Seiko Epson Corp.

• Title: Thin film transistor, solid-state device, display device, and method for manufacturing thin film transistor
• Publication: 1994-01-06 (family/priority associated with a 1992-06-24 filing)
• US family member: US 5,508,216 (per the EP 0 602 250 search-report annex I retrieved); also linked to JP 3173135 B2
• Description: Low-temperature polysilicon TFT with a lightly doped (LDD-type) low-concentration region between channel and source/drain — the archetypal GOLD/LDD TFT.
• § 102 read (element-level): Potentially anticipates a claim reciting merely "a low-concentration impurity region between the channel region and the source/drain region." It does not anticipate the two-element combination central to this disclosure (an overlapped graded second region plus a non-overlapped third region), nor the "different second-impurity-region lengths on the same substrate by operating voltage." More likely § 103 art.
• Cited by '917? Unconfirmed (appears in family-level list only).

A2. US 5,563,427 — Seiko Epson Corp.

• Title: Active matrix panel and manufacturing method including TFTs having variable impurity concentration levels
• Filing: 1993-02-10 — Grant: 1996-10-08
• Description: Active-matrix TFT array in which TFTs are given different impurity concentration levels — i.e., tailoring doping/region concentration per device. This is the single closest retrieved reference to the "different second-impurity-region lengths/concentrations according to operating voltage" concept.
• § 102 read (element-level): Strong § 102/§ 103 candidate against any claim reciting differently-doped/low-concentration regions on TFTs of a common substrate. It does not appear to teach the tapered-gate-through-doping mechanism (concentration gradient reflecting gate taper) that the '917 specification claims as its enhancement of the GOLD structure.
• Cited by '917? Unconfirmed (retrieved from the US 7,061,186 "Patent Citations" list).

A3. US 5,818,067 — LG Semicon Co., Ltd.

• Title: Thin film transistor and method for fabricating thereof
• Filing: 1993-05-20 — Grant: 1998-10-06
• § 102 read: Generic TFT/LDD structure art; anticipates at most a single low-concentration-region claim, not the dual second/third-region architecture.
• Cited by '917? Unconfirmed.

Group B — Japanese TFT/display art (family-level list)

Important caveat on Group B: these came from a "Family Cites Families" block, which aggregates citations across a patent family. I cannot confirm any of them appears on the 6,365,917 front page specifically. Also note that several (JP 3128939, JP 3173135, JP 3338481, JP 3292657, JP 3254335, JP 3834086) show 2001–2006 registration dates because they are Japanese B2 publications of earlier applications — the filing dates (1991–1995) control for prior-art purposes, and all predate 1998-11-25.

Group C — Co-pending SEL applications (potential § 102(e) art)

Both carry filing/priority of 1998-11-17, i.e., eight days before 6,365,917's 1998-11-25 priority date, and they are SEL/Yamazaki documents cited in the family:

• US 6,420,758 B1 — "Semiconductor device having an impurity region overlapping a gate electrode" (SEL). Textually near-identical subject matter to the '917 second impurity region.
• US 6,489,952 B1 — "Active matrix type semiconductor display device" (SEL).

§ 102(e) read: If either discloses the overlapped low-concentration region plus the non-overlapped region for TFTs on a common substrate, it is a serious § 102(e) / § 103 reference because its effective filing precedes the '917 priority date. This is the most strategically interesting group — and the one I could verify only as forward-cited siblings, not as front-page references of the '917.

Group D — Organic-EL art (relevant only to the EL embodiments, not the TFT claims)

The 38-item list on US 7,061,186 is dominated by Eastman Kodak organic-EL patents: US4356429, US4539507, US4720432, US4885211, US4769292, US4950950, US5047687, US5059862, US5059861, US5073446, US5061617, US5151629, US5294869, US5294870, plus JPS6290260A. These date 1980–1994. They are not prior art to the TFT/impurity-region claims; they would bear only on any EL-display claim, and only as § 102 background.

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Do-not-conflate list (identifiers that are NOT this patent's citations)

Per the no-auto-correction rule, these surfaced and I am explicitly not treating them as 6,365,917 references:

• US 6,327,617 — a transposition of 6,365,917 (Motorola reexam context). Different patent.
• US 5,543,636 — SEL's Insulated Gate Field Effect Transistor (the SEL v. Samsung '636 patent). Different patent.
• US 7,139,591, US 7,923,311, US 6,756,258, US 7,061,186 — other SEL patents; several are forward-citers of, not cited-by, the '917.
• The "'917 patent" appearing in a JDSU v. Fiber IPR decision is a different patent.

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Honest confidence statement

• High confidence: the lists above are correctly labeled as forward / family-level citations, and none is confirmed as a front-page reference of 6,365,917.
• Low-to-moderate confidence: that any specific Group A/B item appears on the 6,365,917 front page.
• Zero confidence: any claim-number-specific § 102 mapping — because I still lack authoritative claim text (consistent with the earlier sections' flag).
• Genuinely unknown to me: the examiner, art unit, and the NPL "Other Publications" list for this patent.

Recommended next steps to close the gap

1. Pull the grant PDF front page (patentimages.storage.googleapis.com/.../US6365917.pdf) and read the (56) References Cited block directly — this is the only way to get the true cited-art list.
2. Pull the Google Patents "Patent Citations" tab for US6365917 (the section headed "Patent Citations (N)") — distinct from "Cited By."
3. Retrieve the claims from PatentCenter so any § 102 mapping can cite real claim numbers.
4. Then re-run the § 102 analysis, prioritizing any reference that teaches both (a) a gate-overlapped low-concentration region and (b) a non-overlapped low-concentration region, on the same substrate with differing lengths by operating voltage — that three-element combination is the disclosure's stated point of novelty and is what any anticipation must meet.

I'll research the prior art of record for US 6,365,917 before building the §103 analysis.

Let me pull the front-page "References Cited" data and the closest GOLD/LDD prior art.

Let me try to recover the actual claim text and check a few more specific prior-art teachings.

Obviousness Analysis — U.S. Patent No. 6,365,917 B1 under 35 U.S.C. § 103

Builds on the earlier sections. Bibliographic data, the abstract, the litigation check (no case found), and the PTAB check (no AIA trial; expired 2019‑11‑16) are not repeated here. The claim‑text uncertainty flag from those sections still governs this analysis and is re‑flagged below because it materially limits confidence.

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0. Two threshold caveats before any §103 conclusion

(a) I still do not have the literal granted claims. The authoritative full text supplied to me is truncated mid‑sentence in Embodiment Mode 1 ("Anisotropic etching of the first conduct…"), and my searches did not return the "What is claimed is" section. Therefore this is an obviousness analysis of the disclosed inventive subject matter, mapped to the features the specification itself calls out as inventive. It is not a claim‑by‑claim rejection. If the granted claims carry limitations not visible in the specification's summary (unlikely, but possible), the analysis would need to be re‑run. This is the single largest source of uncertainty in this memo.

(b) The governing law is pre‑AIA § 103. Application 09/440,633 was filed 1999‑11‑16 with a claimed priority of 1998‑11‑25 — both before the AIA's 2013‑03‑16 changeover. So: pre‑AIA § 102(a)/(b)/(e)/(g) for prior‑art status, pre‑AIA § 103(a), and the Graham v. John Deere framework as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). No IPR‑style AIA §103 analysis applies (and per the prior section, no IPR ever existed).

Critical date. Taking the §102(b) measuring date conservatively as one year before the U.S. filing date — 1998‑11‑16 — every reference in the primary combination below predates it and is therefore statutory‑bar art. (I use the filing date rather than the foreign priority date deliberately; it is the more defensible baseline and the references clear it comfortably.)

POSITA. A poly‑Si TFT process‑integration engineer (B.S./M.S. in EE, materials, or applied physics) with 3–5 years in low‑temperature poly‑Si AMLCD backplane development as of late 1998: familiar with LDD/GOLD device design, ion doping/ion implantation through masking layers, sidewall‑spacer and tapered‑gate formation, RIE/ICP etching, and the standard trade‑offs between off‑current, on‑current hot‑carrier degradation, and breakdown voltage.

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1. The features to be tested (proxy for the claims)

Derived from the '917 specification's own framing of what is novel and from the abstract. Each row is a candidate claim element.

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2. Prior art of record and of the field

References appearing in the '917 specification itself (these are the applicant's own admissions, citable as "Applicant's own specification"): the specification states — "Conventionally, it is known that hot carrier resistance increases with a so‑called GOLD structure (gate‑drain overlapped LDD). This technique has begun to be applied to TFTs, but the problem that with a conventional GOLD structure the off current increases … has been unreasonably ignored." And it states that the second (overlapping) region's length is set by the film thickness of the first conductive film / its taper, and that the third (non‑overlapping) region's length "is controlled by the placement of the resist mask." Those are admissions that the mechanisms were known and that the applicant's contribution is the selection and co‑optimization of them.

One prior‑art section I could not obtain. The task instructs me to use "the results from the Prior Art section of this page." I was not furnished a discrete prior‑art block, and my retrieval of the Google Patents page returned the specification, classifications, and "cited by" family — not a quotable "Prior Art" or "References Cited" list. I therefore assembled the table above from (i) references that appear verbatim in the '917 family's own identification‑of‑references lists (Hatano; Choi & Han TED 1998), (ii) references cited on the face of related SEL cases (the US 5,426,327 / 5,770,506 / 5,851,861 / 5,993,614 / 6,033,990 cluster; the JP 07‑202210 / 07‑226518 / 08‑274336 / 09‑229600 / 11‑307777 cluster), and (iii) a field search. I flag this substitution explicitly rather than presenting it as the page's own prior‑art tab.

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3. Grounds of rejection

3.1 Ground I — Hatano (PA‑1) in view of the sidewall‑spacer/offset LDD art (PA‑8, PA‑9): E1 + E2 + E4

Coverage. PA‑1 discloses an n‑channel poly‑Si TFT with a channel, n⁺ source/drain, and an n⁻ region overlapping the gate (Sa‑GOLD) — E1 and E2. PA‑8 and PA‑9 disclose the complementary structure: a low‑concentration drain region that is not under the gate (FID / field‑plated / offset), taught for off‑current and breakdown‑voltage control — E4.

Motivation. This is the strongest and most straightforward ground. The motivation is supplied by the applicant's own specification: the '917 spec concedes that GOLD's off‑current penalty "has been unreasonably ignored." Once the problem is identified — GOLD buys hot‑carrier/on‑current reliability but costs off‑current — the two‑region solution (an overlapping Lov for field relief plus a non‑overlapping Loff for off‑current suppression) is a predictable, catalogued recombination of two known elements, each performing its own known function — the classic KSR "arrangement of old elements" with "a predictable result." A POSITA building an AMLCD pixel/buffer TFT in 1998 would have had every reason to put a known offset/LDD extension next to a known GOLD region.

Expected applicant rebuttal. That Hatano's structure is a sidewall GOLD and that simultaneously forming an offset region would have required an extra mask and been considered wasteful. That is a process‑economy argument, not a technical teaching‑away — and the '917 specification itself resolves it, explaining that the third region's length "is controlled by the placement of the resist mask," i.e., the very mask step the art already used.

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3.2 Ground II — Hatano (PA‑1) or Choi & Han (PA‑2/PA‑3) in view of the T‑shaped/hat‑gate art (PA‑6, PA‑7): E6 (laminated gate; narrower upper electrode)

Coverage. PA‑1 and PA‑2/PA‑3 establish GOLD poly‑Si TFTs; their n⁻ overlap in Hatano is created by poly‑Si sidewalls. PA‑6 (Hisamoto, June 1997) and PA‑7 (Lin, Jan. 1998) independently disclose a self‑aligned T‑shaped gate in which a lower, wider gate portion overhangs a narrower upper conductor — structurally the "first gate electrode wider than the second gate electrode" limitation of E6.

Motivation. KSR makes this combination comfortable: (i) both fields — T‑shaped/T‑gate MOSFETs and GOLD poly‑Si TFTs — are the same art of controlling the drain‑edge field with a gate‑overlap geometry; (ii) PA‑1 itself is a Hitachi Central Research Lab paper, and PA‑6 is likewise a Hitachi self‑aligned T‑gate paper — a POSITA reading the Hitachi literature would encounter both; (iii) the predictable result — using a monolithic overhanging lower gate to define the n⁻ overlap instead of a deposited poly sidewall — is exactly the substitution one of skill would make to remove the sidewall‑deposition and sidewall‑selectivity steps. A "hat"/"T" gate for defining LDD by self‑alignment was a known design idiom.

Corroboration of crowdedness: PA‑12 (U.S. 6,250,138, SEL, 1998‑12‑18) claims a multilayer gate electrode with impurity regions overlapping therewith — filed three weeks after the '917 priority date. That near‑simultaneity is not itself prior art against '917, but it is strong evidence that the multilayer‑gate/overlapping‑region combination was at the ordinary skill level, not beyond it.

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3.3 Ground III — Hatano/Choi & Han in view of dopant‑through‑tapered‑gate art: E3 (graded concentration in the second region)

Coverage. E3 requires that the second impurity region's concentration increase gradually from the channel to the n⁺ region, expressly because the dopant passes through the tapered gate edge whose thickness varies.

Motivation — and this is largely a §103 inherency‑plus‑predictability argument, not a reference‑based one. Ion implantation/ion doping through a masking layer of position‑dependent thickness produces a position‑dependent transmitted dose and projected range. Any POSITA who simply ran the disclosed process — i.e., doped through a tapered gate edge at 80–160 keV, as the '917 spec instructs — would have obtained the graded profile as an inherent, inevitable consequence of the physics. Where the result of a process is the necessary and inherent consequence of the process steps, the discovery of that consequence is not a patentable advance. The '917 specification itself says as much: the gradient "reflects the inclination (change in film thickness of the tapered portion)."

The art also supplies the recognition: PA‑13's background (and the Choi/Han GOLD literature more generally) describes forming the n⁻ region "using the side wall of the gate to provide a taper to the density of the impurity of the drain junction." Additionally, the general tapered‑gate/sidewall‑erosion etching art (PA‑5) taught that a tapered conductor edge is a controllable dose‑shadowing mask.

Flag on PA‑5. I do not have a specific, verified pre‑1998 patent or paper number that squarely claims "tapered gate → graded LDD concentration" as its invention. I am asserting (a) the physics (dose through variable‑thickness absorber varies — indisputable), (b) the existence of tapered‑gate‑edge art generally (indisputable), and (c) the applicant's own admission that the gradient "reflects the inclination." I am not asserting a specific reference I have not verified. This is the weakest reference‑identification link in the memo, though I judge the legal conclusion (that E3 would not have been non‑obvious) to be sound on the inherency theory alone.

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3.4 Ground IV — Any of the above in view of the per‑circuit / mixed‑voltage TFT‑layout art: E5 (different second‑impurity‑region lengths on one substrate, longer for the higher‑voltage device)

This is the element the specification calls "the most important characteristic," so it deserves the most attention — and it is, in my assessment, the most vulnerable element.

Coverage and motivation. E5 is a design‑optimization claim over a known device, and KSR squarely addresses it: "when a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one," and "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill."

The specific motivating facts a POSITA had in 1998:

1. The circuit‑by‑circuit voltage requirement was textbook. PA‑9 (Huang, 1990) is devoted to "field‑plated high‑voltage TFTs and their application to low‑voltage operation" — i.e., the art had already sorted TFTs into high‑voltage and low‑voltage classes and engineered their drain regions accordingly. In an AMLCD, the pixel/buffer TFT sees ~14–20 V and the shift register sees ~3.3–5 V; that split is stated in the '917 specification as a given of the art, not as a discovery.
2. The mechanism was a monotone engineering knob. Given that (a) GOLD/or Lov length governs hot‑carrier/breakdown robustness and (b) Loff length governs off‑current, the incremental step of lengthening Lov on the high‑voltage device and shortening it on the high‑speed device is optimization of a recognized, predictable parameter with a recognized direction of benefit. No new physics, no new structure, no unexpected property.
3. Doing it on one substrate was routine. The '917 specification's own §"Manufacturing" narrative describes nothing exotic: the taper angle is set by the ICP etch (bias power density, CF₄/Cl₂ ratio), and the Loff length is set by resist‑mask placement. Forming two devices with two taper angles on one substrate requires either a second masking/etch step or a mask that varies the etch bias — a mundane integration choice. The specification concedes the process is one of "free combination" of known techniques.
4. The claim's own numbers are a range of optimality. E5 as disclosed is realized simply by selecting Lov from three disclosed working bands (shift register ~0.1–3.0 µm; level shifter/buffer ~1.5–4.0 µm; pixel ~0.5–3.0 µm). "A patent composed of several elements is not proved obvious merely by demonstrating that each of its elements was, independently, known" — but here the elements are not merely individually known; the direction of the adjustment (higher V → longer overlap) is the necessary consequence of the function each region performs.

Corroboration. SEL's own later U.S. 7,462,866 (filed Mar. 17, 2000, i.e., ~4 months after '917) describes as the "known technique" an electro‑optical device in which (i) a part/all of the driver n‑channel TFT's LDD region overlaps the gate, and (ii) the pixel TFT's LDD region does not overlap the gate, with an offset region in between. That is E2 + E4 + a per‑circuit distinction, presented as background art by the same assignee. That document is not §102 art against '917 — I am citing it only as strong evidence that the per‑circuit differentiation of overlapping and non‑overlapping low‑concentration regions was the ordinary‑skill baseline in this exact organization, at this exact time.

The residual non‑obviousness argument an applicant/demand‑defendant would press. E5 is arguably not the same dimension the art varied. The art (and SEL's own 7,462,866 background) differentiated circuits by whether an LDD region overlaps the gate (Lov vs. Loff — a categorical difference), whereas E5 requires differentiating circuits by the length of the overlapping region while both devices can retain overlapping and non‑overlapping regions — a continuous difference. If the granted claims are directed solely to that length difference combined with the graded‑taper second region, the applicant has a colorable argument that the specific combination was not squarely taught. I assess this argument as weak‑to‑moderate: KSR ("mere obviousness to try"; "design incentive") and In re Aller's range‑optimization principle (where the prior art teaches the parameter and the claimed range is an optimization producing no unexpected result) both cut against it, and the specification's own disclosure gives no unexpected‑result data — only the assertion that the longer overlap suits higher voltage.

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3.5 Ground V — SEL's own sibling filings (PA‑10, PA‑11) as §102(e) art

PA‑10 (U.S. 6,420,758 / 6,489,952 / 6,909,114), priority 1998‑11‑17, is the most factually aggressive reference in the set, because it predates the '917 priority date by eight days and comes from the same assignee, describing impurity regions overlapping a gate electrode on a substrate carrying both pixel and driver TFTs.

Three cautions, all of which I flag rather than resolve:

1. §102(e) requires the reference's filing date to precede the applicant's date of invention, not merely the priority date. Invention date is unknown to me; absent a §1.131 affidavit or a foreign priority that reaches back, a POSITA would presume the '917 invention date ≲ 1998‑11‑25, which PA‑10's 1998‑11‑17 filing date precedes. But this is a fact question I cannot settle from the record I retrieved.
2. Pre‑AIA §103(c) may disqualify PA‑10 for obviousness purposes. All are commonly owned by Semiconductor Energy Laboratory Co., Ltd. at the time the '917 invention was made. Under pre‑AIA §103(c) (as amended, and applicable to applications filed on or after Nov. 29, 1999 — a date question I flag), commonly‑owned §102(e)/(f)/(g) art is disqualified from use in a §103 rejection, though it remains available under §102. Given both the issue date and the statute's effective‑date boundaries, I do not have high confidence on whether §103(c) applies to this application, and I state that as a genuine gap rather than papering over it.
3. PA‑11 (U.S. 6,466,843) I cannot date to before 1998; its GOLD‑via‑silicon‑sidewall teaching is substantively on point but its §102(e) date is unverified.

Bottom line for Ground V: useful as corroboration of the state of the art and as a §102 threat, but I would not build a §103 rejection on it without confirming both the effective §102(e) dates and the §103(c) posture.

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3.6 Ground VI — Downstream use/apparatus elements (E8)

Claims to an AM‑LCD having the recited TFTs in the pixel region and/or driver circuits, to an EL panel, and to electronic equipment would be obvious over any of Grounds I–IV plus the admitted, ubiquitous commercial context (the '917 specification's own background states that poly‑Si TFT AMLCDs "have been in the spotlight in recent years"). Where the novel device element is obvious, apparatus claims reciting its conventional incorporation into a known product add nothing patentable. SOI‑substrate variants (SIMOX, Smart‑Cut, ELTRAN) would likewise have been obvious substitutions of a known substrate, and I note the specification itself recites them without any asserted unexpected result.

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4. KSR motivation synthesis (the "why combine" answer, consolidated)

For each pairing above, one or more KSR rationales applies:

No teaching away. I found no reference in this set that teaches away from combining a gate‑overlapping low‑concentration region with a gate‑non‑overlapping low‑concentration region, nor from varying overlap length by circuit voltage. The closest thing to a "teach‑away" is Hatano's reliance on sidewall geometry, which is a preference of implementation, not a disparagement of the claimed alternative — insufficient under In re Fulton/DePuy.

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5. Where a validity challenge is weakest — and where non‑obviousness could survive

Stated candidly, because a one‑sided memo is useless:

1. E3 (the graded concentration within the second region) is legally soft but reference‑thin. I could not verify a pre‑1998 reference that affirmatively discloses "taper the gate edge → graded LDD concentration." I rely on inherency plus the applicant's own admission. If a challenger needs a documentary reference for the gradient, this is the gap.
2. E5 is a design‑choice claim. If the granted claims recite only the two different overlap lengths (without the graded taper, without the drain‑side‑only Loff, and without specific structural geometry), they are vulnerable to an art‑based "optimization of a known parameter" rejection. If instead the granted claims bundle the graded taper + the laminated gate + the per‑circuit length difference into a single structure with the disclosed numerical ranges, the combination is narrower and a non‑obviousness argument gains traction — though the specification supplies no comparative or unexpected‑results data to support it, which is a serious defect for rebutting a KSR‑style rejection.
3. The missing claim text is the decisive unknown. I cannot tell whether the granted claims are narrow structural claims (which could survive) or broad device claims (which I expect would not). Per the earlier sections' standing flag: I do not have authoritative claim text, and I am not reconstructing it.

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6. Confidence and limitations

Two things I did not do and will not pretend to have done: (1) I did not obtain the literal granted claims of 6,365,917, so this is not a claim‑by‑claim rejection chart; and (2) I did not receive a discrete "Prior Art" block for this page, so the reference set above is one I assembled and sourced, not one quoted from that tab. If the user can supply either the claims or that prior‑art list, the mapping in §1 and the grounds in §3 can be tightened into a formal rejection format.