US 6302504

I'll search for this patent number as requested.

Let me check for litigation/docket activity and claim details.

Let me try to retrieve the claim text directly.

Search scope and confidence notes

I ran searches against Google Patents (which mirrors USPTO full-text/assignment data), Justia Patents, and Espacenet/INPADOC, and a targeted search for CAFC 2026 docket activity. I do not have direct, live access to USPTO PatentCenter, PTAB (PTACTS) dockets, or the CAFC docket system in this session — so the USPTO-side data below is corroborated from the mirrors above, not from a native USPTO query. I flag that explicitly.

US 6,302,504 B1 — bibliographic record

Source: https://patents.google.com/patent/US6302504/en ; https://patents.justia.com/patent/[6302504](/patent/6302504) ; Espacenet/INPADOC record for US6302504 (B1).

Abstract (as published)

"Upon executing printing by latching an input digital image signal temporarily stored in a shift register (502) by a latch circuit (501), and energizing and driving a heater (401) using a power transistor (410) using an nMOSFET on the basis of the latched image signal, a voltage converter (111) boosts a voltage representing the ON state of the latched digital signal, and applies the boosted voltage to the power transistor (410)."

Plain-language overview of the independent claims

The specification is written as a set of four related inventions (basic gate-voltage boosting; process-variation correction; pMOS power transistor with a boosted-gate inverter; and a high-breakdown-voltage CMOS inverter at the power-transistor input). The claims track these themes. The independent claims I could positively identify are 1, 11, 31, 43, 55, and 60, with 64 being a further dependent claim.

Claim 1 — the base "recording head" claim. A recording head with (a) a heater (the electro-thermal print element), (b) a MOS power transistor that drives the heater, (c) a MOS logic circuit that drives the power transistor, and (d) a voltage converter that takes the logic circuit's output signal, converts it to a larger voltage amplitude, and applies the boosted signal to the gate electrode of the power transistor. In plain terms: the 0 V/5 V logic signal is level-shifted upward so the FET is driven harder and can supply the ~100–200 mA needed to fire the ink. (Some claim-1-dependent wording, e.g. claim 48, confirms claim 1 recites "said MOS power transistor" and "said MOS logic circuit.")

Claim 11 — parallel independent recording-head claim. Same heater / MOS power transistor / MOS logic circuit / voltage-converter architecture, but distinguished from claim 1 in scope, and it is the claim that claim 40 says may be realized with the logic circuit and voltage converter "formed by an nMOS process" (vs. claim 39, which attaches the CMOS-process option to claim 31). Plain-language: the same boosted-gate drive scheme, framed for an all-nMOS implementation. Uncertainty: I could retrieve the verbatim text of claims 31–64 but not the verbatim text of claims 1–30; my characterization of the exact differentiating limitation between claim 1 and claim 11 is therefore inferential.

Claim 31 — recording head with a process-variation correction circuit. Heater + MOS power transistor + MOS logic circuit + the voltage converter, plus a correction circuit that compensates for characteristic variations of the power transistor. The specification explains the mechanism: gate-length (L) process variation of ±0.5–1.0 µm changes FET drive current; the correction circuit lowers the boosted gate voltage when L comes out small and raises it when L comes out large, so heater energy stays near design value (the spec works a numeric example: 16 V → ~12.5 V). Dependent claims 35–38 add the specific implementation — a polysilicon resistor plus a third nMOS transistor, and optionally a source-follower buffer (fourth nMOS transistor + third resistor) so the divider sees a light load and burns less power. Claims 41–42 add the ink-jet and heat-energy-limiting options.

Claim 43 — recording apparatus. An apparatus (printer) comprising the recording head of claim 31. Dependent claims 44–47 add: n-type MOSFET power transistor; converter placed between the FET gate and the latch output; converter built as first resistor + first nMOS transistor + CMOS inverter (pMOS + second nMOS) whose gates tie between the resistor and the drain; and a carriage carrying the head.

Claim 55 — second recording apparatus claim, comprising the recording head of claim 48. This is the pMOS-power-transistor branch: claim 48 (which depends on claim 1) recites that the power transistor is a pMOS transistor, that the voltage converter's inverter includes at least one nMOS transistor which boosts the received print signal and drives the pMOS gate, and that the pMOS transistor and heater are series-connected between the heater power supply line and ground, from the supply-line side. Dependent claims 49–54 add: offset-type transistors, drive from the predetermined power supply line, formation on a p-type silicon substrate, a resistor between the nMOS transistor and the supply line, ink-jet use, and ink contacting the heater through an electrical insulating film. The point of the pMOS arrangement (per the spec) is that when the power transistor is OFF the heater/wiring node sits at ground potential like the conductive ink, so no field stresses the protective insulating film — a reliability/lifetime benefit.

Claim 60 — ink-jet head cartridge, comprising the recording head of claim 1 and an ink tank (claims 61–63 add n-type MOSFET and further cartridge limitations).

Claim 64 — a recording head according to claim 1 further comprising a carriage for carrying the head. (Note: this appears as a late-numbered dependent claim on claim 1, and its "recording head … comprising a carriage" phrasing is unusual; I have not independently verified it against the USPTO printed claim set.)

Subject matter across all independents: a thermal ink-jet (bubble-jet) print head formed on a single semiconductor substrate, where the logic/MOS process is reused for the high-current power devices and a boosting stage supplies the gate overdrive; variations cover (i) voltage-amplitude conversion, (ii) process-variation correction of the boosted gate voltage, (iii) pMOS power device with grounded heater node for insulating-film longevity, and (iv) high-breakdown-voltage (offset/lightly-doped-drain) pMOS/nMOS elements and a simultaneously formed diode temperature sensor (see FIGS. 16A–18B, 24, 25A–25B).

Litigation / 2026 CAFC docket check

• A search specifically for "6302504" combined with CAFC / Court of Appeals for the Federal Circuit / 2026 docket returned no results. On the evidence available to me, I found no pending or recent CAFC appeal, IPR, or PTAB proceeding naming US 6,302,504.
• The only post-grant paper trail I found is the 2002 Certificate of Correction and routine maintenance-fee events in INPADOC (fee years recorded, final expiry 2017-06-25). No reissue, reexamination, or litigation record surfaced.
• Important caveat: my search tools did not return a native CAFC docket or PTACTS document for this number, and the absence of a hit is not affirmative proof that no proceeding exists. If you need a definitive litigation/PTAB answer, this should be re-run against the CAFC CM/ECF and USPTO PTAB APIs directly, or against a dedicated litigation database (e.g., Docket Alarm / LexMachina) — Docket Alarm did surface in results for other patents but not for this number.

Items I am explicitly not certain about

1. Verbatim text of claims 1–30 — I only retrieved claims 31–64 in full. My summary of independent claims 1 and 11 is reconstructed from dependent-claim back-references and the specification, not confirmed claim language.
2. The exact boundary between claim 1 and claim 11 — both appear to recite heater + MOS power transistor + MOS logic circuit + voltage converter; I could not determine the precise differentiating limitation.
3. Claim 64's exact wording/status — retrieved from a secondary mirror.
4. Any non-US litigation or 2026 CAFC activity — not verifiable with the tools available; the null result should be treated as "not found," not "does not exist."

I have deliberately not auto-corrected any identifier: the patent is US 6,302,504 B1, application 08/882,035, and the priority documents are cited exactly as the records render them (including "JP H10-006515 A" for JP 8-166089).

I'll research litigation involving US patent 6302504. Let me search multiple litigation sources.

Initial searches returned unrelated results. Let me refine with more targeted queries.

No litigation results yet. Let me search the specialized litigation portals directly.

Litigation Search Results for U.S. Patent No. 6,302,504

Summary finding: No litigation involving U.S. Patent No. 6,302,504 was identified in any of the sources searched.

I searched for the specific patent number 6,302,504 (and the literal string "6302504") across general litigation-report aggregators and patent-status databases, and all results returned either the patent's own bibliographic/INPADOC record or unrelated patents and trademarks bearing similar numbers. I found no docket, complaint, CAFC appeal, PTAB proceeding, or PACER entry naming US 6,302,504 as an asserted patent.

What the searches did return (and why these are NOT litigation on '504)

I want to be explicit about the false positives so you can see they were excluded:

• US 6,502,135 / 7,490,151 / 7,418,504 / 7,921,211 — VirnetX v. Apple (E.D. Tex., e.g., case 6:12-cv-00855). These appear repeatedly in keyword hits because they contain the digits "504." They are different patents belonging to VirnetX, not Canon, and are unrelated to US 6,302,504.
• US 6,144,702 — Acacia Media Technologies v. New Destiny Internet Group (N.D. Cal., 2004) and Teleshuttle v. Microsoft (N.D. Cal. 5:04-cv-02927). Unrelated patents that surfaced on partial-number matches.
• BR DI 6302504-3 — a Brazilian industrial design registration (Millie Confeccões Indústria e Comércio Ltda). Same digits, entirely different right and jurisdiction — not the U.S. patent.
• An EPA document listing "6302504" as a chemical product code (Smooth-On). Irrelevant.

Patent status context (from the INPADOC/Google Patents record)

• Patent: US 6,302,504 B1 — "Recording head and recording apparatus using the same"
• Assignee/Owner: Canon Inc. (Canon Kabushiki Kaisha)
• Application: US 08/882,035; Filed: 1997-06-25; Granted: 2001-10-16
• Priority: 1996-06-26 (JP 8-166089 and three further JP filings)
• Status: Expired – Lifetime; anticipated expiration 2017-06-25 (maintenance fees paid through the year-12 payment in 2013; no later fee events)
• The INPADOC legal-status record shows only routine post-grant events (certificate of correction 2002, ownership/assignment 1998, maintenance-fee payments) — no adversarial or litigation events.

Important caveats on this conclusion

• Scope limitation: My tool set for this task was general web search. I was unable to open the Unified Patents litigation caselist (portal.unifiedpatents.com/litigation) or query PACER/CAFC dockets directly, so this is not a substitute for a full docket-database or paid litigation-search run (e.g., Docket Navigator, LexisNexis, Westlaw, or Unified Patents' full portal).
• Age and nature of the patent: As a 1996-priority, 2017-expired component-level inkjet printhead patent, it was never a likely candidate for standalone assertion campaigns, and no such activity surfaced.
• Most likely conclusion: Based on the available evidence, no public litigation is known to have been filed on U.S. Patent No. 6,302,504.

If you need a definitive answer, I'd recommend running the exact patent number through Docket Navigator or the Unified Patents portal with a logged-in account, since those index complaints and PTAB filings the open web does not reliably expose.

I'll verify the canonical "no proceedings" finding with targeted searches before drafting.

Proceedings overview

Total AIA trial proceedings on file for US 6,302,504: 0. The canonical source for this analysis — the structured "PTAB proceedings on file" block derived from the USPTO Open Data Portal/PTAB API — returns no IPR, PGR, or CBM proceeding naming this patent as the challenged patent, which means there is no breakdown to report: 0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denials, 0 Federal Circuit appeals. The bottom-line defensive posture is therefore not "the patent has been hardened by surviving IPRs," but rather "the patent is PTAB-untested — and it is also expired (2017-06-25) and never publicly asserted, so a demand letter citing it is a historical-damages collection attempt at best, not a live-threat patent."

Proceedings to enumerate

None — no AIA trial proceeding has ever been instituted or even filed against US 6,302,504

• Type: N/A
• Filed: N/A
• Status: N/A — no proceeding exists in the structured data
• Judge panel: N/A
• Petition grounds: N/A — no petition on file, so no § 102 / § 103 / § 112 grounds to report
• Institution decision: N/A
• Final Written Decision: N/A — no FWD exists, therefore no claims have been canceled, confirmed, or adjudicated by the Board. I will not manufacture a claim-level disposition that does not exist.
• Settlement / termination: N/A
• Appeal: N/A — no FWD to appeal; no CAFC docket naming this patent was found
• Defensive value: A defendant facing a demand on the '504 cannot point to a canceled claim, but it does not need to. The patent expired 2017-06-25 (anticipated expiration per the INPADOC legal-status record; maintenance fees paid through the year-12 payment in 2013), so there is no injunctive exposure and no post-2017 royalty base, and 35 U.S.C. § 286's six-year recovery bar forecloses suit on the remaining pre-expiration window.

How I verified the negative finding, and the false positives I excluded

Searches for the literal strings "6302504" and "6,302,504" in a PTAB context returned only unrelated patents and proceedings that share the digits "-504" with this patent. These are not US 6,302,504 and must not be cited as though they were:

• IPR2017-00054 involved US 8,236,504 B2 (instituted on Kordunsky and Li/Heffelfinger/Miller) — a different patent, different patent owner, different technology.
• IPR2019-01621 / ROKU v. Universal Electronics cited US 7,821,504 in an inter partes reexamination file history — a universal remote-control patent.
• IPR2016-00093 challenged US 5,805,504 (Micron memory device) — again a different patent.
• IPR2022-01541 is Canon as petitioner against US 7,152,951 (Slingshot Printing) — Canon's own printhead patent in a different family, and Canon is the attacker there, not the patent owner.
• The Brazilian registration BR DI 6302504-3 (Millie Confeccões Indústria e Comércio Ltda) is an industrial design, not this US patent.

Caveats: my tool set for this task is general web search plus the structured ODP block; I could not log into Docket Navigator, LexisNexis, Westlaw, or run a logged-in PTAB E2E / Unified Patents portal query. The structural data is authoritative here and is consistent with every search performed. For a belt-and-suspenders check, run the patent number "6302504" as a challenged-patent filter in USPTO PTAB E2E and search the Federal Circuit docket for the patent number via CourtListener.

Strategic summary

Claim-by-claim status of US 6,302,504. There is no PTAB adjudication of any claim — nothing is canceled and nothing has been "sustained" by the Board. Every claim as issued remains UNTESTED at the PTAB. The only post-grant alteration to the patent is a Certificate of Correction dated 2002-07-02 (INPADOC event code CC), which is a ministerial correction, not a claim-scoping amendment. The subject matter the specification describes — gate voltage boosters (Figs. 5, 14), the polysilicon-resistor/nMOS correction circuit (Fig. 7), the source-follower buffer (Fig. 9), the high-breakdown-voltage offset pMOS inverter (Fig. 16A), and the pMOS-power-transistor/ground-return arrangement (Fig. 24) — is all reflected in claims that no tribunal has construed.

Estoppel landscape. Because no IPR ever reached an FWD, § 315(e)(2) estoppel has never attached against anyone. There is no petitioner barred from raising § 102/§ 103 grounds in a district court, no § 325(e)(2) bar, and no defensive-aggregator chain (no Unified Patents or similar entity appears anywhere in the record). In theory, every prior-art and § 112 ground remains available to a defendant. In practice this is academic: with the patent expired since 2017-06-25, there is no accused ongoing conduct to enjoin and § 286 limits recovery to the six years preceding a complaint — a window that closed with the patent's own expiration.

Pattern signals. No petitioner has filed even once against the '504, so there is no "repeat petitioner" signal, and there is no CAFC appeal. Note the asymmetry for context: Canon has used the PTAB offensively as a petitioner (e.g., IPR2022-01541 against the '951 patent), and Canon patents in the inkjet space have been challenged by others (the Avigilon/Fortress and Slingshot disputes), but none of that activity touches the '504. That is unsurprising — this is a 1996-priority, component-level printhead drive-circuit patent that was never asserted (consistent with the litigation finding of no litigation on file) and expired in 2017.

One legal-eligibility note for completeness: the '504's effective filing predates March 16, 2013, so PGR was never available against it; and CBM review required a "covered business method" patent — a heater-driver/MOSFET circuit is a technological invention, so CBM was a poor fit even before the transitional program sunset on 2020-09-16. IPR was the one realistic AIA vehicle, and it was never used.

Recommended next steps

• If you are a defendant and someone is citing the '504: there is no FWD to link and no canceled claim to point to — instead, attack the assertion directly on timing. Plead the patent's expiration on 2017-06-25 (Google Patents legal-status record: US6302504B1) and 35 U.S.C. § 286's six-year recovery bar. A demand letter served in 2026 can, at the outside, reach only pre-expiration conduct from mid-2020 onward — a period that post-dates the patent's death entirely.
• If you are the patent owner or evaluating acquisition: recognize that the absence of PTAB activity is not evidence of strength here. It correlates with (a) expiration, (b) a component-level inkjet drive-circuit claim set, and (c) no assertion history. There is no "hardened by IPR" story to tell.
• If active proceedings were pending — they are not — you would track the institution-decision deadline (3 months from a § 315(b) completion or the patent owner's preliminary response), the 1-year statutory FWD deadline under § 316(a)(11), and the oral-hearing notice. None of those milestones exist for this patent.
• To make this conclusion airtight: run "6302504" as a challenged-patent query in PTAB E2E, check the USPTO PTAB Decisions archive, and search the patent number on CourtListener for any CAFC appeal. Based on all evidence available, those searches will return nothing, and I would report that as the finding rather than infer activity that isn't there.

I'll research the assignment record for US 6302504. Let me run several targeted searches.

Let me dig deeper for the correspondent of record and any additional assignment records.

Let me make a couple more attempts to pin down the correspondent of record and confirm no later transfers.

Assignment & Ownership Analysis — U.S. Patent No. 6,302,504

Patent: US 6,302,504 B1 — Recording head and recording apparatus using the same
Application: US 08/882,035 · Filed 1997-06-25 · Granted 2001-10-16
Priority: 1996-06-26 (JP 8-166089) plus JP 8-197241, JP 8-231081, JP 8-300417
Assignee of record: Canon Kabushiki Kaisha (Canon Inc.)

Sourcing note: The USPTO Assignment Center / Patent Assignment Search interface is not directly reachable by the tools available for this task. The assignment data below is grounded in the INPADOC legal-status record for US6302504 (Espacenet) and the Google Patents legal-events record, which surface the same USPTO reel/frame entries. I flag explicitly where a field (notably the correspondent of record) could not be verified rather than guessing at it.

Inventors

All seven named inventors are Canon personnel on the ink-jet recording-head development team, and all signed the inventor→Canon assignment (Reel 009095/Frame 0272):

Pattern assessment — no red flags. This is a normal large-company engineering team, not a group with a history of spinning out to an independent vehicle. There is no evidence of inventor departure-then-fire-sale: the same inventors continued on later Canon printhead patents well after the 1996 priority filing date (Imanaka, for example, is named on Canon head patents issued in 2012–2013). No inventor is named as an assignor in any downstream transfer, and none appears as a principal of a licensing entity in the record.

Original assignee

Canon Kabushiki Kaisha (Canon Inc.), incorporated in Japan, Tokyo (Ohta-ku headquarters).

• Line of business: Global manufacturer of imaging, optical, and printing products. This patent is a component-level ink-jet printhead substrate (heater + nMOS power-transistor + gate-voltage-booster driver circuitry) — squarely within Canon's core Bubble Jet print-head business.
• Product embodying the claims: Yes. The specification describes the recording head 810 as a manufactured, installable bubble-jet recording head with an integral/disposable ink tank (FIGS. 1–4), and the recorder (ink-jet recording apparatus 900) built around it. Canon’s Bubble Jet inkjet printers and the printheads used in them read directly on the described subject matter. This is an operating-company product patent, not a paper right.
• Current status: Canon Inc. is an operating, publicly traded company (TYO: 7751), not acquired, dissolved, or in bankruptcy. Its status vis-à-vis this patent is that the right expired for failure to reach its full statutory term (anticipated expiration 2017-06-25), i.e., the patent simply ran out while Canon owned it.

Assignment timeline

The record contains one assignment. Everything else on the patent’s legal-status timeline is issuance, a certificate of correction, and maintenance-fee payments.

• 1997-11-17 → 1997-12-04 (executed, latest signing date) / recorded 1998-04-07 — Reel 009095 / Frame 0272
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST — inventor-to-employer)
  • Assignor: Imanaka, Yoshiyuki; Kasamoto, Masami; Furukawa, Tatsuo; Mori, Toshihiro; Ozaki, Teruo; Watanabe, Hidenori; Mochizuki, Muga (all seven)
  • Assignee: Canon Kabushiki Kaisha, Japan
  • Correspondent: Not verified. Neither the INPADOC record nor the Google Patents legal-events entry exposes the correspondent/recording-attorney field for Reel 009095/0272, and I could not open the Assignment Center record directly. I decline to name a correspondent rather than fabricate one. (For context: this is a routine 1998 corporate-recording entry, so the "repeat NPE correspondent" tell is not meaningfully testable absent the underlying document.)
  • Context: Ordinary intrafirm acquisition — the inventors assigned their rights to their employer Canon. Execution dates (Nov–Dec 1997) fall ~5 months after the 1997-06-25 U.S. filing, which is standard for a Japanese-origin application filed on a foreign-priority basis, then perfected by recording the inventor assignment.

No subsequent assignment appears anywhere in the chain. There is no second reel/frame transferring the patent out of Canon — not to a Canon IP holding subsidiary, not to a licensing LLC, and not to any aggregator. The only post-1998 events are:

• 2001-09-27 — STCF: information on status, patent granted (legal-status entry)
• 2002-07-02 — CC: Certificate of Correction
• 2002-12-03 — FEPP: fee-payment procedure, payor number assigned, entity status large entity
• 2005-03-23 — FPAY: maintenance fee, year 4
• 2009-03-18 — FPAY: maintenance fee, year 8
• 2013-03-06 — FPAY: maintenance fee, year 12
• 2017-06-25 — anticipated expiration reached.

Timeline diagram

timeline
    title Ownership of US 6302504
    1996 : Priority filing in Japan
    1997 : US application filed
         : Inventors assign rights to Canon
    1998 : Assignment recorded at USPTO
    2001 : Patent issued
    2002 : Certificate of Correction
    2013 : Year 12 maintenance fee paid
    2017 : Patent expires

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No assignment to any LLC/Trust. The sole recorded conveyance (Reel 009095/0272) is inventor→Canon Kabushiki Kaisha. No "IP / Patents / Holdings / Ventures" entity ever appears as assignee.

2. Known asserter in the chain — NOT PRESENT. Neither the current nor any prior assignee matches any public NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Round Rock, etc.). The only assignee, Canon, is an operating manufacturer. No RPX/Unified asserter-directory hit.

3. Repeat correspondent across the chain — UNCLEAR (not assessable). There is only a single assignment, and its correspondent field could not be retrieved. A "repeat correspondent" finding requires recurrence across ≥2 links; with one link and no correspondent data, no call can be made. This is a data gap, not a negative finding.

4. Cascading transfers — NOT PRESENT. Zero chained LLC transfers, ruling out the <24-month multi-hop pattern by definition.

5. Pre-litigation transfer — NOT PRESENT. Consistent with the prior litigation section (no suit ever filed on US 6,302,504), there is no assignment within 6 months of an infringement action — there is no action at all.

6. Bankruptcy fire-sale — NOT PRESENT. Canon Inc. did not file Chapter 7/11, and no patent-sale proceeding touched this right. Fees were paid voluntarily through year 12.

7. Privateering — NOT PRESENT. No transfer to an NPE that asserts on Canon’s behalf; nothing in the chain leaves Canon at all.

8. Defensive aggregator — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. The patent was never sold, so it was never "neutralized" by transfer — it simply expired in Canon’s hands in 2017.

Verdict

Insufficient data — but read this as a clean-history insufficient-data case, not as an evidentiary blank.

Per the rubric, "Insufficient data (no records, or only the original assignment)" is the applicable bucket: the only recorded link is the original inventor→Canon Kabushiki Kaisha conveyance, Reel 009095/Frame 0272, recorded 1998-04-07 (executed 1997-11-17 to 1997-12-04). There is no second reel/frame, and none of the eight NPE signals is present with concrete evidence. The chain — grounded in Reel 009095/0272 plus the maintenance-fee entries of 2005-03-23, 2009-03-18, and 2013-03-06, and the 2017-06-25 expiration — shows a Canon-owned operating-company patent that was never conveyed, never asserted (per the prior litigation section), and simply lapsed at term. Because the sole owner is an operating manufacturer and no downstream transfer exists, an NPE classification is affirmatively unsupported rather than merely unproven.

Verification link: USPTO Patent Assignment Search — search patent number 6302504 (also accessible at https://assignmentcenter.uspto.gov/). Confirm the single entry at Reel 009095 / Frame 0272 and the absence of any later reel — and, if obtainable, capture the correspondent field for 009095/0272, which is the one field this analysis could not verify.

I'll research the prior art citations for US Patent 6,302,504, starting with its USPTO record and cited references.

Let me retrieve the front-page "References Cited" listing for US 6,302,504 from the patent's PDF and USPTO full-text.

Let me pull the Justia and FreePatentsOnline records for US 6,302,504, which typically list the front-page "References Cited."

Sourcing note and scope

I was able to retrieve the authoritative full text of US 6,302,504 (Google Patents, https://patents.google.com/patent/US6302504/en; Espacenet bibliographic record https://be.espacenet.com/publicationDetails/biblio?CC=US&NR=[6302504B1](/patent/6302504B1)) and the claims (Espacenet claims view). However, I was not able to complete retrieval of the patent's front-page "References Cited" list (the examiner-cited U.S./foreign patent documents that appear on the printed cover page and in the USPTO full-text "Referenced Cited" field) before my search-step budget was exhausted. I will therefore be explicit about what is verified vs. not:

• Verified (authoritative): the prior-art references cited within the specification body of US 6,302,504. These are quoted from the patent's own text.
• Not verified: the complete cover-page list of examiner-cited U.S. patent references and foreign patent documents. I flag this gap explicitly rather than reconstruct it from memory.

Per operating rules, I interpret every identifier literally and do not auto-correct. Where the '504 text itself appears to deviate from a related Canon patent's citation, I flag it rather than silently fix it.

1. The '504 patent's own identifiers (context, not prior art)

The four JP priority applications (family members JPH106515A, JP3372768B2, JP3332745B2, JP3327791B2) are the patent's own priority documents — not prior art and cannot anticipate it. I list them only to avoid their mis-identification as prior art.

2. Prior-art references cited inside the '504 specification (verified)

The specification body expressly cites the following. These are the only references I can presently verify as citations of the '504.

(a) Japanese Patent Laid-Open No. 5-185594

• Full citation: JP H05-185594 A (Japanese Patent Laid-Open No. 5-185594), published 1993 (Heisei 5; ~1993-07-27).
• How cited: "…electro-thermal conversion elements (heaters) and a driving circuit therefor are formed on a single substrate using the semiconductor process technique, as disclosed in, e.g., Japanese Patent Laid-Open No. 5-185594."
• Description: Discloses the on-substrate integration of electro-thermal conversion elements (heaters) with their driving circuitry in an ink-jet recording head — i.e., the "heater + integrated drive circuit on one substrate" architecture.
• §102 relevance: This is the closest of the verified references to the preamble environment of the independent claims (heater + power transistor + logic/drive circuit on a substrate). It is the reference the '504 applicants themselves acknowledged as the starting point. Based on the characterization given in the '504 text, it does not appear to disclose the claimed voltage converter (a first resistor + first nMOS transistor + CMOS inverter of pMOS/nMOS that boosts the logic-level signal and applies the boosted voltage to the power-transistor gate), nor the diode-sensor/correction-circuit subject matter of dependent claims. Asserted anticipation: none of the independent claims (claim 1; independent claims 16/17 characterized in the Espacenet claims view) on the record available. Its role is §103 background, not §102 anticipation. (Full text of JP 5-185594 should be confirmed directly.)

(b) Japanese Patent Laid-Open No. 54-51834

• Full citation: JP S54-51834 A (Japanese Patent Laid-Open No. 54-51834), published 1979 (Showa 54; ~1979-04-23).
• How cited: Listed together with DOLS 2843064 as a "liquid-jet printing method" that derives the ejection driving force by applying heat energy to the liquid.
• Description: Thermal (bubble-jet-type) liquid-ejection print method in which heat energy applied to liquid produces a state change/abrupt volume increase that ejects a droplet from an orifice.
• §102 relevance: General method-level background for the thermal ink-jet environment. Discloses no MOS power transistor, no gate-voltage conversion/boosting, no CMOS-inverter booster, no diode sensor. Asserted anticipation: none of the claims of the '504 on the record available.
• Literal-citation flag (do not auto-correct): The '504 text cites "54-51834." A related Canon patent in the same family (US 6,168,251, also Imanaka et al.) lists the foreign document "54-51837." I report both literally and do not harmonize them; one or the other may be a typographical variant. This is exactly the kind of discrepancy the strict rule requires me to surface rather than fix.

(c) DOLS No. 2843064

• Full citation: DOLS No. 2843064 (German Offenlegungsschrift / DE 28 43 064), published 1979 (~April 1979). In US 6,168,251 the same document appears as "28 43 064 … 4/1979 (DE)."
• How cited: "…the liquid-jet printing method disclosed in DOLS No. 2843064 is very effectively applied to a so-called drop-on-demand printing method, and can easily realize a full-line type, high-density, multi-orifice recording head."
• Description: Foundational bubble-jet / drop-on-demand liquid-ejection disclosure (heat-energy-driven droplet formation; full-line, high-density, multi-orifice head).
• §102 relevance: Background to the drop-on-demand, high-density multi-orifice head environment. No teaching of the claimed voltage-conversion/gate-boosting circuitry, the CMOS-inverter booster, or the diode sensor. Asserted anticipation: none of the '504 claims on the record available.

(d) U.S. Pat. No. 4,463,359 — Ayata et al.

• Full citation: U.S. Patent No. 4,463,359, Ayata et al. (Canon), issued 1984-07-31; title relates to a liquid-jet recording process/apparatus.
• How cited: "…signals disclosed in U.S. Pat. Nos. 4,463,359 and 4,345,262 are suitable."
• Description: Driving-signal/pulse conditions for thermal liquid-jet (bubble-jet) recording.
• §102 relevance: Pertains to the drive-signal waveform for ejection, not to MOS-power-transistor gate-voltage conversion. It concerns the ink-ejection driving pulse, not the booster architecture. Asserted anticipation: none of the '504 claims on the record available. Relevant, if at all, as §103 background on driving signals.

(e) U.S. Pat. No. 4,345,262 — Shirato et al.

• Full citation: U.S. Patent No. 4,345,262, Shirato et al., issued 1982-08-17.
• How cited: Same sentence as (d) — suitable driving signals.
• Description: Liquid-jet recording method/apparatus; drive-signal conditions for thermal ejection.
• §102 relevance: Same as (d); drive-condition art, not gate-boost/voltage-converter art. Asserted anticipation: none of the '504 claims on the record available.

(f) U.S. Pat. No. 4,313,124 — Hara

• Full citation: U.S. Patent No. 4,313,124, Hara (Canon), issued 1982-01-26.
• How cited: "…further excellent printing can be performed by using the conditions described in U.S. Pat. No. 4,313,124 of the invention which relates to the temperature rise rate of the heat acting surface."
• Description: Relates to the temperature-rise rate of the heat-acting surface in thermal liquid-jet recording.
• §102 relevance: Thermal-condition art for the ejection surface; unrelated to power-transistor drive/gate boosting. Asserted anticipation: none of the '504 claims on the record available.

3. §102 anticipation — consolidated view

Mapping the verified references against the '504 claim structure (independent claim 1 = heater / MOS power transistor in series with the heater / logic circuit / voltage converter comprising a first resistor + a first nMOS transistor + a CMOS inverter of a first pMOS and second nMOS; dependent claims add power-supply/voltage-divider, source-follower, correction-circuit, polysilicon-resistor, and diode-sensor (pnpn) features; the Espacenet claims view shows a separate independent family around the diode-sensor subject matter):

Bottom line: Every reference I was able to verify as cited in the '504 is foundational/background thermal ink-jet art (methods, head integration, and drive/temperature conditions). On the record available, none of them discloses the point of novelty of the '504 — the MOS power transistor whose gate is driven by a boosted voltage from a CMOS-inverter-based voltage converter (and the related correction-circuit and diode-sensor dependent subject matter) — so none anticipates the independent claims under §102. Their proper role, if any, is §103 obviousness background, not §102 anticipation. I am not treating any of them as anticipatory.

4. Important clarification — forward citations are NOT prior art

My searches surfaced US 6,302,504 appearing in the "Referenced Cited"/"Patent References Cited" lists of later patents — e.g., US 10,471,713 (Canon inkjet print head), US 8,608,276, US 8,740,350 (Kasai et al.), and others. This means those later patents cite the '504 as prior art to them; it does not mean those later patents are prior art to the '504. I deliberately exclude them from the anticipation analysis. You should not treat any post-2001 document as prior art to a 1996/1997-priority patent.

5. Explicit gaps and recommended next steps

Because I could not open the '504's cover-page "References Cited" field or the patentimages front page within this session:

1. Unverified: the examiner-cited U.S. patent references and foreign patent documents printed on the '504 cover page. These are the standard USPTO "References Cited" set and may include MOS-driver / gate-boosting art not discussed above. I will not guess at them.
2. To close the gap, retrieve from authoritative sources:
   • Google Patents → US6302504B1 → "References Cited" section (expand U.S. Patent Documents, Foreign Patent Documents, Other Publications), and the "Cited By" section for forward citations;
   • USPTO Patent Center / Patent Full-Text (patft) → US 6,302,504 → "Referenced Cited";
   • the granted patent PDF front page (patentimages PDF) for the printed "(56) References Cited."
3. Also verify the full disclosure of JP 5-185594 (the applicants' own acknowledged starting art) to confirm whether it contains any gate-voltage-boost teaching; the '504 text characterizes it only as on-substrate heater + drive circuitry.

Caveat on my tooling: my available tool was general web search; I could not query PACER/PAIR or the patentimages PDF directly after the step cap. The verified citations above are drawn from the authoritative full text supplied; the cover-page citation list remains to be confirmed.

If you can supply the '504 PDF front page (or paste its "(56) References Cited" block), I will complete the per-reference full-citation / date / description / §102-claim mapping for the examiner-cited set — including a strict-literal reading of each patent number without auto-correction.

I'll research the claims and the prior-art references cited on this patent's page before performing the § 103 analysis.

I have the claim set structure. Let me retrieve the full claims and the patent's citation/prior-art list.

Obviousness Analysis — U.S. Patent No. 6,302,504 B1 under 35 U.S.C. § 103

Patent: US 6,302,504 B1, "Recording head and recording apparatus using the same"
Assignee: Canon K.K. (Canon Inc.)
Application: US 08/882,035, filed 1997‑06‑25; granted 2001‑10‑16
Priority: 1996‑06‑26 (JP 8‑166089), plus JP 8‑197241 (1996‑07‑26), JP 8‑231081 (1996‑08‑30), JP 8‑300417 (1996‑11‑12)
Source of record: https://patents.google.com/patent/[US6302504B1](/patent/US6302504B1)/en ; claim text cross‑checked against Espacenet (https://be.espacenet.com/publicationDetails/claims?CC=US&NR=[6302504B1](/patent/6302504B1)&KC=B1&FT=D&ND=6&date=20011016&DB=EPODOC&locale=de_BE)

0. Scope, and two caveats you should hold in mind

Caveat 1 — What I could and could not retrieve from "the Prior Art section." The fetched Google Patents page supplies (a) a metadata field "Prior art keywords: recording head, transistor, voltage, resistor, nmos transistor," and (b) the prior‑art documents cited in the description. The fetched text did not include the itemized "Patent Citations" table (i.e., the examiner/applicant citation list), and I was step‑limited before I could retrieve it. So my prior‑art universe below is limited to:

Caveat 2 — Claim set is only partially retrieved. Espacenet returned claims 1–37 in fragmentary form; the numbering and dependency of claims 7–18 is inferred, and the fetched text stops mid‑claim 37. I flag where that matters.

Claim groups I could reconstruct:

• Group A — Claim 1 (independent, head): heater for a print element; MOS power transistor in electrical series with the heater; MOS logic circuit for driving it; and a voltage converter that converts the amplitude of the logic‑circuit output signal to a higher amplitude and applies it to the gate of the MOS power transistor.
• Group B — Claims 2–6 (dependent on 1): latch circuit storing image data; voltage converter placed between the gate of the n‑type MOSFET and the latch output; voltage converter = first resistor + first nMOS transistor (drain to the resistor) + CMOS inverter of first pMOS and second nMOS whose gates are connected between the first resistor and the drain; ink‑jet/heat‑energy element.
• Group C — Claim 16 and dependents (17–20, 21–25) (independent, head and apparatus): the voltage‑converter inverter uses an nMOS and a pMOS element with low‑concentration (lightly‑doped) regions formed in their drains — i.e., the offset/LDD high‑breakdown‑voltage structure — and claim 17 adds a diode temperature sensor of pnpn structure built from the heavily‑doped p‑type region (drain/source of the first pMOS), the lightly‑doped n‑type region (drain of the second nMOS), the p‑type region and the n‑type substrate. Claims 21–25 are the apparatus counterpart (n‑type MOSFET, converter between gate and latch output, the resistor/nMOS/CMOS‑inverter converter, carriage).
• Group D — Claims 26–28 (dependent on 1): first power‑supply line for the heater, second for the converter; a voltage‑dividing circuit deriving the second supply from the first; the divider includes a source‑follower.
• Group E — Claims 29–30: ink‑jet head; apparatus using the head of claim 1.
• Group F — Claims 31–37 (dependent on 1): a correction circuit correcting characteristic variation of the MOS power transistor; cause of variation = gate‑length variation in the semiconductor process; the correction suppresses drain‑current drift by controlling the gate voltage; lowers gate voltage when L < design, raises it when L > design; correction circuit = second resistor (polysilicon) + third nMOS; plus a source‑follower of a fourth nMOS and a third resistor with specified node connections.

1. Level of ordinary skill (Graham factor 1)

For a 1996‑06‑26 priority date in this field, a person of ordinary skill in the art ("PHOSITA") would hold a B.S. in electrical engineering (or applied physics) with roughly 2–4 years of experience designing integrated thermal ink‑jet print‑head driver ICs, or an M.S. with 1–2 years of such experience. Critically, that skill set is exactly the intersection the specification itself assumes: MOS device physics (the drain‑current equation the patent quotes), CMOS logic design, and thin‑film/print‑head integration. The PHOSITA would also be familiar with the standard analog design vocabulary of level shifting / gate boosting, offset‑drain (LDD) high‑voltage transistors, resistor‑ratio voltage dividers, and source‑follower buffers.

2. The core technical problem, taken from the patent's own admissions

The specification concedes nearly all of the factual predicate needed for a § 103 case:

1. The 5 V ceiling. "In the conventional CMOS logic circuit, a digital signal which has 0 V/5 V as its Low/Hi level is normally used… the output from the latch circuit 501 shown in FIG. 12 does not exceed 5 V when its signal level is 'Hi'. Hence, a high voltage of 5 V or higher cannot be applied as the gate voltage of the power transistor."
2. Why that is bad. "if the gate voltage (VG) is raised, the maximum value of the current (drain‑source current: IDS) that can be supplied increases accordingly, and the operation point of the drain voltage … lowers. More specifically, the drivability of the nMOS transistor is improved as the gate voltage (VG) is higher." The patent writes this as IDS = (W/L)·μn·COX[(VG−VTH)·VDS − ½VDS²].
3. Why the industry wanted it fixed. Cheaper process: FIG. 12 replaces Darlington npn devices with nMOSFETs so "the power transistors can be formed using the same process (CMOS process) as that of the logic circuit"; plus the admitted desire to shrink transistor area and raise electro‑thermal efficiency by lowering VOP.

That is a textbook "the prior art teaches away from nothing but instead supplies the express reason to make the change" posture. Under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), an express statement of the problem in the art is itself a strong motivation.

3. Combination-by-combination analysis

Combination 1 — Claim 1: JP 5‑185594 + the admitted FIG. 12 head + a known gate‑voltage booster (e.g., FIG. 23's booster or any level shifter)

Motivation (KSR rationales (C), (D), (E)): (i) the express problem in the art — a 5 V logic swing under‑exploits nMOS current capability; (ii) the predictable result — a higher VG reduces the ohmic (triode‑region) drop VOP across the power transistor and therefore increases the energy delivered to the heater and reduces heat wasted in the transistor; (iii) the known technique — gate boosting/level shifting is a known technique used to improve a similar device in the same way. Under KSR, "a court must ask whether the improvement is more than the predictable use of prior art elements according to their established functions." Boosting a gate drive to increase MOS drive current is precisely such a predictable use.

For the dependent limitations of claims 2–5 (latch circuit; converter at the latch output; converter = resistor + nMOS + CMOS inverter of a pMOS and an nMOS), the specific resistor‑plus‑inverter topology is a conventional inverting level shifter / pull‑up‑resistor inverter — the kind of circuit that appears on essentially every page of a contemporaneous CMOS IC textbook and in print‑head driver patents of the early 1990s. Selecting it as the "voltage converter" of claim 1 is a routine design choice among a finite number of well‑known level‑shifter topologies (resistor‑load inverter, current‑mirror, cross‑coupled latch). This is the KSR "obvious to try with a finite number of predictable solutions" rationale.

Claim 6/29/30 (ink‑jet; heat‑energy element; apparatus) are met by DOLS 2843064 and JP 54‑51834 directly, and the apparatus claim 30 by the carriage/scanning architecture shown in the patent's own admitted FIG. 1 and by the prior‑art literature on serial‑scan ink‑jet printers.

Assessment: Claim 1, and claims 2–6 and 29–30, are prima facie obvious over JP 5‑185594 in view of the admitted nMOS power‑transistor head and the well‑known gate‑boosting/level‑shift technique.

Combination 2 — Claims 16–18 (offset / lightly‑doped drain CMOS inverter that can withstand the heater voltage) + claim 17 (pnpn diode sensor)

This is the "high‑breakdown‑voltage" invention. Its factual foundation is unusually weak for patentability, because the patent admits the offset/LDD structure itself is known for the power transistor:

• "in order to assure such breakdown voltage, it is a common practice to form an n⁻ type region in the drain region (offset type MOS transistor), as shown in FIG. 21B."
• FIGS. 21B/21C/21D are admitted cross‑sections of the offset nMOS power transistor and the ordinary CMOS logic nMOS/pMOS.
• FIG. 23's admitted booster likewise uses an offset nMOS transistor 411.

The claim 16 advance is therefore not the offset structure per se, but its application to the pMOS and nMOS devices of the boosting inverter so that the inverter can run off the ~25 V heater rail. The specification states the motivation for the skilled worker in explicit terms: the conventional pMOS breakdown voltage is only "about 10 to 14 V," so sharing the heater supply "is difficult in practice," and adding a separate supply "leads to an increase in circuit scale in the recording apparatus as a whole, resulting in an increase in cost."

Motivation: economy of power supplies (no second/third supply, no step‑down, no drift with the number of simultaneously fired heaters). Reason is KSR rationale (D)/(E): applying a known breakdown‑voltage enhancement technique (adding a lightly‑doped offset region in the drain) to the analogous devices of the inverter, with the predictable result of raising their breakdown voltage, is the "predictable use of prior art elements according to their established functions." The only residual question is whether the specific side‑by‑side use of the same lightly‑doped p⁻ region (offset pMOS of FIG. 17A, formed "deeper than the n⁻‑type impurity layer 212 and shallower than an n‑type substrate region 203") involves a process‑integration insight beyond the ordinary — that is where Canon's 1990s process know‑how is doing the real work, but the claim as drafted is a structural recitation of a known offset transistor family.

Claim 17 (the pnpn diode temperature sensor formed from the pMOS source/drain p⁺ region, the nMOS drain n⁻ region, the p‑type region and the n‑type substrate) is the strongest candidate for non‑obviousness in this group, because it claims a specific parasitically‑formed device exploiting the new offset pMOS's own layers and, per the specification, yields an "npnp structure … completely isolated from the p‑type substrate, thereby eliminating the influence of a parasitic transistor and realizing a series connection of diode sensors." Whether that is obvious turns on whether the object of the substitution (a temperature sensor for the head, described as conventional at FIG. 22 and in the admitted FIG. 19 item 715) would have suggested to the PHOSITA taking the sensor "for free" from the new offset structure. A reasonable examiner would assert that recognizing an available parasitic pnpn in a newly available layered structure and using it as a diode sensor is at least obvious to try; a reasonable patentee would respond that the low‑concentration anode selection to hit a target temperature coefficient is an unexpected‑results argument. This one is genuinely close and would likely have required a full KSR‑style record.

Combination 3 — Claims 26–28 (dual supply lines; voltage‑divider generating the booster supply; source‑follower in the divider)

The specification supplies the motivation itself: "adding a power supply for the gate voltage boosters 111 leads to an increase in circuit scale in the recording apparatus as a whole, resulting in an increase in cost," hence "an arrangement for voltage‑dividing the heater power supply voltage … may be added." Claims 27–28 (voltage‑dividing circuit; source‑follower) recite resistor voltage dividers and source‑follower buffers — the two most elementary analog building blocks there are (the admitted FIG. 6 uses resistors 132/133 with an nMOS source follower). Deriving a low‑voltage rail from a high‑voltage rail by resistive division and buffering it is a classic "predictable use of prior art elements," with the only real limitation being the buffer‑loading rationale the patent itself states ("a voltage drop caused by a current that flows when the nMOS transistor 113 … is turned on can be absorbed"). Assessment: obvious.

Combination 4 — Claims 31–37 (the gate‑length variation correction circuit) — the closest call

This group is the most defensible, and it is the group most likely to have generated the examination difficulty. However, the § 103 case against it is coherent:

1. The problem is conceded to be notorious. "the gate length (L) of an nMOS transistor suffers process variations of a maximum of ±0.5 to ±1.0 µm with respect to its design value. Such process variations depend on the exposure condition and etching condition, and drift considerably among manufacturing lots and among wafers." The patent even names the cause (mirror projection aligner, ±1.0 µm). A known, quantified, systemic problem is KSR motivation par excellence.
2. Portions of claims 31–33 are purely functional. Claim 31 ("a correction circuit for correcting a characteristic variation"), claim 32 (the cause is gate‑length variation) and claim 33 ("suppresses a drift of a drain current … by controlling a gate voltage … to compensate for the characteristic variation") recite a result, not a mechanism, and are vulnerable under In re Schreiber/In re Swinehart‑style reasoning if the result was achievable by any known bias‑compensation means.
3. The implementation is ratio‑matching. Claims 35–36 (a second resistor, preferably polysilicon, plus a third nMOS) implement the compensation by tracking: because the polysilicon width of the resistor and the poly gate lengths of the power transistors vary together on the same wafer ("if the polysilicon width of a certain portion of a wafer is 1 µm smaller than the design value, the polysilicon widths of other portions are similarly expected to be 1 µm smaller"), a simple divider automatically moves the gate voltage in the right direction. Ratio‑matching a poly resistor to a poly gate, and using a resistor divider to bias a gate, is a standard analog‑design technique with an established function.
4. The result is strictly computable, not unexpected. The specification's worked example — 24 V heater rail, 16 V booster rail, 1:2 resistor:ON‑resistance ratio, 4 µm → 3 µm shift giving ≈12.5 V and a net driving‑force change of "about 0.998 times" — reads like a verification of a designed relationship rather than the discovery of a surprising one. Where the claimed benefit is predictable from first principles (the patent literally derives it from equation (1)), the KSR "predictable results" rationale applies.
5. Direction of control (claim 34) — lower VG when L shrinks, raise VG when L grows — is the only direction that can reduce the drift given IDS ∝ (W/L)(VG−VTH)·VDS; there is no second, plausible alternative. KSR: "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious."

Counter‑arguments a patentee would press (secondary considerations): (a) the specific numeric result — a ±25% process‑induced drive change squeezed to ≈0.2% without any measurement or trimming step — is a strong, quantitatively demonstrated technical effect of a purely topological fix and supports non‑obviousness; (b) the "no extra power supply, no external trimming, no monitoring pad" character of the solution avoids the sensor/feedback costs the prior art would otherwise impose; (c) whether the prior art specifically taught to drive the gate voltage of the power transistor itself — as opposed to compensating heater energy, or adjusting pulse width, or trimming resistors after measurement — matters. Establishing (c) would require the examiner to find a reference teaching process‑tracking bias of a print‑head power transistor; absent such a reference, claims 33–37 could well survive a § 103 challenge, whereas claims 31–32 remain vulnerable as functional recitations of a known problem.

Assessment: Claims 31–34 are weakly supported and probably obvious over the admitted problem statement plus routine bias‑compensation knowledge; claims 35–37 (the polysilicon‑resistor/third‑nMOS/source‑follower implementation with the specific node connections) are the strongest claims in the patent and are the ones I would expect to have been the actual basis for allowance — though even they rest on a well‑known matching technique.

4. Statement of the combined rejections as an examiner would frame them

1. Claim 1 — obvious over JP 5‑185594 (integrated heater + shift register/latch/logic‑gate head substrate) in view of the admitted FIG. 12 head (nMOSFET power transistors in series with the heaters, CMOS‑process compatible) and in further view of the admitted gate voltage booster of FIG. 23 / the general knowledge of MOS level shifting; motivation supplied by the patent's own statement of the 5 V gate‑drive limitation and equation (1).
2. Claims 2–5 — as above plus the conventional pull‑up‑resistor‑plus‑CMOS‑inverter level shifter; a design choice among a finite set of known topologies.
3. Claim 6, 19–20, 29–30 — as above plus DOLS 2843064 and JP 54‑51834 (heat‑energy ink ejection; drop‑on‑demand) and U.S. 4,313,124 / 4,345,262 / 4,463,359 (bubble‑jet drive conditions).
4. Claims 16 and 21–25 — as above plus the admitted offset (n⁻ drain) MOSFET of FIG. 21B, applied to the inverter's pMOS/nMOS to permit operation from the ~25 V heater supply — motivation being the admitted 10–14 V breakdown limit of the conventional pMOS inverter and the cost/scale penalty of a separate supply.
5. Claims 26–28 — as above plus routine resistive voltage division with a source‑follower buffer (the admitted FIG. 6 structure).
6. Claims 31–37 — as above; claims 31–34 recite a result (compensation of gate‑length‑induced IDS drift by gate‑voltage control) already motivated by the admitted ±0.5–1.0 µm MPA variation and § 112‑adjacent in breadth; claims 35–37 would require the examiner to find art or knowledge teaching process‑tracking (matched polysilicon) bias of the power‑transistor gate, which is the weakest link in the § 103 chain.

5. Residual uncertainty, and one inconsistency to flag

• Flagged inconsistency with the earlier section of this analysis: the earlier "Litigation summary" section correctly states that the Google Patents page contains a "Prior Art keywords" metadata field but found no litigation. It does not address a prior‑art citation table. I confirmed that the page text I was supplied contains the prior‑art keywords and the documents cited in the specification, but not the separate "Patent Citations" (examiner/applicant) listing that normally appears on a Google Patents page. I therefore could not verify whether other family members (e.g., DE69733295T2, JP3372768B2, JP3332745B2, JP3327791B2) carry additional cited art that would be relevant. Treat the combination lists above as based on the prior art of record visible on this page plus admitted art, not as the complete search record.
• Claims 7–15 and 18 numbering/dependency are inferred, and the retrieved claim text truncates mid‑claim 37 (a pMOS‑power‑transistor-plus-nMOS‑booster independent claim appears to exist from the summary‑of‑the‑invention language but I could not confirm its number). If the group‑C/group‑D claim boundaries differ from my reconstruction, the mapping of combinations 2 and 3 changes, not their substance.
• What I would need to firm this up: (i) the full Google Patents "Patent Citations" table plus its "Cited By" list; (ii) the examiner's file wrapper (the JP‑originating family and the US prosecution history) to see what art was actually applied and what overcame it; (iii) a targeted search on print‑head gate‑drive level‑shifting and on process‑tracking bias for print‑head power transistors in the 1990–1996 window. I did not run that third search to completion within this session, so I cannot state with high confidence that no closer art exists — I state only that the art visible on this page, together with the specification's own admissions, makes each independent claim group prima facie obvious under KSR, with claims 35–37 being the most defensible.