US 5911111

I'll search for this specific patent number and any related litigation.

Let me run a couple more targeted searches for any litigation or CAFC docket activity.

US Patent 5,911,111 — Search Results Summary

Scope note: I ran searches against Google Patents, USPTO-derived records (uspto.report), PTAB document collections reachable via search, and general web/CAFC-adjacent sources for the exact string "5911111" / "5,911,111" and for Intel-side 2026 Federal Circuit activity. I found no USPTO litigation docket entry, no PTAB proceeding, and no CAFC 2026 docket activity involving this specific patent. Searches for CAFC 2026 Intel matters surfaced only unrelated patents (e.g., VLSI's U.S. 8,566,836; 3D Surfaces IPR appeals; PACT XPP v. Intel). I am flagging this as a negative finding rather than a confirmed absence — I did not have direct PACER/Docket Navigator docket access, so I cannot rule out a filing that is not indexed in the sources I could reach.

Important caveat on a look-alike: Several search hits contain the string "US_59111111" (note the extra digit) in WIPO ST.92 documentation. Those refer to a 2022 application number 59,111,111 and have nothing to do with this patent. Per the strict rule, I am not treating them as the same identifier.

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Bibliographic data

Abstract (as printed)

A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance MOS devices. A short silicon polish step after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes surface roughness caused by the grain structure of polysilicon and roughness due to replication of underlying isolation/substrate topography, leaving the layer planarized without increasing defect levels.

Plain-language overview of the independent claims

Claim 1 — Integrated-circuit fabrication process:

1. Deposit a polysilicon-comprising layer above a substrate that has an isolation region in it;
2. Form a tungsten film on top of that polysilicon layer — expressly before the polishing step;
3. Polish the surface so that (a) surface roughness and replication of the underlying topography are substantially eliminated, and (b) the polished surface extends over substantial portions of the isolation region — i.e., a real planarization, not a mere touch polish;
4. Pattern the layer.

Claim 7 — MOS gate-electrode process with linewidth-control purpose:

1. Form an isolation region on a substrate, using LOCOS or shallow trench isolation;
2. Form a gate dielectric above the substrate and isolation region;
3. Deposit a polysilicon-comprising layer above the gate dielectric;
4. Form a tungsten film on that layer, again prior to polishing;
5. Polish so that surface roughness and replication of underlying topography are substantially eliminated and the polished surface extends over substantial portions of the isolation region;
6. Pattern the layer into a gate electrode;
7. Form source and drain regions on opposite sides of the gate electrode.

Dependent claims in brief: claim 2 adds a tungsten silicide film (formed before polishing); claim 3 uses an SiO₂/KOH slurry; claim 4 sets the deposited thickness at ~3000–5000 Å; claim 5 removes ~100–2000 Å during polishing; claim 6 narrows "patterning" to forming a gate electrode. Claims 8–12 mirror these for the claim 7 family, with claim 12 adding the polishing mechanics: substrate pressed at ~0.5–3.0 psi, slurry dispensed on the pad, pad rotated ~10–100 rpm relative to the substrate.

Analyst observations

• The claims are narrower than the specification leads you to expect. The written description is largely about CMP of bare polysilicon (SiO₂/KOH slurry, ~0.5–3.0 psi, ~10–100 rpm, ~20 °C, ~1000 Å removed, IC-1000/Suba-4 stacked pad, Westech polisher). But both independent claims require a tungsten film formed on the polysilicon layer before polishing. Anyone reading only the abstract would overestimate the claim scope.
• Note an internal numerical tension: the "Summary of the Invention" states the polish continues until ~1000 Å of the 3000–5000 Å polysilicon is removed, while the detailed description gives ~400 Å (grain roughness alone), a 100–500 Å range, and a 500–2000 Å range for topography-driven roughness. The 1000 Å figure sits inside the claim 5/11 range of 100–2000 Å.
• Expiry matters for any 2026 analysis. The term ran from the Feb. 24, 1995 parent filing, with anticipated expiration Feb. 24, 2015. That is consistent with the 12-year maintenance fee (2010-12-08) being the last payment. There was a lapse-and-reinstatement episode in 2007–2008 (lapse for failure to pay at the 8-year window, reinstated June 16, 2008), but that did not extend the term. A patent expired in 2015 could not support a 2026 infringement suit over post-expiration conduct, which is a substantive reason — independent of my search results — to doubt any 2026 CAFC docket activity on this number.

Uncertainty / what I could not confirm

• No authoritative hit confirming a Certificate of Correction content (the legal events show one on 2004-06-29, but I did not retrieve the corrected text, and any correction could affect precise claim wording).
• No confirmation of a terminal disclaimer or any reexamination/PTAB record for this patent.
• No confirmed 2026 litigation; treat my negative finding as "not found in searchable sources," not as "proven nonexistent" — a PACER/PTAB-Portal query by patent number would be the authoritative check.

Sources: https://patents.google.com/patent/US5911111/en · https://patents.justia.com/patent/5911111 · https://uspto.report/patent/grant/5911111 · http://patentimages.storage.googleapis.com/fe/64/31/6cf55a0f6acdaa/US5911111.pdf

I'll search litigation-specific sources for this exact patent number.

Let me run additional targeted checks on litigation-specific databases.

Litigation Search — US Patent 5,911,111

Bottom line: I found no litigation involving US Patent 5,911,111. No district court case, no ITC investigation, no PTAB proceeding (IPR/PGR/CBM), and no Federal Circuit appeal asserted this patent in any searchable source. This is a negative finding from the sources I could reach, not a certified absence — see "Confidence and limits" below.

Table of known litigation

There is no row to populate for this patent number.

What I searched and what came back

• Litigation-aggregator / PACER-adjacent sources: searches keyed to the exact strings "5,911,111" and 5911111 plus litigation terms ("litigation," "case," "docket," "infringement," "complaint," "defendant") returned no case record. The only patent-data hits were bibliographic: uspto.report's grant page for 5,911,111 (Intel Corporation, Bohr et al., granted 1999-06-08) and a PatentLeaderboard inventor page for Lawrence N. Brigham.
• PTAB / Unified Patents portal content surfaced by search: every PTAB hit was for different patents (e.g., Unified Patents v. MasterObjects re 10,311,073; Unified Patents v. MemoryWeb re 10,621,228; Greenthread v. Intel/TI proceedings involving Greenthread's own patents). None referenced 5,911,111.
• CAFC: the only 2026 CAFC material surfaced (e.g., the Rule 36 judgment in IdeaHub Inc. v. Unified Patents, LLC, No. 2024-1684, decided April 10, 2026, an appeal from PGR2022-00044) is unrelated to this patent number.
• Citation-graph check: the patent's forward citations (12–18 documents, e.g., US 6,162,714 to LSI Logic; US 6,559,040 to TSMC; EP 1,294,015 to Infineon) are patent citations, not litigation. A citing patent is not evidence of an infringement suit, and I did not treat it as such.

A trap I want to flag explicitly

Several search results contain the string US_59111111_... — note the extra digit — in WIPO ST.92 documentation (the "priority document data package" standard). Those refer to a 2022 application number 59,111,111 (filed July 19, 2022, per the ST.92 examples), a completely different identifier that happens to embed our number as a prefix. Per the strict no-auto-correction rule, I am not treating those as this patent and they are not litigation in any event. Similarly, the strings 5911111 appearing in unrelated IPR exhibit tables (e.g., US 5,978,791 in a Unified Patents filing) are coincidental digit overlaps, not this patent.

Why a negative finding is substantively plausible here (not just a search gap)

This is worth stating because it distinguishes "I couldn't find it" from "it very likely doesn't exist":

1. The patent expired. Term ran from the February 24, 1995 parent filing (Ser. No. 08/394,368, now abandoned), with anticipated expiration February 24, 2015. A patent that expired in 2015 cannot support a 2026 infringement suit over post-expiration conduct, and would only be assertable for damages accruing during its life — subject to the six-year limit of 35 U.S.C. § 286. Any litigation would therefore have had to be filed by roughly early 2021 at the outside to have recoverable damages, and none appears.
2. Ownership profile. The patent was owned throughout by Intel Corporation — a large operating company that practices its own patents and litigates defensively/offensively as a principal, not an NPE monetization vehicle. There is no assignment-out to a PAE in the record.
3. Subject matter. The claims cover an internal front-end wafer-fabrication step (polishing a polysilicon/tungsten gate stack before patterning). This is process-of-manufacture subject matter that is difficult and costly to detect from a finished commercial product, which makes it an unattractive assertion target.
4. The only adversarial public record is administrative, not litigation. The 2007–2008 episode was a maintenance-fee lapse and reinstatement (lapse for failure to pay the 8-year fee; petition granted and patent reinstated June 16, 2008) plus a Certificate of Correction dated June 29, 2004. Neither is litigation, and neither extended the term.

Confidence and limits

• Confidence that no litigation existed during the patent's enforceable life: moderate-to-high on the basis of the converged negative results above plus the structural reasons listed.
• Limits: I did not have direct PACER, Docket Navigator, Lex Machina, or Westlaw Litigation Analytics access in this session. My searches relied on indexed web content, Google Patents' "Cited By" tables, PTAB document repositories, and litigation aggregators surfaced through search. A case that exists only in a docket that is not indexed (e.g., a short-lived, sealed, or voluntarily dismissed complaint) could elude these searches.
• One unverified item carries over from the prior section: the June 29, 2004 Certificate of Correction content was never retrieved. If it revised claim language, that changes claim scope but does not create litigation.

Authoritative follow-up checks (recommended before relying on this)

1. PACER / CourtListener RECAP — party search for "Intel Corporation" as plaintiff combined with patent-number search for 5,911,111 across all district courts, 1999–2015.
2. USPTO Patent Trial and Appeal Board — Patent Trial and Appeal Board End-to-End (PTAB E2E) search by patent number 5,911,111.
3. ITC EDIS — Section 337 investigation search by the 5,911,111 patent number (relevant given Intel's semiconductor import exposure).
4. USPTO Patent Assignment Search — to confirm no assignment to a third-party monetization entity (which would raise the prior probability of an unindexed assertion).

Sources consulted: https://patents.google.com/patent/[US5911111](/patent/US5911111)/en · https://uspto.report/patent/grant/5911111 · https://www.patentleaderboard.com/intel/lawrence-n-brigham/[1012434](/patent/1012434) · https://www.cafc.uscourts.gov/opinions-orders/24-1684.RULE_36_JUDGMENT.4-10-2026_2674421.pdf · WIPO ST.92 documentation (https://www.wipo.int/edocs/mdocs/cws/en/cws_13/cws_13_20.pdf) — identified only as a false-positive match to be excluded.

I'll verify the structured "no proceedings" finding against public sources before drafting.

Two more targeted checks to make the negative finding robust.

Proceedings overview

There are zero AIA trial proceedings on file for US 5,911,111. The USPTO Open Data Portal structured block returns no IPR, PGR, or CBM for this patent, and my independent web checks surfaced no petition, institution decision, Final Written Decision, or appeal bearing this number (see "Search verification" below). The breakdown is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution-denied.

Bottom-line defensive posture for a defendant today: this is not a "hardened by IPR" patent — it is an untested one, and it is untestable in any practical sense because it expired on 2015-02-24. There is no IPR record to mine for estoppel, no FWD to lean on, and no cancelled claims to point a demand letter at. The absence of PTAB activity is not a sign that the patent is strong; it is a sign that nobody ever had a reason to challenge it. All 12 claims (claims 1–12, including independent claims 1 and 7) stand as issued and unadjudicated, but the patent's own term, not any PTAB panel, is what ends the story.

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Proceedings

None. There is no proceeding to list. Per the operating rule against fabricating identifiers, I am not supplying placeholder docket numbers, panels, or dispositions. If a proceeding exists that neither the ODP feed nor public search has indexed, it will carry a real number of the form IPR20XX-##### / PGR20XX-##### / CBM20XX-#####, and it can be confirmed by patent number in USPTO PTAB E2E or the PTAB Center before you rely on it.

Search verification (why the negative finding is credible)

Look-alike warning (carried forward from the earlier section, and material here): the string US_59111111_... in WIPO Standard ST.92 documentation refers to a 2022-filed US application number 59,111,111. It is not US 5,911,111. Any automated docket scrape that tokenizes on the digit string will produce false IPR "hits" from that family of documents. I have not treated them as this patent.

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Strategic summary

Canceled vs. sustained vs. untested. Nothing is canceled. All 12 claims — independent claims 1 and 7 plus dependents 2–6 and 8–12 — are UNTESTED at the PTAB. That is an unusual posture for a claim set this old, but the explanation is straightforward. US 5,911,111 is a 1995-priority Intel process patent covering a pre-gate-patterning polysilicon CMP touch polish on 3000–5000 Å films, with both independent claims further required to include a tungsten film (and, per claims 2/9, a tungsten silicide film) formed on the polysilicon before polishing. It issued into an era and an architecture (LOCOS/shallow-trench isolation, 0.25–0.35 µm-class CMOS) that is now many nodes in the past. There is no live product base to assert it against and no damages period left — which is precisely why no competitor ever needed to spend $500K–$1M on an IPR petition and an expert.

Estoppel landscape — the practical answer is "not applicable, and that is good for you." Because no IPR/PGR was ever instituted, no petitioner is subject to the § 315(e)(2) estoppel bar, and no patent owner has a § 325(e)(2) estoppel argument to deploy. There is likewise no IPR-driven narrowing that limits which prior-art theories remain available to a defendant. If you are nonetheless facing an assertion, your invalidity case is unconstrained by any PTAB record — the 22 examiner-cited references (e.g., US 4,879,258; US 4,944,836; US 4,954,142; US 5,342,879; US 5,466,587; EP 0545263) and the 8 non-patent citations (Kaufman et al., J. Electrochem. Soc. 138(11) 3460–3465 (1991); Landis et al., Thin Solid Films 220:1–7 (1992); Sivaram 1987; Wolf, Silicon Processing for the VLSI Era vol. 2 at 333–334) remain fully available, along with anything else in the art. Note the tight prior-art window: the operative date is 1995-02-24 (the § 120 parent filing, Ser. No. 08/394,368, which was abandoned; the '111 patent is a straight continuation, so it carries the parent's filing date). Art must predate that.

Pattern signals. No repeat petitioner, no serial-filing pattern, no defensive aggregator involvement (Unified Patents has no record for this patent), and no PTAB appeal history to analyze. The only post-grant events in the file wrapper are administrative: a Certificate of Correction on 2004-06-29 (corrected text not retrieved — flagged as an open item in the prior section), a lapse for failure to pay the 8-year maintenance fee on 2007-07-11, reinstatement after payment on 2008-06-16, and the final 12-year fee on 2010-12-08. Anticipated expiration: 2015-02-24.

A note on 2026 institution economics, for completeness. Even hypothetically, an IPR petition against this patent filed today would face near-certain discretionary denial. Current USPTO practice has been expressly skeptical of challenging aged patents, on the theory that a patent owner develops "established expectations" in a patent left unchallenged for a long period; the Institute for Progress/ACT amicus briefing in 2026 catalogued discretionary denials across aged patents (e.g., Intel's petitions in IPR2025-00327/-00328/-00329 against patents of roughly 9 years' vintage; see https://actonline.org/wp-content/uploads/20260706-Google-v.-Cellular-South-Amicus-Brief_Filed.pdf). A 31-year-old patent would sit at the extreme end of that spectrum. Treat this as context, not as a citable holding.

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Recommended next steps

If no PTAB activity exists — say so plainly, and I am. There is no FWD to quote, no disposition to link, and no claim-level outcome to report. Do not represent to a court, an adversary, or a client that claims of US 5,911,111 have been invalidated; they have not. Conversely, do not assume the patent's silence means it is strong.

For a defendant being asserted against (or evaluating a demand letter), the operative points are these:

1. Confirm the expiry date against the PTO record first. Anticipated expiration 2015-02-24 (20 years from the 1995-02-24 parent filing). The 2007 lapse-and-reinstatement did not extend term. Post-expiration conduct cannot infringe, so any demand built on activity after 2015-02-24 is meritless on its face. Pull the full file wrapper and fee history from USPTO Patent Center before responding: https://patentcenter.uspto.gov/ (search application 08/944,041).
2. Verify the Certificate of Correction. The legal events show a correction on 2004-06-29, and the corrected text was never retrieved in this analysis. Any argument that turns on exact claim wording (especially the "tungsten film ... prior to a step of polishing" limitation in claims 1 and 7) must be run against the corrected claims, not the as-printed Google Patents text. Order the corrected grant from Patent Center.
3. If a pre-2015 damages theory is in play, attack the claims directly. There is no estoppel and no IPR narrowing to work around. Both independent claims are narrow: they require a tungsten film (claims 1, 7) or tungsten silicide film (claims 2, 9) formed on the polysilicon before polishing. The specification's headline disclosure — bare-polysilicon CMP with SiO₂/KOH slurry at 0.5–3.0 psi — is not what claims 1 and 7 cover. Exploit that gap, and note the internal numerical tension the earlier section flagged (a "Summary" figure of ~1000 Å removed vs. ~400 Å / 100–500 Å / 500–2000 Å in the description) when construing the removal-amount limitations of claims 5 and 11.
4. Only if a live proceeding actually surfaces, re-run this analysis. If PTAB E2E shows a real IPR20XX-##### or PGR20XX-##### number, the milestones to track are the § 314(b) three-month institution deadline and the § 316(a)(11) one-year trial deadline from institution, with the FWD at claim-level granularity and any § 318 appeal docketed at the Federal Circuit (check CourtListener: https://www.courtlistener.com/?court=cafc).

Authoritative checks I could not perform, and that you should:

• PTAB E2E / PTAB Center search by patent number: https://ptacts.uspto.gov/
• USPTO Patent Center for the '111 file wrapper (Certificate of Correction text, fee/reinstatement history): https://patentcenter.uspto.gov/
• Unified Patents patent portal for any defensive-aggregator filing: https://portal.unifiedpatents.com/patents/patent/US-[5911111](/patent/5911111)-A
• Google Patents legal-events page for family/continuation data: https://patents.google.com/patent/US5911111/en

I'll research the assignment record for this patent across the sources I can reach.

Assignment & Ownership Analysis — US 5,911,111

Headline finding (read this first): Across the sources I could reach, there is no recorded post-issuance assignment for US 5,911,111. Google Patents' legal-events table for this patent contains only maintenance-fee and status codes (FPAY, FEPP, REMI, REIN, LAPS, FP, SULP, PRDP, STCF) plus a 2004-06-29 certificate of correction — no "AS" (assignment) events at all. Independently, uspto.report lists the patent as "currently assigned to Intel Corporation." Two aggregators that ingest USPTO reassignment data both point to Intel as the present owner. I could not retrieve any reel/frame number, any correspondent of record, or any executed assignment document for this patent; searches for reel/frame data returned empty results, and I did not have a direct live query interface to the Assignment Center. No reel/frame numbers are asserted anywhere in this report because I have none.

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Inventors

• All four are named on the parent application Ser. No. 08/394,368 (filed 1995-02-24, now abandoned), of which the 08/944,041 filing is a continuation, and on the PCT counterpart WO 1996027206 (applicant: Intel Corporation).
• No unusual pattern. There is no evidence of inventors departing the original assignee within 12 months of filing. To the contrary, the inventor roster is the classic signature of a captive corporate R&D team — all four remain tied to Intel-assigned filings years later. This is the opposite of the pre-fire-sale departure pattern.
• Caveat: employer attribution rests on patent-assignee data and third-party aggregator profiles, not on employment records or SEC disclosures. I did not verify each inventor's employment contract.

Original assignee

• Intel Corporation — named on the issued patent (grants 1999-06-08) and shown as original assignee. Google Patents shows Current Assignee = Intel Corp.; uspto.report states the grant "is currently assigned to Intel Corporation."
• Primary line of business: design and manufacture of microprocessors, chipsets, and related semiconductor devices — i.e., a vertically integrated operating company that runs its own fabs.
• Does it ship a product embodying the claims? The claims are process claims (a fab method: deposit polysilicon → form tungsten film → CMP planarize → pattern), so they are practiced in manufacturing rather than embodied in a sold article. Intel's fabs did adopt pre-gate-patterning planarization flows in the relevant era, and the patent's own assignee-family evidence (Intel's continued filing on the same subject) supports internal use. I cannot point to a specific Intel product SKU reading on the claims — for process claims that is the expected situation, not a red flag.
• Current status: operating company, publicly traded (NASDAQ: INTC), no bankruptcy; no Chapter 7/11 event touching this patent that I could find. Intel has divested patent portfolios in bulk at various times, but I found no evidence this patent was in any such divestiture.

Assignment timeline

Chronological list of recorded assignments: none found. The Assignment Center / Google Patents legal-events record for this patent shows no conveyance of any type (Assignment, Security Agreement, Merger, Change of Name, License, Release, or Correction of an assignment) recorded after issue, and no assignor/assignee/correspondent fields to report. Per the constraints of this task, I will not invent reel/frame numbers, execution dates, or correspondent names.

What is recorded on the patent's legal-events record, verbatim from the source, is a maintenance-fee and status history — not an ownership history:

• Correspondent of record: not retrievable from the sources I reached. No recurrence analysis is possible, which is itself a limitation on signal 3 below.
• Context sentence: the only "ownership-relevant" fact here is the absence of transfers — Intel appears to have held this patent from issue through expiration, with a 2007–2008 maintenance-fee lapse-and-reinstatement episode that changed status, not title.
• False-positive I explicitly excluded: search hits containing "US_59111111" (six digits after the "US_") are a 2022 WIPO ST.92 sample application, unrelated to this patent. Separately, an Intellectual Ventures Assets 156 LLC → Innovative Silicon Solutions LLC assignment document surfaced in results; US 5,911,111 does not appear on its patent schedule (that schedule lists 7,260,731; 7,870,404; 9,436,264; 9,690,366; 7,302,619; 7,600,166, etc.). I am not linking it.

Timeline diagram

timeline
    title Ownership of US 5911111
    1995 : Priority application filed
    1997 : Continuation application filed
    1999 : Patent issued to Intel Corp
    2004 : Certificate of Correction recorded
    2007 : Maintenance fee lapse event
    2008 : Reinstated after late fee
    2010 : Final maintenance fee paid
    2015 : Patent term expired
    2026 : Still shown as Intel Corp owned

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment of any kind is recorded; there is no LLC, no registered-agent address, and no single-purpose entity anywhere in the record. The chain does not exist to be tested.
2. Known asserter in the chain — not present. Neither Intel nor any of the listed NPEs (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg entities) appears as assignee. I could not query RPX/Unified Patents asserter directories directly, so this call rests on the assignee-of-record data plus the prior section's negative litigation finding.
3. Repeat correspondent across the chain — unclear. There is no assignment chain and no correspondent of record was retrievable, so recurrence cannot be measured. Reported as unclear, not as absent.
4. Cascading transfers — not present. Zero consecutive assignments, let alone multiple chained LLCs within 24 months.
5. Pre-litigation transfer — not present. No assignment within 6 months of any suit; the prior analysis found no suit naming this patent at all.
6. Bankruptcy fire-sale — not present. Intel has not filed Chapter 7/11; no sale-in-bankruptcy vehicle (Kodak/Nortel/Polaroid-style) touches this patent.
7. Privateering — not present. No operating-company-to-NPE transfer of record.
8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at the original operating company. (Note this is the absence of a defensive-aggregation signal, not evidence of neutralization by one.)

Additional structural point: the patent's term ran from the 1995-02-24 priority date and expired 2015-02-24 (consistent with the 2010-12-08 year-12 payment being the last). An expired patent cannot support an infringement action over post-2015 conduct, so no NPE pattern could mature after that date regardless of the record.

Verdict

Insufficient data (no records, or only the original assignment).

Justification: the ownership record for US 5,911,111 consists of the original Intel-held grant and nothing else — the legal-events table contains only fee/status codes (year-4 fee 2002-09-30; year-8 fee with surcharge 2007-10-12; year-12 fee 2010-12-08) and a 2004-06-29 certificate of correction, with no assignment ("AS") entry, no reel/frame, and no assignor/assignee change. Both uspto.report and Google Patents independently show Intel Corporation as current owner, and Intel is a solvent operating company that never declared bankruptcy, so no shell-entity, cascade, privateering, or fire-sale signal is even constructible. The absence of NPE signals here is a genuine negative finding driven by an empty transfer record, not by an inability to classify transfers.

Verification link: USPTO Assignment Center, search by patent number 5911111 — https://assignmentcenter.uspto.gov/ (legacy interface: https://assignment.uspto.gov/patent/index.html). Patent landing pages used: https://patents.google.com/patent/[US5911111A](/patent/US5911111A)/en and https://uspto.report/patent/grant/5911111.

Limitations / open items

• I did not execute a direct live query against the Assignment Center database; the reel/frame, conveyance type, and correspondent of record fields remain unretrieved. An assignment could in principle exist that is not reflected in the aggregators I reached — the empty-search result should be read as "not found in searchable sources," not "proven nonexistent."
• The content of the 2004-06-29 certificate of correction was not retrieved (flagged in the prior section as well). It could alter claim wording but would not be an ownership record.
• The earlier section's finding of no 2026 CAFC/PTAB activity is consistent with everything above and is independently explained by the 2015 expiration. No contradiction found between this section and the prior sections, except to reinforce them.

I'll search USPTO-related sources for this exact patent number and its cited references.

Let me verify details on the closest references and the late-filed ones.

Let me verify the post-priority-date references and a few key disclosures.

Prior-Art Analysis — US 5,911,111 ("Polysilicon polish for patterning improvement")

Scope note on the search. I searched for the literal string "5911111." Results resolved to the USPTO-mirror and third-party databases that carry USPTO data — Google Patents (patents.google.com/patent/US5911111/en), Justia (patents.justia.com/patent/5911111), and uspto.report (uspto.report/patent/grant/5911111) — rather than a direct Patent Center / PAIR query. I hit my tool-call cap before I could individually verify every one of the 22 cited references, so filing dates below are taken from the face-of-patent citation list reproduced in the authoritative full text, treated as the ground truth per your rule. Identifiers are reproduced literally. The WIPO ST.92 hits containing "US_59111111" (extra digit, 2022-07-19 filing) are a different application and are excluded.

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0. Before the mapping — two flags

Flag A — discrepancy with the previously generated section. That section listed the cited art as *"22 U.S./EP documents (e.g., US 4,879,258; US 4,944,836; US 4,954,142; US 5,342,879; US 5,466,587; EP 0545263; US 5,346,587 to Micron)."* Neither US 5,342,879 nor US 5,466,587 appears anywhere in the authoritative 22-item citation list. The closest literal matches in that list are US 5,232,875 (Method and apparatus for improving planarity of CMP operations) and US 5,346,587 (Micron, gate-electrode planarization). Per your strict rule I am not silently correcting them — I am flagging that they appear to be transcription artifacts and are not § 102 references for this patent on the record I can see.

Flag B — the legal frame. Application 08/944,041 was filed 1997-09-02 as a continuation of 08/394,368, filed 1995-02-24 (now abandoned). Because benefit is claimed, the effective filing date is 1995-02-24, and this is a pre-AIA case. Therefore:

• § 102(b) statutory bar → publication/patenting more than one year before 1995-02-24, i.e. before 1994-02-24.
• § 102(a) → publication or patenting before the invention date (no later than 1995-02-24).
• § 102(e) → a U.S. patent granted on an application filed in the U.S. before the invention date, effective as of that filing date. This is the vehicle that makes several post-1995-02-24 publications citable.

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1. The anticipation test the art must meet

Before mapping, note what actually has to be disclosed. Both independent claims require, in order:

The linchpin is the ordering limitation: "forming a tungsten film on said layer, wherein said tungsten film is deposited onto said layer prior to a step of polishing said layer." That is the one element the specification's own CMP narrative does not otherwise require, and it is the element that most of the cited art misses. A reference that planarizes polysilicon and then deposits a silicide/metal does not anticipate; a reference that deposits the silicide/metal into the same stack that is then polished is the only serious § 102 candidate.

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2. Tier 1 — the genuinely close references

2.1 US 5,346,587 A — Micron Semiconductor, Inc.

"Planarization of a gate electrode for improved gate patterning over non-planar active area isolation"

• Filed: 1993-08-12 (Ser. No. 08/105,276) · Granted: 1994-09-13
• § 102 posture: § 102(a) (granted before the invention date) and § 102(e) (U.S. filing 1993-08-12 is before the invention date). Not § 102(b) — grant date is only ~5.4 months before the 1995-02-24 filing, not a year.
• Disclosure: Deposits conductively doped polysilicon over neighboring LOCOS/trench isolation regions so the conductor rises above the isolation topology; planarizes by CMP; forms a selectively reflective layer superjacent and coextensive the planarized conductor; then patterns to form a planarized control gate. Reflective layer expressly includes metal silicides such as tungsten silicide and metals (claims 6–7). Claim 18 recites ~3000 Å polysilicon; claim 19 recites ~1000 Å overlying the field oxide.
• Potentially anticipatory of: Claim 6 (patterning into a gate electrode) and the thickness/planarization sub-limitations of claims 4–5 — but only as limitations. Because claims 4–6 depend from claim 1, a § 102 rejection of claim 1 as a whole is not supportable: in '587 the reflective/silicide layer is formed superjacent and coextensive said planarized conductive material, i.e. after planarization, whereas claim 1 requires the tungsten film before the polishing step. That ordering difference is dispositive against anticipation.
• Why it still matters: This is the single best § 103 reference — same problem (gate patterning over non-planar isolation), same solution family (CMP the gate conductor before patterning), overlapping numeric ranges (3000 Å deposit; 1000 Å over field oxide).

2.2 US 5,422,289 A — National Semiconductor Corp.

"Method of manufacturing a fully planarized MOSFET and resulting structure"

• Filed: 1992-04-27 · Granted: 1995-06-06
• § 102 posture: § 102(e) (U.S. filing 1992-04-27, before the invention date). Grant date post-dates 1995-02-24, so not § 102(a)/(b) on its face.
• Disclosure: Field oxide with raised surface; gate dielectric; polysilicon deposited and planarized to the field-oxide surface so polysilicon fills the voids over active regions; claim 2 planarizes by CMP; claim 3 uses a polishing medium of silica particles and an aqueous alkaline solution (functionally the SiO₂/KOH slurry family of claim 3/10); subsequent masking/etching defines gate, source and drain.
• Potentially anticipatory of: limitations of claims 3, 4 and 7 (alkaline-silica slurry; gate-dielectric-then-polysilicon-over-isolation; source/drain formation). No tungsten film at all → cannot anticipate claim 1 or claim 7 in full.

2.3 US 5,563,096 A — Digital Equipment Corp.

"Semiconductor device fabrication with planar gate interconnect surface"

• Filed: 1995-11-20 · Granted: 1996-10-08
• § 102 posture: ⚠️ Both dates post-date the 1995-02-24 effective filing date. On the record I can retrieve, this is not available as § 102(a), (b) or (e) art unless it carries benefit of an earlier U.S. application — which the sources I reached do not show. It was nonetheless cited on the face of the patent (i.e., by the examiner), which is itself the anomaly worth noting.
• Disclosure (substance): Field isolation (LOCOS; expressly also PBL and STI) not planar with the active area; gate oxide; a gate interconnect material layer of "polysilicon, tungsten silicide or a combination of polysilicon and tungsten silicide," 500–5000 Å; the layer is planarized by CMP (or resist etch-back); the planarized stack is then photoresist-patterned and etched into gates; the stated purpose is uniform resist thickness and improved gate-length control; source/drain and silicide follow.
• Potentially anticipatory of: on substance, this is the closest thing to claim 7 in the entire corpus — a pre-pattern CMP of a poly/tungsten-silicide gate stack over non-planar isolation, expressly for linewidth control. But it is defeated by date, and its silicide is described as an as-deposited stack component rather than a "tungsten film formed on said layer" in the claim-1 sense. I flag this as the reference with the highest duplicate-claim risk if its priority chain turns out to reach back before 1995-02-24 — verifying that chain in Patent Center is the single most valuable follow-up step.

2.4 EP 0545263 A2 — Sony Corp. (see also US 5,502,008 A, Sony)

"Method of forming trench isolation having polishing step and method of manufacturing semiconductor device"

• Published: 1993-06-09 (priority 1991-11-29) → § 102(b) (before 1994-02-24).
• Disclosure: Polishing-based trench isolation formation in a semiconductor device. Companion US 5,502,008 A ("Method for forming metal plug and/or wiring metal layer," priority 1991-05-29, granted 1996-03-26) → § 102(e) as of its U.S. filing.
• Potentially anticipatory of: the claim 7 isolation-forming step (trench isolation with a polish step) and claim 7's "shallow trench isolation" alternative. Nothing directed to polishing the gate conductor itself.

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3. Tier 2 — CMP process, slurry and apparatus art (limitation-level only)

These are the references that make the slurry/parameter dependent limitations (claims 3, 5, 10, 11, 12, 4, 8) look conventional. None touches the tungsten-before-polish element; none can anticipate claims 1 or 7.

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4. Tier 3 — Marginal or non-analogous

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5. Non-patent literature (4 unique citations; the face of the patent lists each twice)

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6. Bottom line

1. No single cited reference anticipates claim 1 or claim 7. Every candidate fails on at least the ordering element — a tungsten film deposited on the poly layer before the polishing step — and most fail additionally on the "polished surface extends over substantial portions of said isolation region" full-planarization element.

2. The best § 102 candidate, narrowly, is US 5,346,587 A (Micron) — but its silicide is explicitly formed superjacent and coextensive the planarized conductor, i.e. post-polish. That ordering gap defeats anticipation while making it the strongest § 103 combination anchor. Its claim 19 (~1000 Å over field oxide) and claim 18 (~3000 Å) track the '111 ranges closely.

3. US 5,422,289 A (National Semiconductor) is the best § 102(e) reference for the chemistry limitations (claims 3/10 — silica + aqueous alkaline), and US 5,476,606 A (Rodel) is the best § 102(e) reference for slurry compositions generally.

4. US 5,563,096 A (Digital Equipment) is the most substantively on-point document in the entire corpus (planarize a poly/tungsten-silicide gate stack over non-planar isolation, then pattern, for gate-length control) but appears to post-date the 1995-02-24 effective filing date on both its filing (1995-11-20) and grant (1996-10-08). If it turns out to claim benefit of an earlier U.S. application, it becomes the most dangerous reference in the set. Verifying its priority chain is the highest-value next step.

5. Statutory-bar population is small. Only these clear the pre-1994-02-24 § 102(b) line: US 3,664,874; US 4,702,792; US 4,758,306; US 4,879,258; US 4,944,836; US 4,954,142; US 4,992,135; US 5,030,584; US 5,036,015; US 5,209,816; US 5,232,875; US 5,244,534; US 5,271,798; EP 0545263 A2 — plus all four NPL items. The rest ride on § 102(a) or § 102(e).

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7. Explicit uncertainties

• I could not retrieve the 2004-06-29 Certificate of Correction (legal events show one for this patent). If it amended claim text, any mapping above is to the as-printed wording only.
• I could not complete PAIR/Patent Center verification of every filing date, nor confirm the benefit chain of US 5,563,096, nor confirm whether US 5,502,008 has a U.S. filing date earlier than its 1991-05-29 foreign priority.
• I did not exhaustively review the eight "cited by" family members (e.g. US 6,162,714 LSI Logic; US 6,559,040 TSMC; EP 1294015 Infineon) for later-filed but earlier-effective art; those are "cited by," not "cited," and none is a § 102 reference on this patent's face, but they are relevant to the family (WO1996027206A2/A3), not to claim 1 of '111 as issued.
• Per the operating rule, the two identifiers US 5,342,879 and US 5,466,587 carried over from the earlier section are flagged, not corrected; they are absent from the authoritative citation list.
• Expiry context: anticipated expiration 2015-02-24 (12-year maintenance fee paid 2010-12-08), with a 2007–2008 lapse/reinstatement episode. Any § 102 analysis above is a validity exercise (relevant to the family/WO members and to historic disputes), not a live-infringement one — a patent expired in 2015 cannot support a 2026 infringement action.

Sources: https://patents.google.com/patent/US5911111/en · https://patents.google.com/patent/US5346587 · https://patents.google.com/patent/US5422289 · https://patents.google.com/patent/US5563096 · https://patents.justia.com/patent/5911111 · https://uspto.report/patent/grant/5911111 · http://patentimages.storage.googleapis.com/fe/64/31/6cf55a0f6acdaa/US5911111.pdf

I'll ground this analysis in the specific prior-art references listed on the patent page before applying § 103.

Excellent — the primary references retrieved are remarkably on-point. Let me verify two more.

Obviousness Analysis — US 5,911,111 Under 35 U.S.C. § 103(a)

Scope note / date discrepancy: The task prompt gives "Current Date: April 26, 2026," while the session clock reads 2026-09-30. This does not change the analysis (the patent expired 2015-02-24), but I flag it so the reader knows which date I treated as operative for "as-of" statements. All obviousness determinations below are as of the February 24, 1995 effective filing date (the § 111 continuation claims benefit of Ser. No. 08/394,368, filed Feb. 24, 1995, now abandoned). Pre-AIA § 103(a) governs.

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1. Threshold corrections to the record before analyzing

These are required by the "no auto-correction" rule and by my obligation to flag contradictions with the previously generated sections.

(a) Two identifiers in the prior "Patent summary" section do not appear in the authoritative prior-art table. That summary listed "US 5,342,879" and "US 5,466,587." Neither appears in the patent's Citations (22) or Non-Patent Citations (8). The two closest genuine entries are:

• US 5,232,875 — Micron, filed 1992-10-15, issued 1993-08-03, "Method and apparatus for improving planarity of chemical-mechanical planarization operations"
• US 5,346,587 — Micron, filed 1993-08-12, issued 1994-09-13, "Planarization of a gate electrode for improved gate patterning over non-planar active area isolation"

I treat the earlier summary's numbers as transcription artifacts and analyze against the authoritative list. Per the literal-interpretation rule, I do not silently renumber them.

(b) US 5,563,096 is cited on the face of the patent but is not available as § 103 prior art. It was filed 1995-11-20 and issued 1996-10-08 — after the applicant's Feb. 24, 1995 effective filing date. Under pre-AIA § 102(e)/§ 103, a U.S. patent is available only if its application was filed before the applicant's invention date. It therefore drops out of every combination below. (It may have been cited by the examiner for background only.)

(c) Prior-art qualification of the remaining cited art. Because the critical date is Feb. 24, 1995 (and, for § 102(b), Feb. 24, 1994):

None of the references is commonly owned with Intel, so pre-AIA § 103(c) does not disqualify any of them from combination.

(d) Claim-construction tension that drives the whole analysis. As the earlier sections flagged, the specification is almost entirely about polishing bare polysilicon, but both independent claims require a tungsten film formed on the polysilicon layer before the polishing step. That means the § 103 attack is not really "was polysilicon CMP known?" (it plainly was) — it is "was it known to (i) planarize a poly gate stack over non-planar isolation by CMP before patterning, and (ii) do so on a stack whose top surface is tungsten?" The answer to both is yes in the cited art.

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2. Person of ordinary skill in the art (PHOSITA)

As of February 1995: a process-integration engineer with a B.S. in EE/Materials Science and roughly 2–5 years in CMOS front-end integration, including hands-on experience with chemical-mechanical polishing of dielectric and metal films and with gate-stack lithography at 0.5 µm design rules and below. This definition matters because:

• The § 289 reference frames the problem as a 0.5 µm / ~1 µm depth-of-focus problem — squarely within this person's daily work.
• Both Landis et al. and Kaufman et al. are PHOSITA-level papers on production CMP tools (Strasbaugh) and processes, not exotic science.

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3. Combination I (primary): Micron '587 + Landis + Kaufman — renders claims 1, 4–8, 11 obvious

3.1 What the references teach (verified content)

US 5,346,587 (Micron, Doan & Dennison, issued 1994-09-13) — the single most damaging reference. Verified from the patent text:

• Identifies the exact problem the '111 patent identifies: light reflecting off the uneven topography of the gate stack causes reflective notching in the photoresist, which is transferred into the conductor by etch, reducing MOS reliability.
• States: "The present invention addresses the reflective notching problem by forming a planarized conductor on a wafer's surface that has a uneven topology that results from the formation of spaced apart, patterned oxide isolation regions including oxide regions formed by LOCOS trench isolation and other advanced isolation technologies."
• Discloses a conductively doped polysilicon layer (claims 5, 13) over LOCOS field oxide and thin gate oxide, planarized by chemical mechanical polishing (claims 4, 12), with a reflective layer superjacent and coextensive therewith, where the reflective material is selected from "metal silicides and metals" (claim 6) and specifically "tungsten silicide and titanium silicide" (claim 7), all patterned into a planarized transistor gate / control gate for an MOS device (claims 9–15; FIG. 3 → FIG. 4A; FIG. 4C shows planarized polysilicon + silicide + reflective insulator).
• States the process "could utilize these steps to form planarized conductive strips on an non-planarized surface wherein the conductive strips comprise various conductive materials including multiple doped polysilicon layers, metal layers and any combination thereof."

National Semiconductor US 5,422,289 (issued 1995-06-06; § 102(e)) — verified from the patent text:

• Articulates the resistance-thickness/reflectivity mechanism verbatim in substance: the LOCOS step is "transferred, in part, to the surface of the polysilicon layer during deposition … These height variations are, in turn, translated into height and thickness variations in the photoresist layer … The resist height variations cause focus variations … while the resist thickness variations cause differences in the optimum amount of optical energy required to expose the full depth of the resist."
• Claims polysilicon planarized by CMP before gate patterning (claims 1–2, 9–10), using a polishing medium "including silica particles and an aqueous alkaline solution" (claims 3, 11) — i.e., the SiO₂/alkaline (KOH/NH₄OH) chemistry of '111 claim 3.
• Discloses that the overlying conductive layer may include "refractory metal silicides, tungsten, titanium, titanium nitride, molybdenum, tantalum and doped polysilicon" (claims 4, 12).

Landis et al., Thin Solid Films 220 (1992) 1–7 (cited on the face of '111; verified abstract and text):

• CMP in production CMOS since 1985, including the IBM 4-Mbit DRAM, "which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization."
• "Polysilicon CMP was judged to be a more cost-effective and robust method than RIE for removal of the polysilicon overburden. This CMP process was adopted early in the development cycle of the IBM 4-Mbit DRAM."
• CMP of shallow trench isolation to a nitride polish stop.
• The motivation sentence a court can quote directly: "A wafer that is truly flat … provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures."
• Also notes "CVD tungsten films are very rough, demanding increased overetch."

Kaufman et al., J. Electrochem. Soc. 138(11) (1991) 3460–3465 (cited on the face of '111; verified text):

• Full W-CMP tool disclosure: wafer in a holder "with the wafer surface in direct contact with a pad-covered table"; "the abrasive slurry flows onto the surface of the pad and the rotation speed of the table and of the holder can be independently varied"; pressure applied via an overarm in the 1–5 kg/cm² range; Rodel pads.

3.2 Element-by-element mapping to claim 1

The sole substantive gap is the order of steps. '587's illustrated sequence planarizes the polysilicon first and then deposits the reflective (silicide/metal) layer. The '111 claim affirmatively requires the tungsten to be present during the polish.

3.3 Why a PHOSITA would have closed that gap (motivation, four independent sources)

1. The problem statement is identical and explicit in the art. '587, '289, Landis, and the '111 specification all describe the same causal chain: non-planar gate stack → resist thickness variation + reflective notching → linewidth loss. When the problem is the motivation and the art supplies the solution, the "teaching, suggestion, or motivation" requirement is satisfied by the problem itself (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007)). No hindsight reconstruction is needed.
2. Landis supplies the express "flat wafer → better photolithographic yields" rationale — the exact benefit '111 claims as its advantage.
3. Landis supplies the express motivation to polish the tungsten rather than leave it rough: "CVD tungsten films are very rough, demanding increased overetch." A PHOSITA who has (per '587) already decided to planarize the gate stack, and who has (per Landis) a rough CVD tungsten film on top of that stack, would predictably extend the polish to the tungsten surface. The '111 specification makes the same observation about tungsten in its own "Background/Detailed Description."
4. Combining the steps into one polish is a recognized economy (MPEP 2144.01, combining steps; MPEP 2144.04, rearrangement of steps where the order does not affect the result). Polishing a conformal W film down to planarity simultaneously planarizes the poly beneath it in the same step, saving a planarization step — a predictable, efficiency-driven modification.

3.4 Reasonable expectation of success

High. By 1995 the art had: production polysilicon CMP (Landis, IBM 4-Mbit DRAM), production tungsten CMP in the same DRAM flow (Landis; Kaufman), the same polishing platform and pad type (Kaufman — Strasbaugh, Rodel; '111 preferred embodiment — IC-1000/Suba-4 from Rodel), and the same alkaline-silica/poly chemistry ('289 claims 3, 11). This is a case of "a finite number of identified, predictable solutions" (KSR) rather than an unpredictable experimentation program.

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4. Combination II: '289 + '587 + one of {US 4,944,836 / US 4,954,142 / Rodel '606} — the polishing-mechanics and slurry claims (3, 5, 11, 12)

Motivation for Combination II: the "objective technical problem" is how to remove a controlled, small, uniform amount of the top of a gate stack without delaminating the polysilicon or damaging the thin gate oxide. The cited art supplies the standard three parameters (pressure, rotation, slurry delivery) and even a worked example on tungsten at 23 °C. Nothing in the '111 specification demonstrates a critical pressure value; the patent simply asserts a preference.

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5. Combination III: '587 + '289 for claim 2 (tungsten silicide) and claim 7 (MOS gate flow)

Claim 2 (tungsten silicide film formed before polishing): this is the weakest claim in the patent. '587 expressly discloses tungsten silicide as the reflective layer superjacent the planarized polysilicon (claim 7), and discloses the resulting planarized structure as a transistor gate. The only delta is again the pre-polish sequencing, addressed in §3.3. At minimum this is substitution of a known material (WSi₂) for a known alternative (W metal) with predictable results; more aggressively, a court or the PTAB could find '587 § 102-anticipatory for claim 2 if the sequencing language is read as a mere statement of intended use of the same physical structure.

Claim 7:

• "isolation region … LOCOS or shallow trench isolation" — '587 expressly recites "oxide regions formed by LOCOS trench isolation and other advanced isolation technologies"; Landis expressly recites STI planarized by CMP in the IBM 16-Mbit DRAM; EP 0 545 263 A2 (Sony) is likewise directed to trench isolation with a polishing step.
• "gate dielectric above said substrate" — '587 (thin gate oxide 33); '289 claim 1; '111's own specification identifies "gate dielectric" as a synonym for gate oxide.
• "pattern … into a gate electrode" — '587 claims 9–15.
• "forming a source region and a drain region on opposite sides of said gate electrode" — '289 claim 1 ("doping the source and drain areas of the active regions"), claims 5–8. Standard, admitted MOS flow.

Motivation: '289's express goal is a fully planarized MOSFET whose gate level is planarized before the gate-defining photolithography, precisely to fix focus/exposure variation across the field. '587's express goal is to fix reflective notching at the gate-patterning step. Combining them for a LOCOS- or STI-isolated high-performance MOS gate is the natural union of two references directed to the same fabrication step.

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6. Claim-by-claim conclusion

Independent claims are the strongest invalidating targets; the numerical-range dependents are the weakest. The claims most likely to survive a § 103 challenge are, paradoxically, the ones reciting the specific 0.5–3.0 psi ceiling (claim 12) and the 100–2,000 Å removal amount (claims 5, 11) — but only if a patentee could show criticality or unexpected results, which the specification does not attempt and, on this record, no secondary-considerations evidence exists.

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7. Counterarguments a patent owner would raise, and the rebuttals

1. "Polysilicon CMP at production quality wasn't routine in Feb. 1995."
   Rebuttal: Landis et al. (1992) reports polysilicon CMP adopted in the IBM 4-Mbit DRAM manufacturing flow and judged more cost-effective and robust than RIE. '289 claims polysilicon CMP with a silica/alkaline medium. The '111 specification's own statement that the Westech polisher "although primarily designed for oxide polishing, may be used for polysilicon polishing with careful control of the polishing parameters" is an admission that the technique was available and required only parameter tuning.

2. "Teaching away: '587 planarizes first, then deposits the reflective layer."
   Rebuttal: '587 contains no disparagement of forming the metal first, and its own disclosure contemplates "multiple doped polysilicon layers, metal layers and any combination thereof" as the planarized conductor. A mere difference in sequence, where the sequence does not change the resulting function of the elements, is a recognized obviousness rationale. Moreover, Landis's note that CVD tungsten is "very rough" cuts the other way — it supplies the reason to polish the W surface rather than leave it.

3. "The invention avoided ARCs, a distinct technical benefit."
   Rebuttal: avoiding the cost and added defectivity of an extra deposition/etch step is a known design trade-off, not an unexpected result. '587 achieves the same goal (improved gate patterning) by planarization instead of an ARC, so the art already taught the substitution of one approach for the other.

4. "Criticality of the low polishing pressure."
   Rebuttal: the specification asserts a preference, gives no comparative data, and admits the pressure range is chosen to "prevent delamination … and to prevent damage to the thin gate oxide layer" — i.e., an articulated, predictable engineering constraint. Under In re Aller, a range overlapping the prior art working window and asserted without criticality is obvious.

5. Secondary considerations. On this record there is no evidence of commercial success, licensing, copying, praise, or long-felt-but-unsolved need attributable to these claims. There is a crowded, well-populated prior-art space (22 cited references, mostly Micron CMP cases, plus IBM's '836/'142 and the Rodel portfolio) — which, under KSR, supports the existence of a known field with a finite set of predictable solutions rather than a breakthrough.

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8. What I could not verify (explicit uncertainties)

• Wolf, Silicon Processing for the VLSI Era, Vol. 2, pp. 333–334 is cited on the patent's face, but I was unable to retrieve its content in this session (search step limit reached). I have therefore not relied on it to supply any claim limitation. If those pages address CMP planarization and/or polycide/refractory-metal gate stacks, they strengthen Combinations I–III; if they do not, the analysis is unchanged because '587, '289, '606, Kaufman, and Landis already carry every limitation. Do not treat my silence on Wolf as a determination about its content.
• I did not retrieve the full text of US 4,879,258 (TI), US 4,944,836 (IBM), or US 4,954,142 (Carr, IBM) directly; their content is described here only as characterized in the specification and in the Rodel '606 background (CMP of dielectric/metal composites, chelating agents for metal selectivity). Those characterizations come from the retrieved Rodel text and are reliable for that purpose, but I have not independently confirmed the claims of '836/'142.
• The Certificate of Correction dated 2004-06-29 on this patent was never retrieved in the earlier sections either. If it amended claim text, the literal claim scope — and therefore any anticipation argument under § 102 — could change. § 103 conclusions here are robust to that (they rely on the substance of the claims as printed).
• I could not reach PACER / PTAB E2E / Docket Navigator; consistent with the earlier sections, I assume no adjudicated validity ruling exists that would be controlling.
• The inference that the "tungsten film" limitation was added during prosecution to distinguish Micron '587 is my speculation, not a record fact — I did not obtain the file history for Ser. Nos. 08/944,041 or 08/394,368.

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9. Bottom line

Every limitation of every claim of US 5,911,111 is disclosed or suggested by the art cited on its own face, chiefly:

• US 5,346,587 (Micron) — planarizing a polysilicon gate layer over LOCOS/trench isolation by CMP, with a silicide/metal (incl. tungsten) layer on the stack, before gate patterning, expressly to cure reflective notching;
• US 5,422,289 (National Semiconductor) — planarizing polysilicon by CMP with silica + aqueous alkaline slurry, over LOCOS, expressly to cure resist-thickness-induced focus/exposure variation at the gate level;
• Landis et al. (1992) — production polysilicon, tungsten, and STI CMP in IBM CMOS, with the express rationale that a flat wafer "provides for better photolithographic and dry etch yields," plus the observation that CVD tungsten is very rough;
• Kaufman et al. (1991) and Rodel US 5,476,606 — the W-CMP tool choreography (slurry on pad, substrate pressed to pad, pad and carrier counter-rotated) and a worked tungsten example at 7 psi / 40–50 rpm / IC1000 pad / 23 °C that lands inside the claimed rotation and temperature ranges and just above the claimed pressure ceiling.

The single genuine gap — that the claims require the tungsten film to be present before polishing, whereas '587 illustrates planarizing the poly first — is closed by a motivation that appears in the prior art itself (identical problem statement; "truly flat → better photolithographic yields"; rough CVD tungsten), by the predictable result of a single-step planarization of a conformal composite stack, and by the recognized permissibility of combining and reordering known process steps. On this record, claims 1, 2, 3, 6, 7, 9, and 10 would be expected to fall to a § 103 rejection, with claims 4, 5, 8, 11, and 12 also likely obvious absent a showing of criticality or unexpected results for the recited numerical ranges.