US 5470392

I'll search for the specific patent number and any related litigation.

US Patent 5,470,392 — Summary

Important sourcing note: the USPTO full text provided to me is authoritative here, and I used it in preference to search snippets. A web search for "5470392" also surfaces JP 特許第5470392号 (JP5470392B2) — a different, unrelated Japanese patent (Panasonic, "電子機器の冷却構造" / cooling structure for electronic equipment, filed 2010). This is a numeric coincidence only; do not conflate it with US 5,470,392. Likewise, do not confuse US 5,470,392 with its Japanese family member JP2791251B2.

Bibliographic data

Abstract (as issued)

A semiconductor processing method includes the steps of carrying a case containing semiconductor wafers and to which an ID card is attached into semiconductor processing equipment at a first side of the semiconductor processing equipment; removing the ID card from the case; taking the semiconductor wafers out of the case; carrying the semiconductor wafers taken out of the case into a processing means on a second side, opposite to the first side, of the semiconductor processing equipment; processing the semiconductor wafers in the processing means; attaching the ID card corresponding to the semiconductor wafers to the case; taking the processed semiconductor wafers out of the processing means at the first side of the semiconductor processing equipment; putting the processed semiconductor wafers into the case to which the ID card is attached; and carrying the case outside the semiconductor equipment at the first side of the semiconductor equipment.

Background / problem solved

Conventional wafer cleaning equipment (FIG. 25) had a "very limited function": take wafers out of a product cassette, wet-clean them, and put them back. ID cards attached to cassettes had to be removed and re-attached outside the tool by hand/other equipment, which blocked full factory automation ("FFA"). Also, the old layout fed cassettes in on one side and removed them on the other, requiring multiple carrying robots. The invention internalizes ID-card removal/keeping/re-attachment and routes cassettes in and out on the same side.

Independent claim (plain language)

Claim 1 is the sole independent claim (claims 2–10 depend from it). It is a method claim covering:

1. Transport an incoming case of wafers to a first side of the processing device.
2. Remove the ID card identifying those wafers from the incoming case at that first side, and store the card.
3. Move the case from the first side to a second side of the device (the two sides are spaced apart; claim 2 narrows this to opposite sides).
4. Load the wafers from the case into the processing device at the second side.
5. Process the wafers.
6. Place an outgoing case for processed wafers at the first side.
7. Attach the ID card to the outgoing case.
8. Unload the processed wafers from the device into the outgoing case at the first side.
9. Transport the outgoing case away from the first side.

In essence: the case goes in and out on one side (the "first side"), while the wafer transfer into/out of the processing portion happens at a spaced second side; the ID card is stripped and re-applied inside the tool so it never leaves the equipment.

Dependent claims (paraphrased):

• 2 — first and second sides are on opposite sides of the device.
• 3 — attaching the card = placing it in an external pocket of the outgoing case.
• 4 — removing the card = taking it out of an external pocket of the incoming case.
• 5 — return the incoming (now empty) case to the first side after the wafers are removed.
• 6 — the return is accomplished by placing the case in a storage area.
• 7 — the outgoing case at the first side is obtained by removing it from that storage area.
• 8 — after returning, the incoming case is transported away from the first side.
• 9 — reusing the incoming case as the outgoing case.
• 10 — the ID card is removed and attached using a robot.

(Note: claim 1 contains the typographical error "processing devise" in the USPTO text; I quote/interpret it literally as "device.")

Description highlights (context for the claims)

• Cassettes (37) have a pocket (51) holding an ID card (38) (FIG. 1).
• Internal ID-card handling robot (30) moves cards to/from an ID-card stocker (31), using an ID-card removing lane (21) and ID-card inserting lane (22) on opposite sides of the robot, plus a card pusher (42) and guide (43).
• Loading sequence (Steps 51–66): cassettes enter carrying-in/carrying-out lane (20), cards are pulled to the stocker, cassettes are shuttled via transfer lanes (24/27), conveyor (35), loader waiting lane (28) to the loader (2); empty cassettes return via a vacant-cassette carrying-out lane (25) or buffer (26).
• Unloading sequence (Steps 101–110): vacant cassettes get ID cards re-inserted, go to the unloader (6) where cleaned wafers are inserted, then all four are carried out together.
• Second embodiment: vacant-cassette stocker (41) replaces the carrying-out lane (25), so empty cassettes need not leave the tool — fewer robots.
• Third/fourth embodiments (described but not claimed in this divisional) extend this to a module: plural cleaning tools (39a/39b), a cassette stocker (16), cassette cleaning equipment (9), and a module-level carrying robot (8).

Litigation / CAFC search result — explicit uncertainty

I searched for the patent number against court/docket sources and found no authoritative evidence that US 5,470,392 has been asserted in litigation or been the subject of a CAFC 2026 appeal. My searches returned only unrelated results (e.g., unrelated PTAB IPR lists, unrelated Apple/Motorola and Nokia matters, and the unrelated Japanese JP5470392B2). Because I only have general web-search access rather than a live PACER/CAFC docket query, I cannot rule out a 2026 filing — treat the "no litigation found" statement as absence of evidence, not evidence of absence. Note also that with a 2012-11-28 anticipated expiration, the patent is long expired, so any 2026 appellate activity would most likely concern damages/royalty tail or a related-family patent rather than prospective injunctive relief.

I'll search for litigation involving US patent 5,470,392.

Let me search more specifically for litigation records on this particular patent.

Let me run a few more targeted checks on litigation databases.

Litigation Search Results — U.S. Patent No. 5,470,392

Bottom line: I could find no record of any litigation involving U.S. Patent No. 5,470,392.

What I searched and what I found

I searched for the specific patent number together with litigation-related terms (patent litigation databases, dockets, CAFC, ITC, and general web). Every result I retrieved concerned different patents or non-patent uses of the number. I did not find any case in which US 5,470,392 (or its parent, US 5,383,482) was asserted.

Specific "near-miss" results that are NOT this patent (and must not be conflated with it):

Note in particular that U.S. Patent 5,372,392 (Norgren) and U.S. Patent 5,470,392 (the patent at issue here) are frequently confused because both are casually called "the '392 patent," but they are distinct patents with distinct subjects. Neither those cases nor the Japanese patent bearing the same numerals should be attributed to US 5,470,392.

Case-by-case table (as requested)

Assessment and caveats

• US 5,470,392 ("Semiconductor device processing method") issued Nov 28, 1995 to Mitsubishi Electric Corp.; it is a division of Ser. No. 07/970,471 (US 5,383,482) with a 1992-07-30 priority date and an anticipated expiration of 2012-11-28. It was reassigned to Renesas Electronics Corp. (recorded 2011-03-18). It is currently Expired – Lifetime.
• The absence of any found litigation is consistent with a fairly narrow, equipment/method patent (wafer-cassette handling with ID-card management) that apparently was never enforced in a reported case.
• Confidence caveat: My searches were limited and I could not exhaustively query every fee-based litigation database (e.g., full PACER, Docket Alarm, Lex Machina, RPX/Unified Patents litigation portal) or every historical district-court docket from the 1990s–2000s. It is possible — though I found no evidence — that an unreported or settled suit exists. I am stating explicitly that I did not find one, rather than asserting affirmatively that none ever existed.

If you need a definitive negative, the next step would be a direct query of the Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist), Docket Alarm, and PACER for "5,470,392" and "5383482," which I was unable to complete here.

I'll verify the structured "no proceedings" data point against the live web before writing this up.

Proceedings overview

There are zero AIA trial proceedings on file against US 5,470,392. The structured "PTAB proceedings on file" block reports that the USPTO Open Data Portal API returns no AIA trial proceedings for this patent as of the most recent ingest, and my independent web searches surfaced nothing contradicting that — no IPR, PGR, or CBM petition naming the '392 patent, in any status (active / claims invalidated / claims sustained / settled / institution denied). The breakdown by status is therefore 0 / 0 / 0 / 0 / 0.

The defensive posture this gives a defendant is not "the patent has survived IPRs and is hardened." It is something more useful: the patent has never been tested at the Board at all, and the reason is almost certainly that it was already expired before the AIA trial regime became usable. US 5,470,392's term ended on 2012-11-28 (Google Patents' "Anticipated expiration" event), and the first IPR was not filed at the USPTO until 2012-09-16. The patent was beyond its enforceable life before any petitioner could realistically have reached the Board. That is a term-expiry defense structure, not an invalidity-adjudication structure — and it is a much cleaner one.

Proceedings on file

None. No IPR####-#####, PGR####-#####, or CBM####-##### number exists for this patent, so there is no petitioner, no panel, no institution decision, no FWD, no settlement, and no Federal Circuit appeal to report. I will not manufacture proceeding numbers, panels, or dispositions to fill the template — that would be fabrication, and in a PTAB due-diligence memo it would be malpractice-adjacent.

Verification trail for the "zero" finding:

I cannot represent this as an exhaustive docket sweep. Web search is not the Board's docket. A definitive "no petitions ever filed" conclusion requires a query against PTAB E2E / PTACTS (https://ptacts.uspto.gov) filtering on the patent number and its family, plus a check of the sibling US 5,383,482, which I could not run from here. That 15-minute check is my top recommended step — but note that the family's expiry date makes a late-filed petition very unlikely.

Two identity traps to flag before anyone relies on a search hit

These are the kind of thing that gets cited incorrectly in a brief:

1. JP5470392B2 is not this patent's Japanese sibling. A search for "5470392" returns a Japanese publication numbered 特許第5470392号 / JP5470392B2 — a Panasonic (パナソニック株式会社) electronic-equipment cooling structure granted 2014-04-16. It is a number collision, not a family member. Do not cite it as the '392's Japanese counterpart.
2. The actual Japanese family member is JP2791251B2 (published as JPH0677305A), claiming priority to JP4-204068, priority date 1992-07-30 — the same priority date as the '392. Its status is "Expired - Fee Related."
3. US 5,470,392 is a division of US 5,383,482 ("Semiconductor processing apparatus and module"), filed 1992-11-02 and granted 1995-01-24 — stated verbatim in the '392 specification: "This disclosure is a division of application Ser. No. 07/970,471, filed Nov. 2, 1992, now U.S. Pat. No. 5,383,482." Any prior-art date analysis must run against the 1992-07-30 priority date (from JP4-204068), not the 1994-11-14 filing date of the '392 divisional. Google Patents reports the '482 as also "Expired - Lifetime." Both family members are dead.

Strategic summary

Claim status: all UNTESTED — but that is a timing artifact, not an endorsement. Claims 1–10 of US 5,470,392 have never been construed or adjudicated by the PTAB, and I found no district court invalidity judgment either. So there is no canceled claim to hand a defendant a free win, and no Board FWD to quote. What the record does show is that the patent is expired: Google Patents records the anticipated expiration event at 2012-11-28, the maintenance-fee trail ends at the Year-12 payment on 2007-05-04 with no further FPAY events, and the assignee chain terminated in a 2011-03-18 assignment from Mitsubishi Denki Kabushiki Kaisha to Renesas Electronics Corporation (effective 2011-03-07), after which no further prosecution or assertion activity appears. All ten claims — independent claims 1 and 9 (claim 9 being the reuse-the-incoming-case claim), and dependent claims 2–8 and 10 — are therefore untested and unenforceable for future conduct.

Estoppel landscape: there is none, which cuts both ways. Because no IPR, PGR, or CBM was ever instituted, § 315(e)(2) estoppel has never attached to anyone. No petitioner is barred, no privy is barred, and — importantly — no defendant inherits a favorable estoppel shield either. If a court ever had to reach validity of this patent, the entire pre-1992-07-30 prior-art universe remains available, with no § 325(d) cloud and no "grounds that reasonably could have been raised" limitation. Practically, that means a defendant's best invalidity theory is unconstrained by Board practice — but the better answer is that you should not be litigating validity at all, because of the term.

Pattern signals: none. No repeat petitioner (there are no petitioners). No PTAB appeal track record, because no FWD exists to appeal — the specification and file history show a 1990s-era Mitsubishi prosecution that ran to grant and stopped. There is no defensive aggregator in the chain: no Unified Patents, RPX, or similar entity appears anywhere in the assignment or family record, and the current owner of record is Renesas Electronics Corporation, an operating company (not the classic troll profile). That combination — expired term, operating-company owner, zero assertion history — makes this patent a low risk target today, but it also means a demand letter citing it would be an unusual and relatively easy letter to answer.

Recommended next steps

1. Lead with the term, not the merits. The specification's own field statement, the "Anticipated expiration" event of 2012-11-28, and the absence of any post-2007 maintenance-fee events establish that US 5,470,392's enforceable term is over. A patent more than six years past expiry cannot support recoverable damages: 35 U.S.C. § 286 bars recovery for infringement occurring more than six years before the filing of the complaint, and by definition no infringing conduct can have occurred after 2012-11-28. Convey this as a legal observation to be confirmed by your own counsel, not as advice — but it should structure any response.
2. Verify the zero-proceeding finding on the live docket at PTAB E2E / PTACTS (https://ptacts.uspto.gov), searching both 5,470,392 and the parent 5,383,482, plus the JP member JP2791251B2. If the ODP "no proceedings" block is confirmed, that absence is itself the signal here: this is not a patent that well-asserted defendants felt compelled to IPR — it is a patent the market let expire.
3. If you receive an assertion anyway, do not chase an IPR. There is no trial-stage clock to watch (no institution decision deadline, no oral hearing, no statutory one-year FWD due date, because no trial exists). The correct motions are a § 286 time-bar / expiration-based dispositive attack and, if the case is pleaded around past conduct, a Rule 12 challenge — not a petition. Filing an IPR against an expired patent with no live claims would burn fees and, under the Board's current discretionary-denial posture, would face its own uphill climb.
4. Preserve the family record. Note: US 5,470,392 (title as granted: "Semiconductor device processing method"; the Google Patents page header reads "Semiconductor device processing method" while the parent's title is "Semiconductor processing apparatus and module") and US 5,383,482 share the 1992-07-30 priority date. Confirm neither has a live continuation or reissue — the family table shows only the two US applications and the JP member, and nothing issued after 1995.

Bottom line for a defendant today: there is no PTAB proceeding to exploit and no canceled claim to point to, because none was ever filed. The exploitable fact is simpler and stronger — US 5,470,392 expired on 2012-11-28 and dropped out of the family's maintenance chain a decade earlier; all of claims 1–10 are simultaneously untested, unenforceable going forward, and effectively unrecoverable for past conduct.

I'll research the assignment record for US 5470392 across the available sources before reconstructing the chain.

Let me dig into the specific assignment records and the corporate history of the assignees.

Ownership & Assignment Reconstruction — US 5,470,392

Patent: US 5,470,392 A — "Semiconductor device processing method"
App. No.: 08/340,350 · Filed: 1994-11-14 · Issued: 1995-11-28 · Priority: 1992-07-30 (JP 4-204068)
Division of: US 07/970,471 (issued as US 5,383,482 A)
Status: Expired – Lifetime · Anticipated expiration: 2012-11-28

Sourcing note: my live query to the USPTO Assignment Center returned no indexed rows in this session, so the assignment details below are taken from the Google Patents legal-events record (which cites the reel/frame) plus the Justia/Google bibliographic pages. Fields I could not confirm (notably the recorded correspondent and the reel/frame of the initial inventor→company assignment) are explicitly flagged rather than guessed.

Inventors

All three list the same corporate address (Itami, Hyogo — the site of Mitsubishi Electric's semiconductor operations), and the patent issued to Mitsubishi Denki Kabushiki Kaisha, so all three were almost certainly company employees on a company-funded invention. Prosecution was handled by Leydig, Voit & Mayer (law firm of record per Justia).

Departure/fire-sale pattern: Not determinable. No public source surfaced ties any inventor to a post-1995 departure or to an assignment executed by the inventors personally. There is no evidence of the "all inventors leave, then portfolio sells" pattern. Note this file's only post-issuance transfer (2011) is a corporate-to-corporate transfer, not an inventor assignment.

Original assignee

Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Tokyo, JP.

• Business: Diversified electrical/electronics manufacturer and one of the historic four pillars of the Japanese semiconductor industry; both a chip producer and a manufacturer of semiconductor process/cleaning equipment — i.e., a party positioned to practice the claimed wafer-cleaning + ID-card handling method internally.
• Product embodying the claims: Moderate confidence that Mitsubishi Electric practiced the claimed method in its own fabs; the claims are directed to a wafer-cleaning method/apparatus with in-equipment ID-card handling, not a sellable article. No licensed or branded product SKU was identified.
• Current status: Operating. Mitsubishi Electric is a going concern and was never in bankruptcy. Its semiconductor business lines were progressively folded into the Renesas lineage (see timeline), which explains the 2011 transfer.
• Current assignee of record (per Google Patents): Renesas Electronics Corporation — also an operating company (major MCU/analog supplier), not an NPE.

Assignment timeline

1. ~1992–1995 (exact execution/recording dates and reel/frame not retrieved) — Reel not available in retrieved sources

   • Conveyance: Assignment
   • Assignor: Yoshiaki Yamada, Junji Iwasaki, Masashi Ohmori (inventors)
   • Assignee: Mitsubishi Denki Kabushiki Kaisha
   • Correspondent: not retrieved (prosecution firm of record was Leydig, Voit & Mayer)
   • Context: Ordinary employee-inventor assignment to corporate employer at filing. (Recorded at USPTO but not exposed in the sources retrieved — flagged as a gap, not fabricated.)

2. 2011-03-07 (executed) / recorded 2011-03-18 — Reel 025980 / 0219

   • Conveyance: Assignment
   • Assignor: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
   • Assignee: Renesas Electronics Corporation (Japan)
   • Correspondent: not retrieved from the indexed record exposed by Google Patents (the USPTO Assignment Center abstract page carries this field, but it did not render in this session). No recurrence to flag — this is the only post-issuance link, so a "repeat correspondent" test cannot be run from two data points in any event.
   • Context: Internal corporate reorganization / portfolio transfer — an operating company moving patents into its affiliated operating semiconductor group (Mitsubishi Electric's semiconductor lineage via Renesas Technology → Renesas Electronics). The recorded instrument is "ASSIGNMENT OF ASSIGNORS INTEREST; ASSIGNOR: MITSUBISHI DENKI KABUSHIKI KAISHA" bearing effective date 2011-03-07.

No further recorded assignments. After reel 025980/0219 the file shows only patent-term events (fee payments in 1999/2003/2007) and the 2012-11-28 anticipated expiration. No assignment to any LLC, no security agreement, no license record, no release.

Timeline diagram

timeline
    title Ownership of US 5470392
    1992 : Priority date 30 Jul 1992
         : Parent app 07/970471 filed 2 Nov
    1994 : Divisional 08/340350 filed 14 Nov
    1995 : Patent issued 28 Nov
    2011 : Assigned to Renesas Electronics
         : Reel 025980 frame 0219
    2012 : Anticipated expiration 28 Nov

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only post-issuance assignee is Renesas Electronics Corporation, a publicly traded operating semiconductor manufacturer — no "IP/Holdings/Licensing/Ventures" suffix, no registered-agent address, no single-purpose LLC. Reel 025980/0219 (2011).

2. Known asserter in the chain — Not present. Neither Mitsubishi Electric nor Renesas Electronics appears on the Acacia / Marathon / IV / IPNav / Wi-LAN / Conversant / Vringo / Pendrell / Round Rock / Spangenberg-type lists, nor in RPX or Unified Patents high-frequency-plaintiff directories that I could surface. Reel 025980/0219.

3. Repeat correspondent across the chain — Unclear / not present. Only one post-issuance recorded link exists, so recurrence cannot be demonstrated; a single appearance is expressly not a finding. The prosecution firm Leydig, Voit & Mayer is the only firm tied to the file, and it is a general-practice IP firm (not an NPE-asserter shop). Correspondent for reel 025980/0219 was not retrievable.

4. Cascading transfers — Not present. One transfer over a ~19-year life (1992→2011); no chained LLCs, no sub-24-month sequencing, no shared correspondent addresses. Reel 025980/0219 only.

5. Pre-litigation transfer — Not present. No infringement litigation naming US 5,470,392 was found; there is no suit for a 2011 assignment to "precede." The 2011 transfer is separated from expiration (2012-11-28) by ~20 months with no assertion activity.

6. Bankruptcy fire-sale — Not present. Mitsubishi Electric never filed Chapter 7/11; this is a going-concern intra-group transfer, not a distressed sale. Compare Kodak/Nortel/Polaroid fact patterns — absent here.

7. Privateering — Not present. No SEC 10-K/8-K or Patent Progress/EFF coverage ties Renesas or Mitsubishi Electric to funding an NPE against competitors using this patent. Reel 025980/0219 shows a plain operating-company-to-operating-company conveyance.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at Renesas Electronics, an operating company, and the patent has since expired.

Verdict

Insufficient data — (for NPE purposes; the ownership chain itself, however, is fully resolvable and shows no NPE activity).

The entire ownership history is Mitsubishi Denki → Renesas Electronics (reel 025980/0219, executed 2011-03-07, recorded 2011-03-18) — an operating-company-to-operating-company intra-group transfer, preceded only by the routine inventor-to-employer assignment. There is no assignment to a licensing-only entity, no known asserter, no litigation, and no cascade; the patent went Expired – Lifetime on its 2012-11-28 anticipated expiration. Under the taxonomy provided, none of the NPE categories is supported by evidence — I did not upgrade to "Operating-company assertion" because there is no evidence of any suit, and the claims (an in-fab wafer-cleaning/ID-card method) do not correspond to a product the assignee sells.

Verification link: https://assignmentcenter.uspto.gov/ (search patent number 5470392) and the mirrored index at https://assignment.uspto.gov/patent/index.html — pull reel 025980/0219 to confirm the assignor/assignee/correspondent fields, which were not renderable in this session.

Data gaps to close if you need 100% completeness: (a) reel/frame and correspondent of the initial inventor→Mitsubishi assignment; (b) the recorded correspondent on reel 025980/0219. Both are worth a manual pull from the Assignment Center; neither is expected to change the verdict.

I'll search for the patent and each of its cited references.

Let me verify the remaining family-level citations and the reissue of the ASQ reference.

Prior-Art Analysis — US 5,470,392 ("Semiconductor device processing method")

0. Scope, sources, and a terminology caution

US 5,470,392 (app. 08/340,350; filed 1994-11-14; issued 1995-11-28; priority 1992-07-30; division of 07/970,471 → US 5,383,482) carries two different lists that are often conflated:

Only the first list is prior art under 35 U.S.C. § 102/§ 103. The second is prior art to the family (and, because JP 4-204068 is the §119 priority document, it is relevant context); the third is not prior art at all. I address all three but flag their status.

Important caveat repeated from the earlier section: a search for the string "5470392" also returns JP 特許第5470392号 (JP5470392B2) — an unrelated Panasonic cooling-structure patent. Numeric coincidence only. Everything below concerns US 5,470,392.

Source for the citation lists: the USPTO full text supplied (Patents (10) claim set, Citations (4), Family Cites Families (3)) and https://patents.google.com/patent/US5470392/en. I do not have the actual Office Actions / file wrapper, so I cannot state which of these references the examiner applied in a rejection — only that they appear on the "considered" list and that the claims issued. Treat the § 102 conclusions below as my independent technical reading.

1. The four examiner-cited references

(The order in which these appear differs slightly between the Google Patents rendering and the body text of the patent; the set is identical.)

R1 — US 4,568,234 A, "Wafer transfer apparatus"

• Full citation: U.S. Patent 4,568,234, filed May 23, 1983 (Ser. No. 06/496,832), issued Feb. 4, 1986; assignee ASQ Boats, Inc. A reissue of this patent exists (appearing as US RE33,341, "Wafer transfer apparatus"), i.e., the family was maintained by the patentee.
• URL: https://patents.google.com/patent/[US4568234A](/patent/US4568234A)/en
• Description: Apparatus that automatically lifts a batch of wafers as a group out of one slotted carrier (typically a plastic cassette) using spring-biased lifter jaws, translates them laterally, and lowers them into a second slotted carrier (typically a quartz boat), and performs the reverse transfer. A pusher engages wafer edges through the bottom of the cassette. The cassette is deliberately tilted to force the wafers into precise parallel alignment. A two-step mode transfers two 25-wafer cassettes into one 50-slot boat. All motions are automatically sequenced (control element 119, stop finger 136, solenoid 142).
• What it teaches relative to US 5,470,392: mechanical loading of wafers out of a case and into a processing carrier, and unloading back into a case; also the general notion that the carrier that holds wafers at input need not be the carrier in which they are processed.
• § 102 anticipation appraisal: No claim is anticipated. R1 discloses elements (a), (d) and parts of (h) of claim 1 in isolation, but it contains no ID card, no card removal, no card storage, no card re-attachment, and no "first side / second side" case-routing geometry. Elements (b), (c), (f), (g), (i) are absent, so claim 1 — and therefore every dependent claim, which incorporates all of claim 1 — cannot be anticipated by R1. At most it is element-level background art (at most § 103 fodder for the "load/unload wafers from a case" concept).

R2 — US 4,658,960 A, "Color coding cassette"

• Full citation: U.S. Patent 4,658,960, filed Oct. 7, 1985 (Ser. No. 06/785,248), issued Apr. 21, 1987; inventor Nob T. Iwasa.
• URL: https://patents.google.com/patent/US4658960/en
• Description: A wafer cassette incorporating a color-code system: interchangeable indicator plates / color code marks (items 5, 7, 20, 40, 50, 60) held in a cover-and-window arrangement on the cassette. The codes identify the process step, processing area, line, equipment, operator, or classification of the material in the carrier, and are sensed by the human eye and by mechanical devices in an automated transport system (the specification expressly discusses automatic material-transport systems, e.g., Mitsubishi Electric's "Auto-Carrier" and Varian Associates' modular transport system). Claim 1 of R2 is drawn to a carrier with indicator plates and a cover plate with an open window; dependent claims 2–15 set out specific code semantics and "being sensed by mechanical devices."
• What it teaches relative to US 5,470,392: this is the closest conceptual prior art to the "ID card" limitation — i.e., a machine-readable identifier physically attached to the wafer cassette, used to route the cassette correctly in a factory-automation transport system.
• § 102 anticipation appraisal: No claim is anticipated. R2 supplies the "identifier on the case" idea, but:
  • the identifier in R2 is part of the cassette (indicator plates under a window), not a card that is removed and separately stored as required by claim 1 steps (b)/(g);
  • there is no removal at a "first side," no storage while the wafers are processed, no re-attachment to an outgoing case, and no one-side-in/one-side-out case routing;
  • dependent claims 3 and 4 (card in an external pocket of the outgoing/incoming case) are likewise not disclosed — R2's code sits in an internal pocket/plates behind a window of the carrier shell, and R2 has no transfer of any identifier from one case to another.
  • Claim 10 (remove/attach ID card with a robot) is also absent — R2's sensing is by external readers, not a robot manipulator. At most R2 supports a § 103 motivation to substitute a machine-readable identifier for a paper card.

R3 — US 5,030,057 A, "Semiconductor wafer transferring method and apparatus and boat for thermal treatment of a semiconductor wafer"

• Full citation: U.S. Patent 5,030,057, filed Nov. 6, 1987, issued Jul. 9, 1991; assignee Tel Sagami Limited.
• URL: https://patents.google.com/patent/US5030057/en
• Description: A cassette→boat transfer system in front of a furnace: cassettes are placed on a first (carrier) stage, a boat on a second (boat) stage; a pushing mechanism lifts the wafers out of the cassette, a chuck mechanism carries them as a batch and deposits them into the boat grooves; and, per the family abstract on the assignee's patent list, an identification mechanism/identification section is provided on the boat in advance, is detected, and the boat is aligned to a predetermined position before transfer, under computer control. Claims relate to the transfer method, the transferring apparatus, and the boat.
• What it teaches relative to US 5,470,392: (i) two-stage, two-location transfer of wafers between a case and processing hardware, with the case and the processing side at spatially separated locations — geometrically reminiscent of the claimed "first side"/"second side"; (ii) an identification means associated with the carrier/boat that is detected to control positioning — an anticipatory seed for the "ID card" idea, though it is an ID feature of the boat, not of the wafer-containing case.
• § 102 anticipation appraisal: No claim is anticipated. R3's "identification mechanism" is used for positional alignment of the boat, and it is never removed from the case, never stored, and never re-attached; it also does not identify the wafers in the case (claim 1's express wording). Elements (b), (f), (g), (i) of claim 1 are missing. R3 is the second-strongest § 103 reference after R2 for the "identification" concept, but it does not meet the anticipatory standard for any of claims 1–10.

R4 — US 4,985,722 A, "Apparatus for coating a photo-resist film and/or developing it after being exposed"

• Full citation: U.S. Patent 4,985,722; priority 1988-02-12; appl. Ser. No. 07/308,470 filed 1989-02-10; issued Jan. 15, 1991; assignee Tokyo Electron Limited (and TEL Kyushu Limited).
• URL: https://patents.google.com/patent/US4985722/en
• Description: A flexible "track" type resist-processing system: a loading section where cassettes (cassette 2 / cassette 10) hold wafers, a vacuum tweezer transferring wafers from the loading section to the processing section, a handling robot that travels a passage alongside a plurality of treatment units (preheat, cool, coater, bake) and loads/unloads wafers into any selected unit, and control means selecting the units and their order by program. Treated wafers are returned to a cassette ("treated wafer" storage).
• What it teaches relative to US 5,470,392: an automated, programmable, cassette-in / cassette-out semiconductor processing tool in which wafers are removed from a cassette, processed through stations, and returned to a cassette, all under computer control — i.e., the general "processing device" environment (usable as the § 103 "prior art processing means") and the motivation to automate cassette handling.
• § 102 anticipation appraisal: No claim is anticipated. R4 has no ID card at all (no removal, no storage, no attachment), no "first side/second side" case-routing, and no case-stocker reuse logic that would map to claims 5–9. It is background art for the "process the semiconductor wafers" and "automated handling" elements only. Note also that R4 was cited in later Tokyo Electron family filings (e.g., US 5,177,514, US 5,701,627, US 8,919,756) as general track-system art — its value here is as context, not as an anticipating reference.

2. Family-level citations (JP family — JP 4-204068 → JP2791251B2 / JPH0677305A)

These appear on the record as "Family Cites Families," i.e., they were cited against the Japanese parent, not against the US divisional. Because JP 4-204068 is the § 119 foreign priority document for both US 5,383,482 and US 5,470,392, they are worth noting but they are not on the US "considered" list for US 5,470,392.

§ 102 appraisal: I could not, within the available search budget, retrieve claim text for these three JP documents, so I cannot responsibly opine on anticipation claim-by-claim. Structurally, however, none of the titles or the family context indicates disclosure of ID-card removal / keeping / re-attachment inside one tool — the feature that distinguishes claim 1. If a full analysis is required, the JP full texts (J-PlatPat) would need to be pulled; I am flagging this as an explicit gap rather than guessing.

3. Forward citations — expressly not prior art

US 5,740,053 (Tokyo Electron, 1998-04-14), US 6,031,384 (Advantest, 2000-02-29), US 6,267,123 and US 6,422,247 (Kabushiki Kaisha Toshiba, 2001/2002 — POD and POD cleaning). These post-date the 1992-07-30 priority date and therefore cannot be § 102/§ 103 art against US 5,470,392. Their only value is evidentiary: they show the trajectory of the art toward PODs/FOUPs with external identifiers, which the '392 disclosure anticipates in general terms.

4. Bottom line: anticipation under 35 U.S.C. § 102

No claim of US 5,470,392 is anticipated by any of the four examiner-cited references (or, on the evidence available, by the JP family citations).

The reason is structural, not marginal. Claim 1 requires, as separate sequential steps:

(b) removing an ID card identifying the semiconductor wafers from the incoming case at the first side and storing the ID card;
(g) attaching the ID card to the outgoing case;

and claims 3/4 require the card to live in an external pocket of the case, claims 5–9 require returning/reusing the incoming case, and claim 10 requires a robot to do the remove/attach. None of R1–R4 discloses any removable, storable, re-attachable wafer-identifying card. R2 comes closest (a machine-readable identifier permanently built into the cassette), and R3 comes closest on an "identification mechanism" (but on the boat, for alignment). Because a dependent claim cannot be anticipated unless all limitations of the claim(s) from which it depends are also disclosed, the absence of elements (b) and (g) in every reference disposes of claims 1–10 together — subject only to the JP-document gap noted above.

Most relevant prior art, ranked:

1. US 4,658,960 (Iwasa) — nearest to the identifier-on-cassette concept; the only cited reference that squarely addresses machine-sensed carrier identification.
2. US 5,030,057 (Tel Sagami) — nearest to the two-location wafer-transfer + carrier-identification/control concept.
3. US 4,985,722 (Tokyo Electron) — best background for an automated cassette-in/cassette-out processing tool.
4. US 4,568,234 (ASQ Boats) — purely mechanical cassette↔boat batch transfer; least relevant.

If a validity challenge were mounted on this art, it would realistically have to be a § 103 combination (e.g., R4 as the processing/handling tool + R2 or R3 for a machine-readable carrier identifier, plus an ordinary-artisan inference to detach and re-apply the identifier to keep the wafer lot associated with the case) — and even then the single-side case in/out routing and internal card stocker of claim 1 would have to be supplied by some other reference not on this list.

5. Explicit uncertainties

• I do not have the prosecution history for US 5,470,392 or its parent US 5,383,482, so I cannot confirm which, if any, of these references was applied in a rejection, or whether they were cited merely as background. The fact that claims issued over this list is consistent with (but not proof of) the "no anticipation" conclusion above.
• The JP family citations (S56-164522, S61-228610, H07-105430) were not retrieved in full text; my § 102 conclusions do not extend to them. This is an identified gap, not a negative finding.
• The US 4,568,234 reissue (US RE33,341) exists, but I could not retrieve its claim text within budget; the analysis above is based on the original US 4,568,234 disclosure, which is the document on the '392 citation list.
• No authoritative evidence of litigation or a 2026 CAFC appeal involving US 5,470,392 was found; that remains absence of evidence, and with a 2012-11-28 anticipated expiration, any such activity would most plausibly concern royalty tails or a related-family patent rather than prospective injunctive relief.

I'll start by researching the prior-art references listed in the patent's Prior Art section, since the task directs me to use them.

Let me research the remaining prior-art references, including the Japanese family citations and the key "cited by" cleaning-machine references.

Obviousness Analysis — U.S. Pat. No. 5,470,392 under 35 U.S.C. § 103

Scope note. Per the task, this analysis is built from the Prior Art section of the US 5,470,392 page — i.e., the four U.S. patent citations and the three Japanese family citations:

All four U.S. references pre-date the 1992-07-30 priority date and are § 102(b)/§ 102(a)/§ 103-eligible. The JP references are cited in the family (i.e., used against the JP parent), which is consistent with their being prior art.

Date caveat on JPH07105430B2. The listing gives its filing date (1989-10-25) but its "B2" (examined/granted) publication date is 1995-11-13, i.e., after the 1992 priority date. If only the B2 publication is relied on, it is not § 103 prior art; a POSITA would need the corresponding post-1989 kokai (A) publication (~1991) to use it. I could not retrieve that number in the searches available, so I flag this and do not lean on it below. URLs: https://patents.google.com/patent/JPH07105430B2/en

1. Legal framework and the person of ordinary skill

Obviousness is assessed under Graham v. John Deere (scope/content of prior art; differences; PHOSITA level; secondary considerations) as refined by KSR Int'l v. Teleflex. Where the prior art teaches or suggests each element, or where the difference is a predictable variation / known technique used to solve a known problem, the claim is invalid. The patent's own Background section supplies both the known problem and, effectively, an admission of the prior-art architecture.

PHOSITA (proposed): a B.S.-level mechanical/electrical/industrial engineer (or equivalent) with ~2–4 years' experience designing or integrating automated semiconductor fab material-handling equipment (cassette/wafer transports, robots, loaders/unloaders, tool automation), familiar with cassette identification schemes and with the "track"/cluster-tool handling conventions of the early 1990s. This level is consistent with the references themselves — the cited patents are largely systems-integration patents (transfer apparatus, cassette coding, track systems).

2. The assessed claim — element breakdown

Claim 1 is the sole independent claim and requires, in order:

Note that claim 2 (opposite sides), 5 (return the emptied case to the first side), 6 (storage area), 7 (outgoing case taken from storage), 9 (reuse of incoming case as outgoing case), and 10 (robot) are narrowing; the substantive heart of claim 1 is E2/E7 (an ID card physically removed, kept inside the tool, and re-applied) plus E1/E6/E8/E9 (case enters and leaves on the same side, while wafer load/unload of the processing portion occurs at a spaced second side).

3. What each prior-art reference discloses against the elements

US 4,568,234 (Asq Boats) — the wafer-transfer core.

• Discloses an automated system that moves a batch of wafers out of one slotted carrier (plastic cassette) and into another (quartz boat), and back, using a pusher/lifter and jaws; "the steps of the various sequential operations are automatically controlled such that manual assistance is not required except for initiating the operations." This maps to E4/E5/E8 (loading/unloading/processing transfer).
• Expressly contemplates two cassettes handled in a two-step process ("two batches of wafers may be sequentially transferred to or from two different plastic cassettes to a single quartz boat") → relevant to E6/E9 (an outgoing/re-used case).
• Has trolleys transporting the boats/carriers between stations → supports E1/E3/E9 (case transport).
• URL: https://patents.google.com/patent/[US4568234A](/patent/US4568234A)/en (reissue USRE33341).

US 4,985,722 (Tokyo Electron) — the automated handling/robot + control architecture.

• A "track system": wafers held in a cassette-like container (2) are introduced, taken out, conveyed through treating units, and returned to a cassette; it provides "substrate handling means … movable and rotatable in any direction" and "control means for selecting said plurality of treating units … and for controlling operations of the conveying means and substrate handling means."
• This maps to automated cassette-in / robot handling / cassette-out (E1, E3, E4, E6, E8, E9) and supplies the robot of dependent claim 10.
• URL: https://www.freepatentsonline.com/[4985722](/patent/4985722).html

US 5,030,057 (Tel Sagami) — cassette-to-boat transfer with identification/detection and computer control.

• Discloses transferring wafers from a cassette (25 wafers) to a boat, with a pushing mechanism (to lift wafers out of the cassette) and a chuck mechanism (to hold/transport them), all "executed … under the control of a computer based on a preset program."
• Family/related Tel Sagami disclosure describes "providing an identification mechanism for positional alignment … detecting the identification mechanism, and aligning … based on a detection result" — i.e., machine detection of an identification feature as part of automated transfer.
• Maps to E3/E4/E5/E8 and, importantly, shows that automatic detection of an identifying feature on/in connection with a carrier was known in this exact field.
• URL: https://patents.google.com/patent/US5030057

US 4,658,960 (Iwasa) — the cassette-identification (ID) concept and the FA motivation.

• Discloses a cassette bearing machine-readable identification ("color coding") used "in conjunction with color sensing apparatus and with the computer" so that "the wafers in the color coded cassette can be transferred and sorted to the right address … speedily and with no error," and to automate "the transport and other handling process."
• It even names the same-assignee environment: "the Auto-Carrier, being used by the Mitsubishi Electric, the color coded cassette is very useful in handling, sorting, delivering the correct cassette to the correct processing area."
• This supplies the concept and motivation for E2/E7 (an identifying article associated with the cassette that is read/handled automatically), though the code is integral to the cassette, not a separately removed card.
• URL: https://patents.google.com/patent/US4658960

JP S56-164522 (Sony) / JP S61-228610 (Canon) — "transferring and distributing method" and "wafer processing equipment." These are generic pre-1992 Japanese disclosures in the same wafer-distribution/processing field; they are cumulative to the U.S. references on the general in/out and transfer architecture and would supply at most the background "state of the art." I could not retrieve their full texts, so I rely on them only as corroborating art, not as the primary teaching.

Post-dating "Cited By" art (US 5,740,053 Tokyo Electron cleaning-machine monitor; US 6,267,123 Toshiba pod cleaning; Ecolab US 6,463,940 / 7,437,213 "smart rack") — not § 103 prior art (all post-1992), but they are useful only to confirm the trajectory: automating identification of wafer carriers and cleaning tools became routine. Do not treat these as prior art.

4. Proposed § 103 combinations and the motivation to combine

Combination 1 — US 4,658,960 + US 4,568,234 + US 4,985,722 (the "identification + transfer + automated handling" combination)

This is the strongest, most natural combination and arguably anticipates/obviates claim 1's functional result.

• US 4,568,234 provides the mechanism and control to take wafers out of a case and put them back into a case (E4/E5/E8) and to handle two cassettes (E6/E9).
• US 4,985,722 provides the automated loading section + robot "movable and rotatable in any direction" + programmed control that carries cassettes in, moves them through the tool, and carries them out (E1/E3/E6/E9, and claim 10's robot).
• US 4,658,960 provides the identifying indicium on the cassette that travels with the lot and the express reason to read/handle it automatically (E2/E7 concept).

Motivation (KSR rationales):

1. Same field, same problem. All three are semiconductor wafer-handling/carrier patents addressing the same environment (cassette-based fab material handling).
2. Explicit problem recognized in the art. Iwasa states that machine identification of cassettes "automate[s] the transport and other handling process" and prevents mis-delivery — precisely the goal the '392 background calls "full factory automation (FFA)."
3. Known technique to solve a known problem. The '392 patent's own Background admits that ID cards were, in the prior art, removed and re-applied outside the tool ("further operations have to be performed at a certain place outside of the wafer cleaning equipment to remove and keep ID cards …"). Once the problem is stated as known, relocating that manual step inside the tool — using the very robots (US 4,985,722) already present to move cassettes — is a predictable deployment of known elements with a reasonable expectation of success.
4. Common assignee/environment link. Iwasa expressly references the Mitsubishi Electric Auto-Carrier, giving an explicit reason a Mitsubishi engineer of ordinary skill would consult it.

Combination 2 — US 5,030,057 + US 4,985,722 + US 4,568,234 (the "cassette-to-processing transfer with detection/control + track robot" combination)

• US 5,030,057 teaches cassette→processing transfer with a pusher/chuck and computer control, and machine detection of an identification feature as part of the transfer cycle.
• US 4,985,722 teaches the automated in/out loading section and handling robot.
• US 4,568,234 teaches the pusher/lifter transfer and re-transfer to a second carrier.

Motivation: Both US 5,030,057 and US 4,985,722 are automated handling systems in the same art, both controlled by stored programs; combining the transfer-plus-detection of the former with the track-system robot of the latter is a routine integration of known elements. There is a reasonable expectation of success because the components are plug-and-play subsystems (load station, transfer device, robot, controller).

Combination 3 — the "integration of carrier-ID handling into the tool" rationale (KSR "design incentive")

Even standing alone, US 4,658,960 supplies a design incentive to keep the identification with the wafer lot through automated handling. Given the admitted prior art of manually removing/reattaching ID cards outside the tool, a POSITA confronting the stated FFA problem would:

• place the ID-card read/remove/re-apply operation on the same lane where the cassettes already enter and leave (claim 1's "first side"), and
• use an existing robot (claim 10),

as a predictable, purely mechanical rearrangement (KSR "arranging parts known to be arrangeable").

5. The crux: what the cited art does not cleanly teach, and why it likely still supports obviousness

Two features deserve scrutiny, and I flag them honestly:

(a) "ID card" removed and stored (E2/E7), rather than a fixed code. US 4,658,960's code is integral to the cassette (painted/molded), and US 5,030,057's identification feature is for boat positional alignment, not a removable lot card. No single listed reference literally shows a removable card pulled off the case and later re-applied. However:

• Claim 1 uses the deliberately generic "ID card identifying the semiconductor wafers," and dependent claims 3/4 merely place it in an "external pocket." A pocket-held card is a predictable mechanical substitute for molded/painted indicia (KSR: known technique / substitution of parts), and the patent itself shows nothing more than a pocket (51) on the cassette (37) holding card (38).
• The functional requirement (identify the lot, keep the identification with the lot through processing) is fully met by the Iwasa concept; removability is a design choice that follows directly from wanting to keep the identification with the wafers while the case is emptied — exactly what happens in US 4,568,234's transfer of the batch out of the plastic cassette.

(b) Same-side in/out (E1/E6/E8/E9) while wafer load/unload occurs at a spaced second side (E3/E4). The '392 patent admits the prior architecture used one side for in and the other for out ("carrying products into the equipment and placing them into a cleaning bath are carried out on one same side …, but carrying products out … is done on the other side"). The claimed improvement — routing the case in and out the same side to reduce the number of robots — is precisely the known problem the patent admits, and combining US 4,985,722's selectable, robot-served treating stations with US 4,568,234's transfer device yields the claimed routing as a predictable layout optimization.

Assessment: a prima facie § 103 case is strong for the functional method of claim 1 as a combination of US 4,658,960 + US 4,568,234 + US 4,985,722 (with US 5,030,057 as an alternative or supplemental teaching of automatic identification/detection). The weakest resistance point is the literal "remove the card and store it, then attach that card to the outgoing case" — the petitioner would bear the burden of showing that a removable pocket card is an obvious design choice over Iwasa's fixed code, which is a rebuttable but real gap.

6. Dependent claims — additional § 103 grounds

Because every dependent claim adds only a known expedient (a side arrangement, a pocket, a buffer/storage station, a robot), they are, with the independent claim, obvious as a matter of the KSR "predictable variations" rationale if claim 1 falls.

7. Rebuttal considerations (secondary considerations / objective indicia)

I did not find evidence of secondary considerations in the record available:

• No evidence of unexpected results — the claimed arrangement is a throughput/robot-count optimization, i.e., the expected benefit.
• No evidence of commercial success nexus, licensing, or industry praise tied to the claims is in the file wrapper excerpt provided.
• Long-felt need cuts both ways: the '392 Background shows the need (FFA; ID cards handled outside the tool) was recognized and stated, which supports obviousness (the problem was known; the art already contained the pieces).
• Copying/industry adoption cannot be shown from the "Cited By" list, and in any event that art post-dates the patent.

The strongest non-obviousness argument the patentee can make is the literal combination of removable-and-stored ID card + same-side case return as an integrated workflow yielding fewer robots — i.e., arguing that no reference teaches or suggests removing the identification from the case at all (as opposed to reading it in place), so the cited art "teaches away" from separating the card from its case. That argument is tenable but narrow, because the separation is the very thing the admitted prior art did (just outside the tool).

8. Conclusion

• Claim 1 is vulnerable to § 103 over the combination US 4,658,960 (cassette identification + FA motivation) + US 4,568,234 (automated wafer transfer out of/into a case) + US 4,985,722 (automated loading section, handling robot, programmed control), with US 5,030,057 supplying additional teaching of automated transfer with machine detection of an identification feature. Motivations: same field; the patent's own admission that ID cards were handled outside the tool; Iwasa's express automation rationale (and its reference to Mitsubishi's own Auto-Carrier); and the KSR "known problem / predictable variation" rationales.
• Claims 2–10 add only known expedients (opposite sides, external pocket, storage/buffer, robot) and are obvious in view of the same references.
• Residual uncertainty / honest caveats:
  1. No single listed reference literally discloses a removable ID card removed and stored inside the tool, then re-applied to the outgoing case; that literal gap is the patentee's best defense and would require the ~"obvious design choice / known substitute" showing.
  2. JPH07105430B2's B2 publication (1995-11-13) post-dates the priority date; its use as § 103 art requires the earlier A publication (not retrieved here). I therefore did not build the case on it.
  3. I could not retrieve the full texts of JPS56-164522 or JPS61-228610; they are treated as cumulative background only.
  4. This is an analyst's invalidity assessment, not a legal opinion or a prosecution record; the examiner evidently allowed these claims over the cited art, so a real challenge would require weighing any unlisted art (e.g., SMIF/automated-carrier ID systems) not present in this page's Prior Art section.

Bottom line: Under § 103, claim 1 would most plausibly be rejected as obvious over US 4,658,960 in view of US 4,568,234 and US 4,985,722 (optionally further in view of US 5,030,057), with all dependent claims obvious over the same art plus routine design choices — subject to the caveats above about the literally "removable card" limitation and the JPH07105430B2 date issue.

Primary sources: https://patents.google.com/patent/US5470392/en · https://patents.google.com/patent/US4568234A/en · https://patents.google.com/patent/US4658960 · https://patents.google.com/patent/US5030057 · https://www.freepatentsonline.com/4985722.html