US 12039332

I'll search for this specific patent number. Let me run several targeted queries.

Let me now search for the granted claims text and any CAFC/litigation references.

Let me attempt to retrieve the granted claim text and check for any litigation involving this patent.

Search & verification note

I ran targeted queries on the exact string "12039332" (and "US 12,039,332") against patent databases (Google Patents, Justia, Patents-Review, Espacenet, Unified Patents, PubChem/patent mirror) and against general CAFC 2026 coverage. Result: I found no CAFC 2026 docket, appeal, or district‑court litigation referencing patent 12,039,332. One query hit returned a false positive — a Brazilian CPF tax number "120.393.328-20" in a municipal purchasing document — which is unrelated. Absence of a hit is not proof that no case exists; I simply could not find one in the sources reachable here.

I also could not retrieve the verbatim granted claim set of US 12,039,332 from the sources available (the Google Patents/Justia pages expose the specification's numbered "Examples" section, which is claim‑like but is not the granted claims). I flag this explicitly below.

Bibliographic summary — US 12,039,332 B2

Sources: https://patents.google.com/patent/[US12039332B2](/patent/US12039332B2)/en ; https://www.patents-review.com/a/20220236989-systems-methods-apparatus-matrix-move.html ; https://patents.justia.com/patent/12039332 ; https://hu.espacenet.com/publicationDetails/originalDocument?FT=D&date=20240716&DB=EPODOC&locale=hu_hu&CC=US&NR=[12039332B2](/patent/12039332B2)&KC=B2&ND=10

Abstract (verbatim)

"Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described."

Plain‑language overview of the disclosure and its independent claims

What the patent is about. It describes a single machine instruction — referred to in the specification as TILEMOVE — that copies an entire two‑dimensional matrix ("tile," stored as a 2‑D overlay on packed data registers, memory, or accelerator storage) from one tile operand to another, element position by element position. The instruction format is given as TILEMOVE{B/W/D/Q} TMM1, TMM2, where B/W/D/Q select byte/word/doubleword/quadword element size, TMM1 is the destination tile identifier (REG field 2844) and TMM2 the source (R/M field 2846). The surrounding context includes tile configuration (TILECONFIG, with a "palette" defining tile name count, bytes per row, rows/columns), tile release (TILERELEASEALL), strided TILELOAD/TILESTORE, context save/restore (XSAVE/XRSTOR) and restart semantics for page faults and unmasked floating‑point exceptions. The stated motivation is that matrix handling is otherwise instruction‑intensive (gather → packed adds → scatter).

Caution on the claims. The numbered "Example 1…Example 24" passages shown on Google Patents/Justia appear in the description as claim‑style enumerated embodiments; the patent's actual granted claims were not exposed by the sources I could reach. The overview below therefore describes the independent‑claim subject matter as disclosed, and I cannot confirm that the granted claims read identically.

The disclosed independent claims fall into four statutory categories:

1. Processor (Example 1). Decode circuitry decodes an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; execution circuitry executes the decoded instruction to move each data element of the identified source matrix to the corresponding data element position of the identified destination matrix. In other words, hardware that natively recognizes and performs a whole‑tile copy as one instruction.

2. Method (Example 8). The same decode‑then‑execute flow expressed as method steps.

3. Non‑transitory machine‑readable medium (Example 15). A stored program instruction causing the processor to perform that method.

4. System (Example 22). A processor plus an accelerator coupled to it, where the accelerator contains the decode circuitry and execution circuitry performing the tile move. (This mirrors the disclosure's matrix‑operations accelerator / grid of chained FMAs.)

Representative dependent subject matter (Examples 2–7, 12–14, 19–21, 23–24):

• The opcode encodes the data‑element size (explicitly doubleword and word are called out).
• Execution moves each row of the source to the corresponding row of the destination, and zeroes any remaining (unconfigured) columns and unconfigured rows of the destination.
• The source matrix operand is implemented as a plurality of registers representing the matrix.
• The execution circuitry raises a fault if the source and destination differ in number of rows, number of columns, or data‑element size.

Additional disclosed execution details (from the specification's FIGS. 25–27 blueprint, whether or not separately claimed): unconfigured destination rows are zeroed; and in an alternative embodiment, rather than physically writing data, the source tile identifier is logically renamed to the destination tile identifier, eliminating the move entirely.

One ambiguity worth noting: the "Examples" block contains a duplicated "Example 24" (the system claim's third dependent element is numbered 24 again, repeating the prior 24). I am reporting this literally as it appears, not correcting it.

Bottom line

US 12,039,332 B2 is an Intel continuation (priority 2017‑03‑20, filed 2022‑01‑28, granted 2024‑07‑16) covering a processor instruction that moves an entire matrix/tile operand into a destination tile, with element‑size encoding, row‑wise copy with zero‑fill of unconfigured positions, register‑backed tile operands, and size‑mismatch faulting. I found no 2026 CAFC docket tied to this number, and I do not have authoritative access to the granted claim language — the claim descriptions above should be treated as disclosure‑level summaries pending confirmation against the issued patent's claim sheet.

I'll search for litigation involving US patent 12039332 across patent litigation sources.

Let me search more targeted litigation databases and the specific patent.

Let me search additional litigation-specific databases and check for any related assertions.

Search Results: Litigation Involving U.S. Patent No. 12,039,332

Bottom line: I found no known litigation involving U.S. Patent No. 12,039,332.

What I searched

I ran searches across general web and patent-litigation-oriented sources (Google Patents, Justia Patents, FreePatentsOnline, PubChem patent record, PatentLeaderboard, plus litigation dockets surfaced by search — CourtListener/RECAP, UniCourt, PacerMonitor, RPX Insight, Unified Patents PTAB filings, and CAFC documents). I specifically queried the exact number 12039332 and "12,039,332".

What the searches returned

• No district court, ITC, PTAB, or CAFC matter naming U.S. 12,039,332 as an asserted or challenged patent appeared in any result.
• All hits for the string "12039332" were false positives unrelated to patents — e.g., an Estonian business registry code (Aeralstewelo OÜ), a Brazilian CPF/national ID fragment, and a GenBank gene identifier (GI-12039332). Per the operating rules, I did not treat these as matches to the patent.
• Litigation-heavy results that did surface (e.g., Netlist v. Samsung/Micron, various IPRs, Unified Patents petitions) involved different patent numbers and are not related to the '332 patent. I excluded them.

About the patent itself (for context)

• Patent: U.S. 12,039,332 B2 — "Systems, methods, and apparatus for matrix move"
• Assignee: Intel Corp (original and current assignee per the record)
• Application No.: US 17/587,637; filed 2022-01-28
• Priority date: 2017-03-20; granted: 2024-07-16
• Subject matter: A TILEMOVE instruction that moves data element-by-element from a source matrix (tile) operand to corresponding positions of a destination matrix (tile) operand, with faulting on mismatched row/column counts or element sizes.
• Status: Active; anticipated expiration listed as 2037-07-01.

This is a portfolio patent held by Intel (a large operating company), not a patent associated with a known monetization/NPE campaign, which is consistent with the absence of litigation found.

Caveats and confidence

• Confidence: moderate-to-high that no litigation exists as of today (April 26, 2026), but not absolute. I could not directly query PACER (paywalled/access-restricted) or the Unified Patents litigation caselist page in an authenticated manner, so negative findings rest on indexed/public search results rather than a definitive docket sweep.
• The patent was granted only in July 2024 and is part of a very large Intel continuation family (related publications include US 2022/0236989 A1, US 2024/0320001 A1, and family members such as US 11,288,068). It is possible a recently filed action is not yet indexed by the sources that surfaced.
• If you need a definitive answer, the reliable next step is a direct PACER docket search and a Unified Patents / Docket Navigator query filtered to this exact patent number — neither of which I was able to complete within this session.

I am not able to confirm any case where U.S. 12,039,332 has been asserted or challenged, and I will not fabricate plaintiff/defendant/case-number details. If you have a specific case number or party name you suspect, I can try to verify that directly.

I'll verify the structured data against live sources before drafting.

PTAB Proceedings on US 12,039,332 — Verification Report

Headline finding: there are no AIA trial proceedings on file against this patent. The canonical structured block reports that the USPTO Open Data Portal returns zero AIA trial proceedings as of the most recent ingest, and my independent web searches surfaced no IPR, PGR, or CBM petition, institution decision, Final Written Decision, or Federal Circuit appeal naming US 12,039,332. I am treating "no PTAB activity on file" as the substantiated answer, with the verification caveat noted below.

Proceedings overview

Total proceedings on file: 0. Breakdown: 0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denials. The patent has never been tested at the PTAB — every claim (including the TILEMOVE-related independent claims and their dependents) is UNTESTED, meaning a defendant today has no PTAB record to leverage and no estoppel shield, but also faces a patent whose validity has never been administratively adjudicated at all. Defensive posture: neutral-to-adverse — you cannot point to a canceled claim, so an IPR-style defense must be built from scratch, and the window for a PGR petition has already closed (see timing note below).

Verification caveat. The structured ODP block is the authoritative source here and it reports no proceedings. Web search returned only generic PTAB materials (unrelated IPRs cited for legal propositions) and no docket entry for this patent. I could not independently corroborate against PTAB E2E in this session; if a petition was filed within the last few weeks it may not yet be indexed. Treat the count as "0 as of the ingest date" and re-run a PTAB E2E query by patent number before relying on it in a filing.

No proceedings to report

Because the count is zero, the per-proceeding template is not populated. Stating it plainly:

• No Inter Partes Review (IPR) has been petitioned or instituted.
• No Post-Grant Review (PGR) has been petitioned or instituted.
• No Covered Business Method (CBM) review — now sunset for all but a closed set of pre-2020 filings — has been filed.
• No petitioner, judge panel, institution decision, FWD, settlement, or CAFC appeal exists to describe. I will not fabricate a proceeding number, panel, or disposition.

Key dates that matter for a defendant

Practical consequence of the dates: PGR is off the table — it requires filing within 9 months of grant, and that window closed 2025-04-16. Any post-grant attack from here is an IPR (patents/printed publications only, §§ 102/103) or an ex parte reexamination. That is a narrower attack surface: § 112 indefiniteness/written-description, § 101 eligibility, and public-use/on-sale art are not available in an IPR.

Second timing trap: if you have been served with a complaint alleging infringement of this patent, § 315(b) gives you one year from service to file an IPR. Given the 2024-07-16 grant, any first-wave assertion very likely started the clock already. Confirm your service date immediately — this is the single most common way a meritorious IPR gets lost.

Strategic summary

Claim status. There is no PTAB claim-level record: no claim of US 12,039,332 has been canceled, confirmed, or construed by the Board. All claims — the TILEMOVE independent claims and their dependents as issued — remain in force and are UNTESTED at the PTAB. The patent's claim set has, however, been shaped by prosecution: the underlying application (17/587,637) is a continuation in a long Intel matrix/tile family with a 2017-03-20 priority date, and the file history shows extensive art cited against sibling cases (e.g., Dandamudi's Addressing Modes, Hwu et al. on CUDA, Dave et al. on FPGA matrix acceleration, MathWorks/MATLAB documentation, and a "Zeroing one or more matrix rows or columns" StackOverflow reference). That prosecution record is your starting prior-art map.

Estoppel landscape. With no FWD, no § 315(e) estoppel has attached to anyone. That cuts both ways. There is no petitioner estopped from re-litigating, and equally no prior petitioner whose lost grounds you can inherit. Any third party may file an IPR tomorrow on any patents/publications art. You are not blocked by another party's estoppel, but you also get no benefit from a prior petitioner's work product.

Pattern signals — none exist for this patent. No repeat petitioner (there is no petitioner), no serial-petition or General Plastic issue, no PTAB appeal activity by Intel, and no defensive aggregator visible in the chain. Notably, Unified Patents maintains a public portal that profiles Intel tile-family patents (e.g., US 12,282,773, "Systems, Methods, and Apparatus for Tile Configuration"), but US 12,039,332 does not appear as a challenged patent in that program on the evidence retrieved. The absence of an aggregator challenge to a 2024-issued Intel patent in a hot AMX/tile-instruction space is itself a mild signal that the commercially relevant claims in this family may be the market-practice siblings (tile configuration, tile load/store, TMMA) rather than the TILEMOVE register-to-register move claimed here.

Why the patent is nonetheless a credible vehicle. TILEMOVE is a register-to-register move, not a memory-touching operation. Per the specification, execution "will cause execution circuitry to move (write) every configured element position of the identified destination matrix (tile) operand with data from corresponding element positions of the identified source matrix (tile) operand," with fault-on-mismatch conditions ("Do the identified source and destination matrix (tile) operands have the same number of rows? / same number of columns? / data elements of the same size?" — FIG. 26). The specification even discloses a rename-based alternative: "the identified source matrix (tile) operand is renamed to be the identified destination matrix (tile) operand. This eliminates the need to do a move and instead uses a logical renaming." That rename disclosure is a double-edged sword — it is a strong invalidity hook (a POSITA may find register renaming/move-elimination well-known, and Intel's own US 2014/0281432 A1, "Systems and Methods for Move Elimination with Bypass Multiple Instantiation Table," is in the cited-art neighborhood) but it also creates infringement-avoidance room (a product that renames rather than copies may be argued outside the literal "move each data element" claim).

Recommended next steps

1. Re-verify the zero count at the source before you rely on it. Run a PTAB E2E / PTAB Public Search by patent number (PTAB E2E: https://ptab.uspto.gov; PTAB decisions: https://www.uspto.gov/patents/ptab/decisions) and cross-check the Google Patents legal-events tab (https://patents.google.com/patent/US12039332/en). If a petition has appeared since the ingest, the analysis above changes materially — an active IPR would give you a § 315(e) estoppel argument against the petitioner and a possible stay vehicle.

2. Confirm your § 315(b) service date now. One year from service of any infringement complaint is a hard bar. If you are inside the window, decide quickly whether to file an IPR; if you are outside it, your PTAB options are limited to joining someone else's instituted IPR (§ 315(c)) — which requires someone else to have filed first.

3. Because there is no FWD to lean on, build the invalidity case in district court where the full § 112/§ 101 toolkit is available. The absence of PTAB activity means you are not estopped from asserting in litigation any ground, but you face the clear-and-convincing standard rather than the PTAB's preponderance standard. The FIG. 26 fault-condition limitations and the FIG. 24 "M rows × N columns" configuration-driven behavior are the natural § 112 indefiniteness and § 103 battlegrounds.

4. Assess the sibling-patent family. The same inventors/assignee span US 10,877,756; US 11,200,055; US 11,977,886; US 12,106,100; US 12,282,773, among others. If you are accused of an AMX/tile-instruction product, you will likely face more than one of these. Coordinating a single prior-art narrative across the family is more efficient than serial one-off challenges, and — under the USPTO's October 2025 proposed rules barring IPRs against patents that have already survived a validity challenge — who files first on any given patent now matters enormously.

5. Treat the zero-count as a signal, not a comfort. Well-asserted patents eventually attract IPRs. A 2024-issued patent with no PTAB activity most plausibly means it has not yet been asserted in litigation, or has been asserted only against parties still inside their § 315(b) window. If you have a demand letter in hand and no IPR exists, you may be one of the first targets — which means the prior-art record is still open and no one else has burned the best references on a failed petition.

Sources consulted: structured "PTAB proceedings on file" block (canonical, ODP-derived); https://patents.google.com/patent/US12039332/en (full specification, examples 1–24, figures 24–27, TILEMOVE execution and fault conditions); publically indexed Intel tile-family patent records. No PTAB decision, institution decision, FWD, settlement, or CAFC opinion specific to US 12,039,332 was located, and none is cited here because none appears to exist.

I'll research the assignment record for US 12039332 across USPTO sources and cross-reference with public corporate records.

Let me pull the Google Patents legal events page and search for specific assignment records.

Let me look for the specific assignment record and the Google Patents legal events for this patent.

I was unable to retrieve the recorded assignment metadata directly (detailed caveat below). The findings below distinguish clearly between what the authoritative patent text and indexed records establish and what could not be confirmed.

Inventors

All eight named inventors, with their listed residences (from the front page of US 12,039,332 and its sibling Intel filings US 11,200,055 B2 and US 11,163,565 B2, which share this team):

Employer determination: The application was filed by Intel Corporation as applicant, and every residence listed corresponds to an established Intel design site (Haifa/Kiryat Tivon, Barcelona, Hillsboro, Chandler, San Jose/Santa Clara, Lexington). High confidence all eight were Intel employees at filing; this is not inferred from naming alone but from the applicant-of-record combined with site co-location.

Unusual-pattern check: No evidence of the pre-fire-sale tell (all inventors departing the assignee within 12 months of filing). This team is a long-lived Intel matrix/tile-instruction group — the same names (Valentine, Sperber, Charney, Baum, Corbal, Toll, Heinecke, Ould-Ahmed-Vall) recur together across Intel matrix filings from 2017 through 2024 (e.g., US 11,200,055; US 11,163,565; US 11,869,389; US 11,714,642-family). No departure signal.

Original assignee

Intel Corporation (Santa Clara, CA) — named as original and current assignee on the face of the patent and in the Google Patents record.

• Primary line of business: semiconductor design and manufacturing (x86 CPUs, accelerators, platforms).
• Product embodying the claims: The claims are directed to a TILEMOVE instruction operating on two-dimensional matrix ("tile") operands, within the same tile-instruction architecture (TILECONFIG, TILELOAD/TILESTORE, TMMA) described throughout the specification. This maps directly onto Intel's Advanced Matrix Extensions (AMX) tile instruction set, introduced with 4th Gen Xeon Scalable ("Sapphire Rapids"). Intel is thus an operating company whose shipping silicon implements the claimed tile-move behavior. (I state the AMX mapping as a strong correspondence, not a legal adjudication of claim coverage.)
• Current status: Operating. Intel has undergone significant restructuring and cost-cutting in 2024–2025, but it has not filed for bankruptcy and remains an active operating concern and the record owner.

Assignment timeline

I could not retrieve or verify any recorded assignment entry for US 12,039,332. My searches did not surface a reel/frame, conveyance type, or correspondent for this patent. I therefore make no claim about reel/frame numbers, execution dates, or recording dates — none can be stated without fabrication.

What the available records do establish:

• The Google Patents legal-events record provided for this patent lists only prosecution lifecycle events (application filed 2022-01-28, publication of US 2022/0236989 A1 on 2022-07-28, grant 2024-07-16, anticipated expiration 2037-07-01). No post-issuance assignment event appears.
• The patent's own front page and indexed records show Intel Corp as both original and current assignee, with no successor owner.
• The application is a continuation in a large Intel family (priority 2017-03-20; sibling filings include US 11,200,055 B2 and US 11,163,565 B2). For continuations, the inventors→Intel assignment is normally recorded against the family and carried forward, but I could not pull the specific entry.

Practical reading: On the evidence available, the ownership chain appears to be a single link — inventors → Intel Corporation — with no subsequent transfer. That is itself the finding: no recorded change of owner, so the original operating assignee still holds the patent. However, because I could not open the Patent Assignment Center record directly to confirm the exact reel/frame and correspondent, treat the "single link" characterization as probable, not verified.

Verification link (search by patent number):
https://assignmentcenter.uspto.gov/ and https://assignment.uspto.gov/patent/index.html

(Had I been able to reach the Assignment Center, this section would list each entry as: executed date / recorded date — Reel NNNNNN/NNNN — conveyance — assignor — assignee — correspondent — context. I have deliberately left that table out rather than populate it with unverifiable values.)

Timeline diagram

Rendered from confirmed public-record facts only (filing, publication, grant). I have not inserted any assignment event, because none was verified.

timeline
    title Ownership of US 12039332
    2017 : Priority date established
    2022 : Continuation filed by Intel
         : Application published
    2024 : Patent granted
         : Intel remains assignee

NPE / troll-pattern signals

Verdict

Insufficient data.

Per the strict definition ("no records, or only the original assignment"), this patent falls in that bucket: the only ownership event I could establish is the original inventors→Intel assignment, and I could not retrieve the underlying reel/frame or correspondent to formally document even that one link. That said, the substance of the record points the other way from a troll pattern — the chain terminates at Intel Corporation, an operating company that ships silicon (AMX-family tile instructions) implementing the claimed tile-move behavior, with no recorded post-issuance transfer and no known litigation (consistent with the earlier litigation finding and with the Google Patents legal-events entry). There is therefore no evidence of any NPE signal; the honest verdict is "insufficient data" rather than "operating-company assertion," because the latter label requires an active assertion campaign, which is absent.

Confidence caveat: The absence of a retrievable assignment record is not proof that no post-issuance record exists. The reliable next step is a direct query in the USPTO Patent Assignment Center filtered to US 12,039,332 (and to application 17/587,637), plus a Docket Navigator / PACER sweep, to confirm the single-link chain and capture the correspondent of record. I was unable to complete either within this session and have not invented the details in their place.

I'll research the prior art citations for US 12,039,332. Let me run targeted searches.

Let me dig deeper into the specific prior-art citations for this patent.

I found a family member (US 11,288,068) with its References Cited section. Let me get the specific citations for US 12,039,332 itself.

Prior‑Art Analysis — US 12,039,332 B2 ("Systems, methods, and apparatus for matrix move")

⚠️ Search status and an important limitation (read first)

The task asked me to pull the USPTO citation record for US 12,039,332 specifically and analyze every cited reference. I must be transparent about what the reachable sources did and did not yield in this session — and I will not fabricate a "References Cited" list.

• I could not retrieve the verbatim front‑page "(56) References Cited" block of US 12,039,332 itself. The Google Patents landing page and Justia page expose the specification and the (claim‑style) "Example" block, but the parsed text returned to me did not include the printed citation list, and I exhausted my search steps before I could open the granted‑patent PDF's front page.
• What I could partially observe is the "(56) References Cited" section of a direct family member that shares this exact specification — US 11,288,068 B2 (same title, same inventors, same examiner Michael Sun, same law firm Nicholson De Vos Webster & Elliott, Appl. 16/487,747, the §371 of PCT/US2017/040545 claiming priority to US provisional 62/473,732 filed 2017‑03‑20). US 12,039,332 is a continuation in that same family (appl. 17/587,637, filed 2022‑01‑28).
• A PubChem patent record for "US‑12039332‑B2" returned a long list of associated document identifiers, but without clear labels distinguishing backward citations (art cited against the patent) from forward citations ("Cited By"). I therefore treat that list as candidate leads, role unverified.

Accordingly, the below is split into (A) references I could directly observe in the family record, (B) candidate references from the citation index, and (C) a conditional §102 assessment. Anything I cannot support from a retrieved source is flagged as unverified — per operating rules I will not invent dates or content.

A. References directly observed in the family record (US 11,288,068 front page)

These appeared under the "(56) References Cited" heading of the sibling patent US 11,288,068 B2. Because the '332 patent shares the specification and examiner, these are the most likely §102/§103 art applied to the same subject matter — but I cannot yet confirm they appear on the '332 front page.

Caveat: the snippet I recovered truncated the full "(56)" list (it jumped from the 1991 U.S. items straight to the EP items and the NPL). There are almost certainly more U.S. patent documents between them that the parse dropped. I am not going to invent them.

I also cannot yet state the substance of A1–A4. I do not have high‑confidence text for US 4,310,879 or US 5,025,407, and I will not describe them from memory as if verified. A1/A2 predate the tile/SIMD‑matrix era and are almost certainly cited as general data‑movement / register‑array background rather than as anticipatory art for the tile‑move claims.

B. Candidate references from the PubChem citation index for US‑12039332‑B2

The record returned a large identifier list. Representative entries (role — backward vs. forward — unverified):

• US 2014/006753 A1; US 8,626,815 B1; US 2014/019713 A1; US 2014/032876 A1; US 2014/052969 A1; US 2014/068230 A1
• US 2014/149480 A1; US 2014/157287 A1; US 2014/172937 A1; US 8,760,994 B2; US 8,817,033 B2; US 8,825,988 B2
• US 8,904,148 B2; US 8,943,119 B2; US 8,984,043 B2; US 9,098,460 B2
• US 2015/054024 A1; US 2015/199266 A1; US 2015/227367 A1; US 2015/242267 A1; US 2015/378734 A1
• WO 2016/003740 A1; US 2016/011870 A1; WO 2016/075158 A1; US 2016/165321 A1; WO 2016/105727 A1; US 2016/188337 A1; WO 2016/105841 A1; US 2016/239706 A1; US 9,442,723 B2; US 9,519,947 B2; US 2017/004089 A1; US 9,557,998 B2; US 2017/053375 A1; US 2017/060811 A1; US 2017/097824 A1; US 9,703,708 B2
• US 2018/0004513 A1 (APP); US 2018/0004510 A1 (SEA); US 2018/032477 A1; US 9,906,359 B2
• US 2019/0042202 A1; US 2019/0042235 A1; US 2019/0042248 A1; US 2019/0042254/255/256/257/260/261 A1; US 2019/0042448 A1; US 2019/0042540/541/542 A1 (a large Intel 2019 cluster)
• US 10,073,815 B2; US 10,146,535 B2; US 10,191,744 B2; US 10,073,815 B2; US 9,996,907 B2; US 9,996,350 B2; WO 2018/125250 A1; WO 2018/174934 A1; WO 2018/174927 A1; WO 2019/002811 A1

How to read this list (my tentative hypothesis, not confirmed): the 2019/2018 cluster — especially the US 2018/0004510‑A1 and US 2018/0004513‑A1 applications and the US 2019/00422xx‑A1 family — are plausibly Intel's contemporaneous tile/TMMA patent publications (the same program that produced the '332 family) and are therefore the most technically on‑point potentially anticipatory references for a "move an entire tile operand" claim. But every identifier above has a role that is unverified: some are almost certainly forward citations ("Cited By," i.e., later patents citing '332) rather than art cited against '332. I am presenting them as leads to verify, not as an established citation record.

C. Conditional §102 assessment against the independent claims

Because I do not have (i) the verbatim granted claims of '332 or (ii) verified full text of the cited references, the following is a framework, not a concluded anticipation opinion. I map the disclosure‑level independent claims (per the previously generated section: processor, method, machine‑readable medium, system — each requiring decode of an instruction with opcode + source matrix operand id + destination matrix operand id, and execution to move each source element to the corresponding destination element position) to candidate references.

Net preliminary view (low confidence): the technically on‑point art for this disclosure lives in the 2018–2019 Intel tile/TMMA publication cluster (candidate group B, notably US 2018/0004510 A1 and US 2018/0004513 A1). If those publications disclose a single‑instruction tile‑to‑tile move with tile operand identifiers and element‑size encoding, they would be the references most worth a full §102 element‑by‑element chart. I cannot today confirm they do, because I could not open their full text or confirm that any of them was actually cited (as opposed to merely co‑filed) in the '332 record.

D. What must be done to convert this into a defensible §102 analysis

1. Obtain the true front page of US 12,039,332 (USPTO PatentCenter / the granted PDF) to capture the exact "(56) References Cited" and "(56) References Cited by the Examiner" lists, with examiner‑initiated vs. applicant‑initiated distinctions (Form SB/08a).
2. Pull the file wrapper (PatentCenter / Global Dossier) to see which references the examiner actually applied under §102 vs. §103, and any information‑disclosure statements.
3. Retrieve full text of the 2018–2019 Intel tile publications (US 2018/0004510 A1, US 2018/0004513 A1, US 2019/00422xx family) and chart each claim element.
4. Confirm the effective filing date for §102 art: the '332 claim set is a continuation claiming priority to 2017‑03‑20 (provisional 62/473,732), subject to any intervening developments — so art must predate the relevant priority to qualify under §102(a)/(e).

Honest bottom line

• I did not obtain, and will not invent, the definitive USPTO "References Cited" list for US 12,039,332. That is the core deliverable you asked for, and I could not retrieve it from the reachable sources in this session.
• The only citation data I directly observed came from the sibling patent US 11,288,068 B2 (same spec/examiner): US 4,310,879 A (Pandeya, 1982), US 5,025,407 A (Gulley, 1991), EP 3547120 A1 (2019), EP 3646169 A1 (2020), and the Crago et al. ACM TACO 2018 NPL reference — with the U.S. list visibly truncated.
• The candidate lead set from the PubChem index (2018–2019 Intel tile/TMMA publications, esp. US 2018/0004510 A1 and US 2018/0004513 A1) is the technically most relevant material for the tile‑move claims, but its role (cited‑against vs. citing) is unverified.
• I cannot responsibly assert that any specific reference anticipates any specific claim of US 12,039,332 under §102 until I have the granted claim text and the verified citation record. I am explicitly declining to fabricate that mapping.

If you can supply the front‑page PDF or the PatentCenter file wrapper for 12,039,332 (or confirm access to it), I will build the complete, element‑by‑element §102 chart you requested.

I'll research prior art relevant to the TILEMOVE claims before drafting the § 103 analysis.

Let me dig for actual prior-art references and cited documents in this family.

I hit the session's search limit, so the following is the analysis I can support with what the searches returned plus general technical knowledge. I flag evidentiary gaps explicitly rather than paper over them.

Obviousness Analysis — U.S. 12,039,332 B2 ("Systems, methods, and apparatus for matrix move") under 35 U.S.C. § 103

0. Threshold caveats (must be stated before the analysis)

1. Claim text. As noted in the earlier sections, I could not retrieve the verbatim granted claims of US 12,039,332. The analysis below maps to the disclosed claim-category subject matter (Examples 1, 8, 15, 22 and their dependents), which is identical in wording across the family (e.g., https://patents.justia.com/patent/20200233665 and https://www.freepatentsonline.com/y2020/0233665.html). If the granted claims differ (scope, added limitations, different statutory category), the conclusions here must be re-run.
2. "Prior Art section of this page." The Google Patents page supplied in this project exposes only prior-art keywords (matrix, source, instruction, tile, data element) and a prior-art date of 2017-03-20. It does not expose a "References Cited" list for the '332 patent. I therefore anchored the analysis to that 2017-03-20 cut-off and to the field indicated by those keywords, and supplemented with references I could verify elsewhere.
3. I found no litigation, IPR, or PTAB record tying US 12,039,332 to any prior-art challenge (consistent with the earlier section). So there is no real-world invalidity holding to report — this is a forward-looking hypothetical analysis.

1. Governing law/framework

Obviousness is judged from the perspective of a person having ordinary skill in the art (POSITA) at the effective filing date, under the Graham factors as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). A combination of familiar elements according to known methods is obvious when it yields no more than predictable results; a "finite number of identified, predictable solutions" makes the combination obvious, and a strong motivation to combine can come from the problem to be solved, market/design pressures, or the reference's own teaching. Here the relevant POSITA is a computer-architecture/microarchitecture engineer with knowledge of an ISA, SIMD/vector register files, and matrix/tensor accelerator design — a crowded, mature art, which itself strengthens the obviousness case.

The four independent claim categories (processor / method / medium / system) all recite the same core: decode circuitry for an instruction having fields for an opcode + source matrix operand ID + destination matrix operand ID, and execution circuitry to move each data element of the source to a corresponding data-element position of the destination. Dependents add: opcode-encoded element size (byte/word/doubleword/quadword); row-wise copy with zero-fill of remaining/unconfigured columns and rows; register-implemented tile operands; and faulting on row/column/element-size mismatch. A disclosed embodiment also uses logical renaming instead of a physical write.

2. Prior-art mapped against the disclosed claim elements

Two references that surfaced (WO 2022/023701 A1, Arm, "data transfer instruction" for 2-D array register storage; US 2022/0100515 A1 / US 11,579,880, Intel TileMoveTo1D/1D) are not prior art to a 2017-03-20 date and I do not use them as such — I cite them only to show that the field converged on exactly this design (useful for the KSR "predictable solution" argument, but not as anticipatory art).

3. The proposed § 103 combinations and motivations

Combination A — [Baseline register-move instruction] + [2-D/matrix register file (Brokenshire/Moyer IBM work)] + [tile-config/zero-fill conventions].
A POSITA starting from MOV/VMOVDQA (element-wise, position-aligned copy) and from known 2-D register-file architectures (IBM's 2-D row/column-addressable register file) would have found it an identified, predictable solution to define a single instruction whose operands are entire 2-D registers and which copies row-by-row. Motivation: the '332 spec states the very problem — that matrix handling is otherwise "instruction intensive," requiring gather → packed adds → scatter. Collapsing that to one instruction is precisely the "better, faster, cheaper" design pressure KSR recognizes, and the result is the predictable sum of the two references' functions (a move instruction plus 2-D operands).

Combination B — Combination A + [masked/zeroing writes (AVX-512-style)] + [opcode-encoded element size].
The dependent "zero any remaining/unconfigured columns and rows" limitation is the well-known zero-writemask behavior; the B/W/D/Q size field is the well-known element-width encoding. Motivation: (i) supporting multiple datatypes with one instruction family is standard ISA design; (ii) zeroing non-participating positions prevents stale-data leakage — the '332 spec itself worries about garbage in unconfigured columns on XRSTOR. No new mechanism is required; only the application of a known masking idiom to the known 2-D operand.

Combination C — Combination A + [tile-configuration consistency checking].
Faulting on a row/column/element-size mismatch is obvious in view of the TILECONFIG consistency-check teaching in the same field: once tiles have configurable shapes, checking that two operands are conformable before a bulk transfer is a routine error-detection step with a predictable benefit (avoiding malformed writes).

Combination D (system claim) — [chained-FMA matrix accelerator] + [decode/execute of the tile-move instruction].
The '332's own FIG. 3/6 describe a matrix-operations accelerator built from a grid of chained FMAs. Putting the tile-move decode/execute inside such an accelerator is the ordinary placement decision for co-processor ISA extensions (do the data movement where the data already lives), and yields nothing more than the expected result.

Combination E (rigor/robustness claim) — + [move-elimination/renaming art].
The disclosed "rename source tile to destination tile" embodiment is obvious over register-renaming and move-elimination art (e.g., US 11,714,652 B2), where a copy is resolved by pointer indirection rather than data movement.

4. The strongest structural weakness to attack the patent: the priority date

This is where I would focus an invalidity case, and it deserves emphasis:

• The '332 claims priority to 2017-03-20, but the application itself was filed 2022-01-28 and is a late continuation. If any granted claim is not fully supported by the 2017-03-20 priority filing (e.g., added matter), its § 102 date slides forward. In that event, Intel's own intervening publications become available as art under § 102(a)(1)/(a)(2) (35 U.S.C. § 374 for the English-language PCT): WO 2018/174935 A1 (pub. 2018-09-27), US 2020/0233665 A1 (pub. 2020-07-23), and US 2022/0197652 A1 — all of which expressly describe TILEMOVE, the B/W/D/Q encoding, zero-fill, register-backed tiles, and mismatch faulting.
• Counter-argument the patent owner will raise: the common-ownership exception (§ 102(b)(2)(C), both owned by Intel) and/or the "obtained from the same inventor" exception (§ 102(b)(2)(A)), plus a perfected priority claim, defeat that art. So this line is only dispositive if the priority claim is broken.
• Net: absent a priority defect, the intra-family publications are likely disqualified art, and the case must rest on the third-party prior art in §2 (IBM 2-D register file, masked-move/zeroing, general register-move, accelerator art).

5. Counter-arguments the patent owner can make (be balanced)

• No single reference and no proffered combination was actually retrieved for the granted claims — I could not obtain the claim sheet, so I cannot assert with confidence that any combination discloses every limitation.
• The specific instruction-format encoding (TILEMOVE{B/W/D/Q} TMM1, TMM2 with TMM1 as REG and TMM2 as R/M) and the tile "palette"/configuration register machinery are fairly specific; a patent owner will argue the combination is not taught by the cited 2-D-register-file art, which addresses general-purpose SIMD rather than a tile ISA with palettes.
• Secondary considerations (if any evidence exists) — e.g., industry adoption of Intel AMX, licensing — could rebut, though intent-to-commercialize alone is weak absent nexus.

6. Bottom line

• Confidence: moderate. On the disclosure-level claim subject matter, the independent claims (decode a tile-move instruction with opcode + source/destination tile IDs; execute element-position-aligned tile copy) are highly vulnerable to § 103 as a predictable combination of (a) conventional register-move instructions, (b) known 2-D/matrix register-file architectures (e.g., IBM's Brokenshire/Moyer work), and (c) conventional masked/zeroing and element-size-encoding practice — with the specification's own "matrix handling is instruction-intensive" statement supplying the motivation.
• The dependent features (B/W/D/Q size encoding, zero-fill of unconfigured positions, register-backed tiles, mismatch faulting) each map onto known idioms and are individually and collectively obvious.
• The cleanest route for a challenger, however, is procedural, not evidentiary: attack the 2017-03-20 priority, which would unlock Intel's own intervening publications (WO 2018/174935 A1; US 2020/0233665 A1) as art.
• I could not verify the verbatim granted claims, a "References Cited" list for the '332 patent, or any pre-2017 third-party reference that discloses a literal tile-to-tile single instruction. Those gaps mean I will not state a flat "the claims are invalid," only that on the available record the claims should not have survived § 103 over the combinations above. If you can supply the granted claim sheet, the '332's cited references, or a specific target reference, I can tighten this into an element-by-element chart.