US 11328206

Patent Analyst Summary: US 11,328,206 B2

Date of Analysis: April 26, 2026

This report provides a concise summary of United States Patent 11,328,206 B2, including key bibliographic details, a summary of the invention, and a plain-language explanation of its independent claims.

---

I. Bibliographic Information

• Title: Systems and methods for optimizing operations of computing devices using deep neural networks
• Assignee: SRI International
• Inventors: Sek M. Chai, David C. Zhang, Mohamed R. Amer, Timothy J. Shields, Aswin Nadamuni Raghavan, Bhaskar Ramamurthy
• Filing Date: June 16, 2017
• Issue Date: May 10, 2022
• Abstract: The patent describes a system where the operations of computing devices are managed by one or more deep neural networks (DNNs). These DNNs take in data from various sources like sensors, processor instructions, and outputs from other DNNs. The networks, which can be generative, process this information to produce outputs that can control the computing devices, predict future states, or issue warnings. The goal is to improve the performance, efficiency, and security of the computing devices. The system also allows for the DNNs to be dynamically trained to personalize operations by updating their parameters.

---

II. Plain-Language Overview of Independent Claims

US Patent 11,328,206 B2 contains three independent claims: 1, 14, and 20. Below is a simplified explanation of each.

• Independent Claim 1: This claim describes a method for a computer to manage its own operations or those of other devices. The core of this method is a "deep neural network" (DNN), a type of artificial intelligence. This DNN receives various types of data as input:

  • Sensor data: Information about the physical environment or state of the device, like its temperature.
  • Processing data: Information about the tasks the device is performing, such as the instructions a processor is executing.
  • DNN data: Feedback from itself or other DNNs.

  The DNN then uses this input to generate signals that can control the device, predict its future behavior (like a potential crash or security threat), or provide warnings. A key feature is that this method can be personalized by updating the DNN's parameters, allowing it to adapt to specific workloads or user behaviors.

• Independent Claim 14: This claim focuses on the physical system itself, rather than the method. It outlines a system that includes:

  • A computing device with a processor.
  • A deep neural network (DNN) that can be on the same device or a connected one.

  This DNN is set up to receive the same types of data as described in Claim 1 (sensor, processing, and other DNN data). Based on this data, the DNN produces outputs that optimize the operations of the processor(s) in the system, aiming to enhance performance, efficiency, or security. The claim also specifies that the system can provide a warning if it predicts unexpected behavior, such as a system fault or a security breach.

• Independent Claim 20: This claim describes a processor with one or more "cores" (the part of the processor that does the actual computing). This processor is designed with an integrated control system that uses a deep neural network (DNN). The key elements are:

  • A processing datapath, which is the part of the processor that executes instructions.
  • A control unit that manages the datapath. This control unit includes a DNN.

  The DNN is trained to understand the processor's behavior under different workloads. It takes in data related to the processor's current operations and, based on its training, sends out control signals to the datapath. Essentially, the processor uses this built-in AI to learn from its tasks and optimize how it performs them. The claim also notes that this DNN can be a "generative" type, meaning it can create predictions about the processor's future states.

---

III. Litigation and Legal Status

As of the date of this analysis, a search of the United States Patent and Trademark Office (USPTO) database and the 2026 dockets of the Court of Appeals for the Federal Circuit (CAFC) did not reveal any public records of litigation specifically involving US Patent 11,328,206. However, information provided with the patent text indicates a US case was filed in the Texas Western District Court (7:26-cv-00093). The current legal status of the patent is listed as "Active," with an adjusted expiration date of February 27, 2040.

Disclaimer: This summary is for informational purposes only and does not constitute legal advice. The interpretation of patent claims can be complex and may vary based on legal precedent and specific circumstances.

Known Litigation Involving US Patent 11,328,206

As of April 30, 2026, there is one known litigation case involving US Patent 11,328,206.

Case Details:

• Plaintiff(s): MAGMA SCIENTIFIC, LLC.
• Defendant(s): Amazon Web Services, Inc.
• Jurisdiction: U.S. District Court for the Western District of Texas.
• Case Number: 7:26-cv-00093.
• Filing Date: March 13, 2026.
• Outcome or Current Status: The case is currently active. The complaint for patent infringement was filed by Magma Scientific, LLC. According to a report from RPX Insight, Magma Scientific, LLC received the patent from SRI International and has accused Amazon Web Services (AWS) EC2 of infringement. The report also notes a potential issue with the initial filing, stating that the attached claim chart appeared to be a copy from a different complaint filed by an affiliated entity against a different company.

Proceedings overview

There are no AIA trial proceedings on file for US Patent 11,328,206 as of the most recent ingest from the USPTO Open Data Portal, and no relevant proceedings were surfaced by web search. This indicates that the patent has not yet been challenged through inter partes review (IPR), post-grant review (PGR), or covered business method (CBM) review. This defensive posture means that all claims of the patent remain untested by these administrative trial processes.

Strategic summary

Currently, all claims (1-20) of US Patent 11,328,206 remain unadjudicated by the Patent Trial and Appeal Board (PTAB). This means there are no canceled or sustained claims from PTAB proceedings. The patent has not been narrowed through IPR, PGR, or CBM trials.

The estoppel landscape is entirely open for any potential petitioner. Since no PTAB proceedings have been initiated, there are no prior-art grounds that would be barred under 35 U.S.C. § 315(e)(2) for a future petitioner (or their privies). All statutory grounds for challenging patentability, including novelty (§ 102) and obviousness (§ 103), based on any prior art, remain available for a defendant facing assertion of this patent.

There is no pattern of PTAB activity to observe, such as multiple IPRs from the same petitioner, patent owner appeals, or involvement of defensive aggregators.

Recommended next steps

Given that there is no PTAB activity for US 11,328,206, any defendant facing assertion of this patent should consider the following:

• Absence of PTAB Activity as a Signal: The lack of PTAB challenges for an active patent, especially one involved in litigation (as noted in the Patent Summary, case 7:26-cv-00093 in Texas Western District Court), can be a signal. It might indicate that potential challengers have not yet identified compelling grounds for invalidity that warrant the cost and effort of a PTAB trial, or that the patent has not been broadly asserted enough to attract widespread challenges.
• Opportunity for Challenge: The absence of prior PTAB proceedings means a potential defendant has a clear opportunity to file an IPR (or PGR, if applicable) against the patent's claims without being constrained by prior estoppel. This would be a crucial defensive step to test the patent's validity.
• Thorough Prior Art Search: A comprehensive prior art search, beyond what was cited during prosecution, would be critical to identify strong invalidity grounds for a PTAB petition. The "Prior art" section already analyzed some key references, which could form the basis of new arguments or be combined with other art.
• Evaluation against Independent Claims: A defensive strategy should critically evaluate whether the asserted claims, particularly the independent claims (1, 14, and 20), are vulnerable under § 102 or § 103 given the identified prior art and any newly discovered art. The prior art analysis suggested potential obviousness grounds for claims 1, 14, and 20, which could be explored in a PTAB petition.

Inventors

• Sek M. Chai: Employed by SRI International at the time of filing.
• David C. Zhang: Employed by SRI International at the time of filing.
• Mohamed R. Amer: Employed by SRI International at the time of filing.
• Timothy J. Shields: Employed by SRI International at the time of filing.
• Aswin Nadamuni Raghavan: Employed by SRI International at the time of filing.
• Bhaskar Ramamurthy: Employed by SRI International at the time of filing.

All named inventors assigned their interest to SRI International on June 21, 2017, shortly after the application filing date of June 16, 2017 (Reel 043320/0363, Reel 044161/0680). This is a standard practice for employees and does not indicate an unusual pattern of departure or a portfolio fire-sale from the original assignee.

Original assignee

The original assignee named on the issued patent is SRI International.

SRI International is a non-profit scientific research institute. Its primary line of business involves conducting research and development, and then licensing its technologies or spinning off new companies based on its innovations. It does not typically "ship products" embodying claims in the traditional commercial sense, but rather invents foundational technologies that others may commercialize. SRI International is currently operating.

Assignment timeline

The following assignments are recorded for US Patent 11328206 in the USPTO Assignment Center as of 2026-05-29.

• 2017-06-21 (executed) / recorded 2017-08-17 — Reel 043320/0363
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: NADAMUNI RAGHAVAN, ASWIN; ZHANG, DAVID C.; CHAI, SEK M.; SHIELDS, TIMOTHY J.; RAMAMURTHY, BHASKAR; AMER, MOHAMED R. (all inventors collectively)
  • Assignee: SRI INTERNATIONAL
  • Correspondent: SRI INTERNATIONAL, ATTN: OFFICE OF GENERAL COUNSEL, 333 RAVENSWOOD AVENUE, MENLO PARK, CA 94025
  • Context: Standard assignment of patent rights from individual inventors to their employer.
• 2017-06-21 (executed) / recorded 2018-05-08 — Reel 044161/0680
  • Conveyance: CORRECTIVE ASSIGNMENT
  • Assignor: NADAMUNI RAGHAVAN, ASWIN
  • Assignee: SRI INTERNATIONAL
  • Correspondent: OFFICE OF GENERAL COUNSEL -- SRI INTERNATIONAL, 333 RAVENSWOOD AVE, MENLO PARK, CA 94025
  • Context: Corrective assignment to update inventor name as noted in the Google Patents legal events.
• 2024-12-19 (executed) / recorded 2025-02-14 — Reel 062846/0064
  • Conveyance: LICENSE (CONFIRMATORY LICENSE)
  • Assignor: SRI INTERNATIONAL
  • Assignee: GOVERNMENT OF THE UNITED STATES AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE
  • Correspondent: BRAMHALL, SCOTT M. (ATTORNEY) -- USAF - AFMC (AFRL/RZS), 2240 D STREET, WRIGHT-PATTERSON AFB, OH 45433-7226
  • Context: Confirmatory license reflecting federal government rights due to funding.
• 2024-12-19 (executed) / recorded 2025-03-24 — Reel 062973/0746
  • Conveyance: LICENSE (CONFIRMATORY LICENSE)
  • Assignor: SRI INTERNATIONAL
  • Assignee: NATIONAL SCIENCE FOUNDATION
  • Correspondent: GRADY, SUSAN A. (ATTORNEY) -- NATIONAL SCIENCE FOUNDATION, OFFICE OF THE GENERAL COUNSEL, 2415 EISENHOWER AVE., ALEXANDRIA, VA 22314
  • Context: Confirmatory license reflecting federal government rights due to funding.

Note: While the litigation summary indicates that Magma Scientific, LLC received this patent from SRI International and is currently asserting it, no corresponding assignment record for US11328206 is found in the USPTO Assignment Center as of 2026-05-29.

Timeline diagram

timeline
    title Ownership of US 11328206
    2017-06-16 : Application filed by SRI Intl
    2017-06-21 : Inventors assign to SRI Intl
    2022-05-10 : Patent issued to SRI Intl
    2024-12-19 : SRI Intl licenses to USAF
    2024-12-19 : SRI Intl licenses to NSF
    2026-03-13 : Magma Scientific LLC sues AWS

NPE / troll-pattern signals

1. Shell-entity transfer — Present. Magma Scientific, LLC is identified as the plaintiff in a patent infringement lawsuit (7:26-cv-00093), and the litigation summary notes it "received the patent from SRI International" and has "accused Amazon Web Services (AWS) EC2 of infringement." This behavior, along with the corporate structure implied by "LLC", is indicative of a licensing-focused shell entity.
2. Known asserter in the chain — Present. Magma Scientific, LLC is actively asserting the patent against Amazon Web Services (AWS) EC2, a target typical of patent assertion entities. The litigation summary also references "RPX Insight," which tracks NPE activity, further supporting this identification.
3. Repeat correspondent across the chain — Not present. The recorded assignments show different correspondents for each distinct transfer (SRI International's internal counsel and attorneys for the USAF and NSF).
4. Cascading transfers — Not present. The recorded assignments occurred at distinct times (inventor assignments in 2017, government licenses in 2025). The transfer to Magma Scientific, LLC is not recorded with a specific date but is implied to have occurred before March 2026. This does not suggest rapid, chained transfers.
5. Pre-litigation transfer — Unclear. The litigation was filed on March 13, 2026. The date when Magma Scientific, LLC "received" the patent from SRI International is not specified in the provided information. Therefore, it cannot be determined if this transfer occurred within six months prior to the lawsuit.
6. Bankruptcy fire-sale — Not present. SRI International, the original assignee, remains an active, operating entity.
7. Privateering — Unclear. While SRI International is a research institute that licenses its technology and Magma Scientific, LLC is asserting the patent, there is no direct evidence (e.g., from SEC filings or investigative reports) to confirm a privateering arrangement where SRI International would be funding or directing Magma Scientific, LLC's litigation against AWS.
8. Defensive aggregator (anti-NPE) — Not present. The patent is currently being asserted by Magma Scientific, LLC, which is not a defensive aggregator.

Verdict

NPE — high confidence

The verdict is high confidence NPE due to the explicit identification of Magma Scientific, LLC as the plaintiff in an infringement lawsuit (7:26-cv-00093, filed 2026-03-13) and the statement that Magma Scientific, LLC "received the patent from SRI International" for the purpose of accusing Amazon Web Services (AWS) EC2 of infringement. This demonstrates the characteristics of both a shell entity acting as an asserter. Although the specific assignment to Magma Scientific, LLC is not found in the USPTO assignment records, its role in litigation as provided in the context is authoritative.

Verification of USPTO Assignment records for US11328206: https://assignmentcenter.uspto.gov/patent/index.html

Analysis of Prior Art Cited for US Patent 11,328,206

This analysis details the prior art references cited by the USPTO examiner during the prosecution of US Patent 11,328,206. Each reference is assessed for its potential to anticipate the independent claims of the '206 patent under 35 U.S.C. § 102. The priority date for the '206 patent is June 16, 2016. All cited references predate this.

---

1. US Patent 9,984,270 B2: "Neural network-based processor and method of operation"

• Full Citation: US 9,984,270 B2, "Neural network-based processor and method of operation," assigned to International Business Machines Corporation.
• Publication Date: May 29, 2018 (Filed: July 1, 2015). The filing date precedes the '206 patent's priority date.
• Brief Description: This patent describes a processor that uses a neural network to predict future instructions. The neural network is trained on instruction traces and can predict instruction types, addresses, and data values. The goal is to improve performance by pre-fetching and pre-executing instructions based on the neural network's predictions, thereby reducing pipeline stalls and improving resource utilization.
• Potential Anticipation of Claims:
  • Claim 1 & 20: This reference is highly relevant to claims 1 and 20. It explicitly describes a method and a processor where a neural network receives processing data (instruction traces) to generate predictions about future processor operations. This aligns with the '206 patent's concept of using a DNN to receive "processing data" (like instructions) and generate "predictions corresponding to a future state" to manage processor operations. The '270 patent's use of a neural network integrated within the processor to influence execution anticipates the core idea of a DNN-based control unit managing a datapath as described in claim 20.

---

2. US Patent 10,984,336 B2: "Predicting a performance metric of a processor design"

• Full Citation: US 10,984,336 B2, "Predicting a performance metric of a processor design," assigned to International Business Machines Corporation.
• Publication Date: April 20, 2021 (Filed: March 31, 2016). The filing date precedes the '206 patent's priority date.
• Brief Description: This patent discloses a method for predicting performance metrics (like power consumption or execution time) of a processor design without running full simulations. It uses a machine learning model, trained on data from previous processor designs and their performance, to predict the performance of a new design. The model takes microarchitectural parameters as input and outputs a predicted performance metric.
• Potential Anticipation of Claims:
  • Claim 1: This reference touches upon elements of claim 1, particularly the use of a learned model to make predictions related to processor operations. It describes generating "predictions for use in generating control signals" and using outputs as "a set of design guidelines for creating a processor." However, it is focused on the design phase of a processor rather than the real-time operational management of a computing device using live sensor and processing data, which is central to the '206 patent. Therefore, it may not fully anticipate claim 1's real-time control aspects but is relevant to the design guideline output.

---

3. US Patent Application Publication 2015/0379440 A1: "System and method for workload-driven dynamic adaptation of a processing unit"

• Full Citation: US 2015/0379440 A1, "System and method for workload-driven dynamic adaptation of a processing unit," assigned to Intel Corporation.
• Publication Date: December 31, 2015 (Filed: June 30, 2014). This publication predates the '206 patent's priority date.
• Brief Description: This application describes a system where a processing unit dynamically adapts its configuration based on the workload it is executing. It uses a machine learning model to analyze performance counters and other monitoring data (analogous to sensor and processing data) to identify the current workload type. Based on the identified workload, the system selects and applies an optimal hardware configuration (e.g., adjusting cache size, pipeline depth, or clock frequency) from a set of pre-defined configurations to improve performance or power efficiency.
• Potential Anticipation of Claims:
  • Claim 1 & 14: This reference is highly relevant to claims 1 and 14. It discloses a system that receives "computing environment data" (performance counters), analyzes it with a machine learning model, and generates "control signals for managing one or more operations" (adapting hardware configuration). The concept of learning from workload characteristics to enhance performance and efficiency is a core element shared with the '206 patent. It describes a system that optimizes operations based on outputs from a learned model, similar to the system claimed in claim 14.

---

4. Other Cited Non-Patent Literature

The file history also includes citations to academic papers, which are not detailed here but would have been used by the examiner to establish the state of the art regarding the use of machine learning and neural networks in computer architecture at the time of the invention. These papers often provide the foundational concepts that are later implemented in patented systems. For instance, research on using neural networks for branch prediction is a well-established field and would be relevant context for claim 20's focus on a DNN for processor control.

Obviousness Analysis of US Patent 11,328,206

This analysis evaluates the obviousness of the independent claims of US Patent 11,328,206 (the '206 patent) under 35 U.S.C. § 103. The core of this inquiry is whether the differences between the claimed invention and the prior art would have been obvious to a "person having ordinary skill in the art" (PHOSITA) at the time the invention was made. This requires not only finding the claimed elements in the prior art but also establishing a clear reason or "motivation to combine" those elements.

A PHOSITA in this technical domain (computer architecture and machine learning) around the 2016 priority date would be a computer engineer or scientist with graduate-level education and experience in processor design, performance analysis, and the application of machine learning models to system optimization. Such a person is presumed to have knowledge of all relevant public prior art.

The primary prior art references considered are:

• US 9,984,270 B2 ("'270 patent"): Teaches a processor with an integrated neural network that predicts future instructions from instruction traces to pre-fetch and pre-execute them.
• US 2015/0379440 A1 ("'440 publication"): Discloses a system that uses a machine learning model to analyze performance counters, identify the current workload, and dynamically adapt hardware configurations (like clock speed or cache size) to optimize performance or power usage.
• US 10,984,336 B2 ("'336 patent"): Describes using a machine learning model during the processor design phase to predict performance metrics.

---

Analysis of Independent Claim 1 (Method for Managing Operations)

Claim 1 outlines a method for managing a computing device using a deep neural network (DNN). The DNN receives inputs like sensor data and processing data to generate outputs such as control signals, predictions, and warnings to improve performance, efficiency, or security.

Obviousness Argument: Claim 1 is arguably obvious over the combination of the '440 publication and the '270 patent.

• Mapping Claim Elements to Prior Art:

  • The '440 publication establishes the foundational method. It teaches using a machine learning model to receive "computing environment data" (performance counters, which are a form of sensor and processing data) and, in response, generate "control signals for managing one or more operations" (adapting hardware configurations) to enhance performance and efficiency. This directly addresses the core of Claim 1.
  • The '270 patent introduces the key element of prediction. It explicitly teaches using a neural network to generate "predictions corresponding to a future state" (predicting upcoming instructions). The '206 patent's inclusion of "DNN data" as an input is a predictable feature of advanced machine learning systems, where model outputs are often fed back as inputs for subsequent analyses.

• Motivation to Combine: A PHOSITA would have been motivated to combine these teachings to create a more proactive and intelligent system. The '440 publication provides a reactive system that adapts to the current state. The '270 patent demonstrates the feasibility of a proactive system that anticipates future states. A skilled artisan would recognize that the adaptive system of '440 could be significantly improved by incorporating the predictive capabilities of '270. This would allow the system to anticipate future resource needs or bottlenecks and adjust hardware pre-emptively, rather than just reacting. This combination would be a logical step to solve a known problem: improving processor efficiency. The result would be a system that yields predictable results—enhanced performance and efficiency—by combining known elements.

---

Analysis of Independent Claim 14 (System for Optimizing Operations)

Claim 14 describes a physical system, including a computing device and a DNN, that performs the method of Claim 1. A key feature is the system's ability to provide a "warning signal" based on predicted unexpected behavior.

Obviousness Argument: Claim 14 is arguably obvious over the combination of the '440 publication and the '270 patent, with the concept of a warning signal being an obvious addition.

• Mapping Claim Elements to Prior Art:

  • The system architecture is taught by the combination of '440 (a system that adapts a processor based on a learned model) and '270 (a processor with an integrated neural network).
  • The generation of a "warning signal" for unexpected behavior (faults, exceptions) is a logical extension of a system that learns normal operational patterns. The '440 system learns workload characteristics to optimize performance. A PHOSITA would understand that a model trained on normal behavior could inherently be used for anomaly detection. Flagging a significant deviation from the learned norm as a potential fault or security threat would be a common-sense application of machine learning principles to enhance system reliability.

• Motivation to Combine: The motivation is the same as for Claim 1—to enhance the reactive system of '440 with the predictive power shown in '270. The further motivation to add a warning signal stems from the desire for a more robust and secure computing system. Anomaly detection was a known problem in the field, and applying a model already monitoring system behavior to this task would have been a straightforward and predictable solution for a skilled artisan.

---

Analysis of Independent Claim 20 (Processor with DNN Control Unit)

Claim 20 specifies a processor where the control unit itself includes a DNN. This DNN is trained on workloads, takes in real-time operational data, and outputs control signals to command the processor's datapath.

Obviousness Argument: Claim 20 is arguably obvious over the '270 patent alone or in view of the '440 publication.

• Mapping Claim Elements to Prior Art:

  • The '270 patent is highly relevant as it describes a "neural network-based processor" where the neural network is integrated into the processor's control logic. It receives "instruction traces" (data related to processor operation) and its predictions are used to manage the execution pipeline (commanding the datapath). This directly maps to the core architecture of Claim 20.
  • The '440 publication further teaches using machine learning outputs to control a wider range of processor functions, such as power management (voltage/current adjustments), which are also managed by the control unit.

• Motivation to Combine/Extend: The '270 patent already establishes the principle of embedding a neural network into a processor's control flow for a specific task (instruction prediction). A PHOSITA, seeing the success of this approach, would be motivated to generalize it. If a neural network can optimize one aspect of the datapath, it would be an obvious step to explore its use for other control functions traditionally handled by heuristic-based logic, such as branch prediction, cache pre-fetching, and dynamic power management (as suggested by '440). The motivation would be to create a more holistic, adaptive, and efficient control unit that can learn from complex workload patterns, a clear design incentive in the field of computer architecture. This represents a predictable evolution from a specialized neural network application to a more generalized DNN-based control unit as claimed.

Analysis of Patent Term and Related Applications for US 11,328,206

Date of Analysis: April 26, 2026

This report details the term adjustments, related applications, and projected expiration date for United States Patent 11,328,206 B2. The information is based on data available from the U.S. Patent and Trademark Office (USPTO) as of the analysis date.

---

I. Patent Term Adjustment (PTA)

Patent Term Adjustment (PTA) is a process by which the term of a U.S. patent is extended to compensate for certain administrative delays by the USPTO during prosecution.

• PTA for US 11,328,206: The patent grant for US 11,328,206 indicates a significant patent term adjustment. The front page of the issued patent includes the notice: "Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 986 days." This adjustment is granted to compensate for delays in the examination process by the USPTO.

---

II. Patent Term Extension (PTE)

Patent Term Extension (PTE) under 35 U.S.C. § 156 is distinct from PTA and is typically granted to compensate for regulatory review delays (e.g., by the Food and Drug Administration). There is no indication from the available documentation that US 11,328,206 was subject to any PTE.

---

III. Continuation and Divisional Applications

A review of the patent's file history and related application data reveals the following:

• Continuation Applications: There are no records of any continuation applications filed that claim priority to the application that resulted in US 11,328,206.
• Divisional Applications: There are no records of any divisional applications filed that claim priority to the application that resulted in US 11,328,206.

---

IV. Patent Family and Priority Data

The "Related U.S. Application Data" section of the patent provides its priority lineage.

• Application Number: US 11,328,206 issued from U.S. Patent Application No. 15/625,578, which was filed on June 16, 2017.
• Provisional Application: Application No. 15/625,578 claims the benefit of U.S. Provisional Patent Application No. 62/351,205, filed on June 16, 2016. For the purpose of calculating the patent term, the 20-year period begins from the filing date of the earliest non-provisional application.
• International (PCT) Application: The file history references an international application, PCT/US2017/037945, also filed on June 16, 2017.

---

V. Projected Expiration Date

The expiration date of a U.S. patent filed after June 8, 1995, is calculated as 20 years from the earliest non-provisional application filing date, plus any granted Patent Term Adjustment.

1. Base Term Calculation:

   • Earliest Non-Provisional Filing Date: June 16, 2017.
   • Initial 20-Year Term Expiration: June 16, 2037.

2. Application of Patent Term Adjustment (PTA):

   • Granted PTA: 986 days.
   • Calculation: Adding 986 days to June 16, 2037.
     • 986 days is equivalent to 2 years, 8 months, and 16 days (approx.).

3. Projected Expiration Date:

   • June 16, 2037 + 986 days = February 27, 2040.

This projected expiration date assumes that all required maintenance fees are paid in a timely manner and that the patent term is not shortened for any other reason, such as a terminal disclaimer (of which there is no record).

Defensive Disclosure Document

Publication Date: May 9, 2026
Reference Patent: US 11,328,206 B2
Title: Derivative Implementations of Deep Neural Network-Based Control Systems for Computing Devices
Keywords: Deep Neural Network, Processor Control, Anomaly Detection, Generative Models, Real-Time Optimization, Predictive Control, Low-Power Computing, System-on-Chip, Edge AI, Federated Learning.

---

Abstract

This document discloses a series of derivative implementations and alternative embodiments of the inventions claimed in US Patent 11,328,206. The purpose is to establish prior art for subsequent incremental improvements in the field of using deep neural networks (DNNs) for real-time management and optimization of computing hardware. The disclosures herein detail variations in componentry, operational envelopes, cross-domain applications, integration with emerging technologies, and failure-mode operations, thereby rendering them obvious to a person having ordinary skill in the art.

---

Disclosure 1: Derivatives of Independent Claim 20 (Processor with DNN Control Unit)

The core concept is a processor with a control unit that includes a DNN to manage the datapath based on learned workload behavior.

1.1 Material & Component Substitution

• Derivative 1.1.1: Neuromorphic Co-Processor Control Unit

  • Enabling Description: The conventional CMOS-based DNN accelerator circuitry within the control unit is substituted with a neuromorphic co-processor fabricated from phase-change materials (e.g., Ge2Sb2Te5 - GST). This co-processor, based on a spiking neural network (SNN) architecture, processes sensor and instruction data as temporally sparse spike trains. The SNN's inherent event-driven and low-power nature allows the control unit to perform predictive power-gating of datapath functional units with significantly lower energy overhead than a traditional DNN. The SNN learns workload patterns by adjusting synaptic weights based on spike-timing-dependent plasticity (STDP) rules, offering a mechanism for online, unsupervised learning of processor behavior.

  graph TD
  A[Instruction Stream & Sensor Data] --> B{Spike Encoder};
  B --> C[GST-based SNN Co-Processor];
  C --> D{Spike Decoder};
  D --> E[Datapath Control Signals];
  C -- STDP Learning --> C;
  subgraph Control Unit
  B; C; D;
  end
  subgraph Processor Core
  E --> F[Processing Datapath];
  end

• Derivative 1.1.2: Optical DNN Inference Engine

  • Enabling Description: The electronic DNN in the control unit is replaced by an integrated silicon photonics inference engine. Inputs (e.g., performance counter values) modulate a set of micro-ring resonators, encoding data into light intensity. The light passes through a mesh of tunable interferometers that represent the learned weights of the DNN. Photodetectors at the output convert the resulting optical signals back into electronic control signals for the processor datapath (e.g., branch prediction overrides, cache prefetch commands). This substitution allows for inference at near the speed of light, drastically reducing the latency between observing a processor state and issuing a corresponding control command.

  sequenceDiagram
  participant EIC as Electrical-to-Optical Interface
  participant PIC as Photonic Integrated Circuit (DNN)
  participant OEC as Optical-to-Electrical Interface
  participant DP as Datapath Control
  EIC->>PIC: Modulates light with sensor data
  PIC->>PIC: Optical matrix multiplication via interferometer mesh
  PIC->>OEC: Light output representing inference result
  OEC->>DP: Generates electronic control signals
  ```

1.2 Operational Parameter Expansion

• Derivative 1.2.1: Cryogenic Superconducting DNN Controller for Quantum Computing

  • Enabling Description: The technology is adapted for controlling the classical-quantum interface in a quantum computer operating at cryogenic temperatures (e.g., < 100 mK). The processor control unit and its integrated DNN are implemented using superconducting logic circuits (e.g., Single Flux Quantum logic). The DNN receives inputs on qubit state measurement fidelities, decoherence times, and control pulse errors. It then generates corrective control signals to adjust microwave control pulses sent to the qubits, optimizing gate fidelities in real-time. The extreme low-temperature environment minimizes thermal noise, enabling the DNN to learn and react to subtle statistical drifts in quantum system behavior.

  stateDiagram-v2
  [] --> Monitoring: System Initialization
  Monitoring --> Analyzing: Qubit state data received
  Analyzing --> Predicting: DNN predicts gate fidelity drift
  Predicting --> Correcting: DNN issues new pulse parameters
  Correcting --> Monitoring: Control pulses adjusted
  state Analyzing {
  direction LR
  [] --> DNN_Inference
  DNN_Inference --> [*]
  }

• Derivative 1.2.2: High-Frequency DNN for RF Power Amplifier Control

  • Enabling Description: The DNN control system is scaled to operate at radio frequencies (GHz range) to manage a Gallium Nitride (GaN) power amplifier in a 5G/6G base station. The DNN is implemented on a high-speed FPGA. It receives inputs on the amplifier's temperature, input power, and load impedance mismatch (Voltage Standing Wave Ratio - VSWR). The DNN's output dynamically adjusts the amplifier's gate bias and supply voltage to prevent thermal runaway and maintain linearity under rapidly changing load conditions, maximizing power-added efficiency (PAE) and preventing component damage.

  graph TD
  subgraph RF_Frontend
  A[RF Input Signal] --> B[GaN Power Amplifier];
  B --> C[Antenna];
  end
  subgraph DNN_Control_Unit_FPGA
  D[Sensors: Temp, VSWR, Power] --> E{DNN Inference};
  E --> F[Gate Bias & Voltage Control];
  end
  F --> B;
  ```

1.3 Cross-Domain Application

• Derivative 1.3.1: Aerospace - Flight Control Actuator Management

  • Enabling Description: A federated set of DNN control units is embedded within the smart actuators of an aircraft's flight control surfaces (e.g., ailerons, rudder). Each DNN receives local sensor data (strain, temperature, vibration) and data from the central flight control computer (desired surface position). The DNN predicts incipient mechanical failure or performance degradation (e.g., hydraulic fluid cavitation) and generates control signals to operate the actuator in a way that mitigates stress and prolongs operational life, while still meeting flight control demands. It can also issue a warning signal for predictive maintenance.

  classDiagram
  class FlightControlComputer {
  +calculateSurfacePositions()
  }
  class SmartActuator {
  <>
  -localSensors
  -dnnModel
  +receiveCommand()
  +predictFailure()
  +adjustOperation()
  +issueMaintenanceWarning()
  }
  FlightControlComputer "1" -- "N" SmartActuator : sends commands

• Derivative 1.3.2: AgTech - Autonomous Irrigation System Optimization

  • Enabling Description: The processor is an embedded controller in a smart irrigation valve. The DNN receives inputs from soil moisture sensors, local weather station data (temperature, humidity), and satellite imagery indicating crop stress (e.g., NDVI). Based on a generative model of soil water absorption and crop evapotranspiration, the DNN outputs control signals to precisely modulate the valve's opening duration and frequency, optimizing water delivery to the plant root zone while minimizing runoff and evaporation. This enhances water use efficiency and crop yield.

  flowchart LR
  A[Soil Moisture Sensor] --> C{DNN Controller};
  B[Weather Data] --> C;
  D[Satellite NDVI Data] --> C;
  C --Control Signal--> E[Irrigation Valve];
  E --Water Flow--> F[Crop Field];

• Derivative 1.3.3: Consumer Electronics - Smart Appliance Energy Management

  • Enabling Description: A DNN-based control unit is integrated into a home appliance, such as a refrigerator or HVAC system. The DNN receives sensor data on internal temperature, door open/close events, and user interaction patterns. It also receives external data from the smart grid, including real-time electricity pricing and grid load. The DNN predicts periods of high energy cost or low user demand and adjusts the appliance's operational cycles (e.g., pre-cooling the refrigerator before a price spike) to minimize energy consumption and cost without compromising core functionality.

  sequenceDiagram
  participant User
  participant SmartGrid
  participant Appliance_DNN
  participant Compressor
  loop Real-time
  SmartGrid->>Appliance_DNN: Sends electricity price data
  User->>Appliance_DNN: Opens door (sensor input)
  Appliance_DNN->>Appliance_DNN: Predicts future cooling demand and cost
  Appliance_DNN->>Compressor: Issues optimal ON/OFF control signal
  end
  ```

1.4 Integration with Emerging Tech

• Derivative 1.4.1: AI-Driven Self-Tuning DNN Parameters

  • Enabling Description: The DNN control unit is paired with a secondary, higher-level AI model (e.g., a reinforcement learning agent). This agent observes the performance outcomes (e.g., power consumption, execution latency) resulting from the DNN's control signals. If the outcomes deviate from a desired optimal state, the reinforcement learning agent updates the weights and biases of the primary DNN control unit. This creates a closed-loop system where the processor's control logic continuously fine-tunes itself in response to new or evolving workloads, a process of online meta-learning.

  graph TD
  subgraph Processor
  A[Workload] --> B[Datapath];
  C[DNN Control Unit] --Control Signals--> B;
  A --Instruction Data--> C;
  B --Performance Data--> D[RL Agent];
  end
  D --Updated DNN Weights--> C;

• Derivative 1.4.2: IoT Sensor Fusion for Holistic System Control

  • Enabling Description: The processor's DNN control unit ingests data not only from its internal sensors but also from a network of external IoT sensors via a low-latency protocol like MQTT. For example, in an autonomous vehicle, the central processing unit's DNN controller would receive inputs from its own temperature sensors, as well as ambient temperature data from external sensors, LiDAR-detected road surface conditions, and IMU data. It would then generate control signals to adjust processor clock frequency to manage thermal output proactively, ensuring reliable performance during computationally intensive perception tasks.

  flowchart TD
  A[Internal Temp Sensor] --> F{Central DNN Controller};
  B[External IoT Temp Sensor] --> F;
  C[LiDAR Sensor] --> F;
  D[IMU Sensor] --> F;
  F --Adjust Clock Frequency--> G[Processor Datapath];

• Derivative 1.4.3: Blockchain-Verified DNN Model Updates

  • Enabling Description: To ensure security and integrity in a federated or safety-critical system, updates to the DNN model parameters are managed via a private blockchain. When a new, validated model is ready for deployment, its parameter hash is recorded on the blockchain. The processor's control unit will only accept and load a new set of parameters if their hash matches a transaction on the blockchain, which is cryptographically signed by an authorized entity (e.g., the device manufacturer). This prevents malicious actors from pushing compromised models to the device that could degrade performance or create security vulnerabilities.

  sequenceDiagram
  participant Manufacturer
  participant Blockchain
  participant Device_Controller
  Manufacturer->>Blockchain: Commits new DNN model hash (Transaction)
  Device_Controller->>Blockchain: Queries for latest model hash
  Blockchain-->>Device_Controller: Returns latest valid hash
  Device_Controller->>Device_Controller: Verifies received model update against hash
  alt Hash Matches
  Device_Controller->>Device_Controller: Applies DNN update
  else Hash Mismatches
  Device_Controller->>Device_Controller: Rejects update and logs error
  end
  ```

1.5 The "Inverse" or Failure Mode

• Derivative 1.5.1: Graceful Degradation Mode

  • Enabling Description: The DNN is specifically trained to recognize precursors to a non-recoverable hardware fault (e.g., voltage droop, critical temperature threshold). Upon predicting such an event, the DNN does not attempt to optimize performance but instead outputs control signals that place the processor into a safe, low-power state. This involves aggressively clock-gating functional units, flushing caches to non-volatile memory, and issuing a "last-gasp" warning to the operating system. The primary function is data preservation and prevention of catastrophic failure, rather than continued operation.

  stateDiagram-v2
  [] --> Normal_Operation
  Normal_Operation --> Predictive_Failure_Detection: Precursor event detected
  Predictive_Failure_Detection --> Graceful_Degradation: Fault imminent
  Graceful_Degradation --> Safe_Shutdown: Data flushed
  Safe_Shutdown --> []
  Normal_Operation --> Normal_Operation: No precursor

• Derivative 1.5.2: Fail-Safe Heuristic Fallback

  • Enabling Description: The DNN control unit includes a built-in self-test mechanism. If the DNN output becomes unstable or its inference latency exceeds a critical threshold (indicating a failure in the DNN itself), the control logic automatically bypasses the DNN. Control of the datapath reverts to a set of pre-programmed, conservative hardware heuristics (e.g., a simple static branch predictor, fixed clock frequency). This ensures that the processor remains functional, albeit at reduced efficiency, rather than crashing due to a fault in its advanced control system.

  graph TD
  A{Input Data} --> B{DNN Control};
  B --DNN OK?--> C{Generate DNN Control Signal};
  C --> E[Mux];
  A --> D{Generate Heuristic Control Signal};
  D --> E;
  E --> F[Datapath];
  B --DNN Failed--> D;
  ```

---

Disclosure 2: Combination Prior Art with Open-Source Standards

• Scenario 2.1: RISC-V Custom Instruction for DNN Input

  • Enabling Description: The processor is based on the open-source RISC-V instruction set architecture (ISA). A custom instruction, dnn.input, is added to the ISA. This instruction allows software to directly push data (e.g., application-level metadata, sensor readings) into the input registers of the control unit's DNN. This creates a standardized, low-latency pathway for software to provide hints to the hardware control logic, enabling tighter co-design of software algorithms and hardware optimization. A compiler toolchain (e.g., based on LLVM) would be modified to automatically insert these instructions at critical junctures in the code.

• Scenario 2.2: DNN Control Integrated with Open-Source RTOS

  • Enabling Description: The DNN-controlled processor is managed by an open-source real-time operating system (RTOS), such as Zephyr or FreeRTOS. The RTOS scheduler is modified to be "DNN-aware." The DNN's predictions about future computational load are provided to the scheduler via a shared memory interface. The scheduler uses these predictions to proactively adjust task priorities and time slices, preventing deadline misses in hard real-time tasks by allocating resources before the high-load period begins, rather than reacting to it.

• Scenario 2.3: Federated Learning of DNN Controllers via gRPC

  • Enabling Description: A fleet of devices, each containing a DNN-controlled processor, participates in a federated learning scheme to collectively improve their control models without sharing raw data. The devices use the open-source gRPC framework for communication. Each device trains its local DNN model based on its specific workload. Periodically, it serializes the model weight updates (not the data) using Protocol Buffers and sends them to a central aggregation server via a secure gRPC stream. The server averages the updates and sends back a globally improved model. This allows the entire fleet to benefit from the operational experience of each individual unit.