US 10805562

I'll search for information about US patent 10805562, including any CAFC 2026 docket activity.

Both searches returned no results. Let me try alternate query formulations.

The initial searches found no direct hits. Let me run more targeted searches for the specific patent and any litigation.

Summary of U.S. Patent No. 10,805,562 (US10805562B2)

Searches performed: I searched for the literal patent number "US10805562," the formatted "10,805,562," and a CAFC-2026 docket query. No CAFC (or other) litigation or 2026 docket entries for this patent were found. The only search hit confirming the patent's bibliographic record was a Google Patents cross-reference, which matches the authoritative full-text record provided to me. I therefore cannot confirm or deny pending appellate activity beyond stating that none surfaced in my searches. All substantive information below comes from the patent record itself (Google Patents full text, fetched 2026-09-03), which I treat as authoritative for the patent's contents.

Bibliographic data

• Title: Imaging device, manufacturing method, semiconductor device, and electronic device
• Patent / Publication No.: US10805562B2 (granted); earlier publication US20180197902A1
• Assignee: Sony Semiconductor Solutions Corporation (original and current assignee)
• Inventors: Ryosuke Nakamura; Fumihiko Koga
• Application No.: US15/742,248, filed 2016-07-01 (U.S. National Phase of PCT/JP2016/069595, filed 2016-07-01)
• Priority date: 2015-07-17 (JP 2015-143164)
• Issue date: 2020-10-13
• Legal status: Active; maintenance fee paid (4th year, large entity, 2024-03-21); adjusted expiration 2037-03-28
• Family members: WO2017014025A1, CN107851649B, JPWO2017014025A1

Abstract (verbatim, condensed)

An imaging device includes a photoelectric conversion unit that receives and photoelectrically converts light, a floating diffusion (FD) layer that accumulates charge generated by the photoelectric conversion unit, and a diffusion layer serving as a source or drain of a transistor. The FD layer is formed with an impurity concentration lower than that of the diffusion layer. In one pixel, both a first photoelectric conversion unit able to accumulate charge and a second photoelectric conversion unit whose charge is sequentially taken out and accumulated in the FD layer are provided, arranged in a line longitudinally along the illumination direction. The technology is applicable to, e.g., a back-illuminated CMOS image sensor.

Technical purpose: In CMOS image sensors, metal impurities ("defect sources") tend to gather in high-concentration impurity diffusion layers (e.g., FDs) during manufacturing, causing white/black point noise. Lowering the FD layer's impurity concentration relative to transistor source/drain diffusion layers suppresses defect gettering and improves image quality.

Independent claims — plain-language overview

There are 10 claims; independent claims are 1, 7, 8, and 9.

• Claim 1 (Imaging device): A photoelectric conversion unit comprising a first and a second photoelectric conversion unit; an FD layer that accumulates charge generated by the second photoelectric conversion unit; and a diffusion layer that is a source/drain of a transistor, where the transistor's gate electrode lies between that diffusion layer and a portion of the first photoelectric conversion unit. The FD layer's impurity concentration is lower than the diffusion layer's.

• Claim 7 (Method of manufacturing an imaging device): Forming the FD layer (which accumulates charge generated by the second photoelectric conversion unit of an imaging device having first and second photoelectric conversion units) and separately forming the source/drain diffusion layer, with the transistor gate electrode between the diffusion layer and a portion of the first photoelectric conversion unit. The FD layer is formed at a lower impurity concentration than the diffusion layer.

• Claim 8 (Semiconductor device): An FD layer that accumulates charge and a source/drain diffusion layer of a transistor, with the transistor gate electrode between the diffusion layer and a portion of a photoelectric conversion unit; the FD layer's impurity concentration is lower than the diffusion layer's. (No imaging-device limitation.)

• Claim 9 (Electronic device): An electronic device containing an imaging device as recited in claim 1 (first and second photoelectric conversion units, low-concentration FD accumulating charge from the second unit, source/drain diffusion layer with gate between it and the first unit).

Dependent claims — brief notes

• Claim 2: The first and second photoelectric conversion units form one pixel and are stacked longitudinally along the light-illumination direction (the "longitudinal spectral structure").
• Claim 3: The low-concentration FD is specifically the one accumulating charge from the second photoelectric conversion unit.
• Claim 4: Two FDs exist — a first FD receiving charge from the first photoelectric conversion unit and a second FD accumulating charge from the second unit; the second FD's concentration is lower than the first FD's.
• Claim 5: A contact electrode takes charge out of the FD from the second photoelectric conversion unit, with an insulator (e.g., SrTiO₃, HfO₂, Al₂O₃) between the contact electrode and the semiconductor substrate to avoid a Schottky junction.
• Claim 6: A laminated structure of a sensor chip (photoelectric conversion unit) and a logic chip (performing arithmetic processing); the low-concentration FD is compared against source/drain diffusion layers on the logic chip.
• Claim 10: Adds structural detail — the first photoelectric conversion unit is a red or blue photodiode in the substrate, the second is a green photoelectric conversion film on the substrate, and the diffusion layer sits between the first photoelectric conversion unit and a third photoelectric conversion unit.

Caveats / uncertainty

• CAFC 2026 activity: No docket results were found linking patent 10,805,562 to any appeal or litigation. Absence of results is not proof of non-existence; I could not access the USPTO Patent Center or CAFC docket directly in this session.
• Citation-data anomaly: The Google Patents "Cited By" list for this patent is dominated by apparently unrelated Charter Communications quasi-licensed wireless-spectrum patents, which look like erroneous citation associations. Only a Semiconductor Energy Laboratory imaging-device patent (US12426435B2) appears plausibly related. I would not rely on the cited-by list for substantive technical family analysis.
• The inventors' names and all technical descriptions above are taken literally from the patent record; no identifiers were auto-corrected.

I'll search for litigation involving US Patent 10805562 across several sources.

Let me search more targeted litigation databases and news sources.

Let me run a few more targeted searches on case docket databases and PTAB records.

Based on my searches of public sources (general web, patent databases, and litigation-focused portals including Unified Patents and PACER-adjacent case databases), I found no known litigation involving U.S. Patent No. 10,805,562 as of the search date of April 26, 2026.

Details of what I checked and found:

• Patent identity: US10805562B2, titled "Imaging device, manufacturing method, semiconductor device, and electronic device," is assigned to Sony Semiconductor Solutions Corporation (inventors: Ryosuke Nakamura and Fumihiko Koga). It issued October 13, 2020, from application US15/742,248 (PCT/JP2016/069595), claiming priority to JP2015-143164 (filed July 17, 2015).
• District court litigation: No district court complaints, case dockets, or judgments naming US10805562 as a patent-in-suit were found.
• PTAB / IPR / PGR proceedings: No inter partes review, post-grant review, or covered business method challenges against this patent were identified.
• ITC investigations: No Section 337 investigations naming this patent were found.
• Search caveats: The only "hits" that surfaced were citation listings (e.g., this patent listed among prior-art/cited references on other patent records, such as unrelated Charter Communications patents and a Justia patent page for a different patent, US12144018) — these are mere bibliographic citations, not litigation. Additionally, I note the USPTO PTAB document found in one search referenced a "'562 patent" — but that was a different patent (referenced in a Sand Revolution/IPR context, not U.S. Patent No. 10,805,562).

Conclusion: To my knowledge and based on the searches performed, U.S. Patent No. 10,805,562 is not currently involved in any known litigation, and I found no record that it has ever been asserted in a lawsuit. The patent remains active (maintenance fee paid, 4th year, in March 2024 per the USPTO assignment/fee record).

If you need a more exhaustive confirmation, I would recommend a paid docket search (e.g., DocketNavigator, LexisNexis, Westlaw, or RPX) and a direct query of PACER and the Unified Patents portal, since free web searches can miss recently filed or sealed complaints.

Let me run a few more targeted searches to be thorough before concluding.

Proceedings overview

There is zero AIA trial activity on file for US 10805562 — the USPTO Open Data Portal returns no IPR/PGR/CBM/DER proceedings for this patent as of the most recent ingest, and supplementary web searches surfaced no older or recently-filed petitions that the ODP has not yet indexed. There are no active proceedings, no claims invalidated, no claims sustained by a Final Written Decision, no settlements, and no institution denials. The bottom-line defensive posture is neutral: the patent is completely untested before the PTAB — all ten claims remain in force, but no petitioner has yet committed resources to challenging them.

Proceedings detail

No per-proceeding entries are possible because no proceeding exists. For completeness, the searches run (USPTO ODP-derived canonical list, plus web queries for "US10805562"/"108,055,62" combined with IPR/PGR/PTAB terms) returned only generic USPTO PTAB API documentation — no petition, institution decision, FWD, termination, or CAFC appeal naming this patent. The odd cluster of "Cited By" records on the Google Patents page (Charter Communications quasi-licensed wireless patents) is a citation-data artifact, not PTAB activity.

Strategic summary

Claim status: all UNTESTED. US 10805562 issued 2020-10-13 with 10 claims (claims 1 and 7–10 independent in substance: claim 1 — imaging device with first/second photoelectric conversion units and a lower-concentration FD layer; claim 7 — manufacturing method; claim 8 — semiconductor device; claim 9 — electronic device; claim 10 — substrate/green-film limitation; claims 2–6 dependent). No claim has been canceled, narrowed, or even examined on the merits by an AIA tribunal. The patent owner, Sony Semiconductor Solutions Corporation, paid the 4th-year maintenance fee (2024-03-21), so the patent is in force and enforceable. For a defendant, this means every claim is presumptively valid and untested — there is no PTAB precedent to lean on, and any validity attack must be built from scratch.

Estoppel landscape: a blank slate, which cuts both ways. Because no IPR/PGR has ever been instituted, there are no § 315(e)(2) estoppels binding anyone. No petitioner, real party in interest, or privy is estopped from raising any § 102/§ 103 ground. For a defendant facing assertion today, all prior-art avenues remain open — but so does the corollary: nobody else has done the heavy lifting of building a record, so you cannot ride another petitioner's coattails. Note the timing traps that make this window fragile: (1) the PGR window (nine months post-grant, since the earliest priority date of 2015-07-17 falls after the 2013-03-16 AIA transition) closed around 2021-07-13 — any future challenge must be an IPR limited to § 102/§ 103 over patents/printed publications; and (2) the § 315(b) one-year bar runs from service of an infringement complaint — if a defendant has already been sued on this patent, its IPR clock may be running or expired.

Pattern signals: none. No repeat petitioner, no defensive aggregator (Unified Patents, etc.) in the chain, no PTAB appeals practice by Sony Semiconductor Solutions on this patent to study, and no district-court litigation activity tied to this patent surfaced in the searches. The absence of any IPR more than five years after grant is itself informative: this is a structural/image-sensor patent in a crowded field where FD-layer doping and longitudinal-spectral pixels are heavily litigated — well-asserted patents in this space typically attract IPRs within a year or two of first suit. The silence suggests either the patent has not been aggressively asserted (or was asserted only recently), or would-be challengers see prosecution-history or prior-art weaknesses that make a different patent the better target.

Recommended next steps

• If you are a defendant and no complaint has been served yet: you have a clean runway — conduct a § 102/§ 103 prior-art search now (Sony's own family, including JP 2007-329161, JP 2010-278086, JP 2011-138927 cited in the specification, plus the examiner-cited art JP 2006-086241, JP 2006-108466, US 2008/0079806, US 8,773,562, and JP 2014-060199) and calendar the § 315(b) one-year date the moment you are served. There is no FWD to quote because there is no proceeding — the absence is the story.
• If you have already been served: check the service date against the § 315(b) bar immediately. If you are inside the one-year window, an IPR petition challenging the lower-concentration-FD claims (claims 1, 4, 7–9, and dependents) on obviousness grounds is the primary lever, but note that an IPR filed after the first substantive response in district court invites § 315(a)(1) treatment, and post-Fintiv discretionary denial is a real risk given a parallel litigation schedule.
• If you are evaluating a demand letter rather than a suit: the fact that no one has filed an IPR in five years cuts against paying a premium — but it also means Sony's claims have never been stress-tested, so a validity position is unproven. Consider whether the asserted claims read on a "floating diffusion layer with lower impurity concentration than a transistor source/drain diffusion layer" — that structural distinction (not the photoelectric conversion stack) is the claim element most likely to distinguish prior art, and it is the element an IPR would target.
• Monitor the ODP PTAB endpoint (data.uspto.gov) for any late-filed petition, since the ODP ingest can lag newly filed proceedings by days to weeks.

No PTAB proceeding numbers, judge panels, institution decisions, Final Written Decisions, settlements, or Federal Circuit appeals exist to cite — nothing has been fabricated above, and if a petition appears after this analysis, it should be verified directly against the USPTO PTAB proceeding docket before reliance.

The web searches returned background material but not the actual assignment record. I'll run more targeted searches on the specific reel/frame found in the patent's legal-events feed and on any post-issuance transfers.

No results. Let me try direct approaches to the USPTO assignment database and alternate search surfaces.

I have reached the search-step limit. Based on the authoritative patent record (Google Patents full text, which mirrors USPTO records) and the searches completed, here is the ownership-chain reconstruction. I must flag one important limitation up front: I could not directly query the USPTO Assignment Center database in this session. The assignment data below comes from the patent's USPTO legal-events feed as reproduced in Google Patents (reel/frame 045667/0616), which is the same underlying record the Assignment Center would return for that patent number. All other searches for litigation, CAFC 2026 docketing, and post-issuance transfers returned no results.

Inventors

• Ryosuke Nakamura
• Fumihiko Koga

Both inventors executed the recorded assignment (effective 2018-01-23) in favor of Sony Semiconductor Solutions Corporation, indicating employment there at the time of the US national-phase filing. The PCT application (PCT/JP2016/069595) was also filed by Sony Semiconductor Solutions Corp. No unusual pattern is present — there is no evidence either inventor departed the assignee shortly after filing, and both names appear only on this standard employer assignment. (One third-party aggregator site, patentleaderboard.com, lists Nakamura under a "Hitachi" profile — that cross-listing appears erroneous/mislabeled and I did not treat it as reliable.)

Original assignee

• Sony Semiconductor Solutions Corporation (Kanagawa, Japan) — named as original and current assignee on the issued patent.
• Line of business: design and manufacture of semiconductor devices, principally CMOS image sensors (including back-illuminated stacked sensors for smartphones and the organic-film / longitudinal-spectral-structure sensors described in this patent).
• Product embodiment: Sony Semiconductor Solutions is one of the world's largest CMOS image-sensor suppliers; the sensor architectures described in the specification (stacked sensor chip + logic chip, back-illuminated photodiodes, organic photoelectric conversion films) are squarely within its commercial product lines.
• Current status: Operating. Wholly owned semiconductor subsidiary of Sony Group Corporation. The 4th-year maintenance fee was paid 2024-03-21 (large-entity status), consistent with an operating company actively maintaining the asset.

Assignment timeline

The Assignment Center search for this patent, to the extent verifiable through the mirrored USPTO legal-events feed, shows exactly one recorded assignment — the original inventor-to-company transfer. No post-issuance assignments are recorded.

• 2018-01-23 (executed) / recorded 2018-03-21 — Reel 045667/0616
  • Conveyance: Assignment of Assignors' Interest
  • Assignor: Ryosuke Nakamura; Fumihiko Koga
  • Assignee: Sony Semiconductor Solutions Corporation
  • Correspondent: Not determinable from available records — the USPTO/Google legal-events entry does not carry the correspondent field, and I could not reach the Assignment Center directly to capture it. No recurrence analysis possible on this single record.
  • Context: Standard inventor-to-employer assignment of the US national-phase application (US15/742,248) — not a transfer between companies.

No assignments were recorded at issuance (2020-10-13) or afterward. This is itself the key finding: the original assignee, Sony Semiconductor Solutions Corporation, still owns US 10805562.

Timeline diagram

timeline
    title Ownership of US 10805562
    2015 : Priority filing in Japan
    2016 : PCT filed by Sony Semiconductor Solutions
    2018 : Inventors assign to Sony Semiconductor Solutions
    2020 : Patent issued
    2024 : Maintenance fee paid

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The patent never moved from an operating company to an LLC/IP Holdings-type entity. Current assignee is Sony Semiconductor Solutions Corp, a manufacturing operating company. (Reel 045667/0616 is the only transfer, and it runs to the operating company, not away from it.)

2. Known asserter in the chain — not present. Neither the current assignee (Sony Semiconductor Solutions) nor any prior assignee appears on public NPE/asserter lists (Acacia, Marathon, IV, Wi-LAN, Conversant, etc.). Sony is a large operating company, not a licensing entity.

3. Repeat correspondent across the chain — not present / unclear. Only one recorded assignment exists, so there is no chain in which a correspondent could recur. The correspondent of record for reel 045667/0616 was not visible in the records I could access; no finding is made on this signal.

4. Cascading transfers — not present. There is a single assignment, not multiple chained transfers in <24 months or otherwise.

5. Pre-litigation transfer — not present. No infringement litigation naming this patent was found in any search (including CAFC 2026 docket queries). The sole assignment (2018) predates issuance (2020) and is a routine employer assignment, not a litigation-venue or standing-arrangement transfer.

6. Bankruptcy fire-sale — not present. Sony Semiconductor Solutions has not been in Chapter 7/11; no bankruptcy-related patent sale exists.

7. Privateering — not present. No evidence Sony transferred this patent to an NPE to assert against competitors, and no SEC-filing or press coverage suggests such an arrangement.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN; it terminates at the original operating-company assignee.

Verdict

Insufficient data (only the original assignment exists on record, and no assertion activity was found).

The record shows a single, routine inventor-to-employer assignment (reel 045667/0616, executed 2018-01-23, recorded 2018-03-21), and US 10805562 remains with Sony Semiconductor Solutions Corporation — a large, operating, product-shipping company that paid its 4th-year maintenance fee in 2024. No NPE signals of any kind surfaced: no shell transfers, no chained assignments, no litigation or CAFC docket entries, and no defensive-aggregator endpoint. Because there is no evidence of assertion activity either by Sony or by any transferee, the accurate classification under the given rubric is "insufficient data" — though the available evidence points to a benign operating-company holding rather than any troll pattern. For verification, the USPTO Assignment Center search page is at https://assignmentcenter.uspto.gov/ (patent-number search: 10805562); the recorded assignment appears in the USPTO legal-events feed as reel/frame 045667/0616.

I'll search the USPTO and patent databases for US 10805562 and its cited references.

Prior-Art Analysis — U.S. Patent No. 10,805,562 (US10805562B2)

Searches run for: "US10805562," the literal string "10805562," and each examiner-cited reference number individually. I retrieved the USPTO record via Google Patents' full-text mirror and verified content for the key cited references where the searches returned it. Note: I reached the tool-call limit before I could pull the full text of every cited reference; where content is established only by the bibliographic/citation record rather than verified full text, I say so explicitly below rather than implying I read it.

1. Record verification (scope guard)

The number 10805562 = US10805562B2 ("Imaging device, manufacturing method, semiconductor device, and electronic device," Sony Semiconductor Solutions Corp., inventors Ryosuke Nakamura / Fumihiko Koga, priority 2015-07-17, issued 2020-10-13) is confirmed. I did not substitute any similar number. The five examiner-cited patent documents on the face of the patent are (per the authoritative record):

Three further references appear in the family citation record (JP5564847B2, JP5509846B2, JP2014060199A), and three in the applicant's own background (PTL1–3: JP 2007-329161A, JP 2010-278086A, JP 2011-138927A).

Important framing on § 102: Anticipation requires a single reference to disclose every element of a claim, arranged as claimed. As shown below, none of the five cited references anticipates any of the independent claims (1, 7, 8, 9). The cited set is § 103 art, not § 102 art. I identify the closest § 102 candidates and the specific reason each falls short.

2. Reference-by-reference analysis

Reference 1 — JP 2006-086241 A (JP2006086241A)

• Full citation: JP 2006-086241 A, "Solid state imaging device and manufacturing method thereof," Sony Corp. (family: JP4604621B2).
• Filing/priority: 2004-09-15 (JP App. 2004-294560). Publication: 2006-03-30.
• Description (verified): A MOS/CIS pixel with an element-isolation region, a reading (transfer) gate, a photodiode PD, and a floating diffusion FD-1. FD-1 comprises a low-concentration region 31 adjoining the reading gate and a high-concentration region 32 spaced from the sidewall; the transistor (reset/amp) source/drain regions are formed as low-/high-concentration diffusion layers. The manufacturing method forms the FD's low-concentration region in the same step as the transistor's low-concentration diffusion layer and the FD's high-concentration region in the same step as the channel diffusion layer. Stated object: high sensitivity and improved conversion efficiency in a miniaturized pixel.
  • Source: https://patents.google.com/patent/JP2006086241A/en ; https://patents.google.com/patent/JP4604621B2/en
• § 102 mapping:
  • Claim 8 (semiconductor device) — closest fit, because '241 discloses an FD that accumulates charge plus source/drain diffusion layers of transistors. But its FD low-concentration region is formed in the same implant step as the transistor's low-concentration diffusion layer (i.e., nominally the same doping), and its high-concentration region is higher. It therefore does not disclose the claimed limitation "impurity concentration of the floating diffusion layer is lower than … the diffusion layer." No anticipation of claim 8.
  • Claims 1, 7, 9 — '241 has no first and second photoelectric conversion units and no FD that accumulates charge generated by a second (on-substrate/film) conversion unit; it is a conventional single-PD CIS. No anticipation.
  • Best role: § 103 art showing FD doping to be a separately controllable implant variable — the single most useful combination reference in the cited set.

Reference 2 — JP 2006-108466 A (JP2006108466A)

• Full citation: JP 2006-108466 A, "Semiconductor device for physical value distribution detection," Sony Corp. (inventor: Mishina Koji).
• Filing/priority: 2004-10-07. Publication: 2006-04-20.
• Description (verified via Sumobrain abstract): Compensates for differences in signal transformation between color pixels. In the unit pixel, the signal-transformation capability is adjusted per color pixel by, e.g., adjusting the gate length/width of the amplifier transistor 42, adjusting the density of impurities constituting the floating diffusion 38 in units of color pixels, or adjusting the FD volume via a load wire.
  • Source: https://www.sumobrain.com/patents/jp/Semiconductor-device-physical-value-distribution/JP2006108466A.html
• § 102 mapping:
  • This is the most on-point of the cited references for the "different FD doping" idea. It expressly teaches that the impurity density of the floating diffusion may be adjusted on a per-color-pixel basis.
  • Claims 3 and 4 are the closest targets: claim 4 requires a second FD (for the second conversion unit) with concentration lower than a first FD (for the first unit). '466 discloses per-pixel FD impurity-density adjustment but does not disclose the relative direction (lower vs. higher) between two FDs, nor an FD lower than a source/drain diffusion layer, nor the two-photoconversion-unit geometry. No anticipation; strong § 103 art for claims 3–4.
  • Claim 1 / 8: no first/second PE units with the claimed gate geometry. No anticipation.

Reference 3 — US 2008/0079806 A1

• Full citation: US 2008/0079806 A1, "Imaging device and endoscopic apparatus," Fujifilm Corp. (Inuiya, Ohashi, Ihama). Granted as US 8,848,047 B2. App. No. 11/861,361.
• Filing: 2007-09-26. Publication: 2008-04-03. Priority: JP 2006-09-28.
• Description (verified): An imaging device with (i) in-substrate photoelectric converting devices (photodiodes arranged in the semiconductor substrate) and (ii) on-substrate photoelectric converting devices (first electrode / photoelectric-converting layer / second electrode stacked above the substrate), a color-filter layer transmitting a wave range different from that absorbed by the converting layer, and a signal-reading section that reads the charge from both device types. Object: obtain RGB color image data and IR image data in a single imaging pass with high precision (the film stack is the "upper" converter above the substrate).
  • Source: https://patents.google.com/patent/US20080079806 ; https://www.patents-review.com/a/20080079806-imaging-device-endoscopic-apparatus.html
• § 102 mapping:
  • Claim 2 is the closest concept (two photoelectric conversion units of different construction in one pixel, at different heights above the substrate), but the on-substrate and in-substrate devices are described as arranged on the same plane (side-by-side, with the film device over a subset of substrate PDs), and '806 does not describe them as "arranged in a line in a longitudinal direction along the direction of illumination," nor does it teach any FD/lower-FD-doping limitation. No anticipation of claim 1 or 2.
  • Claim 10 (green film on substrate + red/blue substrate PDs) is architecturally related but '806's device is IR-plus-visible, not the claimed R/B/G stack. No anticipation.
  • Best role: the primary § 103 architecture reference for the stacked/film-above-substrate pixel.

Reference 4 — JP 2008-085159 A (JP2008085159A)

• Full citation (per the citation record): JP 2008-085159 A, "Imaging device and endoscope apparatus," Fujifilm Corp. Priority: 2006-09-28. Publication: 2008-04-10. (Appears to be the JP counterpart of Reference 3 / US20080079806A1.)
• Content caveat: I could not verify the full text of this Japanese publication. One of my searches returned a different, unrelated document — a JFE Steel "Magnetic steel sheet having insulating film" matter carrying the string "JP2008085159A" as an application number — which is a number-association artifact, not this reference. The only clean corroboration is that the number appears as a "Domestic Patent Reference" on Fujifilm imaging-device records (e.g., JP2010067828A). I therefore treat its content as established only by the citation record (Fujifilm imaging-device/endoscope family), not verified text.
• § 102 mapping: on the citation record, same subject matter as Reference 3 → at most architecture art; no anticipation of claims 1, 2, 8, 9, or 10. Any petition relying on it must pull the actual JP text (JPO) before committing to a ground.

Reference 5 — US 8,773,562 B1

• Full citation: US 8,773,562 B1, "Vertically stacked image sensor," Apple Inc.
• Priority: 2013-01-31. Issued: 2014-07-08.
• Description (verified): A multi-chip (three-chip), wafer-bonded, backside-illuminated image sensor: a photodiode chip bonded to a transistor-array chip bonded to a logic chip. Floating diffusion nodes are located on the transistor-array chip; the disclosure includes storage nodes for global shutter, multiple photodiodes per pixel, differently-doped FD nodes and doping/potential engineering along the photodiode→FD path, discussion of Schottky vs. ohmic contacts, triple wells, and isolating barriers between inter-chip connections.
• § 102 mapping:
  • Claim 6 (sensor chip + logic chip laminate) is the direct target: Apple discloses the sensor-chip/logic-chip laminate with FD nodes on the transistor-array chip. However, claim 6 also requires the sensor-side FD to be lower-doped than the source/drain diffusion layers on the logic chip, and I could not verify that Apple discloses that specific relative-doping comparison. No anticipation of claim 6 on the current record (strong § 103 reference).
  • Claim 4 (multiple FDs, different concentrations): Apple's differently-doped FD nodes support a § 103 combination, but Apple does not disclose first-FD (from a first PE unit) vs. second-FD (from a second, film-type PE unit) with the claimed relative direction. No anticipation.
  • Claim 5 (insulator between contact electrode and substrate): Apple discusses Schottky/ohmic contacts and isolating barriers, but not the specific tunneling-insulator-at-the-FD-contact structure. No anticipation.

3. Family-cited and applicant-admitted references (for completeness)

4. Additional references surfaced in searching (NOT in the citation record)

Because the task asks me to "identify the most relevant prior art," I must flag — clearly and with a caveat — that my searches surfaced uncited references that are more squarely § 102-relevant to the doping limitation than anything the examiner cited. These are not part of US10805562's citation record; I did not fabricate them, and each should be verified before use.

5. § 102 bottom line

• No anticipation by any cited reference. The five examiner-cited references each disclose, at most, one of the two pillars of the claim set: (a) the two-photoelectric-conversion-unit / stacked architecture (Fujifilm US2008/0079806A1, JP2008085159A; the applicant-admitted Sony PTLs), or (b) the notion that an FD may be doped differently from other diffusion layers or adjusted per pixel (Sony JP2006086241A; Sony JP2006108466A; Apple US8773562B1). None discloses the combination required by independent claims 1, 7, 8, and 9 — specifically, an FD that (i) accumulates charge generated by a second photoelectric conversion unit and (ii) is doped lower than the source/drain diffusion layer whose gate lies between that layer and a portion of the first conversion unit.
• Closest § 102 candidates within the cited set: claim 8 vs. JP2006086241A, and claims 3–4 vs. JP2006108466A — but each fails on the explicit "lower-than-source/drain" (or "second-FD-lower-than-first-FD") relative-doping limitation and/or the two-unit geometry. Formal § 102 rejections over these references would not hold.
• Most vulnerable claims remain 7 (method) and 8 (broad semiconductor device) — but on § 103 grounds over JP2006086241A / JP5564847B2 (separate FD implant step at a lower dose), not on the cited § 102 art.
• Most defensible claims: claim 5 (insulator between the contact electrode and the FD/substrate — no cited reference discloses this) and, to a lesser degree, claim 10's specific three-color geometry.
• Recommendation: if a validity challenge is contemplated, the uncited references in § 4 — above all US 2005/0023580 A1 and JP H05-291550 A — should be pulled in full and considered as primary § 102/§ 103 art against the broader device claims; the examiner-cited set is better suited to a § 103 combination (Fujifilm/Sony architecture + Sony per-pixel FD-doping teaching + Apple chip-stack).

Verification caveats: Full text was verified for JP2006086241A, JP2006108466A, US2008/0079806A1, and the US2010/0200895A1 / US2005/0023580A1 / JPH05291550A excerpts; content for JP2008085159A, JP5509846B2, JP2014060199A, and PTL1–3 is established only by the citation/admission record and was not independently read. No patent number or technical identifier above has been auto-corrected.

I'll verify a couple of load-bearing reference disclosures before building the § 103 combinations.

Obviousness Analysis Under 35 U.S.C. § 103 — US 10,805,562

0. Cross-reference flag before I begin

The prior sections contain an internal inconsistency I am required to flag: the "Litigation summary"/"Strategic summary" refer to "claim 10 — substrate/green-film limitation" as independent ("claims 1 and 7–10 independent in substance"), while the "Patent summary" correctly lists independent claims as 1, 7, 8, and 9. Literal reading of the claim set controls: claim 10 is dependent on claim 1 ("10. The imaging device according to claim 1, further comprising a substrate, wherein..."). I treat claim 10 as dependent throughout. Nothing else in the prior sections is contradicted by this analysis.

All prior art below comes from the reference set catalogued in the Prior Art section (the five "Patent Citations," the three "Family Cites Families," and the three PTLs the applicant itself identified in the Background). Search-verified additions are labeled as such.

1. The legal frame

• Governing law: AIA § 102/§ 103 applies (priority 2015‑07‑17, post‑2013‑03‑16). Each cited reference published before 2015‑07‑17 and is § 102(a)(1)/(a)(2) art.
• Graham v. John Deere factors: (1) scope/content of the prior art; (2) differences between prior art and claims; (3) PHOSITA level; (4) secondary considerations.
• KSR Int'l v. Teleflex (550 U.S. 398 (2007)) supplies the rationales I rely on, all of which are available without an express TSM in a reference:
  1. combining prior art elements according to known methods to yield predictable results;
  2. simple substitution of one known element for another;
  3. use of a known technique to improve a similar device in the same way;
  4. application of a known technique to a known device ready for improvement;
  5. "obvious to try" — a finite number of identified, predictable solutions;
  6. design incentives/known needs in the field.
• Doping-level cases: In re Aller, 220 F.2d 454 (CCPA 1955) (discovery of an optimum value of a process variable is generally obvious); In re Peterson, 315 F.2d 571 (CCPA 1964) and Titanium Metals v. Banner, 778 F.2d 775 (Fed. Cir. 1985) (range overlap / broad ranges disclosed in prior art); In re Applied Materials, 692 F.2d 1289 (Fed. Cir. 1982); MPEP § 2144.05(II). These are directly on point because the asserted distinction is an implant dose relationship, not a new structure.
• Procedural posture: no IPR/PGR and no litigation has ever tested this patent (per the earlier sections). There is therefore no FWD, no claim construction, and no patentee statement in a contested record to work from. Everything below is a fresh-attack analysis.

2. PHOSITA

A person of ordinary skill at the 2015 priority date: a B.S. in EE/Applied Physics/Materials Science (or equivalent) plus 2–5 years in CMOS image-sensor process integration or pixel design, or an M.S. with 1–3 years. That person knows: 4T CMOS pixel layout (PD – transfer gate – FD – reset/amp/select), the use of ion-implantation mask sets to set discrete diffusion-layer doses, FD conversion gain vs. capacitance trade-offs, back-illuminated and stacked (chip-laminated) sensor architectures, and organic photoelectric conversion films formed over a silicon substrate. Both the patent and every reference in the set are addressed to that person.

3. Constructions that shape the § 103 attack

4. The reference set and what each contributes

Corroborating search results this session (not part of the cited record, but confirm the state of the art): Sony's own vertical-spectroscopic disclosures — an organic film over stacked B and R photodiodes with FD1/FD2/FD3 and a through electrode to the amplifier gate (e.g., https://patents.justia.com/patent/20200221042; https://patents.justia.com/patent/[11302728](/patent/11302728)), and WO2013088983A1's first/second charge-accumulation sections with a vertical transfer gate feeding an FD (https://patentimages.storage.googleapis.com/e4/8b/eb/b42c6252775e97/WO2013088983A1.pdf). These are useful corroboration that the structure was communal knowledge; note their publication dates relative to 2015‑07‑17 before relying on them as art.

5. Combination 1 (PRIMARY): Admitted PTLs (JP2007‑329161A / JP2010‑278086A / JP2011‑138927A) + A1 JP2006086241A — claims 1, 2, 3, 9, and via 1 → 4, 10

Why the admitted PTLs are the correct primary: the applicant wrote into its own specification that the art already taught the exact pixel architecture the claims are built around — a photoelectric conversion unit on an upper part of a semiconductor substrate whose photoelectric conversion signals are accumulated in the semiconductor substrate. That is elements [1.1] and [1.2] (first PCU + film PCU; the film's charge accumulated in a substrate diffusion node). Under KSR and MPEP § 2129, an applicant's characterization of what the art already discloses is an admission usable in the obviousness case.

Why A1 supplies the rest: A1 is a Sony CMOS pixel showing PD → read gate → FD, with the FD also serving as the reset transistor's source diffusion layer, and — decisively for § 103 — A1's granted method claim recites separate masking and implantation for the FD relative to other diffusion layers, and formation of an FD region in the same implant step as the transistor's low-concentration diffusion layer. A1 therefore teaches both the process lever (claim 7) and the concept that FD concentration is an independent, deliberately-chosen variable (claims 1, 3).

Element-by-element (claim 1)

Motivation to combine (articulated, KSR-grounded)

1. Same field, same problem, same solution type. All references are CMOS/stacked image-sensor disclosures; A1's stated objective is high sensitivity in a micronized element while suppressing junction leakage/dark-current effects at the FD. The patent's stated problem is noise/white-points originating in the FD. A PHOSITA seeking to improve the admitted film-over-substrate pixel would apply A1's known FD-doping technique to the film's FD node. (KSR rationales 1, 3, 4.)
2. A1 expressly teaches that FD dose is independently maskable. Because A1's own method forms the FD's region through a dedicated opening, there is a structural and process teaching that FD concentration need not track the transistor S/D concentration — which is precisely the relationship the claim recites. This is not hindsight; it is A1's stated fabrication scheme.
3. Known desirability of reduced FD junction field. Lowering the implant dose at a charge-accumulation junction reduces junction field and leakage; A1 is directed to exactly that failure mode. The patent's own rationale for the low-dose FD (avoiding defect sources gathering at a high-concentration layer) is the same physical consequence, obtainable by the same act — lowering the dose. (KSR rationale 5.)
4. Predictable result / reasonable expectation of success. Nothing in the claim requires a new material, new geometry, or new process. The patent's own FIGS. 3–9 method is three conventional resist-masked ion implants; the specification identifies no criticality, no data, and no unexpected process window for the 1e18–1e20 range it prefers.
5. The claim recites no numbers. The only quantitative support (1e18–1e20 cm⁻³ for FD vs. ≥1e20 cm⁻³ for the other layers) overlaps at 1e20 and describes a differential of, at most, one order of magnitude at the low end. Under Peterson/Aller, that is a range/dose optimization the prior art renders prima facie obvious absent a showing of criticality.

Claim 2 — longitudinal arrangement: admitted PTLs + A3 (film above in-substrate PDs, same incident-light direction) + A5 (vertical stacking). Covered.
Claim 3 — simply the relative-concentration limitation applied to the film's FD: same evidence as [1.5].
Claim 9 — electronic device containing such an imaging device: the specification's own FIG. 14/15 apparatus; a conventional combination of a known sensor with a camera signal-processing chain; no separate substantive limitation.

6. Combination 2 (structural alternative): A3 US20080079806A1 + A1 JP2006086241A (+ optional A2 JP2006108466A) — claims 1, 2, 3, 9, 10

Use this if the petitioner prefers a US printed publication as primary. A3 expressly discloses in-substrate photoelectric converting devices and on-substrate photoelectric converting devices (first electrode / photoelectric-converting layer / second electrode) in the same pixel plane above the substrate, each with separate signal readout — elements [1.1] and the longitudinal stacking of claim 2. The residual gaps are (a) that A3 does not state the film's charge is accumulated in a floating diffusion in the substrate, and (b) the concentration differential. Gap (a) is closed by A2/admitted PTLs; gap (b) by A1. Motivation: A3 is aimed at endoscope/low-light imaging where noise and dark current dominate; a PHOSITA modifying A3's readout node would look to the mainstream CMOS-pixel art (A1) for FD noise mitigation. Claim 10 (red/blue PDs in the substrate + green film on the substrate + the diffusion layer between the first and third PCU) is the vertical-spectroscopic configuration A3 shows generically (substrate PDs + overlying film) and that Sony's own family art corroborates; selection of which color the film handles is an unpatentable design choice absent evidence of a color-critical result.

7. Combination 3: A5 US8773562B1 + A1 (+ admitted PTLs) — claims 4, 6, 8

Claim 4 (two FDs, second lower than first). The admitted PTLs/A3 structure inherently has two distinct accumulation nodes (film node and PD-transfer node). Setting them to different concentrations is the classic optimization of a result-effective variable: the specification itself supplies the reason (the film's FD accumulates charge for a long time, so its leakage budget is tighter). A1 already teaches graded, region-dependent FD concentrations within a single node (regions 31/32), which is a fortiori a teaching to differentiate between nodes. A5 adds "different doping for the one or more gates within the pixel architecture" and adjustable-conversion-gain FDs, showing node-dependent doping as a known design tool. This claim is likely the second-easiest to invalidate after claim 8.

Claim 6 (sensor chip + logic chip laminated; the compared diffusion layer is on the logic chip). A5 is the strongest reference in the record for chip lamination: it discloses a photodiode chip + transistor array chip + logic chip vertical stack, with the FD on the transistor array chip, and (in the continuation family, US2014/0211056, US2016/0043126) a transfer gate extending vertically between chips so that the gate lies between the PD (lower chip) and a drain region on the upper chip, plus differently doped inter-chip contacts. Motivation: stacking separates photodiode area from readout area to shrink pixels — the stated purpose of A5 and of the art generally — and the FD dose is then a free design variable. Caveat: A5 places the FD on the transistor array chip, not the logic chip. A petitioner will need either (i) art placing readout transistors in the logic chip, or (ii) the argument that claims 1/6 read on a two-chip sensor+logic laminate, which A5's three-chip stack makes obvious to pursue. Do not treat claim 6 as a "clean" obviousness case on this record.

Claim 8 (semiconductor device, no imaging limitation). The broadest claim. A1 alone establishes FD + transfer gate + photodiode geometry, with the FD doubling as a transistor source/drain. The only additions are (i) the low-concentration FD relationship and (ii) a second PCU ("a portion of a photoelectric conversion unit" is all claim 8 requires — A1's PD satisfies even this in the alternative reading). Combining A1 with A3/admitted PTLs for the film PCU, and invoking Aller/Peterson for the dose, makes claim 8 the most vulnerable claim in the patent. Note also: because claim 8 requires only "a photoelectric conversion unit" while claim 1 requires first and second units, claim 8 is broader than claim 1 and the only claim that a single-reference-plus-optimization theory can reach.

8. Combination 4 (method): claims 7 and its dependents — A1 + JP2014060199A (Toshiba) + A3/admitted PTLs

Claim 7 requires only that the FD and the S/D diffusion layer be formed in separate steps, with the low/high concentration relationship. This is squarely taught:

• A1/JP4604621B2: "the formation of the first region in the floating diffusion is performed in the same process as the formation of the low concentration diffusion layer of the transistor... when the second region in the floating diffusion is formed, a mask that opens the second region is formed on the substrate, and impurities are introduced into the active region from the mask." That is literal separate masking for the FD relative to other diffusion layers.
• JP2014060199A (Toshiba) supplies method-level art for forming the diffusion layers of a solid-state imaging device.
• The patent's own FIGS. 3–9 admit the method is three ordinary resist/opening/ion-implantation steps (resist 101/103/105, openings 102/104/106) with the gate electrodes used as part of the implant pattern. A PHOSITA performs separate implants as a matter of routine mask-set design.

Motivation/expectation: adding a mask step to set a distinct FD dose is a routine process-integration choice, and A1 already did it for a related purpose. No critical process parameter is claimed (KSR rationales 1, 3, 4; In re Aller).

9. Claim-by-claim bottom line

10. Where the case breaks — and the patentee's best rebuttals

(a) Claim 5 is the patent's real defensive wall. The patent itself concedes that further lowering the FD concentration creates a Schottky junction and "an increase in the contact resistance becomes apparent," and that the claimed cure is an insulator 110 (SrTiO₃, ZrO₂, TiO₂, La₂O₃, Y₂O₃, HfO₂, Ta₂O₃, HFSiO₄, Al₂O₃) producing a tunneling contact. A5 discloses Schottky contacts in a stacked imager and differently doped inter-chip contacts, which supports the problem recognition and the motivation to manage contact-barrier behavior — but A5 does not disclose an insulator between an FD contact electrode and the substrate. Unless a petitioner adds MIS/tunnel-oxide contact art (or organic-film sensor through-electrode art with an interposed insulating layer), claim 5 should be expected to survive. Note the claim-drafting consequence: a petitioner who invalidates claim 1 but not claim 5 leaves a viable asserted claim standing.

(b) Teaching away / unexpected results aimed at claim 1 — weaker than it looks. A1 deliberately retains a high-concentration FD region 32 for contact purposes; the patentee will argue A1 teaches away from a wholly low-concentration FD. Two responses: (i) claim 1 recites only a relative relationship between the FD and the transfer-node diffusion layer, not an absolute ceiling or a prohibition on a contact enhancement region, so any measured differential satisfies it; and (ii) the patent's own preferred values (FD 1e18–1e20 cm⁻³ vs. others ≥1e20 cm⁻³) describe at most a modest reduction, whereas the Schottky problem the patentee relies on arises only at the further reduced ~1e17–1e19 cm⁻³ values tied to the FIG. 10/claim 5 embodiment. The unexpected-difficulty story therefore does not reach claim 1's scope.

(c) Problem-recognition argument. The patentee can argue the invention resides in identifying that defect sources gather in the high-concentration FD. That is a genuine nonobviousness theme, but it is a problem-recognition argument unsupported by any comparative data in the specification — the specification asserts white-point/white-scratch/black-point suppression and "improving the yield" without a single measurement. Under KSR, "[t]he combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results"; and the physical mechanism invoked (metal-impurity precipitation at heavily doped n⁺ regions reducing upon lowered doping) is a known semiconductor-fabrication phenomenon, which undercuts "unexpected."

(d) File-history blindness. The record shows a non-final action (2019‑12‑10) followed by allowance (2020‑06‑10). Issued claim 1 is materially narrower than the originally-filed "An imaging device including: a photoelectric conversion unit..." formulation, having been amended to add the first/second PCU split and the gate-placement clause. The inference — flagged as inference, not fact — is that the examiner's allowance rested on those added structural limitations rather than on the concentration differential alone. If so, the petitioner's burden concentrates on the two-PCU mapping (A3/A2/admitted PTLs) and not on the doping limitation, which may already have been implicitly conceded as unpatentable-in-substance or at least insufficiently distinguishing. Obtain the file wrapper before finalizing any petition or invalidity contention.

(e) Secondary considerations (Graham factor 4) — thin, and mostly cut against the patentee. Commercial success: Sony Semiconductor Solutions is a leading image-sensor supplier, but the record contains no evidence of a nexus between sales and the FD-implant dose; that feature is invisible to customers. Long-felt need: the need to suppress FD leakage/dark-current in miniaturized pixels was long recognized and actively being solved (A1 in 2006), which cuts against rather than for patentability. Copying/praise/licensing: nothing on the record. Improved yield: asserted in the specification as attorney characterization, not evidence; and post-filing evidence of yield improvement must be tied by nexus to the claimed dose differential.

(f) Citation-data caveat carried forward. The Google Patents "Cited By" list is dominated by unrelated Charter Communications wireless patents — a bibliographic artifact (already flagged earlier). Do not use it. The two substantively relevant citations in that list are SEM image-sensor-related only.

11. Practical recommendation

• Lead theory for a validity challenge: admitted PTLs (JP2007‑329161A / JP2010‑278086A / JP2011‑138927A) + JP2006086241A, with US20080079806A1 and US8773562B1 as structural secondaries. This reaches claims 1, 2, 3, 4, 7, 8, 9, 10.
• Do not file without: (i) the actual texts of JP2006108466A, JP2008085159A, JP5564847B2, JP5509846B2 and JP2014060199A (never retrieved in this analysis — their content could materially strengthen or complicate the mapping); (ii) the prosecution file wrapper; and (iii) additional art for claims 5 and 6, which this record does not defeat.
• The single most useful structural insight for any § 103 attack: claim 1's "gate electrode... between the diffusion layer and a portion of the first photoelectric conversion unit" is nothing more than the transfer gate of a conventional 4T pixel. That reduces the entire claim to (a) a film-over-photodiode pixel — admitted prior art by the applicant — plus (b) a lower implant dose at the film's accumulation node, which A1 shows how to set independently by mask and which In re Aller/Peterson treat as routine optimization.

Confidence: HIGH on all claim text, the A1/A3/A5 disclosures verified this session, and the applicant's own Background admissions; MODERATE on the A2/A4/Group-B contributions and on the prosecution-history inference in § 10(d); no assertion above should be relied on for a filing without retrieving the full text of the unverified references.