US 9773865

I'll search for this specific patent number across USPTO and litigation sources.

Let me run additional targeted searches for litigation and any 2026 court activity.

Analysis: US Patent 9,773,865 ("9773865")

Identity note (literal interpretation): The number "9773865" as provided resolves in the authoritative record to US 9,773,865 B2 — publication US9773865B2, application US 14/492,123. I did not auto-correct; this is the matching patent.

Search outcome up front: My searches did not surface any CAFC 2026 docket or any live USPTO litigation proceeding referencing this patent. Searches for "865"-related litigation returned only unrelated patents (e.g., U.S. 11,972,865 B1 in a WebMD/Alice dispute; a Regeneron '865 patent; a stethoscope '865 patent) — none of these are US 9,773,865, and I am not conflating them. I cannot confirm the existence of any 2026 appellate activity for this patent from the available results. Treat the litigation-status portion as unverified.

Bibliographic data (from the authoritative patent record)

Assignee caveat: Elpis Technologies Inc. is the record assignee as a WiLAN (Quarterhill) subsidiary that acquired a semiconductor-process patent portfolio from IBM (publicly announced Feb. 2020), and it later lapsed this patent for non-payment of maintenance fees. I could not verify any 2026 CAFC involvement.

Abstract (verbatim)

"A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin."

Plain-language overview of the independent claims

Claim 1 — Single-step oxidation + water wet-etch removal (the core method).
Build a finFET in which the (dummy) gate crosses over the fin perpendicularly. Then, in one oxidation step, grow a gate spacer on the gate's exposed surfaces and a fin spacer on the fin's exposed surfaces — with the claim expressly requiring the gate's exposed surfaces to include at least a vertical surface and the fin's exposed surfaces to include at least a horizontal and a vertical surface. Finally, strip the fin spacer with a water wet etch. Crucially, the claim recites that both spacers are exposed to the same water wet etch, yet only the fin spacer is removed and the gate spacer remains. The inventive hook is selectivity-by-material rather than by masking/directional etching.

Claim 8 — Dummy-gate embodiment with material-specific oxides, maskless removal.
Pattern a dummy gate above and perpendicular to a semiconductor fin using a hardmask that stays in direct contact with the dummy gate's top surface. Oxidize the exposed surfaces to form silicon dioxide gate spacers on the dummy gate's opposite vertical sidewalls, and a germanium oxide fin spacer on both the top surface and vertical sidewalls of the fin. Then remove the germanium-oxide fin spacer without any mask, exposing the fin's top and sidewalls while leaving the SiO₂ gate spacers intact. This claim hard-codes the SiO₂/GeO₂ chemistry pairing that makes the differential removal possible.

Claim 14 — SOI/fin-level process integrated with replacement metal gate.
Form fins in the top (SOI) layer of an SOI substrate so the buried oxide is exposed between fins. Pattern a polysilicon dummy gate above and perpendicular to the fins with a hardmask in direct contact on top. Simultaneously grow SiO₂ gate spacers (only along the dummy gate's vertical sidewalls, since the hardmask does not oxidize) and a GeO₂ fin spacer (on the fins' vertical sidewalls and top). Remove the GeO₂ fin spacer by exposing both spacers to a wet water etch (gate spacers survive). Finally, replace the hardmask and polysilicon dummy gate with a metal gate.

Dependent-claim highlights: SOI substrate (claims 2, 9); rapid thermal oxidation (3, 10, 16); low-temperature oxidation (4, 11, 17); the Ge-fin/GeO₂ vs. polysilicon-gate/SiO₂ material pair (5); epitaxial/merged source-drain formation (6, 12, 18); a second nitride spacer, typically after epitaxial source-drain growth (7, 13, 19); and replacement-gate details — remove hardmask + polysilicon selective to spacers and fill the vacated space with metal (15).

Technical essence

The patent's stated problem is that conventional conformal-deposit-then-RIE spacers are tapered, suffer corner rounding, and become destructive to scaled fins (RIE can eat into the fin). The disclosed fix is to grow the spacer by oxidation instead of depositing it: because the dummy gate (e.g., polysilicon) and the fin (e.g., germanium) oxidize into chemically distinct oxides (SiO₂ vs. GeO₂), a benign water wet etch can selectively clear the fin's oxide while leaving the gate's oxide spacer intact — avoiding a masked RIE step. Oxidation options cited include rapid thermal oxidation (~500 °C, ~5 s), high-pressure wet oxidation (H₂O/O₂, 5–20 atm, 650–800 °C as written), and low-temperature oxidation (≤~700 °C, e.g., HIPDX high-pressure oxidation). The specification also notes the process may extend to planar devices, nanowires, and gate-first flows.

Confidence / uncertainty statement

• High confidence on all bibliographic fields, the abstract, claim text, and overview — these come directly from the authoritative patent document supplied.
• Low/uncertain on any 2026 CAFC docket or litigation: no such record appeared in search results. I found no evidence of a CAFC 2026 appeal involving US 9,773,865, and I explicitly decline to assert one exists. Note the record internally lists some OCR/typographical oddities (e.g., "650-80° C," "HIPDX") that I have preserved rather than silently corrected.

I'll search for litigation involving US patent 9773865 across patent litigation resources.

The first search returned an unrelated "386 Patent" (a Kubota loader-arm IPR). Let me search more specifically, including the current assignee Elpis Technologies.

Let me search the litigation databases directly.

Summary: No litigation identified for US 9,773,865

I was unable to identify any litigation involving US Patent No. 9,773,865 ("Self-forming spacers using oxidation"). Before giving you the details, an important interpretive note and the limits of my search:

⚠️ Critical identification warning

Searches for the bare string "9773865" return results for a completely different patent that is also commonly abbreviated as "the '386 Patent" — an IPR involving Kubota North America Corp. and a vertical-lift compact utility loader arm (JP705, McIlwraith, Beltrami, KR996 references). That is not US 9,773,865. I did not count it. Any litigation search on this number must be careful not to conflate the two.

What I confirmed about the patent itself (from the authoritative patent record)

• Patent: US 9,773,865 B2 — "Self-forming spacers using oxidation"
• Application: US 14/492,123, filed 2014-09-22; priority date 2014-09-22; granted 2017-09-26
• Inventors: Kevin K. Chan, Masaharu Kobayashi, Effendi Leobandung
• Original assignee: International Business Machines Corp.
• Current assignee: Elpis Technologies Inc. (assignment recorded 2020-05-11, effective 2020-03-06)
• Legal status: Expired – Fee Related. Maintenance fees were not paid; the patent lapsed effective 2021-09-26 (docketed 2021-11-01 under 37 CFR 1.362). Anticipated expiration would otherwise have been 2034-09-22.
• Family: Continuations/divisionals US 10,068,967; US 10,566,417; US 10,833,156 (same title, same priority).
• Cited-by (later patents), not litigation: US 9,916,982 (GlobalFoundries) and IBM's own US 10,971,584 / US 10,446,664 — these are patent citations, not lawsuits.

Litigation findings

None found. Neither the Google Patents record for this patent nor my web searches surfaced any district court, ITC, PTAB, or CAFC proceeding naming US 9,773,865 as an asserted or challenged patent.

Important caveats — please verify independently

1. I could not reach the Unified Patents litigation portal or PACER directly. My searches for portal.unifiedpatents.com and for Elpis Technologies case lists returned no usable results, and I hit the tool-use limit before completing them. So this is "not found," not a definitive "none exists."
2. Elpis Technologies Inc. is a known patent-holding/monetization entity that acquired large portfolios of IBM semiconductor patents around 2020. It is plausible that such a portfolio was asserted in campaigns, but I could not confirm that US 9,773,865 specifically was ever asserted, and I will not speculate that it was.
3. Because the patent lapsed in September 2021, any infringement action asserting it would have had to be filed before expiration (past damages still potentially recoverable for pre-lapse conduct, but the patent is no longer enforceable going forward), which further reduces the likelihood of active litigation.

Bottom line: Based on the sources I could reach, there is no known litigation involving US 9,773,865. For a definitive answer, I recommend querying the Unified Patents litigation portal and PACER/RECAP by patent number and by assignee "Elpis Technologies Inc." directly, applied to patent number 9,773,865 only.

I'll verify the structured-data default with targeted searches before concluding.

Let me run a few more targeted searches on the patent's family and any litigation/PTAB linkage.

PTAB / AIA Trial Analysis — US 9,773,865 B2

"Self-forming spacers using oxidation" · inventors Chan, Kobayashi, Leobandung · original assignee IBM Corp. · current assignee Elpis Technologies Inc. · App. No. 14/492,123 · filed/priority 2014-09-22 · granted 2017-09-26

Proceedings overview

Total AIA trial proceedings on file against US 9,773,865: zero.

The structured "PTAB proceedings on file" block supplied in this prompt — sourced from the USPTO Open Data Portal — returns no IPR, PGR, or CBM proceedings for this patent, and targeted web searching surfaced no AIA trial referencing US 9,773,865 or application 14/492,123. There is therefore no breakdown to report: 0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denials. Bottom line for a defendant: you get no free invalidity judgment from the Board, and no estoppel shield — but you also do not need one, because the patent lapsed for non-payment of maintenance fees effective 2021-09-26 and is recorded by the Office as "Expired – Fee Related." That status, not any PTAB outcome, is the controlling defensive fact.

⚠️ Confidence note: I hit my tool-call budget before I could exhaustively query PTAB E2E / PTAB Decisions directly. I found no proceeding, and the ODP structured data says there is none, but treat this as "no evidence of activity" rather than a certified negative docket check. A defendant should re-run the search at the PTAB E2E portal (https://ptacts.uspto.gov/ptacts/public-informations/) and against Docket Navigator / Unified Patents' portal before finalizing a non-infringement/invalidity budget.

Proceedings

(None)

There are no proceeding sections to populate. I will not manufacture IPR numbers, panels, or dispositions for a patent with no AIA trials. For completeness, here is what I affirmatively did not find, so the negations are precise:

Search noise warning. Several public results mention a "'977 patent" as prior art or claim subject matter — e.g., Philips' '977 in an ITC/PTAB dispute, Nobel Biocare's '977 in IPR2015-01786, and U.S. Patent 6,629,977 in Smith & Nephew's IPR2016-00819. None of those are US 9,773,865. They are different patents that happen to share the last three digits. Do not let a search engine tell you this patent was invalidated.

Strategic summary

Claim status. Because no AIA trial ever reached a Final Written Decision on US 9,773,865, no claim of the patent has been canceled or amended by the Board. The patent issued with 19 claims — independent method claims 1, 8, and 14, with dependents 2–7, 9–13, and 15–19 — and all 19 stand (or stood) as issued. The claim set is therefore "UNTESTED by the PTAB," which in a normal case would mean the patent is undamaged and fully available to the patent owner. The invalidity risk to a defendant is entirely in the district court or the Board on a fresh petition, not in any existing record.

Estoppel landscape. With no FWD under 35 U.S.C. § 318(a), § 315(e)(2) estoppel has never attached to anyone. No petitioner is barred, and no defendant enjoys the collateral benefit of a prior petitioner's work product. Any prior-art ground — § 102 anticipation, § 103 obviousness, § 112 written description/enablement/indefiniteness — remains available to a fresh petitioner, subject only to the ordinary § 315(b) one-year bar if that petitioner was served with a complaint. Practically, this means a defendant is starting from scratch: no institution decision to lean on, no adopted claim constructions, no expert discovery to inherit.

The real defensive signal is the patent's legal status, not the PTAB docket. The Office's Legal Events record shows the maintenance-fee reminder mailed 2021-05-17, lapse for failure to pay effective 2021-09-26, and a 2021-11-23 docket entry "Lapsed due to failure to pay maintenance fee, effective 20210926." This is a large-entity owner (Elpis Technologies Inc., the Canadian monetization vehicle that took assignment from IBM effective 2020-03-06 per REEL/FRAME 052620/0961) that simply stopped paying the 3.5-year maintenance fee on an IBM FinFET-spacer patent. The same lapse is recorded across the family (US 10,068,967; US 10,566,417; US 10,833,156 — all "Expired – Fee Related." See the Google Patents family view: https://patents.google.com/patent/US9773865/en).

Note the family-structure nuance for a defendant: US 10,068,967 (divisional off this application), US 10,566,417, and US 10,833,156 are separate patents with their own claim sets, not claims of US 9,773,865. US 10,833,156 in particular claims a structure (a metal gate with oxide spacers of equal height, a nitride gate cap, and stepped nitride spacers) — different subject matter from the method claims of the '865 patent. If a demand letter bundles the family, check each patent number independently; do not assume an analysis of '865 covers '156.

Pattern signals. No repeat petitioner, no serial filings, no appellate history, and no aggregator campaign on the PTAB side. Historically the patent was held by a monetization entity (Elpis/IBM), which is exactly the profile that attracts IPRs — and yet none were filed against this patent. That is consistent with the patent being of marginal independent value once the family lapsed in 2021.

Recommended next steps

1. Lead with the lapse, not with invalidity. A defendant receiving a demand that cites US 9,773,865 today is being asserted on an expired patent. Rights lapsed 2021-09-26 for non-payment of the 3.5-year maintenance fee (35 U.S.C. § 41(b); 37 C.F.R. § 1.362). Confirm current status at USPTO Patent Center before responding: https://patentcenter.uspto.gov/. Any damages theory is limited to infringement before 2021-09-26 and further capped by the six-year lookback of 35 U.S.C. § 286 — i.e., the recoverable window is roughly 2020-09-30 to 2021-09-26, a very narrow slice.

2. Check for reinstatement. The owner can attempt revival by petition under 37 C.F.R. §§ 1.378(b)–(d) (unintentional delay) if the fee was missed unintentionally, and interim rights may be affected by § 41(c)(2). If the patent has been reinstated since the ODP ingest, re-run this analysis — a revived patent is enforceable again for prospective conduct, though intervening rights under § 41(c)(2) and 35 U.S.C. § 252-style equitable intervening rights may protect a defendant's prior product designs.

3. If the family — not just '865 — is asserted, treat each patent separately. For each asserted patent number, pull the patent number, the claims asserted, and confirm (a) expiration/lapse status, and (b) whether any AIA trial exists. Run each number through PTAB E2E (https://ptacts.uspto.gov/ptacts/public-informations/) and Docket Navigator. Do not accept a demand letter's claim that a family member was "upheld by the PTAB" — there is no such record for any member of this family on the evidence I found.

4. Preserve invalidity defenses without a PTAB record. Since no estoppel has attached and no claim has been canceled, the entirety of the prior art — including the 18 references of record and the two non-patent citations (Kobayashi 2009 on radical oxidation of germanium; Sekine 2001 on low-temperature radical oxidation) — is fair game in district court. Note that the patent's own prosecution history leans on "beta value" control in rapid thermal oxidation (see US 7,439,607, "Beta control using a rapid thermal oxidation," among the cited art), which is a natural § 103 attack surface if the patent is ever revived and asserted.

5. Do not spend IPR budget yet. Filing a petition against an expired, lapsed patent is generally a waste — the Board will not institute where there is no live controversy of sufficient value, and the cost/benefit fails. Reserve petition drafting until the owner demonstrates live rights and a served complaint.

Verification links: USPTO PTAB E2E — https://ptacts.uspto.gov/ptacts/public-informations/; PTAB Decisions — https://www.uspto.gov/patents/ptab/decisions; CourtListener (for any CAFC appeal) — https://www.courtlistener.com/; patent text and full family — https://patents.google.com/patent/US9773865/en.

Bottom line for a defendant: "No PTAB activity on file" is accurate, and the patent has not been narrowed by the Board — but the patent lapsed in 2021 for failure to pay maintenance fees, so the practical defensive posture is "the troll has no live patent to assert unless it revives, and even then only for a six-year pre-expiration window", not "the patent is hardened." Confirm status in Patent Center the same day you receive any demand.

I'll research the assignment chain and the current assignee before writing up.

Assignment Record Reconstruction — US 9,773,865 B2 ("Self-forming spacers using oxidation")

Source caveat up front: The two reel/frame numbers below are taken from the legal-events record embedded in the authoritative Google Patents full text supplied for this patent (https://patents.google.com/patent/US9773865/en). I was not able to complete a live pull of the USPTO Assignment Center's correspondent-of-record fields within this session — the Assignment Center index did not return records for the queries run. Correspondent / attorney-of-record data is therefore reported as "not retrieved" rather than guessed. Verify at https://assignmentcenter.uspto.gov/ (search by patent number 9773865) or https://assignment.uspto.gov/patent/index.html.

Inventors

Pattern note (not a finding of wrongdoing): All three inventors were IBM employees and assigned to IBM by pre-printed ASSIGNMENT OF ASSIGNORS' INTEREST within ~2 weeks of filing; all three appear on the sibling continuations in this family (US 10,068,967; US 10,566,417; US 10,833,156). There is no evidence of inventors departing before a fire-sale — the inventors simply never held title. The relevant anomaly in this chain is the assignee, not the inventors.

Original assignee

International Business Machines Corporation (Armonk, NY) — named on the issued patent; assignee of record per Reel 033784/0075.

• Line of business: Diversified enterprise IT — hybrid cloud, software, consulting, mainframe/systems. Through 2015 IBM also operated a semiconductor manufacturing business (300 mm fabs at East Fishkill, NY and Burlington, VT) that fabricated FinFET/SOI devices — i.e., IBM was a practicing entity with respect to the claimed FinFET spacer-formation methods at filing.
• Product embodying the claims: Partially — the claims recite a method of forming a gate spacer by oxidizing exposed surfaces of a dummy gate and a germanium fin. IBM's 22 nm/14 nm SOI FinFET process line was the natural embodiment. Caution: IBM's implementation used different materials in at least some flows, and I cannot confirm from available records that an IBM-shipped process practiced every limitation. Treat "shipped an embodying product" as plausible but unverified.
• Current status: Operating. IBM remains a going concern (NYSE: IBM). It did not file bankruptcy. It exited semiconductor manufacturing — the Microelectronics division (fabs) was transferred to GlobalFoundries, announced October 2014 and closed July 2015, roughly five years before the 2020 patent transfer. That timeline matters: by the time of the Elpis sale, IBM had no in-house fab practicing the claims.

Assignment timeline

1.

• 2014-09-09 to 2014-09-12 (executed) / recorded 2014-09-22 — Reel 033784/0075
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
  • Assignor: Chan, Kevin K.; Kobayashi, Masaharu; Leobandung, Effendi
  • Assignee: International Business Machines Corporation, New York
  • Correspondent: not retrieved — the Assignment Center correspondent field was not captured in this session; no correspondent is reproduced in the Google Patents legal-events text. Do not treat as a repeat-correspondent finding.
  • Context: Original inventor-to-employer assignment on filing (internal), not a monetization event.

2.

• 2020-03-06 (effective) / recorded 2020-05-11 — Reel 052620/0961
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNOR'S INTEREST)
  • Assignor: International Business Machines Corporation
  • Assignee: Elpis Technologies Inc. (recorded address: Canada)
  • Correspondent: not retrieved — same limitation as above.
  • Context: Transfer to asserter / monetization vehicle. This was part of a publicly announced portfolio sale: on 2020-02-20 Wi-LAN Inc. (Quarterhill Inc., TSX: QTRH) announced that its wholly-owned subsidiary Elpis Technologies Inc. had acquired IBM's "semiconductor manufacturing process technologies" patents; a second, additional IBM portfolio to Elpis was announced 2020-09-30. Terms confidential. Sources: WiLAN press release, 2020-02-20, WiLAN press release, 2020-09-30.

Post-2020 developments with no patent-level assignment recorded

• 2021-09-26 (effective) / 2021-11-01 (recorded in legal events): Patent expired for failure to pay maintenance fees (37 CFR 1.362). The 3.5-year maintenance fee was never paid. US 9,773,865 — and its entire family (US 10,068,967; US 10,566,417; US 10,833,156) — is listed Expired – Fee Related. The asset lapsed ~19 months after Elpis acquired it.
• 2023-06-15: Quarterhill completed the sale of 90% of Wi-LAN Inc. to Owlpoint IP Opportunities JVF LP — a JV of Arena Investors, LP and Owlpoint Capital Management, LLC — for up to ~C$71.4M; Quarterhill retained 10%. This is a share-level transaction; it changed Elpis's ultimate parent but I found no corresponding recorded patent assignment on this patent. Source: Quarterhill press release.

Total recorded assignments against this patent: two. One is the original inventor assignment; one is the IBM→Elpis transfer. There is no cascading chain of LLCs at the patent level.

Timeline diagram

timeline
    title Ownership of US 9773865
    2014 : Inventors assign to IBM
         : Application filed 22 Sep 2014
    2017 : Patent issued 26 Sep 2017
    2020 : IBM assigns to Elpis Technologies
         : WiLAN unit buys IBM chip portfolio
    2021 : Patent expires for unpaid maintenance fee
    2023 : WiLAN 90 percent stake sold to Owlpoint JVF
         : Share sale only with no patent assignment

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Patent moved from an operating company (IBM) to a licensing-only subsidiary. Evidence beyond the name: (a) Reel 052620/0961 records IBM → Elpis Technologies Inc., Canada, effective 2020-03-06; (b) Elpis is publicly disclosed as a wholly-owned subsidiary of Wi-LAN Inc., whose business is stated as "monetizing patents … by granting non-exclusive licenses" (Quarterhill 2021 AIF: https://s206.q4cdn.com/205234780/files/doc_financials/2021/ar/AIF-2021.pdf); (c) the acquisition was a confidential-terms bulk portfolio purchase, the classic acquisition posture for a licensing vehicle. No Elpis product line was identified. Note the entity address is a Canadian corporate address, not a Delaware/Texas registered-agent service — so the "registered-agent address" sub-tell is not present.

2. Known asserter in the chain — PRESENT.
Wi-LAN / WiLAN is expressly on the enumerated asserter list, and Elpis Technologies Inc. is a wholly-owned WiLAN subsidiary used as the acquisition vehicle for the IBM semiconductor portfolios (2020-02-20 and 2020-09-30 press releases). WiLAN has litigated patents since 2007 (e.g., Apple, NVIDIA IPRs, SK hynix license) and, post-2023, its subsidiary Eridanus Technologies, Inc. sued AMD in W.D. Tex. (1:23-cv-01036) — note this is a different "ETI" subsidiary, not Elpis, and the patents there are single-member STMicro families, not US 9,773,865 (RPX, 2023-09-04).

Important limitation: I found no evidence that US 9,773,865 itself was ever asserted. No litigation, ITC action, or demand-letter campaign naming this patent surfaced. The patent lapsed in 2021, which strongly implies Elpis/WiLAN did not consider it worth the maintenance fee. The "known asserter owns it" signal is present; an actual assertion of this patent is not evidenced.

3. Repeat correspondent across the chain — UNCLEAR / NOT RETRIEVED.
The correspondent-of-record for Reel 033784/0075 and Reel 052620/0961 was not captured in this session, and the Assignment Center index did not return the records on query. I am therefore not making a repeat-correspondent finding. This is the single highest-value item to pull manually — if the same attorney appears on both 052620/0961 and on other WiLAN/Elpis/Quarterhill acquisition recordings, that is a confirming tell. Flag for follow-up, not a conclusion.

4. Cascading transfers — NOT PRESENT.
Only one assignee-to-assignee transfer is recorded (IBM → Elpis, 2020). No chained LLC sequence within 24 months. The 2023 Quarterhill→Owlpoint event is a stock sale of WiLAN, not an assignment of this patent, and no new reel/frame exists for it.

5. Pre-litigation transfer — NOT PRESENT (no litigation to anchor against).
The IBM→Elpis transfer was effective 2020-03-06; no first infringement suit naming US 9,773,865 was identified, so the "within 6 months before first suit" test cannot be satisfied.

6. Bankruptcy fire-sale — NOT PRESENT.
IBM never filed for bankruptcy protection; this was a discretionary portfolio divestiture, announced publicly by the buyer. Not a Chapter 7/11 sale (no Kodak/Nortel/Polaroid analogue).

7. Privateering — NOT PRESENT on available evidence.
Privateering requires assertion on the operating company's behalf and typically revenue sharing or coordination. Here IBM was exiting semiconductor manufacturing (GlobalFoundries transfer closed July 2015) and appears to have made a clean outbound sale of process patents with confidential terms. No evidence that IBM directs, funds, or shares in Elpis/WiLAN assertions on these assets. (It cannot be fully excluded, since deal terms were confidential — hence "not present on available evidence" rather than "excluded.")

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at a WiLAN subsidiary, which is the inverse of this signal. The patent is neutralized only by maintenance-fee lapse (2021-09-26) — a different mechanism from defensive aggregation.

Verdict

NPE — high confidence

Two independent strong signals. (1) Known asserter: Reel 052620/0961 (effective 2020-03-06, recorded 2020-05-11) transfers title from IBM to Elpis Technologies Inc., a publicly disclosed wholly-owned subsidiary of Wi-LAN Inc. — WiLAN being an enumerated high-frequency patent-assertion entity — as part of two announced (2020-02-20; 2020-09-30) confidential bulk acquisitions of IBM semiconductor-process patents. (2) Shell/single-purpose acquisition vehicle: the assignee is a licensing-only Canadian subsidiary with no identified product, whose stated business is granting non-exclusive patent licenses. That is 2 strong signals → high confidence.

Two material qualifiers the reader must carry forward: the correspondent-of-record was not retrieved (so signal 3 is open, not negative), and no assertion of US 9,773,865 was ever identified — the patent expired 2021-09-26 for non-payment of the first maintenance fee, meaning the enforcement risk on this specific asset is effectively nil. The ownership chain is NPE-controlled, but the asset is dead.

Verify: https://assignmentcenter.uspto.gov/ (search patent 9773865; request Reels 033784/0075 and 052620/0961, including correspondent fields) · https://patents.google.com/patent/US9773865/en · family continuations US 10,068,967 / US 10,566,417 / US 10,833,156 — all also Expired – Fee Related.

Recommended next pulls: (a) Assignment Center correspondent fields on both reels; (b) an RPX Insight / Unified Patents search on "Elpis Technologies Inc." as plaintiff to determine whether the sibling continuations in this family were ever asserted; (c) if (b) is positive, re-run the pre-litigation-transfer test with the actual first-suit date.

I'll verify the specific patent and dig into its cited references. Let me run targeted searches.

Prior-art analysis — US 9,773,865 ("Self-forming spacers using oxidation")

Identification confirmed. The number 9773865 resolves, literally, to US 9,773,865 B2 (application US 14/492,123, filed 2014‑09‑22, granted 2017‑09‑26, IBM / now Elpis Technologies). I did not search or conflate any other number. This section builds on the previously generated bibliographic, claim-overview, technical-essence, and litigation sections rather than repeating them.

Important framing: what "anticipates" can mean here

The reference list below is the set of documents the examiner/third parties cited on the face of US 9,773,865 (19 US patent citations + 2 non‑patent citations, plus 7 "family‑cites‑families" references surfaced through the family members US 10,068,967 / 10,566,417 / 10,833,156). Because this application was filed after 16 March 2013, AIA 35 U.S.C. § 102 governs; every cited item published before the 2014‑09‑22 priority date, so each qualifies as § 102(a)(1) prior art as to date.

However, a true § 102 anticipation requires a single reference disclosing every element of the claim as arranged. All three independent claims (1, 8, 14) share the distinctive combination: a single oxidation step that grows chemically distinct oxides on the gate and the fin, followed by a selective water wet etch that removes the fin oxide while leaving the gate oxide spacer intact (claims 1/8/14; and claim 14 adds simultaneous SiO₂/GeO₂ growth + replacement metal gate).

No cited reference discloses that combination. None of the 19 references teaches growing two different oxide chemistries from one oxidation step and then differentially stripping one with a benign water wet etch. Accordingly, no reference below is a clean § 102 anticipation of claims 1, 8, or 14; they are cited for individual features and are best understood as § 103 obviousness/background art. Where a reference maps only to a feature recited in a dependent claim, it cannot anticipate that dependent claim standing alone either, because the dependent claim incorporates all elements of its base claim. I state for each entry which claim(s) its disclosure is most pertinent to, and flag the shortfall.

(Descriptions for references I did not directly retrieve are drawn from the authoritative title/assignee/date fields in the patent record plus my general knowledge; treat those as medium confidence and verify full text before relying on them for a validity opinion.)

A. The 19 patent citations (primary § 102/§ 103 references)

B. The two non‑patent citations (both highly pertinent to the chemistry)

1. Kobayashi et al., "Radical oxidation of germanium for interface gate dielectric GeO₂ formation in metal‑insulator‑semiconductor gate stack," J. Appl. Phys., vol. 106, no. 10, 104117 (2009), pp. 104117‑1 to 104117‑7.
   Description: Radical oxidation of a germanium surface to form GeO₂. This is the scientific basis for the claim's "germanium oxide fin spacer" (claims 5, 8, 14). Notably it is prior work of inventor Masaharu Kobayashi himself. Most pertinent to: claims 5, 8, 14 (Ge fin → GeO₂). Not anticipation — no gate, spacer geometry, or selective wet‑etch removal disclosed.

2. Sekine et al., "Highly Reliable Ultrathin Silicon Oxide Film Formation at Low Temperature by Oxygen Radical Generated in High‑Density Krypton Plasma," IEEE Trans. Electron Devices, vol. 48, no. 8 (Aug. 2001), pp. 1550‑1555.
   Description: Low‑temperature formation of ultrathin SiO₂ using oxygen radicals. Most pertinent to: claims 4, 11, 17 (low‑temperature oxidation). Not anticipation — no finFET/spacer structure.

C. "Family‑cites‑families" references (surfaced via the continuations/divisionals) — arguably the closest art

These did not appear on the ‑865 face but were cited in the related family members, and several are closer to the claimed subject matter than the face citations:

D. Bottom line on § 102 anticipation

• No cited reference — patent or non‑patent — anticipates claim 1, 8, or 14. None discloses the single‑step oxidation producing chemically distinct gate vs. fin oxides followed by a maskless water wet etch that removes only the fin oxide.
• Closest references by feature:
• US 7,439,607 B2 (RTO/beta control) — most relevant to the oxidation‑modality limitations (claims 3/4/10/11/16/17); the ‑865 specification's "beta value"/"rapid thermal oxidation … less than about 700 °C" language closely tracks this reference.
• Kobayashi et al. 2009 and Sekine et al. 2001 — the enabling chemistry for the Ge→GeO₂ and low‑temperature SiO₂ limitations (claims 5, 8, 14 and 4/11/17).
• US 2014/0103455 A1 (IBM, oxide spacers) and US 9,147,682 B2 (TSMC, fin spacers) — the nearest spacer art, though both build spacers by deposition/fill rather than by the claimed selective oxidation.
• A proper § 103 combination aimed at claims 1/8/14 would most plausibly pair an oxide‑spacer/fin‑spacer reference (US 2014/0103455 A1 or US 9,147,682 B2) with a selective‑oxidation/GeO₂‑vs‑SiO₂ reference (Kobayashi 2009 or Sekine 2001), and add a metal‑gate reference (US 2013/0307088 A1 / US 2010/0078733 A1) for claim 14. Whether such a combination would have rendered the "single oxidation step + differential water wet‑etch removal" obvious is the crux; on the face of the record the examiner allowed the claims over all of the above.

Confidence / caveats: High confidence that the 19 patent citations and 2 NPL items are the correct set cited on this patent's face (taken directly from the authoritative record). Medium confidence on the substantive descriptions of items I did not open in full text (all except US 5,854,505; US 7,439,607; US 2014/0103455; and US 2006/0172497, which I retrieved). I could not complete full‑text retrieval for the remaining references before exhausting my search steps, so verify each reference's actual disclosure before relying on this for a validity or invalidity contention.

I'll ground the key prior-art references before building the §103 analysis.

Obviousness Analysis — US 9,773,865 B2 under 35 U.S.C. § 103

Scope note (consistent with the earlier sections): This analysis builds on the bibliographic, claim-construction, and "no litigation found" sections already generated. It does not repeat them. The prior art considered is the art of record in the patent's own Prior Art section (18–19 cited references + the two non-patent citations), supplemented where I found additional public art via search — flagged as such, since the task directs me to the page's Prior Art section first.

1. Analytical frame

The obviousness attack lives or dies on one feature: forming the gate spacer and the fin spacer in a single oxidation step, then exploiting the chemical difference between the resulting oxides (SiO₂ on a polysilicon gate vs. GeO₂ on a germanium fin) so that a water wet etch strips the fin spacer while leaving the gate spacer. Claim 1 recites this explicitly, including the negative limitation that "both the fin spacer and the gate spacer are exposed to the water wet etch, but only the fin spacer is removed." Claims 8 and 14 hard-code the SiO₂/GeO₂ chemistry and add maskless removal / replacement-metal-gate integration.

Everything else in the claims — finFET with a perpendicular gate, SOI substrate, hardmask on the dummy gate, epitaxial source/drain, second nitride spacer — is squarely conventional and independently taught by the art of record.

2. The art of record that matters most

Additional public art I located (not on the page's list — flagged): WO 2003/054951 A1 expressly teaches "germanium oxide is employed as a disposable spacer material. Germanium oxide is preferred as it has the property of dissolving in water … removed very safely in water, and very selectively from other films traditionally used in semiconductor processing." (source). The differential solubility is quantified elsewhere: GeO₂ ≈ 4.47 g/L vs. SiO₂ ≈ 0.12 g/L in water (~37×) (JP2024124744A).

3. Claim 1 — the core combination

Combination A = US 2014/0103455 (finFET + oxide spacers + SOI) + US 7,439,607 (RTO of a semiconductor surface) + Kobayashi 2009 (conformal GeO₂ by radical oxidation) [+ optionally WO 2003/054951 for the GeO₂/water selectivity].

Limitation mapping:

Motivation to combine (KSR):

1. The patent admits the problem is known. The Background states conventional conformal-deposit-then-RIE spacers are tapered, suffer corner rounding, and that as fins scale they "may become more vulnerable to defects as an indirect result of spacer etching." An admitted, recognized problem supplies the "design need" prong of KSR. US 2014/0103455 addresses precisely this by moving to oxide spacers.
2. Predictable result. Oxidizing a Si-containing surface → SiO₂ and a Ge surface → GeO₂ are both known, routine, and predictable; combining two known oxidation behaviors on two different exposed materials is the paradigmatic "combination of familiar elements according to known methods … yielding no more than predictable results" (KSR, 550 U.S. 398, 416).
3. Only water in the removal step. Using water as a selective GeO₂ remover is expressly motivated by WO 2003/054951 and by the ~37× solubility gap; a PHOSITA would select water because it is maximally benign to SiO₂ and to the fin.
4. RTO specificity is taught by the very reference the spec echoes. US 7,439,607 contains near-verbatim language reused in the '865 specification ("Among the variables that may be controlled in the rapid thermal oxidation process are temperature and time… one factor that may control the thickness of the oxide … is a desired beta value"). That textual overlap is itself evidence that the RTO route (claim 3) was known and obvious.

→ Claim 1 is prima facie obvious. (Claim 2 = SOI, taught by US 2014/0103455. Claim 3 = RTO, US 7,439,607. Claim 4 = low-temp oxidation, Sekine 2001.)

4. Claim 5 — the Ge-fin / polysilicon-gate chemistry pair

Combination B = Kobayashi 2009 (Ge → GeO₂) + US 5,845,505 (Sony; thermal oxidation of Si / silicon-oxide gate films) + US 2014/0103455.

The claim merely names the two well-known oxidation products: germanium → GeO₂, polysilicon → SiO₂. Both conversions are individually known (Kobayashi; US 5,845,505), and pairing them so that one oxide is water-removable and the other is not is the natural, predictable consequence. WO 2003/054951 seals it by naming GeO₂ as the water-dissolvable disposable spacer.

5. Claim 8 — dummy gate + hardmask + maskless removal

Combination C = TSMC/IBM dummy-gate-with-hardmask art (US 2013/0307088; US 8,835,237) + US 2014/0103455 + Kobayashi 2009 + WO 2003/054951.

• Hardmask in direct contact on the dummy gate's top surface: conventional dummy-gate/RMG practice.
• SiO₂ gate spacers only on the opposite vertical sidewalls: the specification's own reasoning — the hardmask (nitride/oxide) does not oxidize — is inherent to selecting an oxidation-resistant hardmask, a routine design choice.
• GeO₂ on both the top and vertical sidewalls of the fin: Kobayashi's orientation-independent radical oxidation makes this the expected result.
• Removing without a mask: this is the entire point of a material-selective water removal (WO 2003/054951: "selectively from other films traditionally used in semiconductor processing"). Maskless selective removal is a result-effective, predictable outcome — no RIE, no photomask.

Dependents 9–13 (SOI; RTO; low-temp; merged epi S/D; nitride spacer) are each met by US 2014/0103455 (SOI), US 7,439,607 (RTO), Sekine (low-temp), US 7,125,805 (disposable spacer + elevated S/D), and US 6,144,071 (nitride spacer).

6. Claim 14 — SOI + simultaneous oxidation + RMG

Combination D = US 2014/0103455 (SOI finFET flow, fins in SOI layer, BOX) + US 2013/0307088 & US 8,835,237 (polysilicon dummy gate + hardmask + replace dummy with metal gate) + Kobayashi 2009 + WO 2003/054951.

• "fins in a top layer of an SOI substrate such that the underlying BOX is exposed between fins" — standard SOI fin formation (US 2014/0103455; GlobalFoundries US 2015/0017774).
• "polysilicon dummy gate … hardmask in direct contact" — ordinary RMG.
• "simultaneously forming SiO₂ gate spacers and GeO₂ fin spacer" — the natural consequence of one oxidation over two materials with different oxidation products.
• "removing GeO₂ without removing SiO₂ by exposing both to a wet water etch" — taught/predictable as above.
• "replacing the hardmask and polysilicon dummy gate with a metal gate" — the RMG step of US 8,835,237 / US 2013/0307088.

→ Claim 14 obvious. Claim 15 (remove hardmask + dummy gate selective to spacers; fill with metal) is a routine RMG sequence taught by US 8,835,237. Claims 16–17 = RTO/low-temp (US 7,439,607 / Sekine). Claims 18–19 = epi S/D + nitride spacer (US 7,125,805; US 6,144,071).

7. Motivation-to-combine synthesis (the KSR factors)

• Need / problem recognized in the art: RIE spacer etch damages scaled fins — admitted in the '865 Background and addressed by US 2014/0103455's oxide-spacer approach.
• Known techniques with predictable results: RTO (US 7,439,607), low-temp radical oxidation (Sekine), GeO₂ formation (Kobayashi 2009) — all pre-date 2014-09-22.
• Reasonable expectation of success: material-selective wet removal of GeO₂ over SiO₂ was known and quantified (WO 2003/054951; solubility data), and orientation-independent oxidation of Ge for 3D devices was explicitly reported (Kobayashi).
• No unexpected result / no criticality: the claims recite results that follow directly from the known differential chemistry; the "single step" is an economy, not a new technical effect.

8. Where the patent can push back (non-obviousness defenses)

To be balanced, the strongest counter-arguments are:

1. "Single-step oxidation of both gate and fin" is the twist. The art of record (US 2014/0103455) deposits oxide spacers; WO 2003/054951 deposits GeO₂ and dry-etches it. A patentee could argue no reference teaches growing both spacers by one oxidation over two different materials. The rebuttal is that this is precisely a predictable combination of Kobayashi's Ge oxidation and routine Si/polysilicon oxidation, motivated by the admitted RIE problem.
2. The negative limitation ("both exposed … but only the fin spacer is removed") could be argued as a result not taught in the finFET context — but it is the inherent consequence of the chosen materials and is expressly taught in a disposable-spacer context (WO 2003/054951).
3. Secondary considerations: none of record. There is no evidence in the patent or the litigation/assignment record I could reach of commercial success, licensing of this patent specifically, long-felt need, or failure of others attributable to the claims. (Note: the earlier sections established the patent lapsed for non-payment of maintenance fees effective 2021-09-26, and no litigation was found — facts that undercut any narrative of a valuable, widely-asserted invention.)

9. Bottom line

• Claims 1–4 and 8–17 are prima facie obvious over US 2014/0103455 A1 in view of US 7,439,607 B2 and Kobayashi et al. (2009), further in view of Sekine et al. (2001) for low-temperature oxidation, and — for the SiO₂/GeO₂ selectivity and maskless water removal — WO 2003/054951 A1 (additional art) and the known GeO₂/SiO₂ water-solubility differential.
• Claims 5 and 18–19 are obvious over the same combination plus US 5,845,505 (Si/SiO₂ oxidation), US 7,125,805 (disposable spacer + elevated S/D), and US 6,144,071 (nitride spacers).
• Claims 14–15 are obvious over the above plus US 8,835,237 / US 2013/0307088 (dummy-gate/replacement-metal-gate).
• Claims 6–7, 12–13 are obvious over the epi-S/D and nitride-spacer art of record.

10. Confidence & caveats

• High confidence in the claim text and in the content of US 2014/0103455 A1, US 7,439,607 B2, and Kobayashi 2009 — all verified via the URLs above.
• Moderate confidence on references I could only see by title (e.g., US 5,845,505, US 6,144,071, US 7,125,805, US 8,835,237). Their relevance is inferred from their titles and their citations in this patent's classification space; I have not verified their full disclosures. Any formal §103 challenge would require PIN-citing their specific passages.
• Flag: WO 2003/054951 A1 and the solubility data are not in the patent's Prior Art section — they are additional art I found by search. They are the most on-point teachings of a water-dissolvable GeO₂ disposable spacer and should be treated as a separate string, not as "art already considered by the examiner."
• The fact the patent issued over the art of record means an examiner did not view any single listed reference as anticipatory or as a complete §103 combination; the analysis above therefore rests on the combination, which is the correct §103 vehicle.
• No 2026 CAFC activity was identified (consistent with the earlier Litigation section); nothing in this analysis depends on any litigation finding.