US 9570389

I'll search for the specific patent number and check for any litigation or CAFC activity.

Let me try more targeted searches for USPTO records, litigation, and CAFC dockets.

US Patent 9,570,389 — Search Results and Summary

Search scope note: I ran searches against Google Patents, general web, and litigation-docket sources for the literal number 9570389 (and for "9,570,389"). I did not find any district-court complaint, PTAB proceeding, or CAFC 2026 docket naming this patent. I could not directly query USPTO PatentCenter or the CAFC docket in this session, so I cannot rule out an unreported or very recent filing — treat the "no litigation found" conclusion as absence of evidence, not proof of no disputes.

Important non-result (do not conflate): Several search hits reference U.S. Patent No. 9,967,389 (ProudLion IP, LLC v. Amazon.com; also suits against OPPO, LG, Microsoft, Samsung — "System And Method For Selectable Alteration Of Operation And Appearance Of A Portable Computing Device"). That is a different patent number (9,967,389 ≠ 9,570,389) and unrelated subject matter. It is not the patent you asked about and I have not treated it as related.

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Bibliographic Data (from the patent text itself)

Abstract

An interconnect structure includes a dielectric layer having one or more trenches, one or more interconnect lines, and one or more first liner layers. Each interconnect line sits within a trench, with at least one first liner layer between the trench bottom surface and the interconnect bottom surface. The structure also has one or more second liner layers, at least one of which is affixed directly to the interconnect top surface and at least one interconnect side surface. At least one air gap is positioned between the trench side surface and the interconnect side surface. A corresponding method of manufacture and product-by-method are also disclosed.

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Plain-Language Overview of the Independent Claims

Claim 1 — The structure (apparatus).
A semiconductor interconnect structure where:

• A dielectric layer has trenches (each with a bottom and sidewall).
• Metal interconnect lines sit inside those trenches, and their side surfaces have had material removed so they are free of sidewall voids.
• A first liner layer (e.g., TaN, TiN, WN, CoN, RuN, or self-formed MnSiₓO_y) sits between each trench bottom and the interconnect bottom.
• A second liner layer covers the interconnect's top and side surfaces directly (a different/second liner material than the first).
• An air gap occupies the space between the trench sidewall and the interconnect sidewall.

Inventive core: combine a re-deposited cap/liner (second liner) directly on the copper with a void-freed sidewall and an air gap in the sidewall recess — addressing resistance, electromigration, and time-dependent dielectric breakdown (TDDB).

Claim 9 — The method of manufacture.
The process steps:

1. Produce an initial structure: dielectric with trenches; interconnect lines in the trenches; a first liner layer between the trench bottom and interconnect bottom and between the trench sidewall and interconnect sidewall.
2. Remove the first liner from the interconnect top surface and side surface, along with a quantity of material from the interconnect side surface and from the dielectric at the trench sidewall — creating an air gap between the trench sidewall and the interconnect sidewall.
3. Deposit a second liner layer (a second liner material) onto the interconnect top surface and side surface.

Plain language: etch back the liner and a bit of the surrounding dielectric/metal to carve out a sidewall air gap, then re-line the exposed metal.

Claim 18 — Product of the method (product-by-process).
Covers the structure that results from essentially the Claim 9 process (produce initial structure → remove liner + material to form the air gap → deposit second liner). It is defined by how it is made rather than purely by structure.

(Claim 19 is oddly drafted: it is titled "product of a method of manufacturing" yet depends from claim 9 with "the method further comprising" adding the capping-layer step. Its dependency/form is internally inconsistent — worth flagging if validity or scope is at issue.)

Notable dependent claims:

• Cl. 2/10/19: add a capping layer on the dielectric top and interconnect top, enclosing the air gap, with a second liner between the interconnect top and capping layer.
• Cl. 4/12: capping dielectric has K < 4 ("low-K"); Cl. 5/13: K between 4 and 7.5 ("high-K").
• Cl. 6/14: second liner is a highly conductive metal cap material.
• Cl. 7/15: second liner is more adhesive to the interconnect metal than the first liner.
• Cl. 8/17: interconnect top is recessed enough to be free of triple points (the metal/dielectric/cap-layer junction the inventors identified as the TDDB weak point).
• Cl. 16: the removed quantity is effective to render the sidewall free of sidewall voids.

Technical Rationale (as stated in the specification)

The inventors observed in cross-section microscopy that (a) thick liners raise interconnect resistance while thin liners worsen electromigration/TDDB, (b) sidewall voids degrade electromigration performance, and (c) the triple point between interconnect, dielectric, and capping layer is the weakest TDDB location. The patent's approach: remove the initial liner sidewall plus a controlled amount of surrounding material to eliminate voids and triple points, form an air gap for reduced capacitance, then deposit a fresh, more-adhesive second liner on the exposed top and sidewalls.

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Uncertainty / Caveats

• Litigation: No evidence found tying US 9,570,389 to any CAFC 2026 docket or active litigation. I cannot verify PatentCenter's assignment/reassignment history beyond what the patent page reports (IBM, REEL/FRAME 036891/0551).
• Legal status: The patent lapsed for failure to pay maintenance fees (USPTO codes LAPS/STCH, effective 2021-02-14). "Expired – Fee Related" is a status assumption, not a legal conclusion.
• Term: The 2035-10-27 anticipated expiration is the patent's own stated figure and assumes all maintenance fees paid (they were not).
• The full authoritative patent text was used for all structural/claim details; where web results contradicted it, the patent text was preferred, and the 9,967,389 hits were excluded as a different patent number.

I'll search for litigation involving US patent 9570389 across patent litigation databases.

Let me try more targeted searches on litigation databases.

Let me run additional targeted searches specifically for this patent number and its family.

Litigation Search Report — U.S. Patent No. 9,570,389

Bottom line

No litigation involving U.S. Patent No. 9,570,389 was found. After searching patent‑litigation resources (Unified Patents litigation resources, Justia/CourtListener dockets, CAFC opinions, PTAB/PACER‑derived documents, and general web sources), I could not identify any district‑court action, ITC investigation, PTAB proceeding, or CAFC appeal in which U.S. 9,570,389 was asserted, challenged, or otherwise at issue.

About the patent (for identification purposes)

• Patent: U.S. 9,570,389 B1 — "Interconnect structure"
• Application: 14/923,811, filed October 27, 2015; granted February 14, 2017
• Assignee: International Business Machines Corporation (IBM)
• Inventors: Dinesh A. Badami, Baozhen Li, Wen Liu, Chih‑Chao Yang
• Subject matter: BEOL semiconductor interconnect — trench/dielectric structure, first and second liner layers, air gap between trench sidewall and interconnect sidewall
• Related family member: U.S. 9,514,981 B1 (application 14/970,687, filed December 16, 2015) — a continuation of the same disclosure
• Legal status: Expired – Fee Related. Per the Google Patents legal events, the maintenance fee reminder was mailed October 5, 2020; the patent lapsed for failure to pay maintenance fees on March 22, 2021 (effective date February 14, 2021), and was recorded as expired under 37 CFR 1.362.

Important caveat on search hits (do not conflate)

My searches surfaced several references to a "789" or "'389 patent," but none of them is U.S. 9,570,389. These are distinct patents with similar or overlapping digits, and I'm flagging them so they are not mistaken for litigation against this patent:

• U.S. 7,187,389 — asserted by IBM against Zillow (W.D. Wash., No. 2:20‑cv‑00851); held ineligible under §101. Different patent.
• U.S. 9,967,389 — asserted by ProudLion IP, LLC against Amazon and against OPPO/LG/Microsoft/Samsung (W.D. Tex.). Different patent.
• U.S. 8,673,939 — Celgene v. Synthon (D.N.J.). Different patent.
• A Samsung/eMagin dispute referencing an unrelated "'389 patent" (different number entirely).

Confidence and limitations

• High confidence: U.S. 9,570,389 issued to IBM in 2017 and lapsed in 2021 for non‑payment of maintenance fees — this is directly supported by the patent's own legal‑events record.
• Moderate confidence on the no‑litigation finding: I found no evidence of litigation, and the patent's short life (2017–2021) plus its expiry make litigation unlikely. However, I cannot guarantee exhaustiveness. A definitive negative would require a paid docket search (e.g., Lexis CourtLink, Docket Navigator, Westlaw KeyCite, or a PACER full‑text search) covering 2017–2026, which public web search may not fully surface — particularly for cases where the patent was listed only in an exhibit or infringement contention rather than the docket caption.
• I did not locate any PTAB IPR/PGR, ex parte reexamination, or ITC §337 investigation naming U.S. 9,570,389.

Conclusion: Based on available sources, there is no known litigation involving U.S. Patent No. 9,570,389.

Proceedings overview

Zero AIA trial proceedings are on file for U.S. Patent No. 9,570,389. The canonical PTAB list supplied in the structured data (USPTO Open Data Portal ingest, source of truth per the operating rules) returns no IPR, no PGR, and no CBM naming this patent — so the breakdown is 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials. The bottom-line defensive posture for a defendant is unusual and worth stating precisely: this is not a "hardened" patent and it is not a "wounded" one — it is an untested patent that died of its own accord. US 9,570,389 expired on 2021-02-14 (fee lapse recorded 2021-03-22) for failure to pay maintenance fees, so the practical defensive value of its clean PTAB record is close to nil: there is nothing left to invalidate and, absent a petition to revive or a challenge to the lapse, nothing left to assert.

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No proceedings to report

There is no ### {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to populate. I ran web searches against PTAB decision repositories, PTAB E2E-style document hits, law-firm PTAB activity listings, and general web indices for the literal strings 9570389, 9,570,389, and the application number 14/923,811. Every hit resolved either to this patent's own Google Patents/DOI record or to unrelated patents. I did not invent or infer a proceeding number to fill the template.

Near-miss hits — disambiguated so they are not misread as activity on this patent

Sibling family member US 9,514,981 B1 (continuation, app. 14/970,687) is likewise absent from the PTAB record — relevant because a petitioner challenging the family would normally attack both members. The family's only citations are its own sibling application (listed as a non-patent citation: "Badami et al., 'Interconnect Structure,' U.S. Appl. No. 14/970,687") and IBM's Appendix P related-applications listing.

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Strategic summary

Claim status on the PTAB record: everything is UNTESTED. Claims 1–19 of US 9,570,389 have never been construed by the Board, never been the subject of an institution decision, and never been canceled, confirmed, or amended through an AIA trial. There is no Final Written Decision, no certificate canceling claims, and no substitute-claim amendment. If a demand letter or complaint cites any of claims 1–8 (structure, including the independent apparatus claim 1), claims 9–17 (method, including independent claim 9), or claims 18–19 (product-by-process, including independent claim 18), the correct statement is that those claims are PTAB-untested, not that they are invalid — and, separately, that the patent is expired and unenforceable for failure to maintain, which is a far more dispositive defense than a § 103 theory would have been.

Estoppel landscape: § 315(e)(2) estoppel is inapplicable. Estoppel runs only from a Final Written Decision, and no FWD exists; no petitioner exists to be estopped. Conversely, there is no preclusive benefit to a defendant either — nobody has spent the money to build an invalidity record you could inherit. If a revival/petition-to-revive event ever put this patent back in force (I found no evidence of one; the record ends at the 2021 fee lapse), a fresh petitioner would face an entirely open field: the 14 examiner-cited references (including US 6,245,667; US 6,849,537; US 8,298,911; US 8,513,809; US 8,629,560; US 9,054,160; US 9,142,533; and publications such as US 2009/0081862 A1 and US 2011/0024909 A1) are all still available, subject only to the ordinary IPR prior-art limits of § 311(b) (patents and printed publications only), and PGR would be time-barred since the 9-month PGR window closed on 2017-05-14.

Pattern signals: None of the usual tell-tales are present. No repeat petitioner, no defensive aggregator (no Unified Patents, RPX, or similar filing), no patent-owner appeal activity, no PTAB trial at all. The prosecution history is a single IBM-filed application with one continuation, and the patent's asserted life ran roughly 2017-02-14 to 2021-02-14 — about four years, during which it attracted neither litigation (per the prior section's finding) nor a single post-grant petition. For a BEOL interconnect patent in the semi-conductor process space, that combination is unsurprising: operating companies rarely assert process-technology patents of this vintage against each other, and challengers had little reason to pay for an IPR on a patent with no assertion campaign against them.

Recommended next steps

• If you are a defendant and the patent is being asserted now: lead with the status, not the merits. The patent lapsed for non-payment of maintenance fees effective 2021-02-14 (USPTO events LAPS/STCH, "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362"; "FP – Lapsed due to failure to pay maintenance fee," effective 2021-02-14). Confirm current status directly in USPTO Patent Center for application 14/923,811 and in PTAB E2E, and confirm whether any petition under 37 CFR 1.378 to revive has been filed and granted — the provided record shows none through the last ingest.
• If you want the definitive negative: the absence of PTAB activity here is well supported by the ODP ingest plus multiple independent web searches, but a truly exhaustive negative on AIA trials is best confirmed via a PTAB E2E / Patent Trial and Appeal Board End-to-End search on the patent number and on the application number, plus a run against Docket Navigator or Lexis CourtLink for any 2017–2026 proceeding in which the patent appeared. I could not execute authenticated queries against PTAB E2E or PACER in this session.
• If active proceedings were pending (they are not): the milestones would be statutory — institution decision within 3 months of the preliminary response (or its due date), and a Final Written Decision within 12 months of institution under § 316(a)(11). None of that applies here; there is no institution date to count from.
• Do not cite a PTAB outcome in a demand-letter response. Citing "the IPR that invalidated claim 1" of this patent would be a fabrication; no such IPR exists. The accurate, quotable points are (i) zero AIA trials on file, and (ii) expiration for fee non-payment.

Sources consulted: the structured PTAB-proceedings block (USPTO ODP, no AIA trials), Google Patents record for US9570389B1 (legal events and citation lists), US9514981B1 (family record), the CAFC opinion in IBM v. Zillow, No. 21-2350 (unrelated '389 patent), and the Nat'l Law Review PTO Litigation Center report of 2016-10-31 (unrelated IPR2017-00138 on patent 8,576,389).

I'll verify the assignment record before reconstructing the chain.

Inventors

Pattern notes (nothing anomalous found):

• All four inventors executed the assignment to IBM on 2015-10-26, one day before the 2015-10-27 filing date. This is the standard IBM bake-the-title-in-before-filing pattern, not a "departing inventors" pattern.
• I found no evidence of any of the four inventors departing IBM within 12 months of filing, and no evidence of a follow-on inventor assignment to any third party. I could not independently verify current employment for any inventor from a primary source, so treat the "no departures" statement as absence of evidence.
• The four inventors named here are the same four named on the sibling continuation US 9,514,981 B1 (application 14/970,687, filed 2015-12-16, same family ID 57399968). Same-inventor continuation pairs are routine, not a signal.

Original assignee

International Business Machines Corporation (IBM), Armonk, New York — named as both original and current assignee on the issued patent.

• Primary line of business: IBM is a global technology company (hybrid cloud, software, consulting, mainframe; historically a semiconductor manufacturer). At the 2015 filing date IBM was still operating its own fabs; in 2015 it announced/closed the transfer of its Microelectronics (semiconductor foundry) business to GlobalFoundries. IBM Research continued BEOL/interconnect work.
• Did they ship a product embodying the claims? Qualified yes on the technology, unverifiable as to this specific claim set. The patent is a BEOL interconnect process/structure disclosed as a manufacturing technique rather than a product SKU. IBM filed and prosecuted it as an internal-research patent (IBM Yorktown Heights / Albany NanoTech-style BEOL work is reflected in the cited art). No commercial part number, datasheet, or product literature tying the now-expired claims to a shipping product was located.
• Current status: Operating. IBM is not in bankruptcy, has not been acquired or dissolved. Note the 2015 GlobalFoundries divestiture did NOT move this patent: no assignment from IBM to GlobalFoundries (or to any IBM semiconductor spin-out) is recorded against US 9,570,389, and its sibling US 9,514,981 likewise remains IBM-owned. The patent simply lapsed.

Assignment timeline

Recorded assignments against US 9,570,389 / application 14/923,811 — one entry in the USPTO record:

• 2015-10-26 (executed) / recorded 2015-10-27 — Reel 036891/0551
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (see document for details)
  • Assignor: BADAMI, DINESH A.; LI, BAOZHEN; LIU, WEN; AND OTHERS (Yang, Chih-Chao)
  • Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION, New York (Armonk, NY 10504)
  • Correspondent: Not retrievable from the sources available to me. The Google Patents legal-events entry for this reel/frame reproduces only the "Owner name / Free format text / Effective date" fields and omits the correspondent block; my targeted searches for the reel/frame cover sheet did not surface the legible PTO-1595. I therefore cannot name the recording attorney/firm, and I will not infer one. For context only (not a finding for this patent), IBM assignments of this era are typically recorded through IBM's own IP Law department or a designated outside firm — but I have no record-level support for that here.
  • Context: Internal/in-house acquisition — inventor-to-employer title transfer executed pre-filing. This is the standard IBM pre-filing assignment, not a sale, securitization, or transfer to an asserter.

No other assignment records were found. There are no post-issuance recorded assignments of US 9,570,389 — no merger, no change of name, no security agreement, no license recordation, no release, no correction, and no transfer to any third party. That absence is itself the principal finding: IBM retained title from execution through the patent's lapse.

Related-family cross-check (do not conflate): the continuation US 9,514,981 B1 (application 14/970,687) carries a separate IBM assignment recorded at Reel 037302/0474, executed 2015-10-26 (the same pre-filing execution date). That is a distinct reel/frame on a distinct application in the same family — it is not a second assignment of US 9,570,389, and the two should not be merged into one chain.

Chain termination: No assignment exists after 2015-10-27 because the patent expired for failure to pay maintenance fees (fee reminder mailed 2020-10-05; lapse events recorded 2021-03-22, effective 2021-02-14, under 37 CFR 1.362). An expired patent has no residual licensing value, which is consistent with — though not proof of — the absence of any later transfer attempt.

Timeline diagram

timeline
    title Ownership of US 9570389
    2015 : Inventors execute assignment to IBM
         : Filed as application 14 923 811
         : Recorded at Reel 036891 Frame 0551
         : Continuation filed as 14 970 687
    2017 : Patent US 9570389 B1 issues
    2020 : Maintenance fee reminder mailed
    2021 : Patent lapses for non-payment
         : No recorded third-party transfer

NPE / troll-pattern signals

Verdict

Insufficient data — in the specific sense defined for this exercise: the record consists of only the original assignment (Reel 036891/0551, executed 2015-10-26, recorded 2015-10-27, inventors → IBM). There is no post-issuance chain to analyze.

Justification: the entirety of the ownership record is a single pre-filing inventor-to-employer assignment to International Business Machines Corporation, and no further assignment — to an NPE, an aggregator, or anyone else — appears in the record through the patent's 2021-02-14 lapse for non-payment of maintenance fees. Because there is exactly one link and its correspondent of record could not be recovered, scoring an NPE verdict (in either direction) would require inference the record does not support. Substantively, the evidence is affirmatively inconsistent with the NPE pattern: no shell-entity assignee (Signal 1 not present), no listed asserter (Signal 2 not present), no cascade (Signal 4 not present), no pre-suit transfer (Signal 5 not present), no bankruptcy sale (Signal 6), no privateering (Signal 7), and no defensive aggregator (Signal 8) — i.e., IBM retained the patent until it expired for free, which is the opposite of a monetization chain.

Caveats / limits on this report

• I could not query USPTO Assignment Center's application-programming interface directly in this session; the reel/frame above is taken from the patent's own legal-events record (authoritative for the filing), and I could not retrieve the underlying PTO-1595 cover sheet. The recording correspondent and the recorded assignee address for Reel 036891/0551 remain unverified.
• If a post-2021 assignment or a nunc pro tunc recordation exists but is not indexed into the Google Patents legal-events feed, I would not have seen it. A definitive negative requires a direct Assignment Center query.
• The sibling reel 037302/0474 belongs to US 9,514,981, not to US 9,570,389 — flagged to prevent the two being conflated into a false "two-assignment" chain.

Verification links

• USPTO Assignment Center (search by patent number 9570389): https://assignmentcenter.uspto.gov/
• Legacy Assignment Search (indexed UI): https://assignment.uspto.gov/patent/index.html
• Google Patents legal events for US 9,570,389: https://patents.google.com/patent/[US9570389B1](/patent/US9570389B1)/en

I'll verify the patent record and each prior-art citation. Let me run targeted searches against USPTO/patent records.

Prior-Art Analysis — U.S. Patent No. 9,570,389 B1

Analyst note: This section builds on the earlier bibliographic/claim and litigation sections and does not repeat them. My job here is (a) confirm the literal record for 9,570,389 and (b) map each of the patent's own cited references against the claims.

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1. USPTO record check — literal number 9,570,389

I searched for the literal string 9570389. The authoritative record remains the patent text already supplied and the parallel public records (Google Patents US9570389B1, Justia patent/9570389), which agree:

Disambiguation (carried forward): I did not return or conflate 9,967,389 (ProudLion), 7,187,389 (IBM v. Zillow), 8,673,939, or any other similar number. All analysis below is exclusively for 9,570,389.

Search limitation: I could not open USPTO PatentCenter's fee/assignment tabs directly in this session; the record above is from the fetched patent document and mirrored public databases. Treat the status as a stated assumption, as in the earlier sections.

Legal framework used: Because 14/923,811 was filed 2015-10-27 (post-AIA), AIA 35 U.S.C. § 102(a)(1) governs. Every one of the 14 cited references was published before 2015-10-27, so each qualifies at least as a printed publication under § 102(a)(1). The question for § 102 is whether any single reference discloses all elements of a given claim.

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2. The claims to be anticipated (element shorthand)

Claim 1 (structure):

• E1 dielectric with top surface + trench having bottom surface and side surface
• E2 interconnect line in the trench (bottom/top/side surfaces), where the side surface has had material removed so as to be free of sidewall voids
• E3 first liner (first liner material) between trench bottom and interconnect bottom
• E4 second liner (second liner material) affixed directly to the interconnect top surface AND to the interconnect side surface
• E5 air gap between the trench side surface and the interconnect side surface

Claim 9 (method): M1 initial structure (dielectric+trench+interconnect+first liner between trench bottom/interconnect bottom and between trench sidewall/interconnect sidewall); M2 remove first liner from top + side surface together with a quantity of interconnect material and dielectric material to yield the air gap; M3 deposit second liner on top + side surface.

Claim 18: product-by-process of the same three steps.
Claim 19: as drafted, depends from claim 9 and adds a capping layer (form internally inconsistent — flagged in the earlier section).

Threshold conclusion: Because claim 1 requires the combination of E1–E5 (and claim 9 requires M1–M3), a reference anticipates only if it teaches all of them. On the record I reviewed, none of the 14 cited references appears to disclose the full combination, so strictly speaking none anticipates claims 1, 9, 18, or 19, and therefore none anticipates their dependents either. They are better characterized as § 103 obviousness references and as evidence of the state of the art. The per-reference mapping below identifies which element(s) each reference does supply, i.e., where it would be relied upon in an obviousness rejection.

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3. Reference-by-reference mapping

3.1 US 6,245,667 B1 — "Method of forming via"

• Dates: TW priority 1999-10-18; granted 2001-06-12.
• Assignee as listed in the 9,570,389 IDS: "Semiconductor Manufacturing Corp." Discrepancy note: a search hit for this number shows a Taiwan priority application (TW 88117958, 1999-10-18) and an assignment record to Winbond Electronics Corp. I have not auto-corrected the IDS listing; the two sources disagree and I flag it rather than resolve it.
• Description (from full text): borderless-via process; barrier layers (e.g., TiN) on a patterned metal (Al-Cu) stack with sidewall spacers formed by depositing and etching back a second barrier layer, then dielectric over the stack, and a via landed on the barrier/spacer.
• Element mapping: supplies a liner/barrier on a conductive-line sidewall (partial E4 concept) but on a patterned metal stack, not a damascene trench-and-sidewall geometry. Absent: E5 (air gap), E2 (void-freed sidewall recitation), E3 (liner specifically between trench bottom and interconnect bottom), and the "second liner directly on top and side of the interconnect" re-deposition.
• Potential § 102 anticipation: None of claims 1–19. Best use: § 103 background on barrier/liner-on-sidewall.

3.2 US 6,849,537 B2 — "Method of suppressing void formation in a metal line"

• Dates: priority 2000-08-31; granted 2005-02-01. Assignee: Micron Technology (inventor Honeycutt).
• Description: forms an interconnect line; deposits a third refractory-metal layer over the line such that it lies on the top surface and on the opposing side surfaces, then etches back leaving that layer only on the side surfaces/top — i.e., discrete sidewall spacers plus a top metal layer on the conductor. Purpose is suppressing void formation in Al lines.
• Element mapping: This is the most on-point cited reference for E4 ("a liner affixed to the interconnect top surface and the interconnect side surface") and it is also thematically about void formation (cf. E2). Absent: the dielectric trench with a trench sidewall (the line here projects above an insulator surface); E5 (air gap); E3 as recited.
• Potential § 102 anticipation: None of claims 1–19 as a whole. It would be the principal reference in a § 103 attack on the E4/E2 limitations, combined with an air-gap reference (e.g., 3.3 or 3.9).

3.3 US 2009/0081862 A1 — "Air gap structure design for advanced integrated circuit technology" (examiner-cited)

• Dates: filed/priority 2007-09-24; published 2009-03-26. Assignee: TSMC.
• Description: forms openings in a material layer; deposits a blanket film (vertical sections on opening sidewalls); converts it to an etchable material; fills the openings with interconnect material; removes the vertical sections to create voids; then deposits a capping layer over the surface and over the voids but not filling them, thereby creating air gaps. Expressly states air gaps are formed after creation of conductive lines and "alternatively, a barrier layer."
• Element mapping: supplies E1 (dielectric layer with openings), E5 (air gap between the opening sidewall and the interconnect), and the claim-2 concept (air gap enclosed by a capping layer), plus a liner/barrier adjacent the interconnect. Absent / questionable: the second liner affixed directly to the interconnect top surface and side surface (in '862 the sacrificial vertical section that becomes the void sits on the dielectric sidewall, and the barrier is between metal and that section); and the affirmative "side surface free of sidewall voids" recitation.
• Potential § 102 anticipation: Not of claims 1, 9, 18 or 19 (missing E4/M3's "directly on top and side" second liner). Closest cited art to a claim 2-type capping-layer-encloses-air-gap subcombination; strongest § 103 partner for the air-gap element.

3.4 US 2011/0024909 A1 — "Bilayer metal capping layer for interconnect applications" (examiner-cited)

• Dates: filed 2008-02-28 (ser. 12/039,280); published 2011-02-03; granted as US 8,034,710 B2 on 2011-10-11. Assignee: IBM. Inventors: Chih-Chao Yang; Satya V. Nitta.
• Description: a first metallic capping layer (e.g., CoWP) selectively on the Cu conductive feature, a dielectric capping layer over the dielectric and first cap, and a second metallic capping layer (e.g., Ru) on the first cap in the via opening; discusses adhesion of metallic caps to Cu and EM resistance.
• Element mapping: supplies the "highly conductive metal cap material" concept behind claims 6 and 14, the adhesion rationale behind claims 7 and 15 (metallic cap adheres better to Cu than a dielectric cap), and a capping layer (claims 2/3/10/11/19). Absent: air gap (E5), side-surface liner (E4), void-freed sidewall (E2), trench geometry as claimed.
• Note on inventorship: Chih-Chao Yang is a named inventor on both this reference and 9,570,389. Because '909 published 2011-02-03 — well over a year before the 2015-10-27 filing — it is § 102(a)(1) prior art regardless of the shared inventor, so the common-inventor exception does not remove it.
• Potential § 102 anticipation: None of claims 1–19 standalone. Principal § 103 reference for claims 6/7/14/15 and for the capping-layer dependents.

3.5 US 2011/0210448 A1 — "Interconnect Structures Incorporating Air-Gap Spacers"

• Dates: priority 2007-09-14; published 2011-09-01. Assignee: IBM.
• Description: interconnect structures in which air-gap spacers are incorporated alongside interconnect lines to lower capacitance.
• Element mapping: supplies E5 (air gap located between the interconnect side surface and the surrounding dielectric). Absent: E4 (second liner directly on interconnect top and side), E2 (void-freed sidewall), and the sequence of removing the first liner from the top/side together with a quantity of interconnect and dielectric material (M2).
• Potential § 102 anticipation: None of claims 1–19 standalone. § 103 partner on the air-gap element.

3.6 US 8,298,911 B2 — "Methods of forming wiring structures"

• Dates: priority 2009-03-26; granted 2012-10-30. Assignee: Samsung Electronics.
• Description: damascene wiring-structure formation methods, including liner/barrier and dielectric processing in trenches.
• Element mapping: general E1/E3 (trench + liner) background. Absent: air gap (E5), second-liner-on-top-and-side (E4), void-freed sidewall (E2).
• Potential § 102 anticipation: None. General state-of-the-art (§ 103 background only).

3.7 US 8,513,809 B2 — "Semiconductor device"

• Dates: priority 2010-05-12; granted 2013-08-20. Assignee: Elpida Memory.
• Description: semiconductor device with interconnect/liner structure.
• Element mapping: background on liner/barrier layers in interconnects. Absent: air gap, second-liner re-deposition, void-freed sidewall.
• Potential § 102 anticipation: None.

3.8 US 2013/0277842 A1 — "Copper interconnect with CVD liner and metallic cap"

• Dates: priority 2012-04-20; published 2013-10-24. Assignee: IBM. (Family sibling appears among the "similar documents" as US 9,059,176 B2.)
• Description: a CVD-deposited liner on a copper interconnect together with a metallic cap on the copper.
• Element mapping: directly on point for claim 6 / claim 14 (second liner material is a "highly conductive metal cap material") and for the claim 7 / claim 15 adhesion rationale (cap/liner more adhesive to Cu than the diffusion barrier). Absent: air gap (E5), and the second liner being on both top and side surfaces after an air gap is created.
• Potential § 102 anticipation: None of claims 1–19 standalone; strongest cited art for the "highly conductive metal cap" dependent claims, useful in § 103.

3.9 US 8,629,560 B2 — "Self aligned air-gap in interconnect structures"

• Dates: priority 2007-01-26; granted 2014-01-14. Assignee: TSMC.
• Description: self-aligned air gaps formed in interconnect structures.
• Element mapping: E5 (air gap between sidewall regions and conductors) and the general concept of sealing an air gap. Absent: E4 (second liner directly on interconnect top and side), E2 (void-freed sidewall recitation).
• Potential § 102 anticipation: None of claims 1–19 standalone; § 103 air-gap art.

3.10 US 2014/0151888 A1 — "Air-Gap Formation in Interconnect Structures"

• Dates: priority 2012-11-30; published 2014-06-05. Assignee: TSMC.
• Description: formation of air gaps in interconnect structures (air-gap BEOL integration).
• Element mapping: E5 (air gap adjacent interconnects). Absent: E4, E2, and the claimed removal sequence.
• Potential § 102 anticipation: None standalone; § 103 air-gap art.

3.11 US 8,779,590 B2 — "Semiconductor device and method of producing the same"

• Dates: priority 2011-06-16; granted 2014-07-15. Assignee: Kabushiki Kaisha Toshiba.
• Description: semiconductor device production with interconnect/liner layers.
• Element mapping: general liner/interconnect background. Absent: air gap, second-liner re-deposition, void-freed sidewall.
• Potential § 102 anticipation: None.

3.12 US 9,054,160 B2 — "Interconnect structure and method for fabricating on-chip interconnect structures by image reversal"

• Dates: priority 2011-04-15; granted 2015-06-09. Assignee: IBM.
• Description: image-reversal process flow for fabricating on-chip interconnect structures (a patterning technique often used to open up/shrink features for gap formation).
• Element mapping: relevant to the method-of-manufacture framework of claim 9 (patterning/etching sequence). Absent: the specific M2 removal of the first liner from the top/side together with interconnect and dielectric material to form the air gap; E5; E4.
• Potential § 102 anticipation: None standalone; § 103 process-flow art.

3.13 US 2015/0162278 A1 — "Trench interconnect having reduced fringe capacitance"

• Dates: priority 2013-12-05; published 2015-06-11 (i.e., before 9,570,389's 2015-10-27 filing, so § 102(a)(1) art). Assignee: IBM.
• Description: a trench interconnect engineered to reduce fringe capacitance (typically via a recessed/air-gap or low-k sidebar geometry). Note the reference digits "2278" are unrelated to the "789" confusion addressed in the earlier section.
• Element mapping: relevant to E5 (fringe-capacitance reduction associates with air-gap/recessed sidewall geometries) and to the recessed interconnect top concept behind claim 8/17. Full-text confirmation needed before asserting any element is met.
• Potential § 102 anticipation: None confirmed; flagged as a § 103 air-gap/capacitance reference pending full-text review.

3.14 US 9,142,533 B2 — "Substrate interconnections having different sizes"

• Dates: priority 2010-05-20; granted 2015-09-22. Assignee: TSMC.
• Description: substrate-level interconnections of differing sizes (packaging/substrate interconnect scale).
• Element mapping: not on point for BEOL damascene trench/liner/air-gap elements.
• Potential § 102 anticipation: None. Least relevant of the 14.

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4. Consolidated anticipation table

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5. Non-patent citations (also part of the 9,570,389 record)

1. Badami et al., "Interconnect Structure," U.S. Appl. No. 14/970,687, filed Dec. 16, 2015.
   • This is the continuation of 14/923,811, granted as US 9,514,981 B1 (same family ID 57399968, same inventors). It is not § 102 prior art to 9,570,389: same inventors, same disclosure, common priority date (2015-10-27). It functions only as a related-family/§ 102(b)(2)(C)-type common-ownership consideration, not as anticipating art.
2. IBM, "List of IBM Patents or Patent Applications Treated as Related," Appendix P, dated Dec. 18, 2015, 2 pages.
   • An IDS cover document; evidentiary only, not prior art.

The five forward citations on the Google Patents page (KR 102645957 B1; US 10,204,829 B1; KR 20230001949 U; US 11,282,781 B2; US 11,239,165 B2) all post-date the 2015-10-27 filing and therefore cannot be prior art to 9,570,389.

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6. Which references are "most relevant," and in what posture

1. US 2009/0081862 A1 (TSMC) — closest cited art on the air-gap-plus-capping-layer core (E5 and claim 2's enclosed-air-gap feature) and the only cited reference that affirmatively creates voids then seals them.
2. US 2011/0024909 A1 / US 8,034,710 B2 (IBM; Yang/Nitta) — closest on the metallic-cap/adhesion limitations (claims 6, 7, 14, 15) and the capping-layer dependents; examiner-cited.
3. US 6,849,537 B2 (Micron) — closest on the "liner on the interconnect's side surfaces" concept (E4), and thematically on void-formation suppression (E2).
4. US 2013/0277842 A1 (IBM) — closest on CVD liner + metallic cap (claims 6/14).
5. US 2011/0210448 A1, US 8,629,560 B2, US 2014/0151888 A1 (air-gap families) and US 2015/0162278 A1 — the air-gap (E5) cluster.

Bottom line for § 102: None of the 14 cited references anticipates any of claims 1–19, because each omits at least one limitation of independent claim 1 (most commonly E4 — a second liner affixed directly to the interconnect top and side surface after an air gap is formed — and the affirmative E2/M2 "side surface free of sidewall voids" recitation). Their realistic role is as § 103 references, typically in a two- or three-reference combination: an air-gap reference (e.g., '862, '448, '560, '888) + a metal-cap/liner reference (e.g., '909/8,034,710 or 2013/0277842) + optionally a liner-on-sidewall reference (6,849,537).

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7. Caveats and limitations

• Depth of review: I reviewed full text for US 6,245,667, US 6,849,537, US 2009/0081862, US 2011/0024909/US 8,034,710, and US 2013/0277842, and abstracts/bibliographic data for the remainder. My element mapping for US 2011/0210448 A1, US 8,298,911, US 8,513,809, US 8,629,560, US 2014/0151888, US 8,779,590, US 9,054,160, US 2015/0162278, and US 9,142,533 is based on titles/abstracts and should be confirmed against full text before any validity opinion.
• Anticipation calls are provisional. "No anticipation" means no reference in the record was shown to disclose all elements in a single teaching; a hidden embodiment in an unreviewed reference could change that.
• Number fidelity: I did not auto-correct any identifier. Where sources disagreed (e.g., the assignee of US 6,245,667), I flagged the discrepancy rather than resolving it, per the operating rules.
• § 102 vs § 103: Anticipation under § 102 requires every element in one reference; obviousness under § 103 permits combination. Most of these references are materially more useful under § 103, and I have labeled them accordingly rather than overstating § 102 exposure.
• No litigation/validity input: This is a prior-art mapping only; it does not incorporate the (absent) litigation record discussed previously.

I'll verify the disclosures of the key prior-art references cited on the patent page before building the §103 analysis.

Let me verify the remaining air-gap and liner references cited on the patent page.

Obviousness Analysis — U.S. Patent No. 9,570,389 B1 under 35 U.S.C. § 103

Builds on the "Patent summary" and "Litigation summary" already generated. No contradiction found with those sections; the claim numbering, family relationship (continuation → US 9,514,981 B1), and lapsed-fee status are carried forward unchanged.

Source of prior art: Per instruction and per the patent page, I use the "Citations (14)" / "Patent Citations (14)" list appearing in the Prior Art section of the US9570389 Google Patents page. All 14 references pre-date the 2015-10-27 effective filing/priority date, so each qualifies as prior art under §102(a)(1)/(a)(2) and is available for §103 combination. I verified the substantive disclosure of the five most important references by retrieval; the remaining nine I could not open before hitting a tool limit — that is flagged in the caveats.

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A. Governing framework and level of ordinary skill

Under Graham v. John Deere and KSR Int'l v. Teleflex, the inquiry is (1) scope/content of the prior art, (2) differences between the prior art and the claims, (3) the level of ordinary skill, and (4) secondary considerations.

Level of ordinary skill in the art (PHOSITA): I would define this as an engineer with a master's degree (or equivalent experience) in electrical engineering, materials science, or applied physics and 2–5 years of experience in BEOL (back-end-of-line) interconnect integration for advanced CMOS nodes, including damascene processing, liner/barrier deposition (PVD/CVD/ALD), planarization, and reliability physics (electromigration (EM), time-dependent dielectric breakdown (TDDB), RC delay). This level matters because the patent's entire premise — that a thick liner hurts resistance while a thin liner hurts EM/TDDB, and that the "triple point" is the TDDB weak spot — was well-known integration lore reflected across the cited art.

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B. Claim 1 element chart vs. the cited prior art

Claim 1 is a structure claim. Mapping each limitation to the cited references:

Result of the chart: No single reference discloses every limitation. But every limitation is disclosed by some cited reference, and the missing pieces (second liner on sidewall; sidewall air gap; metal cap on top) are complementary art in the same field (BEOL interconnects) addressing the same problems (EM, capacitance, voiding). That is the classic §103 fact pattern.

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C. Primary obviousness combination (structure, claim 1)

Combination 1: US20110210448A1 (IBM air-gap spacers) + US20110024909A1 (IBM bilayer metal capping) + US6849537B2 (Micron void suppression).

What each teaches:

• US20110210448A1 supplies the dielectric/trench/interconnect/liner structure with a sidewall air gap between the trench wall and the metal column, plus a cap that "may partially fill the air-gap" (element 1(h), and much of 1(a)–(e)).
• US20110024909A1 supplies the "second liner" as a selective metallic cap deposited directly on the copper after planarization, and — critically — supplies the reason: the "metallic capping layer typically has better (i.e., increased) adhesion strength to the underlying conductive feature … results in improved EM resistance," with ">10 times EM resistance" for selective Co on Cu (elements 1(f), 1(g)-top, and claim 7 rationale).
• US6849537B2 (Micron) supplies the second refractory-metal layer formed on the interconnect top and side surfaces (element 1(g)-side) and frames side surface protection as the way to suppress void formation in the line (element 1(b)).

Motivation to combine (KSR factors):

1. Same field, same problem, finite set of known solutions. All three are interconnect-reliability/capacitance references. A PHOSITA seeking simultaneously to (i) lower effective k between lines and (ii) raise EM/TDDB margin would predictably look to air-gap spacers and metallic caps — both were "known techniques" in 2015.
2. Predictable results / mechanical combination. Air gaps reduce inter-line capacitance (stated in both air-gap references); a metal cap on Cu improves adhesion and EM. Combining them changes only the sidewall treatment, with a reasonable expectation of additive benefit (lower capacitance and better EM).
3. "Simple substitution of one known element for another." Replacing the dielectric sidewall spacer / dielectric cap with a more-adhesive metal liner on the exposed Cu is exactly the substitution US20110024909A1 already frames as beneficial.
4. Explicit design incentive from the patent itself. The '389 specification concedes the goals are known ("install an optimal liner thickness; eliminate sidewall voids after deposition; … remove triple points"). Motive flows from the admitted problem, not from hindsight.

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D. Alternate combination (equally viable)

Combination 2: US20090081862A1 (TSMC air-gap) + US20130277842A1 (IBM CVD liner + metallic cap) + US20110210448A1.

• US20090081862A1 teaches forming air gaps by removing converted sidewall material and capping over the voids — structurally the claimed "air gap between trench side and interconnect side, enclosed by a capping layer" (claim 2/10/19 support).
• US20130277842A1 teaches the liner + metallic cap stack ("diffusion barrier 110 … metal liner 112 … metallic cap 122 … capping layer") and explains the metal liner's "increased affinity for copper."
• Together these render claim 1 obvious; adding US20110024909A1 or US20130277842A1 to US20090081862A1 also renders claim 2 obvious (cap enclosing the air gap), because both already show a cap that pinches off/seals voids.

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E. Method claim 9 (and product-by-process claims 18–19)

Claim 9 steps map almost one-to-one onto the air-gap-spacer arts:

Motivation: The claimed method is essentially the air-gap-spacer process (US20110210448A1) with the post-planarization metal-cap step (US20110024909A1) appended. The '389 specification itself states the removal "may be achieved by various means including … selective plasma dry etch or wet chemistry," which is precisely the technique recited and performed in US20110210448A1 ("selective chemical etch means," DHF/NH₄OH) and US20090081862A1 ("selective etch process may be a wet HF dip"). A PHOSITA would have had a reasonable expectation that removing the sidewall material and re-lining the exposed Cu would (i) lower capacitance and (ii) re-passivate the freshly exposed Cu — the two results the patent claims.

Claims 18–19: Claim 18 is a product-by-process covering the same three steps; it rises and falls with claim 9 (process limitations control patentability of product-by-process claims). Claim 19 is defectively drafted (already flagged in the Patent summary — it is captioned "product of a method" but depends from claim 9 and adds a process step via "the method further comprising"). For §103 purposes it adds only the capping layer, which is disclosed by US20110210448A1/US20090081862A1 (cap pinch-off over the gap).

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F. Dependent claims

Claims 3–7 and 10–15 are strong obviousness candidates: they recite only material/selection choices (metal-cap material, dielectric-cap material, relative adhesion, K value) that the cited references expressly discuss, and K-value ranges are a classic case of "obvious to try" / optimization of a result-effective variable.

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G. The one genuinely contestable limitation — "free of triple points" (claims 8 & 17)

Claims 8/17 (and the "free of sidewall voids" language woven into independent claim 1) are the narrowest, most defensible aspects.

• The "triple point" (metal / dielectric-top / cap junction) as the TDDB weak spot is the patent's own empirical discovery (FIGS. 6–7), and the specific combination of recessing the metal top so the triple point is eliminated is not plainly disclosed by any single cited reference I verified.
• However, an obviousness case still exists: the sidewall air gap of US20110210448A1 / US20090081862A1 is formed at the top corner of the line and is then sealed by the cap; that geometry inherently displaces the metal/dielectric/cap junction with a low-k gas, and both references teach deliberate top-corner/via-gouging treatment. Combined with US20110024909A1's teaching that a metal cap is deposited on a recessed/selectively-grown Cu surface, a PHOSITA could reasonably arrive at a recessed top free of triple points without undue experimentation. So claims 8/17 are arguably obvious, but this is the limitation most likely to survive a §103 challenge.

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H. Potential non-obviousness / teaching-away arguments, and rebuttals

1. US20110210448A1 arguably teaches away from the claimed removal step. In its background it criticizes Lee et al. because they "use plasma based methods to remove the dielectric spacer to form the air-gap and they do this with the metal interconnect already present in the structure which could lead to a degradation of the conductive properties of the interconnect." The '389 claim 9 removes liner + interconnect material with the interconnect present. A patentee could argue this is a teaching away. Rebuttal: the criticism is aimed at a specific plasma technique, not at the general concept; US20110210448A1's own process performs a wet extraction (DHF/NH₄OH) with the metal already present, and US20090081862A1's wet HF dip does the same. A single reference's preference for a different chemistry is generally insufficient to show teaching away unless it "criticizes, discredits, or otherwise discourages" the claimed approach as a whole.
2. Micron (US6849537B2) is aluminum, subtractive, not damascene. A patentee may argue non-analogous art. Rebuttal: it is still "metal interconnect lines in a dielectric on a semiconductor substrate," and it addresses the identical problem (void formation/EM) using a sidewall liner; it is reasonably pertinent and thus analogous under In re Bigio / KSR.
3. Hindsight risk. The strongest patentee argument is that no cited reference simultaneously (a) removes interconnect material to eliminate voids, (b) forms a sidewall air gap, and (c) re-lines the exposed top and side with a more-adhesive metal. That simultaneity is the invention's real contribution; the §103 answer turns on whether the motivation to combine is articulated on the face of the references (largely yes for the capacitance and EM rationales; weaker for the void-removal + triple-point rationales).

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I. Secondary considerations (objective indicia)

• No objective indicia are of record. The patent lapsed for non-payment of maintenance fees (effective 2021-02-14; USPTO codes LAPS/STCH), and there is no commercial-success, licensing, copying, or industry-praise evidence in the file or in the sources reviewed. Absent a nexus showing, secondary considerations do not rebut the prima facie §103 case.
• Practical note: because the patent is expired and (per the Litigation summary) apparently never asserted, a formal validity opinion is largely academic — but if one were prepared, the vulnerability ranking would be: claims 3–7 / 11–15 (most vulnerable) > claims 1, 2, 9, 10, 18, 19 > claims 8, 17 (most defensible).

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J. Conclusion

Claim 1 would be obvious over US20110210448A1 + US20110024909A1 + US6849537B2 (or the alternate US20090081862A1 + US20130277842A1 + US20110210448A1 combination), with motivation supplied by the known goals of reducing inter-line capacitance (air gap) and improving Cu adhesion/EM resistance (metallic second liner), plus the known desirability of suppressing sidewall voids.

Claims 9 and 18 would be obvious as the air-gap-spacer method of US20110210448A1/US20090081862A1 with the post-CMP selective metal-cap step of US20110024909A1/US20130277842A1. Claim 19 is obvious for the same reason and is additionally defective in form.

Claims 3–7 and 11–15 would be obvious as design choices expressly discussed in the cited references (metal-cap materials; dielectric-cap materials; relative adhesion; K < 4 and K = 4–7.5 ranges).

Claims 8 and 17 ("free of triple points") present the strongest, though not conclusive, non-obviousness argument, because the specific elimination of the triple point by recessing the metal is the patent's own empirical insight and is not squarely disclosed by the cited art — although it is arguably reached by combining the recessed-cap and air-gap teachings.

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K. Caveats (per operating rules)

• Verified full text: US20110024909A1, US20130277842A1, US20110210448A1, US6849537B2/US20030157788A1, US20090081862A1. Not independently verified (search limit reached): US6245667B1, US20110210448's sibling disclosures, US8298911B2, US8513809B2, US8629560B2, US8779590B2, US9054160B2, US20140151888A1, US20150162278A1, US9142533B2. Conclusions about those are based on their titles/abstracts only and should be confirmed before any formal reliance.
• The Non-Patent Citations (Badami et al., U.S. Appl. No. 14/970,687; IBM Appendix P) are the applicant's own co-pending continuation/family materials, not independent prior art for §103 combination purposes.
• This is an analytical opinion, not a legal conclusion of invalidity; obviousness is ultimately a question of law, and no claim has been construed by a court. Where the patent text and web results could conflict, I followed the authoritative patent text and the cited-reference disclosures.