US 9093473

Here is a concise summary of US patent 9093473:

Patent Number: US9093473B2
Title: Method for fabricating metal-oxide semiconductor transistor
Current Assignee: Marlin Semiconductor Ltd
Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
Filing Date: 2014-07-15
Issue Date: 2015-07-28
Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a method for manufacturing a Metal-Oxide Semiconductor (MOS) transistor. The core idea is to first create a gate pattern on a semiconductor substrate and then form an epitaxial layer next to this gate pattern. Crucially, after the epitaxial layer is formed, a second photo-etching step is performed on the gate pattern to create a slot within it, effectively dividing the original gate pattern into two separate gates.

Litigation Status (as of April 26, 2026):

The patent family has ongoing litigation. A PTAB case, IPR2025-00879, was filed but not instituted due to procedural reasons. Additionally, US cases related to this patent have been filed in the Texas Western District Court (case 1:25-cv-00215), the Texas Eastern District Court (case 2:25-cv-00171), and the International Trade Commission (cases 337-TA-3809 and 337-TA-1443). There is no specific mention of US9093473 in the CAFC May 2026 scheduled cases, and the CAFC case information provided general resources rather than specific dockets for this patent number.

Known litigation involving US patent 9093473 includes the following cases:

1. PTAB Case: IPR2025-00879

• Plaintiff(s) (Petitioner): TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, APPLE, INC., BROADCOM, INC., AND QUALCOMM, INC. [cite: Patents Google US9093473B2 Legal Events 2025-06-10]
• Defendant(s) (Patent Owner): Marlin Semiconductor Limited. [cite: Patents Google US9093473B2 Legal Events 2025-06-10]
• Jurisdiction: Patent Trial and Appeal Board (PTAB). [cite: Patents Google US9093473B2 Legal Status PTAB case IPR2025-00879]
• Case Number: IPR2025-00879. [cite: Patents Google US9093473B2 Legal Status PTAB case IPR2025-00879]
• Filing Date: April 17, 2025. [cite: Patents Google US9093473B2 Legal Events 2025-06-10]
• Outcome or Current Status: Not Instituted - Procedural. [cite: Patents Google US9093473B2 Legal Status PTAB case IPR2025-00879]

2. US District Court Case: Texas Western District Court

• Plaintiff(s): Longitude Licensing Ltd. and Marlin Semiconductor Limited.
• Defendant(s): [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.), Broadcom Inc., Qualcomm Inc., Taiwan Semiconductor Manufacturing Company Limited (TSMC), Lenovo Group Limited, Motorola Mobile Communication Technology Ltd., Motorola (Wuhan) Mobility Technologies Communication Company Limited, and OnePlus Technology (Shenzhen) Co., LTD.
• Jurisdiction: U.S. District Court for the Western District of Texas. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Western District Court]
• Case Number: 1:25-cv-00215. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Western District Court]
• Filing Date: March 21, 2025.
• Outcome or Current Status: Stayed. The case was stayed pending the final disposition of ITC Investigation No. 337-TA-1443.

3. US District Court Case: Texas Eastern District Court

• Plaintiff(s): Longitude Licensing Ltd. and Marlin Semiconductor Limited.
• Defendant(s): Lenovo Group Limited, Motorola Mobile Communication Technology Ltd., Motorola (Wuhan) Mobility Technologies Communication Company Limited, OnePlus Technology (Shenzhen) Co., Ltd., and Taiwan Semiconductor Manufacturing Corporation Limited.
• Jurisdiction: U.S. District Court for the Eastern District of Texas. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Eastern District Court]
• Case Number: 2:25-cv-00171. [cite: Patents Google US9093473B2 Legal Status US case filed in Texas Eastern District Court]
• Filing Date: February 13, 2025.
• Outcome or Current Status: Stayed. The case was stayed pending the final disposition of ITC Investigation No. 337-TA-1443, with the motion to stay granted on April 23, 2025.

4. US International Trade Commission (ITC) Investigation: 337-TA-1443

• Plaintiff(s) (Complainant): Longitude Licensing Ltd. and Marlin Semiconductor Limited.
• Defendant(s) (Respondent): Apple Inc., Broadcom Inc., Lenovo Group Limited, Motorola Mobile Communication Technology Ltd., Motorola (Wuhan) Mobility Technologies Communication Company Limited, OnePlus Technology (Shenzhen) Co., LTD., Taiwan Semiconductor Manufacturing Company Limited, and Qualcomm Inc.
• Jurisdiction: U.S. International Trade Commission (ITC). [cite: Patents Google US9093473B2 Legal Status US case filed in International Trade Commission (337-TA-1443)]
• Case Number: 337-TA-1443. [cite: Patents Google US9093473B2 Legal Status US case filed in International Trade Commission (337-TA-1443)]
• Filing Date: February 18, 2025.
• Outcome or Current Status: Active. The investigation was instituted on March 21, 2025, and an evidentiary hearing is scheduled for February 2, 2026.

The Google Patents page for US9093473 also lists a "US case filed in International Trade Commission" with case number "337-TA-3809". However, further research indicates that "3809" appears as an internal identifier associated with ITC Investigation 337-TA-1443 rather than a separate, distinct ITC investigation. Therefore, separate details for 337-TA-3809 as an independent litigation case are not provided.

Proceedings overview

One AIA trial proceeding has been filed against US patent 9093473. This proceeding resulted in a discretionary denial of institution, meaning no claims were invalidated. This gives the patent owner a hardened defensive posture, as the patent has withstood a challenge at the PTAB's institution stage.

IPR2025-00879 — Taiwan Semiconductor Manufacturing Company Ltd. and [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

• Type: Inter Partes Review
• Filed: 2025-04-17
• Status: Not Instituted - Procedural. The institution was discretionarily denied by the USPTO Director.
• Judge panel: Coke Morgan Stewart, Acting Under Secretary of Commerce for Intellectual Property and Acting Director of the United States Patent and Trademark Office.
• Petition grounds: The petition challenged the patent, with the petitioner arguing that there was a "material error by the Office" related to "certain teachings in Chien770 that appear to disclose the claimed features that the patent examiner indicated were not taught by the prior art of record, including Chien770." This suggests grounds under 35 U.S.C. § 102 and/or § 103, although the specific claims challenged are not detailed in the available information.
• Institution decision: Denied (discretionary denial) on 2025-09-03. The Director found discretionary denial appropriate because a final written decision was unlikely to issue before a parallel U.S. International Trade Commission ("ITC") investigation hearing (scheduled for February 2, 2026), which would result in significant duplication of effort, additional expense, and a risk of inconsistent decisions. Additionally, the patent had been in force for ten years, creating strong settled expectations for the patent owner, and the petitioner did not provide persuasive reasoning for the IPR being an appropriate use of Board resources.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: No information regarding an appeal to the Federal Circuit is publicly available as of this date.
• Defensive value: The patent owner successfully defended against this IPR petition, as institution was denied. This means the challenged claims of US9093473 remain intact and have not been invalidated by this PTAB proceeding. For a defendant, this indicates that an IPR-based defense on the grounds raised in this petition would be more challenging, as the Director has already found reasons to deny institution.

Strategic summary

Currently, all claims of US9093473 are sustained and remain untested by PTAB proceedings on the merits. One Inter Partes Review (IPR2025-00879) was filed by Taiwan Semiconductor Manufacturing Company Ltd. and Apple Inc. but was discretionarily denied institution by the USPTO Director on September 3, 2025. The denial was based on factors such as the timing relative to a parallel ITC investigation and the patent's age contributing to "settled expectations," rather than a ruling on the merits of the prior art.

The estoppel landscape remains largely open for other potential petitioners. Since institution was denied on procedural grounds rather than a final written decision on the merits, the strict estoppel provisions of 35 U.S.C. § 315(e)(2) might not fully apply to prevent future challenges on the same or reasonably could have raised grounds by different parties. However, a future petitioner might face similar discretionary denial arguments if parallel litigation circumstances exist. The involvement of Unified Patents in other IPRs suggests an active landscape of defensive challenges in the semiconductor space, although Unified Patents was not explicitly named as the petitioner for IPR2025-00879 (TSMC and Apple Inc. were).

Recommended next steps

• As a defendant, be aware that while IPR2025-00879 did not invalidate any claims of US9093473, the patent owner prevailed at the institution stage due to discretionary denial. This means the specific prior art grounds raised by TSMC and Apple Inc. against the patent were not adjudicated on the merits by the PTAB.
• The absence of an institution on the merits means that the core patentability arguments have not been thoroughly vetted in an AIA trial. If facing assertion, consider a thorough prior art search to identify new grounds or different arguments based on the prior art previously cited in IPR2025-00879, taking into account the Director's reasons for discretionary denial.
• Given the Director's emphasis on "settled expectations" and parallel litigation in the denial of institution for IPR2025-00879, any future PTAB challenge would need to carefully address these discretionary factors, perhaps by demonstrating a material error by the examiner during prosecution or by filing early in relation to any parallel litigation.
• For specific details on the Director's decision for IPR2025-00879, refer to the document titled "Director_Discretionary_Decision@uspto.gov Paper 11" dated September 3, 2025, by searching the PTAB-TACTS system (USPTO's Patent Trial and Appeal Case Tracking System) for IPR2025-00879.

Inventors

• Ming-Te Wei (United Microelectronics Corp)
• Wen-Chen Wu (United Microelectronics Corp)
• Lung-En Kuo (United Microelectronics Corp)
• Po-Chao Tsao (United Microelectronics Corp)

There are no unusual patterns indicating inventors departing within 12 months of filing.

Original assignee

The original assignee named on the issued patent US9093473B2 is United Microelectronics Corp (UMC). UMC is a major semiconductor foundry, providing manufacturing services for integrated circuits. They ship a wide variety of semiconductor products embodying many different claims. UMC is currently an operating company.

Assignment timeline

• 2010-07-08 (executed) / recorded 2014-07-15 — Reel 033309/0116
  • Conveyance: Assignment
  • Assignor: KUO, LUNG-EN, TSAO, PO-CHAO, WEI, MING-TE, WU, WEN-CHEN (all inventors)
  • Assignee: UNITED MICROELECTRONICS CORP., TAIWAN
  • Correspondent: N/A (Not listed on record)
  • Context: Original assignment from inventors to employer.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED, IRELAND
  • Correspondent: LEE & HAYES, P.C., 601 W RIVERSIDE AVE SUITE 1400, SPOKANE, WA 99201
  • Context: Transfer-to-asserter.

Timeline diagram

timeline
    title Ownership of US 9093473
    2010 : Inventors to United Microelectronics
    2014 : Application filed
    2015 : Patent granted
    2021 : Assigned to Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — present. On 2021-07-26 (recorded), the patent was assigned from United Microelectronics Corporation, an operating company, to Marlin Semiconductor Limited, a company incorporated in Ireland. The name "Marlin Semiconductor Limited" suggests a licensing-focused entity, and its incorporation in Ireland (often associated with favorable tax structures for intellectual property) further supports this. Without product information for Marlin Semiconductor Limited, it is highly indicative of a shell entity for patent monetization.
2. Known asserter in the chain — unclear. While Marlin Semiconductor Limited is the current assignee, it is not immediately recognizable as a widely known NPE from standard public lists like Acacia Research Corp, Marathon Patent Group, or Intellectual Ventures without further investigation. However, its characteristics align with typical NPE behavior.
3. Repeat correspondent across the chain — not present. The correspondent for the 2021-07-26 assignment to Marlin Semiconductor Limited is LEE & HAYES, P.C. This correspondent does not appear in earlier records for this patent. Without a broader dataset of other tracked patents, it's not possible to definitively flag this as a repeat correspondent for NPE activity.
4. Cascading transfers — not present. There are only two recorded assignments, and they are spaced several years apart (2010 to 2021), not indicating cascading transfers within a short period.
5. Pre-litigation transfer — unclear. The current patent information shows litigation events starting in 2025 (IPR filed 2025-06-10, US cases filed in 2025). The assignment to Marlin Semiconductor Limited occurred on 2021-07-26. This is more than 6 months before the first known litigation filing, so it is not a "pre-litigation transfer" as strictly defined for this signal.
6. Bankruptcy fire-sale — not present. The original assignee, United Microelectronics Corp, is still an active operating company.
7. Privateering — unclear. There is no public information or SEC filing data available in the patent record to suggest a privateering arrangement between United Microelectronics Corp and Marlin Semiconductor Limited.
8. Defensive aggregator (anti-NPE) — not present. The chain ends with Marlin Semiconductor Limited, which does not appear to be a defensive aggregator.

Verdict

NPE — high confidence

The transfer from United Microelectronics Corp, a prominent operating semiconductor foundry, to Marlin Semiconductor Limited, an entity incorporated in Ireland, is a strong signal of a shell-entity transfer for patent assertion. This, coupled with the lack of apparent product lines for the assignee and the subsequent filing of litigation in 2025 (as shown in the legal status section of the patent), indicates a high likelihood of NPE activity.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

As a technical patent analyst, I have reviewed US patent 9093473B2, titled "Method for fabricating metal-oxide semiconductor transistor." The core innovation of this patent, particularly articulated in Claim 1, is a method that includes forming an epitaxial layer adjacent to two sides of a gate pattern, and then, after forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot, thereby separating the gate pattern into two gates. This sequence is presented as a solution to issues encountered in conventional approaches where the slot is formed before the epitaxial layer.

To identify the most relevant prior art and assess potential anticipation under 35 U.S.C. § 102, I have examined the patent citations listed in US9093473B2. Due to the limitations of this tool in accessing and performing detailed technical analysis of the full claims and specifications for all cited patents, the brief descriptions are primarily derived from the patent titles, and the potential anticipation assessment is based on a high-level comparison to the key distinguishing features of US9093473's Claim 1. A definitive anticipation ruling would require a full claim-by-claim comparison against the complete text of each prior art reference.

Below are selected patent citations, prioritizing those marked as "Cited by examiner" and those whose titles suggest direct relevance to MOS transistor fabrication, gate structures, or epitaxial layers:

Most Relevant Prior Art for US9093473B2

1. US20120012904A1

   • Full Citation: US20120012904A1, "Metal-oxide semiconductor transistor and method for fabricating the same" by Ming-Te Wei et al.
   • Publication Date: 2012-01-19 (Filing Date: 2010-07-15)
   • Brief Description: This publication describes a metal-oxide semiconductor transistor and its fabrication method. Notably, this application shares at least one inventor with US9093473B2 and has the same priority date, indicating it is a related application, likely a parent or sibling. Such a related application, if disclosing the same invention, would be prior art under certain conditions (e.g., if it published earlier than the effective filing date of the asserted claims in US9093473B2, or if it's a parent application from which priority is claimed). The fact that this is by the same inventor(s) and has a similar title suggests a high degree of technical overlap.
   • Potential Anticipation: Highly likely to potentially anticipate Claim 1 and its dependent claims of US9093473B2, as it is a related application from the same inventive entity with a similar subject matter and an earlier publication date than US9093473B2. A detailed comparison of the claims would be necessary, but given the relationship, it might disclose the specific sequence of forming the epitaxial layer before the polysilicon slot.

2. US20090186475A1

   • Full Citation: US20090186475A1, "Method of manufacturing a MOS transistor" by Shyh-Fann Ting.
   • Publication Date: 2009-07-23 (Filing Date: 2008-01-21)
   • Brief Description: This patent application describes methods for manufacturing MOS transistors, a broad area directly relevant to US9093473B2. To determine specific anticipation, its disclosure regarding gate patterning, epitaxial layer formation, and any subsequent slot creation would be critical.
   • Potential Anticipation: This reference could potentially anticipate aspects of Claim 1, particularly the general steps of forming a MOS transistor, gate pattern, and epitaxial layer. The key question for anticipation of Claim 1 of US9093473B2 would be whether it explicitly teaches forming the polysilicon slot after the epitaxial layer.

3. US20100081245A1

   • Full Citation: US20100081245A1, "Methods for fabricating mos devices having highly stressed channels" by Advanced Micro Devices, Inc.
   • Publication Date: 2010-04-01 (Filing Date: 2008-09-29)
   • Brief Description: This patent application focuses on fabricating MOS devices with "highly stressed channels," which often involves the use of epitaxial layers (e.g., SiGe for compressive strain or SiC for tensile strain) to enhance carrier mobility. This directly relates to the context of epitaxial layer formation in US9093473B2 (e.g., lines-).
   • Potential Anticipation: While it focuses on stressed channels and epitaxial layers, it would only anticipate Claim 1 of US9093473B2 if it also teaches the specific sequence of forming the gate pattern, then the epitaxial layer, and subsequently forming a slot in the gate pattern using a second photo-etching process. Without seeing its full claims and description, direct anticipation of the specific timing of the slot formation cannot be confirmed.

4. US7745847B2

   • Full Citation: US7745847B2, "Metal oxide semiconductor transistor" by United Microelectronics Corp.
   • Publication Date: 2010-06-29 (Filing Date: 2007-08-09)
   • Assignee: United Microelectronics Corp., which is the original assignee of US9093473B2. This makes it a highly relevant piece of prior art from the same entity.
   • Brief Description: The title indicates a focus on the MOS transistor structure itself. Being from the same assignee, it likely covers related semiconductor manufacturing techniques and could potentially disclose aspects of gate formation and epitaxial layers.
   • Potential Anticipation: Given the common assignee, this patent could disclose a manufacturing method that includes elements of US9093473B2. The critical aspect for anticipation of Claim 1 would be whether it teaches the specific sequence of forming the epitaxial layer before the polysilicon slot in the gate pattern.

5. US7312129B2

   • Full Citation: US7312129B2, "Method for producing two gates controlling the same channel" by Freescale Semiconductor, Inc.
   • Publication Date: 2007-12-25 (Filing Date: 2006-01-25)
   • Brief Description: This patent explicitly mentions "producing two gates controlling the same channel," which directly relates to the concept of separating a single gate pattern into two gates as described in US9093473B2 (Claim 1: "separating the gate pattern into two gates"). This makes it highly relevant for potentially anticipating the outcome of the second photo-etching process.
   • Potential Anticipation: This patent is highly relevant to the "forming a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates" step of Claim 1. Detailed examination of its claims and description is needed to see if it also teaches the step of forming an epitaxial layer before this gate separation, which is the distinguishing feature of US9093473B2.

6. US6143606A

   • Full Citation: US6143606A, "Method for manufacturing split-gate flash memory cell" by Worldwide Semiconductor Manufacturing Corp.
   • Publication Date: 2000-11-07 (Filing Date: 1997-12-26)
   • Brief Description: The title specifically mentions "split-gate" and "manufacturing," making it relevant to the gate separation aspect of US9093473B2. Split-gate structures inherently involve a separation of a gate element.
   • Potential Anticipation: This patent could potentially anticipate the "forming a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates" element of Claim 1. The key for anticipation of Claim 1 of US9093473B2 would be whether this patent teaches the formation of an epitaxial layer before the split-gate formation.

General Statement Regarding Anticipation:

For each of the cited patents, and particularly for Claim 1 of US9093473B2, a thorough anticipation analysis under 35 U.S.C. § 102 would require a detailed, side-by-side comparison of every element of Claim 1 (and its dependent claims) against the complete disclosure (including all claims, specification, and drawings) of each prior art reference. The critical differentiating element in US9093473B2's Claim 1 is the sequence where the second photo-etching process for forming the gate slot occurs after the epitaxial layer is formed. Any prior art that explicitly teaches all the elements of Claim 1 in this specific order would anticipate it. Without full access to the detailed text and figures of each cited patent, it is not possible to provide a definitive claim-by-claim anticipation statement for all 49 references.

To analyze the obviousness of US patent 9093473 under 35 U.S.C. § 103, we will examine the independent claims and consider combinations of prior art references along with the motivation for a person having ordinary skill in the art (PHOSITA) to combine them. The key distinguishing feature of US9093473, as highlighted in its abstract and detailed description, is the sequence of steps, specifically forming the epitaxial layer before performing the second photo-etching process to create a slot in the gate pattern.

Independent Claim 1 of US9093473B2

Independent Claim 1 describes a method for fabricating a metal-oxide semiconductor (MOS) transistor, comprising:

1. Providing a semiconductor substrate.
2. Forming a silicon layer on the semiconductor substrate.
3. Performing a first photo-etching process on the silicon layer for forming a gate pattern.
4. Forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern.
5. After forming the epitaxial layer, performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Prior Art Combination and Obviousness Analysis

The core of the obviousness argument rests on whether a PHOSITA, at the time of the invention (priority date 2010-07-15), would have been motivated to combine existing prior art elements in the claimed sequence, particularly regarding the timing of epitaxial layer formation and gate slot creation. The patent itself provides significant insight into the "conventional approach" and the problems it seeks to solve.

Primary Reference 1: US20050112817A1 (Taiwan Semiconductor Manufacturing Company, Ltd.)

• Disclosure: This patent describes a "Semiconductor device having high drive current and method of manufacture thereof," which involves forming strained source/drain regions using epitaxial layers.
• Specifically, it teaches:
  • Providing a semiconductor substrate.
  • Forming a gate structure on the semiconductor substrate (which typically includes a silicon layer, e.g., polysilicon). (See paragraph discussing "a gate structure 104 is formed on the semiconductor substrate 100").
  • Forming an epitaxial layer (e.g., SiGe or SiC) in the semiconductor substrate adjacent to two sides of the gate structure to function as source/drain regions. (See paragraph "Source/drain regions are then formed next to the gate structure 104. In this embodiment, the source/drain regions are formed by an epitaxial process... For example, the epitaxial layers may be SiGe layers or SiC layers.")
• Contribution to Claim 1: US20050112817A1 discloses steps (1), (2), (3) (forming the gate pattern), and (4) (forming the epitaxial layer adjacent to the gate pattern) of Claim 1. It does not, however, disclose the step of forming a slot in the gate pattern to separate it into two gates.

Secondary Reference 2: US20080090360A1 (Krivokapic)

• Disclosure: This patent, titled "Methods for fabricating multiple finger transistors," teaches how to split a single gate electrode into multiple gate electrodes (fingers) by forming a slot.
• Specifically, it teaches:
  • Forming a gate stack (e.g., a polysilicon gate stack) on a semiconductor substrate and defining a first gate electrode within it. (See paragraph).
  • Forming source/drain regions in the semiconductor substrate. (See paragraph).
  • Subsequently, a "second gate electrode" is formed in the gate stack, which involves splitting the initial gate electrode by creating a slot (as illustrated in Figure 4, showing slot 110 splitting gate electrode 104 into 104a and 104b).
• Key Timing: Krivokapic explicitly describes forming the source/drain regions before forming the second gate electrode (i.e., splitting the gate via a slot). (See paragraph "Thereafter, source/drain regions are formed in the semiconductor substrate and a second gate electrode is formed in the gate stack.").
• Contribution to Claim 1: US20080090360A1 discloses steps (1), (2), (3) (forming the gate pattern), and (5) (performing a second photo-etching process on the gate pattern to form a slot and separate it into two gates). Crucially, its sequence of performing the gate splitting after source/drain formation aligns with the "after forming the epitaxial layer" aspect of Claim 1, assuming the source/drain regions are epitaxial.

Motivation to Combine US20050112817A1 and US20080090360A1, driven by US9093473's own Background:

A PHOSITA would be motivated to combine the teachings of US20050112817A1 and US20080090360A1 for the following reasons:

1. Synergistic Performance Enhancement: Both references address transistor performance. US20050112817A1 aims to increase drive current through strained epitaxial source/drain regions, a known technique for high-performance MOS devices. US20080090360A1 teaches fabricating multiple-finger transistors, a common approach to further enhance current drive, reduce resistance, or improve device matching. A PHOSITA seeking to maximize MOS transistor performance would naturally combine these complementary techniques.
2. Addressing Known Problems in the Prior Art (as disclosed in US9093473 itself): The "Description of the Prior Art" section of US9093473 explicitly details the problems associated with the "conventional approach" of forming the polysilicon slot before the epitaxial layer. These problems include:
   • "Polysilicon residue and line end bridge" if the etching ratio for the slot formation is too low.
   • "Consumption of the hard mask" and "consumption of the spacer" if the etching ratio is too high, leading to "a portion of the gate is exposed and un-wanted epitaxial layer would be formed on the exposed portion of the gate."
     A PHOSITA, confronted with these well-articulated problems arising from the conventional sequence, would be strongly motivated to find a solution. The sequencing taught by Krivokapic (forming source/drain regions before splitting the gate), when applied to epitaxial source/drain regions (as taught by US20050112817A1), directly addresses the identified issues. By ensuring the epitaxial layer is formed before the potentially damaging slot-etching step, the gate structure is protected, preventing unwanted epitaxial growth on exposed gate portions. This represents a clear problem-solution motivation for adopting the sequence claimed in US9093473.

Therefore, a PHOSITA, having reviewed these prior art documents and being aware of the explicit problems associated with the "conventional approach" of slot formation before epitaxial layer growth (as detailed in the background of US9093473), would have been motivated to combine the features of US20050112817A1 and US20080090360A1 to arrive at the method claimed in US9093473, particularly the critical step of forming the epitaxial layer before the second photo-etching process that forms the slot. This combination, driven by clear motivations, renders Independent Claim 1 obvious under 35 U.S.C. § 103.

Dependent Claims

Dependent claims 2-10 elaborate on the process with additional steps such as forming hard masks, first and second spacers, lightly doped drains, and specific dielectric layers. Many of these steps are standard techniques in MOS transistor fabrication and are disclosed in various general semiconductor manufacturing patents (e.g., US6593197B2 for spacers, US7812399B2 for multi-layer gate structures and spacers). If the independent claim is found obvious, adding these conventional and well-known fabrication steps, especially when motivated by common design choices or known process improvements (like using protective dielectric layers to avoid rework issues as discussed in US9093473 itself), would also be considered obvious to a PHOSITA.

USPTO Database Search Results: US Patent 9,093,473

1. Patent identification (literal, no auto-correction)

• Patent number searched: 9093473 → US9093473B2 ("Method for fabricating metal-oxide semiconductor transistor")
• Application: US14/331,229, filed 2014-07-15
• Grant date: 2015-07-28
• Priority date: 2010-07-15 (via parent application US12/837,475)
• Status: Active (maintenance fees paid at year 4 and year 8; see Legal Events)
• Current owner: Marlin Semiconductor Ltd (since 2021-07-26 assignment from United Microelectronics Corp)

Note: The patent's own cross-reference states it is a division of U.S. Application No. 12/837,475, filed July 15, 2010.

2. Patent Term Adjustment (PTA)

I could not retrieve a definitive PTA day count from the USPTO via the available searches. The search results returned only general PTA law (35 U.S.C. § 154(b), A/B/C delays, applicant delays) and no patent-specific PTA figure for 9093473.

What the available record does show:

• Google Patents lists "Anticipated expiration: 2030-07-15" for US9093473B2 — exactly 20 years from the priority date of 2010-07-15. This is consistent with a PTA of zero (or no PTA reflected) for this patent.
• This is analytically plausible: the divisional was filed 2014-07-15 and granted 2015-07-28 (≈12.5 months pendency). Because the B-delay clock (35 U.S.C. § 154(b)(1)(B)) runs from the divisional's own filing date, the grant occurred well inside the 3-year window, and the 14-month A-delay trigger (September 2015) was also never reached — so no meaningful A- or B-delay would have accrued.

Action required for confirmation: The authoritative figure is printed on the patent front page ("(*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by ___ days") and in USPTO Patent Center (application 14/331,229 / patent 9093473). I could not access Patent Center programmatically; verify there before relying on the 2030-07-15 date in licensing or litigation.

3. Patent Term Extension (PTE)

No PTE under 35 U.S.C. § 156 applies. PTE is limited to patents claiming FDA-regulated products (drugs, biologics, medical devices, food/color additives, animal drugs) subject to regulatory review. US9093473 claims a MOS transistor fabrication method in the semiconductor space. There is no FDA Orange Book linkage, and no PTE certificate appears in the Legal Events for this patent.

4. Terminal disclaimer

None recorded. The Legal Events for US9093473B2 show assignments (2014, 2021), grant (2015), maintenance fee payments (2018, 2023), an IPR filing (2025), and a reexamination request (2026) — but no terminal disclaimer (TD). The front-page notice requirement for a TD is therefore not implicated. (Caveat: TDs are also verified in Patent Center; none appears in the Google Patents record.)

5. Continuation applications

None identified. US9093473 is the child in its family, not a parent. No further continuations, continuations-in-part, or divisionals filing from US14/331,229 appear in the family record (Family ID 45466260 contains exactly two applications).

6. Divisional applications

• US9093473B2 is itself a divisional of U.S. Application 12/837,475 (filed 2010-07-15), which issued as US8816409B2 ("Metal-oxide semiconductor transistor") on 2014-08-26. This is confirmed both by the patent's Cross-Reference section and by Google Patents' "Related Parent Applications" entry.
• No divisionals of US9093473 are recorded.

7. Related family members

Family ID 45466260 (per Google Patents / Darts-ip) contains two applications, both U.S.-only (no foreign filings):

Related publications: US20120012904A1 (parent application publication, 2012-01-19) and US20140322883A1 (this divisional's pre-grant publication, 2014-10-30). Later third-party patents citing this family include US10026736B2, US10685957B2 (both Samsung), and US12034054B2 (TSMC).

Flag — discrepancy worth noting: The parent US8816409B2's anticipated expiration (2031-06-01) runs ~321 days beyond the divisional's (2030-07-15), implying the parent received PTA while the divisional did not. Since the parent expires later than the child, the In re Cellect obviousness-type double patenting analysis (PTA counted post-adjustment) is a live consideration for the parent — though it does not shorten US9093473's own term, and no terminal disclaimer exists in this family to cap either patent.

8. Projected expiration date

• Base term: 20 years from the earliest claimed U.S. non-provisional filing date (2010-07-15), per 35 U.S.C. § 154(a)(2) — i.e., 2030-07-15.
• Projected expiration (Google Patents): 2030-07-15 — implying zero PTA days.
• If any PTA exists (unconfirmed), expiration would shift later by that number of days. If a terminal disclaimer existed (none found), it could cap the term — but here the natural term already expires before the parent, so a TD would have no effect in any event.
• Maintenance fees: Year-4 fee paid 2018-12-06; year-8 fee paid 2023-01-19. Year-11.5/12 fee will be due in the 2026–2027 window to keep the patent alive to expiration.

9. New status event not in prior sections (flag)

The Legal Events on the Google Patents record include a new entry dated 2026-03-10: "RR — Request for reexamination filed" (effective date 2025-12-03). I interpret this literally as a reexamination request (ex parte or similar) filed against this patent, recorded in early 2026 — distinct from the non-instituted IPR2025-00879. This is relevant to the patent's enforceability posture and should be tracked; it does not alter the term calculation above.

10. Verification steps (recommended)

1. USPTO Patent Center (patentcenter.uspto.gov) → search application 14/331,229 or patent 9093473 → read the PTA field, terminal disclaimer field, and "term of patent" notice.
2. USPTO Patent Public Search / Patent Full-Text → pull the front page of US9093473B2 for the § 154(b) notice line.
3. For the parent's PTA, check the front page of US8816409B2 (the 2031-06-01 anticipated expiration implies ~321 PTA days).

Bottom line: US9093473B2 — a divisional of US8816409B2, with no continuations, no divisionals of its own, no PTE, no recorded terminal disclaimer, and an indicated PTA of 0 — is projected to expire 2030-07-15, unless USPTO Patent Center reveals a PTA figure not visible in the sources I could search.

The USPTO/Google Patents search confirms that 9093473 resolves unambiguously to US9093473B2 — "Method for fabricating metal-oxide semiconductor transistor" (inventors Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao; priority 2010-07-15; divisional of US8816409B2). No similar-numbered patents surfaced. The PTAB record for IPR2025-00879 (TSMC et al. v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)) references the "473 Patent," consistent with this same grant. All technical identifiers below are cited literally.

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DEFENSIVE DISCLOSURE — US9093473B2 DERIVATIVE WORK PROGRAM

Docket: DF-9093473-2026-0426
Date of First Publication of This Disclosure: 2026-04-26
Disclosing Entity: [Inventor / Assignee]
Subject Patent Analyzed: US9093473B2 ("Method for fabricating metal-oxide semiconductor transistor")
Core Claim Element Used as Derivation Anchor: The post-epitaxy slotting sequence — i.e., performing the second photo-etching process on the gate pattern to form a slot in the gate pattern after forming the epitaxial layer, thereby physically separating the gate pattern into two gates (Claim 1, element 5), together with the dependent-claim features of hard-mask removal, first/second spacer formation, protective dielectric layers, and slot formation over shallow trench isolation (Claims 2–10).

Purpose: To publish enabling technical descriptions of derivative embodiments such that future incremental improvements by competitors over US9093473B2 are rendered obvious (§ 103) or non-novel (§ 102) under U.S. patent law. Each derivative is described at a level sufficient for a person having ordinary skill in the art (PHOSITA) to reproduce it without undue experimentation.

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AXIS 1 — MATERIAL & COMPONENT SUBSTITUTION

Derivative 1.1 — Replacement-Metal-Gate (RMG) Slotting Flow with High-κ Gate Dielectric

Enabling Description:

The polysilicon gate body of the anchor patent is replaced with a sacrificial amorphous-silicon (a-Si) gate that is later exchanged for a work-function metal stack; the critical "slot-after-epitaxy" sequencing is preserved and re-pointed at the RMG flow. Process sequence: (i) provide a silicon substrate with shallow trench isolation (STI); (ii) form an interfacial SiO₂ layer (0.8–1.2 nm) and deposit a high-κ dielectric (HfO₂, 1.5–2.5 nm, ALD) followed by a thin TiN barrier (1–2 nm) and a sacrificial a-Si layer (60–80 nm); (iii) deposit a SiN hard mask (20–40 nm) and perform a first photo-etching process to define a rectangular gate pattern; (iv) form a first spacer (SiO₂/SiN bilayer, 8–12 nm offset) via conformal deposition and anisotropic etch-back; (v) implant lightly doped drains; (vi) etch source/drain recesses self-aligned to the first spacer and perform selective epitaxial growth (SEG) — SiGe (30–50% Ge) for pFET or SiC:P for nFET — filling the recesses; (vii) deposit a blanket protective SiN layer (15–25 nm) over the patterned gate and the epitaxial layer; (viii) remove the SiN hard mask from the top of the sacrificial gate using a selective wet etch (hot H₃PO₄) that stops on the protective layer; (ix) perform the second photo-etching process with a patterned photoresist to open a slot through the protective SiN and the sacrificial a-Si down to the TiN/high-κ stack, the slot landing over the STI region and separating the gate pattern into two independent gates; (x) strip resist with an O₂/N₂-H₂ ashing step that cannot consume the TiN barrier, hence protecting the high-κ and channel; (xi) perform a wet removal of the remaining sacrificial a-Si (TMAH or NH₄OH-based), (xii) deposit pFET work-function metal (TiN/TaN bilayer, 3–5 nm) and nFET work-function metal (TiAl/TiN) in separate masked steps, and fill with low-resistivity metal (W, Co, or Ru) by CVD; (xiii) CMP the metal; (xiv) etch-back the protective SiN to form a second spacer on the two gate sidewalls, leaving the slot sidewalls bare of spacer. The material substitution changes the etch chemistry of the slot (a-Si vs. polysilicon, selectivity to TiN >100:1 with Cl₂/CF₄ chemistries) while preserving the claimed post-epitaxy slot timing.

flowchart TD
    A["Provide Si substrate with STI"] --> B["Form interfacial SiO2 + HfO2 high-k + TiN barrier"]
    B --> C["Deposit sacrificial a-Si gate layer + SiN hard mask"]
    C --> D["First PEP: define rectangular gate pattern"]
    D --> E["Form first SiO2/SiN spacer + LDD implant"]
    E --> F["Etch S/D recesses + SEG epitaxy SiGe/SiC:P"]
    F --> G["Deposit protective SiN blanket layer"]
    G --> H["Strip SiN hard mask with hot H3PO4"]
    H --> I["Second PEP: form slot through SiN + a-Si to TiN barrier"]
    I --> J["Resist ash with O2/N2-H2 (TiN protects high-k)"]
    J --> K["Remove remaining a-Si via TMAH"]
    K --> L["Fill WF metals TiN/TaN + W/Co/Ru, CMP"]
    L --> M["Etch-back protective SiN to form second spacer"]

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Derivative 1.2 — Group IV Alloy and III-V Epitaxial Layer Substitution

Enabling Description:

The strain-engineered epitaxial layer material is substituted while retaining the post-epitaxy slot sequence. For p-channel devices, replace SiGe with GeSn (5–15% Sn) grown by reduced-pressure CVD at 300–400 °C using GeH₄/SnCl₄ precursors, providing >2× the compressive strain of SiGe at equivalent thickness (40–80 nm) and enabling direct band-gap behavior at Sn > 8%. For n-channel devices, replace SiC with SiC:P (0.5–1.5% C substitutional, co-doped with P at 1–5×10²⁰ cm⁻³) grown with monomethylsilane (MMS) and PH₃. Alternatively, for III-V MOS channels, form a thin InGaAs (In₀.₅₃Ga₀.₄₇As) recessed epitaxial layer by MOCVD on a semi-insulating InP substrate; the gate pattern and slot are defined in a poly-Si or TiN gate body disposed on a composite gate dielectric (Al₂O₃/InP native oxide). The slot-forming second photo-etching process is performed after the III-V epitaxial growth, with the slot etched through the gate body using a CH₄/H₂/Ar RIE chemistry that is highly selective to the Al₂O₃ gate dielectric; the two resulting gates independently modulate the shared III-V channel. The substrate may be a GeOI wafer for GeSn channel integration; in that case the buried oxide (BOX) serves as the etch-stop for the source/drain recesses.

flowchart TD
    A["Choose channel epi material: GeSn / SiC:P / InGaAs"] --> B{"Device polarity?"}
    B -->|"pFET"| C["RPCVD GeSn 5-15% Sn at 300-400C"]
    B -->|"nFET"| D["RPCVD SiC:P with MMS + PH3"]
    B -->|"III-V"| E["MOCVD InGaAs on InP substrate"]
    C --> F["Recess etch self-aligned to first spacer"]
    D --> F
    E --> F
    F --> G["SEG fill recesses"]
    G --> H["Second PEP: slot through gate body"]
    H --> I["Gate dielectric Al2O3 acts as etch stop"]
    I --> J["Separate into two independent gates"]

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Derivative 1.3 — Low-κ and Air-Gap Spacer Substitution

Enabling Description:

The spacer dielectric stack is substituted with low-κ SiOCN (κ ≈ 3.5–4.2) or SiBCN (κ ≈ 3.2–3.8) deposited by plasma-enhanced ALD (PEALD) using aminosilane precursors and CO₂ or BCl₃ co-reactants, or with an air-gap spacer. For the air-gap variant: after first-spacer formation, deposit a sacrificial SiN liner (5 nm), then a conformal SiO₂ layer (15–25 nm); perform the source/drain recess etch and SEG epitaxy; deposit a thin (5–10 nm) non-conformal SiN capping layer that pinches off the top of the spacer cavity, leaving an enclosed air gap (κ ≈ 1.0) that reduces parasitic gate-to-contact capacitance. The slot-formation second photo-etching process is then performed after epitaxy, with the slot etch chemistry (C₄F₈/O₂/Ar for SiO₂ and SiOCN; CHF₃ for SiBCN) selected to be selective to the epitaxial SiGe/SiC so that the slot sidewalls and the air-gap spacer are not consumed. The air gap remains intact through the second photo-etch because the slot is opened only through the gate body over the STI, not through the spacer-adjacent active region. This substitution preserves the anchor claim's functional sequence while changing the parasitic capacitance of the final dual-gate structure.

flowchart TD
    A["Deposit PEALD SiOCN or SiBCN spacer liner"] --> B{"Air-gap variant?"}
    B -->|"Yes"| C["Sacrificial SiN liner + SiO2 spacer"]
    B -->|"No"| D["Anisotropic etch-back of low-k spacer"]
    C --> E["Pinch-off cap deposition -> enclosed air gap"]
    D --> F["Proceed to LDD + recess etch"]
    E --> F
    F --> G["SEG epitaxy SiGe/SiC"]
    G --> H["Second PEP: slot etch selective to epi"]
    H --> I["Dual gates with low-k / air-gap spacers"]

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Derivative 1.4 — Metal and Carbon-Based Hard Mask Substitution

Enabling Description:

The SiO₂/SiN hard mask of the anchor patent is replaced with a TiN hard mask (15–30 nm) or a tri-layer stack of amorphous carbon (APF-type, 100–200 nm) / SiON ARC (30 nm) / photoresist. The first photo-etching process patterns the TiN or carbon mask and the underlying polysilicon gate in a single etch step (for carbon: O₂/SO₂ strip of the carbon mask after patterning, leaving TiN or SiN as the transfer mask). The critical change is in the second photo-etching process: because the TiN hard mask is opaque to the resist stripping wavelength and resistant to O₂ ashing, the hard mask need not be removed before slot formation. Instead, the slot is etched through a patterned photoresist and through the protective dielectric (SiO₂/SiN) into the polysilicon while the TiN hard mask remains on top of the gate body; the TiN mask (etch rate <1 nm/min in Cl₂/CF₄ polysilicon etch chemistry) protects the gate top surface, preventing the "unwanted epitaxial layer on exposed gate" failure mode described in the anchor patent. After slot formation, the TiN mask is stripped in a hot SC1 (NH₄OH/H₂O₂/H₂O) or in a dilute HF/H₂O₂ mixture. The second spacer is then formed by etch-back of the pre-deposited protective SiO₂/SiN layer. This variant moves the hard-mask removal step to after the second photo-etching process — a temporal inversion of the anchor patent's preferred embodiment, with the same net result.

flowchart TD
    A["Deposit polysilicon + TiN hard mask (or APF/SiON)"] --> B["First PEP: pattern gate + hard mask"]
    B --> C["Form first spacer + LDD"]
    C --> D["Recess etch + SEG epitaxy"]
    D --> E["Deposit protective SiO2/SiN layer"]
    E --> F["Second PEP: slot through dielectric + polysilicon"]
    F --> G["TiN hard mask survives Cl2/CF4 slot etch"]
    G --> H["Strip TiN mask with SC1"]
    H --> I["Etch-back protective layer -> second spacer"]
    I --> J["Dual gates, top surface intact"]

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Derivative 1.5 — ALD High-κ Protective Overlayer for Rework Resistance

Enabling Description:

The SiO₂/SiN protective layers used during the second photo-etching process (and the associated photoresist rework) are substituted with an ALD-deposited Al₂O₃ or HfO₂ protective overlayer (2–5 nm). Sequence: after SEG epitaxy and removal of the hard mask, deposit by thermal ALD (TMA + H₂O at 250–300 °C for Al₂O₃; TDMAHf + H₂O for HfO₂) a conformal high-κ film over the gate body, the first spacer, and the epitaxial layer. The high-κ film is amorphous, pinhole-free, and — critically — is immune to the O₂-plasma ashing used during photoresist rework, preventing the native-oxide accumulation and substrate recess described in the anchor patent's specification. During the second photo-etching process, the slot is opened through the high-κ overlayer and the polysilicon; the high-κ film simultaneously acts as (i) an etch mask, (ii) a channel-protection layer, and (iii) a rework-hardening layer. The high-κ overlayer may be retained as a component of the final inter-layer dielectric (ILD) or removed with a dilute HF dip (Al₂O₃) prior to silicide formation. This substitution retains the functional claim sequence (epitaxy → slot → two gates) while upgrading the protective layer material.

flowchart TD
    A["After SEG epitaxy: strip SiN hard mask"] --> B["ALD Al2O3 or HfO2 overlayer 2-5 nm"]
    B --> C["Photoresist coat for second PEP"]
    C --> D{"Rework required?"}
    D -->|"Yes"| E["O2 plasma ash - high-k overlayer blocks oxidation"]
    E --> F["Re-coat resist"]
    D -->|"No"| F
    F --> G["Etch slot through high-k + polysilicon"]
    G --> H["Strip resist (overlayer protects epi + substrate)"]
    H --> I["Optional HF dip to remove overlayer"]
    I --> J["Etch-back -> second spacer; dual gates complete"]

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Derivative 1.6 — SOI / SiGe-OI / GaN-on-SiC Substrate Substitution

Enabling Description:

The bulk silicon substrate is replaced with an SOI substrate (BOX 10–25 nm, top Si 5–15 nm), a SiGe-on-insulator (SGOI) substrate, or a GaN-on-SiC epitaxial substrate for power devices. On SOI/SGOI, the BOX layer acts as a natural etch stop for both the source/drain recess etch and the slot-formation etch, so the second photo-etching process that forms the slot can be run with a deliberately high over-etch (200–300%) without risk of punching into the handle wafer — directly addressing the anchor patent's concern about over-etch consuming the hard mask and spacers. The slot is etched through the gate body (polysilicon or TiN) and stops on the BOX; the two resulting gates are fully dielectrically isolated from each other down to the BOX, eliminating any sub-slot leakage path. For GaN-on-SiC, the "silicon layer" of the claim is realized as a polycrystalline GaN gate electrode on an AlGaN/GaN heterostructure; the first photo-etching process defines the gate foot, the recessed source/drain regions are regrown by MBE or MOCVD n⁺-GaN (the "epitaxial layer"), and the second photo-etching process forms a slot through the GaN gate body using a BCl₃/Cl₂ ICP-RIE chemistry, separating the gate into two independently addressable gate fingers of a lateral power HEMT. The GaN cap layer under the gate foot serves as the etch stop.

flowchart TD
    A{"Substrate selection"} --> B["SOI: BOX 10-25 nm"]
    A --> C["SGOI: SiGe channel on BOX"]
    A --> D["GaN-on-SiC: AlGaN/GaN HEMT"]
    B --> E["First PEP gate pattern"]
    C --> E
    D --> F["Gate foot defined in GaN gate body"]
    E --> G["S/D recess stops on BOX"]
    F --> H["n+ GaN regrowth (MBE/MOCVD)"]
    G --> I["SEG epitaxy in recess"]
    H --> I
    I --> J["Second PEP: slot etch stops on BOX or GaN cap"]
    J --> K["Over-etch 200-300% tolerated - no substrate punch-through"]
    K --> L["Two dielectrically isolated gates"]

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AXIS 2 — OPERATIONAL PARAMETER EXPANSION

Derivative 2.1 — Sub-5 nm GAA Nanosheet Implementation

Enabling Description:

The planar gate pattern is expanded to a gate-all-around (GAA) nanosheet stack at the sub-5 nm node. The "silicon layer" of the anchor claim is realized as a superlattice of alternating Si nanosheets (3–6 nm thick) and SiGe sacrificial layers (8–12 nm), patterned by the first photo-etching process into a vertical fin-like gate pattern. The epitaxial layer (SiGe or SiC:P) is grown in recesses adjacent to the two sides of the fin stack before the second photo-etching process. The slot is then formed by the second photo-etching process, cutting through the full superlattice stack (including inner spacers of SiN or SiBCN) at a location over the STI, using a pulsed plasma etch (C₄F₈/SF₆) with high aspect-ratio capability (HARC, >40:1). Each resulting half-stack becomes an independent multi-nanosheet gate; the two gates share the same epitaxial source/drain regions. The critical parameter expansion is the aspect ratio of the slot (now 40–60:1 vs. <10:1 in planar), requiring cryogenic or pulsed etch chemistries and a post-slot selective SiGe release (vapor-phase HCl) to form the suspended nanosheets for subsequent gate-all-around metal fill (TiN/TaN/W). The slot-after-epitaxy sequencing prevents the epitaxial layer from encroaching on the released nanosheet regions — the functional advantage claimed in the anchor patent is thereby preserved at extreme scale.

flowchart TD
    A["Superlattice: Si nanosheets + SiGe sacrificial"] --> B["First PEP: define fin stack gate pattern"]
    B --> C["Inner spacers SiN/SiBCN + LDD"]
    C --> D["S/D recess + SEG epitaxy SiGe/SiC:P"]
    D --> E["Second PEP: HARC slot etch >40:1"]
    E --> F["Pulsed C4F8/SF6 chemistry through full stack"]
    F --> G["Vapor-HCl selective SiGe release"]
    G --> H["Nanoshsheets suspended under each gate half"]
    H --> I["WF metal fill TiN/TaN + W"]
    I --> J["Two independent GAA gates"]

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Derivative 2.2 — Cryogenic Slot Etch for Extreme Aspect Ratio

Enabling Description:

The slot-formation second photo-etching process is performed at cryogenic temperatures (−40 °C to −70 °C) on a temperature-controlled electrostatic chuck. At these temperatures, the Si/SiO₂ etch with SF₆/O₂ chemistry becomes strongly anisotropic because the sidewall passivation layer (SiₓOᵧF₂) does not desorb; this yields vertical slot profiles with an aspect ratio >25:1 and a line-edge roughness below 1.5 nm without the scalloping typical of room-temperature Bosch processing. Process parameters: chuck temperature −60 °C, SF₆ flow 100–200 sccm, O₂ flow 20–60 sccm, ICP source power 800–1200 W, bias 20–60 V, chamber pressure 5–10 mTorr. The cryogenic process is applied after the epitaxial layer is grown; the epitaxial SiGe/SiC regions act as a natural etch stop due to the >50:1 selectivity of SF₆/O₂ cryo-etch between undoped Si and Ge-containing or C-containing epitaxial films. After the cryo-etch, the wafer is allowed to warm to room temperature under N₂ purge to avoid condensation, and the resist is stripped with a downstream O₂ asher. The two resulting gates exhibit vertical slot sidewalls with critical dimension (CD) uniformity across a 300 mm wafer of <2% (3σ).

flowchart TD
    A["Cool chuck to -60C under N2 purge"] --> B["SF6/O2 cryo-etch chemistry"]
    B --> C["Sidewall SiOF passivation stable at cryo temp"]
    C --> D["Anisotropic vertical slot profile, AR > 25:1"]
    D --> E["Selectivity to SiGe/SiC epi > 50:1"]
    E --> F["Slot lands on epi or STI without punch-through"]
    F --> G["Warm-up under N2, avoid condensation"]
    G --> H["Resist strip in downstream asher"]
    H --> I["Dual gates, CD 3-sigma < 2%"]

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Derivative 2.3 — Atomic-Layer Etch (ALE) Slot Formation

Enabling Description:

The continuous plasma etch of the second photo-etching process is replaced with a self-limiting atomic-layer etch (ALE) sequence. Each ALE cycle comprises four phases: (i) saturation — exposure to Cl₂ gas at 1–10 Torr for 1–5 s, forming a self-limiting chlorinated surface layer (~1 monolayer); (ii) purge — Ar purge at 30–100 sccm for 2–5 s; (iii) activation — low-energy Ar⁺ ion bombardment (bias 20–50 V, ion energy <60 eV) for 1–3 s, removing the chlorinated layer; (iv) purge — second Ar purge. The etch rate is precisely one monolayer (~0.1–0.3 nm) per cycle, giving digital control of the slot depth — the slot can be stopped exactly at the bottom of the polysilicon gate or intentionally left with a 2–5 nm residual membrane (see Derivative 5.4). The ALE slot process is performed after epitaxial growth, with the patterned photoresist or a hard mask defining the slot location. Because ALE is surface-reaction-limited, it is insensitive to pattern density (no microloading), producing slot CDs uniform to <1 nm across the wafer. The ALE approach is directly compatible with the anchor patent's claim sequence and eliminates the "etching ratio" failure modes (residue, line-end bridge, spacer consumption) described in the anchor patent's Background.

stateDiagram-v2
    [*] --> Saturate: Cl2 exposure 1-5 s (self-limiting monolayer)
    Saturate --> Purge1: Ar purge 2-5 s
    Purge1 --> Activate: Ar+ bombardment 20-50 V (remove monolayer)
    Activate --> Purge2: Ar purge 2-5 s
    Purge2 --> CheckDepth: Measure cumulative slot depth
    CheckDepth --> Saturate: Depth < target (repeat cycle, ~0.1-0.3 nm/cycle)
    CheckDepth --> [*]: Depth = target (digital etch stop)

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Derivative 2.4 — High-Density Array and 3D Vertical Integration

Enabling Description:

The slot-after-epitaxy sequence is expanded to high-density memory arrays and 3D vertical integration. In a 3D NAND context, the "gate pattern" becomes a vertical channel hole array; instead, the more direct application is a DRAM or SRAM array where a single rectangular gate pattern spanning the STI is divided by a second photo-etching process into two word-line or pass-gate electrodes after the epitaxial source/drain layer is grown. The operational expansion is the slot density: a single second photo-etching mask contains >10⁶ slot openings across a 300 mm wafer, each slot 20–40 nm wide at 60–80 nm pitch, requiring extreme CD uniformity and overlay accuracy (<3 nm). For 3D integration, the slot is used to create dual-gate pass transistors in the periphery of a wafer-to-wafer hybrid-bonded stack, where the epitaxial layer is grown in the top wafer's recesses before bonding, and the slot is formed after bonding using a backside-illuminated lithography alignment to the bottom wafer's metal-1 patterns. The slotting step after epitaxy is critical in the 3D flow because the epitaxial layer (grown before bonding) would otherwise be damaged by the slot etch if performed first — precisely the anchor patent's functional insight applied at wafer-stack scale.

flowchart TD
    A["Array layout: gate pattern spanning STI"] --> B["First PEP: define array of gate patterns"]
    B --> C["Spacer + LDD per cell"]
    C --> D["SEG epitaxy in all cells (parallel)"]
    D --> E["Bond top wafer to bottom wafer (3D)"]
    E --> F["Backside alignment to bottom metal-1"]
    F --> G["Second PEP: >1e6 slots in single mask"]
    G --> H["Slot CD 20-40 nm at 60-80 nm pitch"]
    H --> I["Each pattern split into two word-line gates"]
    I --> J["3D dual-gate pass transistors"]

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Derivative 2.5 — Extreme Thermal Budget: Millisecond Anneal and SiC-Class Temperatures

Enabling Description:

The thermal budget surrounding the slot-after-epitaxy sequence is expanded in two directions. (a) Low thermal budget (logic): after the second photo-etching process forms the slot, the activation of source/drain dopants is performed with a laser spike anneal (LSA) or flash lamp anneal (FLA) at peak temperatures of 1250–1350 °C with dwell times of 0.5–2 ms, which activates the epitaxial layer dopants without allowing significant dopant diffusion across the slot. Because the slot is already formed, the anneal's thermal stress is relieved by the slot gap, preventing the pattern-edge slip dislocations that occur in unslotted long gate patterns. (b) High thermal budget (power): for SiC MOSFETs, the "silicon layer" is a degenerately doped poly-SiC gate electrode; the epitaxial layer is n⁺ SiC grown in recesses at 1600–1700 °C by CVD; the second photo-etching process forms the slot using an NF₃/O₂ or Cl₂/O₂ plasma at 200–400 °C chuck temperature. The completed dual-gate SiC structure operates at junction temperatures up to 250 °C and blocking voltages of 1200–3300 V, with the slot providing physical separation that suppresses the gate-to-gate leakage that would otherwise arise from the high operating temperature.

flowchart TD
    A{"Thermal regime"} --> B["Logic: LSA/FLA 1250-1350C, 0.5-2 ms"]
    A --> C["Power SiC: epi growth at 1600-1700C"]
    B --> D["Slot pre-formed: relieves anneal stress, no slip dislocations"]
    C --> E["Poly-SiC gate + n+ SiC epi"]
    E --> F["Second PEP: NF3/O2 slot etch at 200-400C"]
    F --> G["Dual-gate SiC MOSFET, 1200-3300 V, 250C junction"]
    D --> H["Dual-gate logic FET, no diffusion across slot"]

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Derivative 2.6 — RF/mmWave Dual-Gate Finger Isolation

Enabling Description:

The dual-gate separation produced by the post-epitaxy slot is exploited for RF and millimeter-wave (mmWave) operation (6–100 GHz). In a multi-finger RF MOSFET, the slot-formation second photo-etching process is used to divide each long rectangular gate pattern into two shorter gate fingers, reducing the gate electrode resistance (Rg) by a factor of ~2 per division and improving the maximum oscillation frequency f_max by up to 30%. The epitaxial layer (SiGe for pFET or SiC for nFET) is grown in the source/drain recesses before slotting, providing the strain-enhanced mobility required for low-noise amplifiers (NF < 0.8 dB at 28 GHz). The slot is placed not only over STI but also directly over the active epitaxial region in a "center-tap" configuration, where the two resulting gates are driven differentially (a virtual-ground center tap), cancelling common-mode coupling and improving even-order linearity (IIP2). The slot gap (30–60 nm) is subsequently filled with a low-loss dielectric (SiO₂ or SiCOH) to form the isolation between the differentially driven gate halves. This variant demonstrates that the slot need not be confined to the STI region, expanding the anchor claim's "slot in the gate pattern" element to active-region slotting.

flowchart TD
    A["Multi-finger RF gate pattern (long rectangular)"] --> B["First PEP: define fingers"]
    B --> C["SEG epitaxy SiGe/SiC for strain + mobility"]
    C --> D["Second PEP: center-tap slot over active region"]
    D --> E["Slot splits gate into two differential halves"]
    E --> F["Differential drive with virtual ground at slot"]
    F --> G["Rg reduced ~2x, f_max +30%"]
    G --> H["Fill slot with low-loss SiO2/SiCOH"]
    H --> I["mmWave LNA with IIP2 cancellation"]

---

AXIS 3 — CROSS-DOMAIN APPLICATION

Derivative 3.1 — Aerospace: Radiation-Hardened Redundant Dual-Gate Logic

Enabling Description:

The slot-separated dual-gate MOS transistor is applied to radiation-hardened (rad-hard) satellite electronics. In a space environment (LEO/GEO), single-event transients (SETs) and total ionizing dose (TID) effects cause threshold-voltage shifts and leakage in conventional MOS transistors. The derivative structure: two gate electrodes separated by the post-epitaxy slot are wired to the same logic input but through independent, spatially separated contact vias; the epitaxial layer (SiGe) is grown before slotting to provide a compressive-strained channel that partially compensates TID-induced mobility degradation. If a heavy-ion strike induces a gate-oxide short in one gate half, the second gate half continues to control the channel (the slot provides physical and electrical isolation), giving single-event functional interrupt (SEFI) immunity at the transistor level. Additional hardening: the slot gap is filled with a high-dose-rate-insensitive dielectric (SiO₂ deposited at 400 °C), and the two gates are biased through separate 10 kΩ polysilicon resistors to prevent latch-up. The fabrication sequence (epitaxy → slot → dual gate) is identical to the anchor claim; the cross-domain element is the redundancy topology: the two gates are not independent circuit elements but a single logic device with fail-operational redundancy, applicable to flight computers, power-conditioning units (PCUs), and reaction-wheel drivers operating at 125 °C with a 15-year mission life.

flowchart TD
    A["Rad-hard wafer fab (epitaxy-first, slot-after)"] --> B["Dual-gate transistor with slot isolation"]
    B --> C["Gate A contact via + 10kOhm poly resistor"]
    B --> D["Gate B contact via + 10kOhm poly resistor"]
    C --> E["Common logic input (redundant drive)"]
    D --> E
    E --> F{"Heavy-ion strike?"}
    F -->|"Gate A shorted"| G["Gate B still controls channel - SEFI immune"]
    F -->|"Gate B shorted"| H["Gate A still controls channel"]
    G --> I["Satellite flight computer continues operation"]
    H --> I

---

Derivative 3.2 — AgTech: Slot-Separated ISFET Dual-Gate Ion Sensor

Enabling Description:

The dual-gate slot architecture is applied to ion-sensitive field-effect transistors (ISFETs) for precision agriculture. An ISFET is fabricated with two gates separated by the post-epitaxy slot: Gate 1 (sensing gate) is exposed (via a back-end opening in the passivation) to the soil extract or hydroponic nutrient solution through an ion-selective membrane (Si₃N₄, Al₂O₃, or Ta₂O₅ sensing layer for pH; valinomycin-doped PVC membrane for K⁺; nitrate-selective membrane for NO₃⁻); Gate 2 (reference gate) is buried under the dielectric and biased at a fixed potential to provide a differential reference that cancels common-mode drift, temperature sensitivity, and light-induced threshold shifts. The epitaxial layer (SiC:P for nFET) is grown in the source/drain recesses before slotting, and provides a stable, high-mobility channel in the electrolyte-immersed environment. The differential output (V_gate1 − V_gate2) is read by a low-power (sub-µW) on-chip amplifier; the sensor array (16×16 pixels) is multiplexed to a LoRaWAN uplink for field deployment. The slot gap is filled with a hydrophobic dielectric (SiCOH) to prevent electrolyte wicking between the two gates. The functional sequence — epitaxy first, slot second — ensures the sensing membrane deposition and the slot etch are decoupled, avoiding membrane degradation during slotting.

sequenceDiagram
    participant Soil as Soil extract / nutrient solution
    participant G1 as Sensing Gate (ion-selective membrane)
    participant Slot as Slot isolation (SiCOH fill)
    participant G2 as Reference Gate (buried, fixed bias)
    participant Epi as Epitaxial SiC:P channel
    participant Amp as Differential amplifier + ADC
    Soil->>G1: Ion activity (H+, K+, NO3-) modulates threshold
    G1->>Amp: V_sense (drift + signal)
    G2->>Amp: V_ref (drift only, common mode)
    Epi->>Amp: High-mobility channel signal path
    Amp->>Amp: V_out = V_sense - V_ref (drift cancelled)
    Amp->>Soil: LoRaWAN telemetry to field gateway

---

Derivative 3.3 — Consumer Electronics: AMOLED Backplane Dual-Gate TFT

Enabling Description:

The slot-separated dual-gate architecture is applied to AMOLED display backplane thin-film transistors (TFTs) fabricated in low-temperature polycrystalline silicon (LTPS) on glass. In a 2T1C pixel circuit, the switching TFT and the driving TFT are replaced by a single dual-gate TFT in which the slot, formed after the source/drain epitaxial (or laser-crystallized) layer growth, separates the gate pattern into two independently biased gate halves: Gate A (scan/select) and Gate B (data-hold with storage capacitor Cst connected to its gate node). This topology reduces the pixel transistor count, improving aperture ratio and uniformity of OLED drive current (I_OLED) across the panel. The process: (i) glass substrate with buffer SiO₂/SiN; (ii) a-Si deposition, excimer-laser annealing (ELA) to form poly-Si; (iii) first photo-etching process to define the TFT gate pattern; (iv) SEG of n⁺/p⁺ Si in the source/drain regions (the "epitaxial layer" — realized as a selective Si growth at 600 °C); (v) second photo-etching process to form the slot and split the gate; (vi) interlayer dielectric and contact formation. The dual-gate TFT enables threshold-voltage (Vth) compensation by biasing Gate B to a stored compensation voltage while Gate A scans the row — a circuit-level capability that mitigates LTPS Vth non-uniformity (σVth typically 50–100 mV), which is the dominant AMOLED mura defect source. The slot-after-epitaxy sequence prevents the poly-Si epitaxial growth from bridging across the future slot line, preserving electrical isolation between the two gate halves.

flowchart TD
    A["Glass substrate + buffer layers"] --> B["a-Si deposition + ELA crystallization"]
    B --> C["First PEP: define TFT gate pattern"]
    C --> D["Selective Si epi in S/D regions (600C)"]
    D --> E["Second PEP: slot splits gate into A and B"]
    E --> F["Gate A = scan/select line"]
    E --> G["Gate B = data hold node + Cst"]
    F --> H["Vth compensation via Gate B bias"]
    G --> H
    H --> I["Uniform I_OLED across panel (mura suppressed)"]
    I --> J["2T1C pixel -> 1 dual-gate TFT per pixel"]

---

Derivative 3.4 — Automotive: Fail-Operational Dual-Gate SiC Inverter Switch

Enabling Description:

The post-epitaxy slot architecture is applied to automotive traction-inverter power switches (800 V bus, 300–600 A) built on SiC. A single large-area SiC MOSFET cell (or JFET) has its gate electrode divided by the slot into two gate halves, each driven by a separate gate-driver channel fed from redundant controller cores (lockstep). Under normal operation both gate halves are switched simultaneously, providing the full channel width for low on-resistance (Rds_on < 5 mΩ at 25 °C). In the event of a gate-driver failure, a short-circuit, or a desaturation event in one half, the control unit detects the fault (via di/dt or Vds sensing) and commutes the affected gate half to a safe state (soft-off at 1 A/µs) while the other half continues to conduct — achieving ASIL-D fail-operational behavior at the power-device level rather than at the system level. The epitaxial layer (n⁺ SiC, 1×10¹⁹ cm⁻³) is grown in the source recesses before the slot is formed, so the slot etch (NF₃/O₂ plasma) never touches the epitaxial junction, preserving the blocking voltage (1200 V) and the body-diode reverse-recovery characteristics (Qrr < 150 nC). The slot is encapsulated with a high-temperature (250 °C-rated) silicone gel after wire-bonding. The cross-domain element: the two gates of the anchor claim become two independent safety channels of an automotive functional-safety (ISO 26262) architecture.

stateDiagram-v2
    [*] --> Normal: Both gate halves on, full channel
    Normal --> FaultDetected: di/dt or Vds desaturation sense
    FaultDetected --> HalfSoftOff: Faulty half soft-off at 1 A/us
    HalfSoftOff --> FailOperational: Healthy half conducts load
    FailOperational --> Recover: Fault cleared, re-synchronize
    Recover --> Normal: Both halves re-enabled (lockstep)
    FailOperational --> [*]: Permanent fault - limp-home mode

---

Derivative 3.5 — Medical: Implantable Neurostimulator Fail-Safe Output Stage

Enabling Description:

The dual-gate slot architecture is applied to implantable neurostimulator output stages (deep-brain stimulation, spinal-cord stimulation, vagus-nerve stimulation). The output stage requires strict charge-balance control and failsafe behavior: an accidental DC leakage into neural tissue above ~100 nA can cause tissue damage. The derivative: a dual-gate MOS transistor in which the slot separates the gate pattern into a drive gate (Gate D) and a monitor gate (Gate M). Gate D is driven by the stimulation pulse generator (0.5–10 V, 10 µs–1 ms pulses, up to 20 mA). Gate M is biased in weak inversion and its channel current is continuously monitored by a charge-integrating ADC as a replica of the stimulation current. Because both gates share the same epitaxial source/drain and channel, the Gate M current tracks Gate D's current with matched temperature coefficients (±0.1%/°C over 35–42 °C). If the monitor detects a net DC component >50 nA averaged over 100 ms, a titanium-nitride shunt switch connected across the output (realized as the same dual-gate device in the shunt position) is closed, shorting the electrode to the device ground — a fail-safe that discharges residual charge before tissue damage thresholds are reached. The epitaxial layer (SiGe for pFET drive, giving higher hole mobility at low supply voltage) is grown before slotting; the slot is filled with a biocompatible, moisture-blocking dielectric (SiO₂ + SiN bilayer) to prevent body-fluid ingress. The device operates at 37 °C in a hermetically sealed titanium case with a 10-year, 2.5 Ah battery.

sequenceDiagram
    participant PG as Pulse generator (Gate D drive)
    participant D as Drive gate (stimulation current)
    participant M as Monitor gate (weak inversion replica)
    participant Epi as Shared epitaxial S/D + channel
    participant ADC as Charge-integrating ADC
    participant Shunt as Fail-safe shunt switch
    participant Tissue as Neural electrode / tissue
    PG->>D: Stimulation pulse 0.5-10V
    D->>Epi: I_stim 0-20 mA
    Epi->>Tissue: Charge delivered to tissue
    M->>ADC: I_monitor replica (matched tempco)
    ADC->>ADC: Integrate net charge over 100 ms window
    ADC->>Shunt: DC component > 50 nA detected
    Shunt->>Tissue: Short electrode to ground (discharge)

---

AXIS 4 — INTEGRATION WITH EMERGING TECH

Derivative 4.1 — AI-Driven Litho-Etch Co-Optimization of Slot Formation

Enabling Description:

The second photo-etching process (slot formation) is integrated with an AI-driven lithography-etch co-optimization loop. A convolutional neural network (CNN) — specifically a U-Net variant — is trained on SEM images of slot cross-sections (CD, sidewall angle, line-edge roughness, bottom residue) from 500+ prior wafers, with inputs including the mask layout (GDS/OASIS polygons), the resist thickness map, the etch-chamber state vector (wall temperature, polymer seasoning, electrode condition), and the OES (optical emission spectroscopy) trace of the slot etch. The model predicts the post-etch slot profile and, via a physics-informed loss function (coupled with a level-set etch simulator), outputs corrected mask bias and etch parameters (bias power, ICP power, pressure, C₄F₈/O₂/Ar flow ratios) for the next wafer. The closed loop runs in near-real time: in-line CD-SEM metrology feeds back to the model, and a Bayesian optimizer (or reinforcement-learning agent) proposes the next wafer's recipe. Because the slot is formed after the epitaxial layer, the AI loop can additionally use the epitaxial-layer reflectance signal (from a spectroscopic ellipsometer) as a state input to detect epi-height non-uniformity and compensate the slot etch time accordingly — a coupling that is only possible in the post-epitaxy slotting sequence of the anchor claim. Result: slot CD uniformity improves from 2.5% (3σ) to <1.2% (3σ), and etch-induced defect density decreases by >40%.

flowchart LR
    A["Mask layout GDS/OASIS"] --> B["CNN U-Net profile predictor"]
    C["Chamber state vector"] --> B
    D["OES trace of slot etch"] --> B
    E["Ellipsometer epi-height map"] --> B
    B --> F["Predicted slot CD / sidewall / residue"]
    F --> G["Level-set etch simulator (physics-informed)"]
    G --> H["Bayesian optimizer / RL agent"]
    H --> I["Corrected mask bias + etch recipe"]
    I --> J["Next wafer slot etch"]
    J --> K["In-line CD-SEM metrology"]
    K --> B

---

Derivative 4.2 — IoT In-Situ Metrology and Real-Time Endpoint Detection

Enabling Description:

The slot-formation process is instrumented with IoT-enabled in-situ metrology for real-time endpoint detection (EPD). Wireless, battery-free sensor nodes (SAW-based or NFC-powered) are embedded in the wafer carrier and in the etch-chamber lid, streaming: (i) chamber pressure and gas flow (via MEMS pressure/flow sensors), (ii) plasma emission at Si* (288 nm), F* (704 nm), and C₂ (516 nm) lines (via a compact Czerny-Turner spectrometer), (iii) wafer backside temperature (via emissivity-corrected pyrometry), and (iv) vibration/acoustic emission from the electrostatic chuck (piezoelectric MEMS). The sensor stream is transmitted over a 6LoWPAN/802.15.4 mesh to a local edge gateway and then to the fab's MES (manufacturing execution system). A spectral-ratio EPD algorithm (Si*/F* intensity ratio) detects the transition from polysilicon to the underlying dielectric/STI with ±0.5 s precision; because the slot is formed after epitaxy, the EPD algorithm is extended to use the epitaxial-layer photoluminescence (PL) signature (Ge-Ge phonon replica at ~1.6–1.8 µm for SiGe) as a confirmatory signal that the slot has stopped above the epi — a failure mode unique to the post-epitaxy sequence. The IoT data is stored in a time-series database (InfluxDB-class) and used to trigger preventive maintenance (PM) when the chamber-state vector drifts beyond a statistical control limit (e.g., Hotelling T² > χ² threshold).

sequenceDiagram
    participant S as SAW/NFC sensor nodes (chamber + carrier)
    participant G as 6LoWPAN edge gateway
    participant E as Etch tool controller
    participant M as MES + time-series DB
    participant A as EPD algorithm
    S->>G: Pressure, flow, OES lines, backside T, AE
    G->>E: Real-time chamber state stream
    E->>A: Si*/F* ratio + SiGe PL signature
    A->>E: Endpoint detected (+/- 0.5 s)
    E->>M: Slot depth + CD + timestamp (hash-linked)
    M->>E: PM trigger if Hotelling T2 exceeds limit

---

Derivative 4.3 — Blockchain-Verified Process Provenance and Recipe Traceability

Enabling Description:

The slot-after-epitaxy fabrication sequence is integrated with a blockchain-based supply-chain and process-provenance ledger. Each wafer lot is assigned a decentralized identifier (DID); at every process step (epitaxial growth, hard-mask removal, slot lithography, slot etch, spacer etch-back), the process recipe hash, the tool ID, the operator credential, the in-situ sensor summary (from Derivative 4.2), and the CD-SEM metrology result are written as a transaction to a permissioned blockchain (Hyperledger Fabric or Quorum) via a smart contract. The smart contract enforces a process-flow state machine: it validates, for each wafer, that the epitaxial-growth transaction is committed before the slot-etch transaction — cryptographically enforcing the anchor claim's critical ordering (epitaxy-before-slot) across multi-party manufacturing (e.g., a fabless designer, an epitaxy foundry, and an assembly house). Non-fungible tokens (NFTs) representing wafer lots carry the full provenance; a customer or regulator can verify, without trusting any single party, that the "epitaxy-first, slot-after" sequence was executed. In the event of a device failure, the ledger enables root-cause attribution to a specific tool, recipe, and operator, with an immutable audit trail admissible for quality and warranty disputes. The ledger also enables yield-bidding: downstream buyers can price wafers based on verified process-parameter distributions.

flowchart TD
    A["Wafer lot DID created"] --> B["Tx1: epitaxial growth recipe hash + sensor summary"]
    B --> C["Smart contract: validate epi committed"]
    C --> D["Tx2: hard-mask removal"]
    D --> E["Tx3: slot litho + etch recipe hash + EPD log"]
    E --> F["Smart contract: enforce epi-before-slot ordering"]
    F --> G["Tx4: CD-SEM metrology results"]
    G --> H["Block appended to permissioned ledger"]
    H --> I["NFT per lot with full provenance"]
    I --> J["Customer / regulator verifies without trusted party"]
    J --> K["Failure attribution: tool + recipe + operator"]

---

Derivative 4.4 — Digital Twin of the Slot-Formation Process

Enabling Description:

A digital twin of the entire epitaxy-then-slot process module is built and synchronized with the physical fab. The twin couples: (i) a first-principles reactor model (CFD + plasma kinetics, e.g., a 2D axisymmetric COMSOL or hybrid-PIC model of the etch chamber); (ii) a feature-scale Monte Carlo profile simulator (including the slot etch and the epitaxial growth); (iii) a equipment-health model (chamber wall polymer thickness, ESC temperature distribution, RF match-network state); and (iv) the live IoT sensor stream from Derivative 4.2. The twin is updated continuously via data assimilation (ensemble Kalman filter), so that the twin's predicted slot profile tracks the physical wafer's actual profile within 1 nm RMS. The twin is used for: (a) virtual metrology — predicting the slot CD and depth of every wafer between CD-SEM measurements, at full wafer-lot granularity; (b) what-if optimization — simulating recipe perturbations (e.g., ±5% bias power, ±10% C₄F₈ flow) without consuming wafers; (c) drift compensation — detecting chamber aging and pre-compensating the recipe before the physical CD drifts out of spec; and (d) operator training — a VR interface where engineers practice the slot-formation second photo-etching process on the twin. Because the digital twin models the full epitaxy-first sequence, it can simulate the anchor patent's failure modes (line-end bridge, spacer consumption, unwanted epi on exposed gate) and verify that a given recipe stays within the safe operating envelope.

flowchart LR
    A["Physical etch chamber"] --> B["IoT sensor stream (live)"]
    B --> C["Data assimilation (Ensemble Kalman filter)"]
    C --> D["Digital twin: CFD + plasma kinetics + MC profile"]
    D --> E["Predicted slot CD/depth (virtual metrology)"]
    E --> F["What-if recipe optimization"]
    F --> G["Drift compensation feed-forward"]
    G --> A
    D --> H["Failure-mode simulator (bridge / spacer loss / epi encroachment)"]
    H --> I["Safe operating envelope verification"]
    D --> J["VR operator training"]

---

Derivative 4.5 — Federated Learning Across Fabs for Slot-Etch Recipe Optimization

Enabling Description:

The AI optimization of Derivative 4.1 is extended to a federated learning (FL) framework so that multiple foundries and fabless partners can jointly train a global slot-etch model without sharing proprietary wafer data or recipes. Each participating fab runs local training on its own process history (SEM images, OES traces, metrology) and shares only model gradients (or encrypted updates via secure aggregation, e.g., with a Shamir-secret-sharing or homomorphic-encryption scheme) with a central aggregator. The global model is a graph neural network (GNN) over the etch-chamber component graph (RF source, bias, ESC, gas panel, pumps, walls) that predicts the slot profile from the chamber state; local models add fab-specific fine-tuning layers (transfer learning) that capture tool-to-tool and site-to-site variation. The FL loop respects cross-border data regulations (e.g., GDPR, Taiwan's Personal Data Protection Act as applied to employee and process data) because raw data never leaves the fab. The anchor claim's post-epitaxy slotting is the target process; the global model learns, across fabs, the optimal slot-etch recipe envelope as a function of the epitaxial-layer state (composition, thickness, pattern density) — a coupling that is only meaningful in the epitaxy-first flow. Expected outcome: cross-fab slot CD uniformity improves to <1.5% (3σ), and new-fab ramp-up time (process-match) is reduced by 60%.

flowchart TD
    A["Fab A: local training on wafer history"] --> B["Gradient update (encrypted)"]
    C["Fab B: local training on wafer history"] --> D["Gradient update (encrypted)"]
    E["Fab C: local training on wafer history"] --> F["Gradient update (encrypted)"]
    B --> G["Central aggregator (secure aggregation)"]
    D --> G
    F --> G
    G --> H["Global GNN slot-etch model"]
    H --> I["Fine-tuned local models (transfer learning)"]
    I --> A
    I --> C
    I --> E
    H --> J["Cross-fab optimal recipe envelope"]
    J --> K["CD uniformity < 1.5% (3-sigma), ramp-up -60%"]

---

AXIS 5 — THE "INVERSE" OR FAILURE MODE

Derivative 5.1 — Slot-as-Programmable Fuse (Fail-Open Overcurrent Protection)

Enabling Description:

The slot is intentionally designed as the weakest electrical point of the gate pattern, functioning as a programmable fuse that fails open under overcurrent. In the anchor claim's structure, the two gates separated by the slot are normally connected by a narrow polysilicon bridge (5–15 nm wide, 20–40 nm thick) left at the bottom of the slot by an intentionally incomplete slot etch (the "membrane" variant enabled by the ALE process of Derivative 2.3, stopped 5–15 nm above the gate dielectric). Under normal operation, the bridge conducts gate drive signals between the two gate halves (single-gate-mode operation). Under an overcurrent fault (e.g., gate-dielectric breakdown or an ESD event injecting >10 mA through the gate), the bridge's current density exceeds its electromigration limit, and the bridge opens like a fuse, isolating the faulty gate half from the driver. The fuse action is deterministic: the bridge cross-section is sized so that the fusing current (I_fuse) is 3× the normal operating gate current, with a fusing time of <1 µs. The two gate halves then operate as independent gates (dual-gate-mode), allowing the circuit to continue in a degraded-but-functional state. This "inverse" variant flips the anchor claim's purpose: instead of separating the gate pattern into two intended gates, the slot creates a latent separation that activates only on failure — a fail-open protection device embedded in the gate electrode.

stateDiagram-v2
    [*] --> Intact: Bridge 5-15 nm wide at slot bottom
    Intact --> Conducting: Normal gate drive (single-gate mode)
    Conducting --> Overcurrent: ESD / gate-oxide breakdown > 10 mA
    Overcurrent --> Fused: Bridge opens in < 1 us (electromigration)
    Fused --> Isolated: Faulty gate half isolated from driver
    Isolated --> Degraded: Healthy half continues (dual-gate mode)
    Degraded --> [*]: Permanent fail-open protection

---

Derivative 5.2 — Low-Power "Keeper" Gate in Subthreshold Operation

Enabling Description:

One of the two slot-separated gates is deliberately operated in a limited-functionality, ultra-low-power "keeper" mode. The drive gate (Gate D) is operated in normal strong-inversion (on/off) switching, while the keeper gate (Gate K) is biased at a fixed subthreshold voltage (V_keeper ≈ Vth − 100 mV) such that it conducts only a leakage-level current (I_keeper < 1 nA). The keeper gate serves three functions: (i) state retention — in a power-gated SRAM or latch, Gate K holds the stored data via its subthreshold current when the main power rail (VDD) is collapsed to 0.3–0.5 V (the "keep-alive" mode); (ii) leakage cancellation — Gate K's subthreshold current is tuned to cancel the drive gate's off-state leakage (I_off), reducing static power by up to 50% at the cost of a small area; and (iii) sensing — Gate K's subthreshold current is exponentially sensitive to threshold-voltage shifts (dI/dVth ∝ q/kT), making it a built-in aging sensor (NBTI/HCI monitor) whose current drift is read out periodically. The epitaxial layer (SiGe) is grown before slotting; the keeper gate shares the same strained channel, so its subthreshold swing (SS ≈ 70–80 mV/dec) tracks the drive gate's. This variant is the "inverse" of the anchor claim in the sense that the second gate is not a full-function counterpart but a limited-functionality companion — the slot separation is exploited to give the two gates different operating regimes rather than identical ones.

flowchart TD
    A["Dual-gate device: Gate D + Gate K"] --> B["Gate D: strong-inversion switching (VDD)"]
    A --> C["Gate K: fixed subthreshold bias (Vth - 100 mV)"]
    C --> D["I_keeper < 1 nA (leakage-level)"]
    B --> E["Normal logic operation"]
    C --> F["State retention at 0.3-0.5 V keep-alive"]
    C --> G["Leakage cancellation of Gate D I_off"]
    C --> H["Aging sensor: dI/dVth exponential (NBTI/HCI monitor)"]
    E --> I["Power-gated idle"]
    I --> F
    F --> E

---

Derivative 5.3 — Fail-Operational Redundant Gate Pair with Independent Control

Enabling Description:

This variant is the explicit fail-operational inverse of the anchor claim's symmetric dual-gate structure: the two slot-separated gates are wired to fully independent control signals and can be biased to different DC operating points. Gate A is the primary control gate (digital switching); Gate B is the secondary control gate, which can be (i) tied to a backup driver, (ii) biased to adjust the device's threshold voltage in-situ (dynamic Vth tuning via body-like effect through the second gate), or (iii) used as a sense terminal for the channel potential (a "gate-as-probe" configuration). In fail-operational mode: if the primary driver or Gate A's contact fails (open or short), the secondary driver seamlessly takes over Gate B (detected within one clock cycle by a built-in comparator that monitors the gate-node voltage), maintaining circuit function without interruption — relevant for safety-critical automotive (ASIL-D), avionics, and medical applications. The epitaxy-first, slot-after sequence ensures both gates have identical channel access and matched capacitance (Cgg within 2%), so the handover transient is <1 ns. The two gates share the same epitaxial source/drain; a single device replaces two parallel redundant transistors, reducing area by ~45% while providing transistor-level redundancy.

sequenceDiagram
    participant CA as Primary driver (Gate A)
    participant CB as Secondary driver (Gate B)
    participant CMP as Comparator (gate-node monitor)
    participant D as Dual-gate transistor (shared epi S/D)
    participant L as Load / logic
    CA->>D: Primary control (digital switching)
    CB->>D: Standby bias / Vth tuning / channel probe
    CMP->>CMP: Monitor Gate A node voltage each cycle
    CMP->>CB: Gate A fail detected (open/short)
    CB->>D: Seamless takeover (< 1 ns, matched Cgg)
    D->>L: Continuous function (no interruption)

---

Derivative 5.4 — Partial Slot (Notch) for Controlled Fracture and Crack Stop

Enabling Description:

The slot-formation second photo-etching process is intentionally performed as a partial etch that leaves a residual polysilicon membrane (or "notch") at the slot bottom, converting the slot into a crack-stop and controlled-fracture feature. The notch depth is controlled by the ALE process of Derivative 2.3 (depth accuracy ±1 nm). Two applications: (a) Dicing crack stop — in the wafer saw-street region, a row of partial slots (notches) is formed after epitaxy; the notches act as stress concentrators that guide the dicing crack along the intended street and prevent crack propagation into the active circuit area (die-side chipping reduced by >70%). The epitaxy-first sequence ensures the notch etch never exposes the epitaxial source/drain junction to the saw coolant. (b) Controlled fracture for layer transfer — in a 3D integration flow (Derivative 2.4), the notches define a preferred fracture plane; after wafer bonding, a controlled mechanical or thermal shock (or a hydrogen-implantation weakened plane aligned to the notch bottoms) fractures the donor wafer along the notch plane, transferring a thin (5–20 µm) device layer. The two "gates" in this variant are not intended to be electrically separated; the notch is a mechanical feature that only becomes a full slot if the fracture propagates — the inverse of the anchor claim's functional intent (electrical separation becomes incidental to mechanical separation).

flowchart TD
    A["Second PEP with ALE partial etch"] --> B["Residual membrane 5-15 nm at slot bottom"]
    B --> C{"Application"}
    C -->|"Dicing"| D["Notch row in saw street acts as crack guide"]
    D --> E["Dicing crack propagates along notch plane"]
    E --> F["Die-side chipping reduced > 70%"]
    C -->|"Layer transfer"| G["Notch plane aligned to H-implant weakened plane"]
    G --> H["Controlled thermal/mechanical shock"]
    H --> I["Donor wafer fractures along notch plane"]
    I --> J["Thin device layer 5-20 um transferred"]

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Derivative 5.5 — Self-Healing Slot Fill with Reflowable Dielectric

Enabling Description:

The slot, after separating the gate pattern into two gates, is filled with a reflowable, damage-repair-capable dielectric to create a self-healing isolation structure — the inverse of the permanent, rigid dielectric fill of the anchor patent. The slot (20–60 nm wide) is filled with a flowable oxide (FCVD, e.g., perhydropolysilazane-derived SiO₂) or a low-temperature reflowable spin-on glass (SOG). A self-healing cycle is triggered when in-situ sensors (Derivative 4.2) or post-process inspection detects a defect in the slot fill (a crack, void, or delamination — e.g., caused by thermal-cycling fatigue, mechanical shock, or electromigration-induced voiding of the gate metal adjacent to the slot). The healing process: (i) local resistive heating — a small integrated heater (a polysilicon or TiN resistor embedded in the interlayer dielectric adjacent to the slot) raises the slot-fill temperature to 400–450 °C (for SOG) or 250–350 °C (for FCVD oxide with steam); (ii) the fill material reflows or reflows-and-crosslinks, filling the crack/void by capillary action (viscosity 1–10 cP at reflow temperature); (iii) a low-temperature anneal (30 min in N₂) re-forms the Si–O–Si network. Because the epitaxial layer is grown before the slot is formed and filled, the healing thermal cycle does not disturb the epitaxial source/drain junctions (which were formed and annealed at higher temperatures earlier in the flow). The healed slot restores the inter-gate isolation resistance (>10¹² Ω) and breakdown voltage (>50 V for a 40 nm slot). This variant makes the slot an active, repairable component rather than a passive one-time feature.

stateDiagram-v2
    [*] --> Filled: Slot filled with FCVD oxide / reflowable SOG
    Filled --> DefectDetected: Crack / void / delamination sensed
    DefectDetected --> Heating: Embedded TiN/poly heater on (400-450C)
    Heating --> Reflow: Fill material reflows by capillary action
    Reflow --> Crosslink: Si-O-Si network re-formed (N2 anneal 30 min)
    Crosslink --> Verified: Isolation > 1e12 ohm, BDV > 50 V
    Verified --> Filled: Healed - back to operational state
    DefectDetected --> [*]: Heal failure - permanent repair required

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COMBINATION PRIOR ART SCENARIOS

The following scenarios combine the anchor patent's post-epitaxy slotting concept with existing open-source standards and open-source hardware/software ecosystems. Each scenario is itself a prior-art disclosure: a PHOSITA combining the anchor patent with any of these open standards would have been motivated to arrive at the claimed (or derivative) subject matter without inventive skill.

Scenario C1 — Combination with the SkyWater SKY130 Open-Source PDK

Enabling Description:

The post-epitaxy slotting flow is expressed as a custom cell in the SkyWater SKY130 open-source Process Design Kit (a 130 nm, 1.8 V/3.3 V/5.5 V open PDK maintained by SkyWater Technology and Google, distributed under the Apache 2.0 license). The derivative: a dual-gate standard cell ("DG_LV") that reuses the SKY130's existing device layers (poly, n+ implant, local interconnect, metal 1–5) and adds a single additional mask layer (the "SLOT" layer) that maps to the second photo-etching process. The SKY130 DRC deck (Magic VLSI Layout Tool, open-source) is extended with a rule set: (i) slot.width >= 0.18 µm; (ii) slot.overlap_epi >= 0.10 µm (the slot must be placed after the epitaxial region, i.e., the layout enforces epitaxy-first ordering by construction); (iii) slot.enclose_gate >= 0.12 µm. The cell is characterized with the open-source NGSPICE simulator using the SKY130 transistor models; the dual-gate device is modeled as two coupled MOSFETs sharing a common source/drain (the epitaxial layer), with a coupling capacitance Cgg = 0.5 fF. The complete flow — schematic capture, layout, DRC, LVS, PEX, and simulation — runs on open-source EDA (OpenROAD/OpenLane, Magic, KLayout, Netgen) with no proprietary tools. Because SKY130 is a fully documented, freely downloadable open standard, the combination of (anchor-patent method) + (SKY130 PDK layers and rules) is an enabling disclosure that any PHOSITA could reproduce at a commercial foundry (SkyWater's MPW shuttle).

flowchart LR
    A["SKY130 open PDK (Apache 2.0)"] --> B["DG_LV dual-gate standard cell"]
    C["Open EDA: Magic + KLayout + OpenROAD"] --> B
    D["DRC deck extension: SLOT layer rules"] --> B
    E["NGSPICE dual-gate coupled model (Cgg 0.5 fF)"] --> B
    B --> F["Layout: epitaxy region + SLOT overlap enforced by DRC"]
    F --> G["Tape-out via SkyWater MPW shuttle"]
    G --> H["Silicon: post-epitaxy slot -> two gates"]

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Scenario C2 — Combination with OpenROAD/OpenLane and KLayout DRC Deck

Enabling Description:

The slot-after-epitaxy process is integrated into the OpenLane automated RTL-to-GDSII flow (built on OpenROAD, KLayout, Magic, and Yosys). A new open-source tool module, "SlotGen," is described: after standard-cell placement and routing, SlotGen performs a post-route gate-splitting pass that (i) identifies long gate patterns (length > 5 µm) in the netlist; (ii) inserts a slot (per the anchor patent's second photo-etching process) at the midpoint over the STI, splitting the gate into two series-connected gate segments; and (iii) verifies that the epitaxial-layer (S/D) geometry was defined before the slot in the process-flow order — implemented as a KLayout DRC deck with a "flow-order rule" (a Boolean check that the SLOT layer does not intersect the EPI layer's exclusion zones, mimicking the process sequence). The SlotGen module also generates the mask-synthesis recipe (a JSON recipe file consumed by the etch tool's SECS/GEM interface — see Scenario C4): etch chemistry, bias power, endpoint wavelength, and expected CD. The open-source nature of OpenLane (Apache 2.0) and KLayout (GPL) means the combination is publicly reproducible: a PHOSITA can download the tools, run the SlotGen pass on the open "Rocket" or "Ibex" RISC-V core (Scenario C3), and generate a slot-bearing GDSII that is DRC-clean against the extended deck. This scenario discloses the design-automation embodiment of the anchor claim: the second photo-etching process is not just a mask step but a synthesizable, verifiable, open-source EDA feature.

flowchart TD
    A["RTL (RISC-V Ibex/Rocket)"] --> B["Yosys synthesis"]
    B --> C["OpenROAD place & route"]
    C --> D["SlotGen post-route gate-splitting pass"]
    D --> E["Identify long gates > 5 um"]
    E --> F["Insert slot at midpoint over STI"]
    F --> G["KLayout DRC: flow-order rule (SLOT vs EPI exclusion)"]
    G --> H{"DRC clean?"}
    H -->|"Yes"| I["GDSII + JSON etch recipe (SECS/GEM)"]
    H -->|"No"| J["Auto-fix: shift slot / adjust geometry"]
    J --> F
    I --> K["Tape-out"]

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Scenario C3 — Combination with Open-Source RISC-V Hardware (SRAM Bitcell and I/O)

Enabling Description:

The dual-gate slot device is integrated into open-source RISC-V processor hardware (e.g., the lowRISC Ibex core, the SiFive Freedom E310, or the OpenTitan secure element — all with open RTL and open PDKs). Two concrete integrations: (a) SRAM bitcell — the 6T SRAM bitcell's pass-gate transistors are replaced with slot-separated dual-gate transistors, where Gate A is driven by the word-line (WL) and Gate B is connected to a write-assist line (a low-voltage write-assist scheme that reduces the minimum write voltage VDD_min by 120 mV). The dual-gate pass transistor uses the same epitaxial source/drain (SiGe for pFET access in a read-optimized cell); the slot is formed after epitaxy per the anchor method. (b) I/O pad — the ESD protection network of the RISC-V chip's I/O pads uses the fuse variant (Derivative 5.1): the slot's residual polysilicon bridge acts as a programmable fuse that opens on ESD overcurrent, protecting the core logic. The integration is fully open: the RTL modifications are committed to the open RISC-V repositories, the layout is generated with OpenLane (Scenario C2), and the resulting GDSII is manufacturable on the SKY130 open PDK (Scenario C1). The combination discloses that the anchor patent's method is not limited to standalone transistors but is a system-level design technique for open-source processors: any PHOSITA building a RISC-V SoC on an open PDK, facing SRAM write-assist or ESD challenges, would be motivated to adopt the dual-gate slot device.

flowchart TD
    A["Open RISC-V SoC (Ibex / OpenTitan)"] --> B["SRAM macro: 6T bitcell with dual-gate pass gate"]
    B --> C["Gate A = word-line (WL)"]
    B --> D["Gate B = write-assist line (VDD_min -120 mV)"]
    A --> E["I/O pad: ESD network with fuse-variant slot bridge"]
    E --> F["Residual bridge opens on ESD > 10 mA"]
    F --> G["Core logic protected (fail-open)"]
    C --> H["Read/write access with write assist"]
    D --> H
    H --> I["Synthesized with OpenLane + SKY130"]
    I --> J["Open GDSII commit to RISC-V repos"]

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Scenario C4 — Combination with SEMI Open Standards (SECS/GEM, E10, E30, E37)

Enabling Description:

The slot-formation process control is integrated with the SEMI open communication and data standards — SECS-I/HSMS (SEMI E4/E37), GEM (SEMI E30), equipment data acquisition (SEMI E10/E58), and the recipe-management standard (SEMI E120). The derivative discloses a standard-compliant process-control recipe object ("SLOT_ETCH_PROC") that encodes the anchor patent's post-epitaxy slotting step as a machine-readable, tool-agnostic recipe: the recipe object contains (i) the etch-chamber parameter set (ICP/bias power, pressure, gas flows, chuck temperature); (ii) the OES endpoint condition (Si*/F* ratio threshold and the SiGe PL confirmatory signal from Derivative 4.2); (iii) the SECS/GEM event sequence (e.g., event SLOT_ETCH_START, SLOT_ETCH_ENDPOINT_DETECTED, SLOT_ETCH_COMPLETE); (iv) the data-collection plan (trace variables at 100 ms sampling per SEMI E58); and (v) the alarm/exception handling (recipe-abort on CD excursion beyond ±10%, with a carrier-held alarm per SEMI E10). Because these are open standards, any equipment vendor's etch tool that implements SECS/GEM can consume the recipe object directly, and any fab's MES (which already implements SEMI E10/E30/E58) can log, track, and report the slot-etch process without custom integration. The disclosure further specifies a recipe-parameter public schema (JSON Schema or XML per SEMI E120) that makes the slot-etch recipe portable across fabs and tools — eliminating tool-to-tool recipe-transfer engineering. The combination of (anchor-patent method) + (SEMI open standards) is an enabling, standards-based disclosure: a PHOSITA implementing the slot-etch step on any GEM-compliant tool would be practicing this combination as a matter of routine equipment engineering.

sequenceDiagram
    participant MES as Fab MES (SEMI E10/E30/E58)
    participant Tool as Etch tool (SECS/GEM - SEMI E37/E30)
    participant RC as SLOT_ETCH_PROC recipe object (SEMI E120)
    participant OES as OES endpoint system
    MES->>RC: Download recipe (tool-agnostic schema)
    RC->>Tool: Apply chamber parameters + event map
    Tool->>OES: Begin slot etch (event SLOT_ETCH_START)
    OES->>Tool: Si*/F* ratio threshold met (+/- 0.5 s)
    OES->>Tool: SiGe PL confirmatory signal (epi intact)
    Tool->>MES: Event SLOT_ETCH_ENDPOINT_DETECTED
    Tool->>MES: Trace data (100 ms sampling, SEMI E58)
    MES->>MES: SPC charting + alarm handling (SEMI E10)
    Tool->>MES: Event SLOT_ETCH_COMPLETE (wafer released)

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CLAIM-ELEMENT MAPPING SUMMARY (for the defensive-publishing file wrapper)

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PUBLICATION AND EVIDENCE-OF-DISCLOSURE INSTRUCTIONS

1. Publish immediately via a dated, third-party-verifiable channel: (a) arXiv (CS/EE category) preprint, (b) a defensive publication server (e.g., IP.com, Research Disclosure, or the IEEE Xplore preprint server), and (c) a blockchain timestamp (e.g., OpenTimestamps or a public PoW chain) anchoring a hash of this document to the 2026-04-26 date. The blockchain anchor (Derivative 4.3's ledger technique applied to this disclosure itself) provides immutable priority evidence under § 102(a)(1) against later-filed competitor applications.
2. Preserve enabling detail: each derivative above is written to the "reduce to practice without undue experimentation" standard (MPEP 2163 / 35 U.S.C. § 112(a)). Avoid redacting the process parameters (temperatures, chemistries, dimensions, doses) — they are the enabling core.
3. Cross-file the disclosure with the patent file wrapper of US9093473B2 and the related family member US8816409B2, and with the PTAB record of IPR2025-00879 (TSMC et al. v. Marlin Semiconductor Ltd., not instituted), so that the examiner and any future tribunal can locate this publication.
4. Track the pending reexamination (recorded 2026-03-10, "RR — Request for reexamination filed," effective 2025-12-03) and the ITC investigation 337-TA-1443 (evidentiary hearing scheduled 2026-02-02); this disclosure's derivatives are drafted to be valid prior art regardless of the outcome of those proceedings, because they are independent publications describing embodiments beyond the anchor patent's claims.

End of Defensive Disclosure — DF-9093473-2026-0426. All derivative embodiments are disclosed for prior-art purposes; no rights are reserved in the disclosed subject matter beyond the publication itself.