US 8549339

An analysis of United States Patent 8,549,339 reveals a technology focused on managing power and communication in multi-core processors, which has been the subject of significant litigation.

Summary of U.S. Patent 8,549,339

• Title: Processor core communication in multi-core processor
• Assignee: The current assignee is Redstone Logics LLC. The original assignee was Empire Technology Development LLC.
• Inventors: Andrew Wolfe, Marc Elliot Levitt
• Filing Date: February 26, 2010
• Issue Date: October 1, 2013
• Abstract: The patent describes techniques for handling communication between processor cores in a multi-core processor. The processor includes a first set of cores in one region that dynamically receive a first supply voltage and clock signal, and a second set of cores in another region that dynamically receive a second supply voltage and clock signal. An interface block is coupled to both sets of cores to facilitate communication between them.

Plain-Language Overview of Independent Claims

U.S. Patent 8,549,339 has three independent claims: 1, 15, and 21.

• Claim 1: This claim describes a multi-core processor with at least two groups of processor cores. Each group of cores receives its own independent power supply voltage and its own independent clock signal that is managed by a phase lock loop (PLL). A special "interface block" connects these two groups of cores, allowing them to communicate with each other.

• Claim 15: This claim outlines a method for managing communications within a multi-core processor that has different groups of processor cores. When a request to change the clock frequency for one group of cores is made, communications between that group and another group are temporarily paused. Communications are resumed only after it's confirmed that the clock signals for both groups of cores are stable. This prevents errors that could occur from the temporary instability of a changing clock signal.

• Claim 21: This claim is very similar to claim 1, describing a multi-core processor with two sets of cores, each with its own independent supply voltage from a power control block and its own independent clock signal from a clock control block. It also specifies an "interface block" to handle communication between these two sets of cores.

Litigation Involving U.S. Patent 8,549,339

As of early 2026, U.S. Patent 8,549,339 has been actively litigated by its current owner, Redstone Logics LLC, against several major technology companies. Cases have been filed in the Western and Eastern Districts of Texas against defendants including MediaTek, NXP Semiconductors, Samsung, AMD, Apple, and NVIDIA.

The lawsuits generally allege that the companies' multi-core processors, which often use architectures like ARM big.LITTLE or DynamIQ Shared Unit, infringe on the patent's claims for managing separate power and clock domains for different sets of processor cores. Some of these legal disputes have been resolved, with court records indicating a settlement in the case against NXP Semiconductors and a notice of resolution in the case against MediaTek.

No specific dockets for US patent 8,549,339 were found in a search of the U.S. Court of Appeals for the Federal Circuit (CAFC) for 2026, suggesting that any appeals from the district court cases may not have reached that stage or were not filed under this specific patent number within that timeframe.