Prior art

To the Senior US Patent Analyst,

The following is an analysis of the prior art cited in US Patent 8,549,339, titled "Processor core communication in multi-core processor." This analysis is based on the patent's own cited references and an understanding of 35 U.S.C. § 102 regarding novelty and anticipation.

Analysis of Prior Art for US Patent 8,549,339

Subject Patent:

• Patent Number: 8,549,339
• Title: Processor core communication in multi-core processor
• Filing Date: February 26, 2010
• Issue Date: October 1, 2013
• Assignee: Empire Technology Development LLC.

Summary of the Invention:
US Patent 8,549,339 describes a multi-core processor architecture where different sets of processor cores can operate with independent and dynamically adjustable supply voltages and clock signals. The invention includes an interface block to facilitate communication between these different sets of cores. A key aspect is the management of this communication during changes in clock frequency, including idling and resuming communication based on the stability of phase-locked loops (PLLs) associated with the different clock domains.

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Cited Prior Art Analysis:

The following patents were cited as prior art during the prosecution of US Patent 8,549,339.

1. US Patent 6,711,447 B1

• Full Citation: US Patent 6,711,447 B1, "Modulating CPU frequency and voltage in a multi-core CPU architecture"
• Publication Date: March 23, 2004
• Filing Date: January 22, 2003
• Brief Description: This patent discloses a method for modulating the frequency and voltage of individual CPUs in a multi-core architecture. It describes selecting a CPU to operate at a lower frequency and voltage to reduce power consumption, while other CPUs may operate at a higher performance level.
• Potential Anticipation of Claims: This reference appears to anticipate the general concept of having different processor cores operating at different voltages and frequencies. It could potentially anticipate the broader aspects of Claim 1 and Claim 21, which describe a first set of processor cores with a first supply voltage and clock signal and a second set with a second, independent supply voltage and clock signal. However, the '447 patent may not explicitly detail the "interface block" for communication or the specific PLL-based management technique for idling and resuming communication as recited in the dependent claims of the '339 patent.

2. US Patent 7,219,245 B1

• Full Citation: US Patent 7,219,245 B1, "Adaptive CPU clock management"
• Publication Date: May 15, 2007
• Filing Date: June 3, 2004
• Brief Description: This patent describes a system for adaptively managing the clock frequency of a CPU based on workload. It includes monitoring CPU activity and adjusting the clock frequency to balance performance and power consumption.
• Potential Anticipation of Claims: The '245 patent teaches dynamic frequency scaling, which is a component of the '339 patent's invention. It could be argued to anticipate the concept of dynamically receiving a clock signal as mentioned in Claim 1 and Claim 21. However, it appears to focus on a single CPU's clock management rather than the communication and synchronization between multiple cores operating in independent clock domains, which is a central element of the '339 patent's claims.

3. US Patent 7,263,457 B2

• Full Citation: US Patent 7,263,457 B2, "System and method for operating components of an integrated circuit at independent frequencies and/or voltages"
• Publication Date: August 28, 2007
• Filing Date: January 3, 2006
• Brief Description: This patent discloses a system where different components on a single integrated circuit can operate at independent frequencies and voltages. It addresses the challenges of communication between these different "voltage and frequency islands."
• Potential Anticipation of Claims: This patent is highly relevant as it describes the core concept of independent voltage and frequency domains on a chip. It likely anticipates the foundational elements of Claim 1 and Claim 21, which describe two sets of processor cores with independent supply voltages and clock signals. The '457 patent also discusses the need for communication between these domains, potentially touching upon the function of the "interface block" in the '339 patent. The novelty of the '339 patent would likely reside in the specific implementation of the interface block and the method of managing communication during frequency changes as detailed in claims like Claim 12, Claim 13, and Claim 15.

4. US Patent 7,853,808 B2

• Full Citation: US Patent 7,853,808 B2, "Independent processor voltage supply"
• Publication Date: December 14, 2010
• Filing Date: January 18, 2007
• Brief Description: This patent describes a multi-processor system where each processor has an independent voltage supply. This allows for individual control of the voltage to each processor to optimize power and performance.
• Potential Anticipation of Claims: This reference reinforces the concept of independent voltage domains for different processors, which is central to Claim 1 and Claim 21 of the '339 patent. While it focuses on independent voltage supplies, its teachings contribute to the general state of the art that the '339 patent builds upon. The inventive step of the '339 patent would likely be argued to be the combination of independent clock domains and the specific communication management protocol.

5. US Patent Application Publication 2009/0106576 A1

• Full Citation: US 2009/0106576 A1, "Methods and systems for digitally controlled multi-frequency clocking of multi-core processors"
• Publication Date: April 23, 2009
• Filing Date: October 17, 2007
• Brief Description: This application describes a multi-core processor where individual cores or groups of cores can be clocked at different frequencies. It discloses a digital control system for managing these multiple clock domains.
• Potential Anticipation of Claims: This is a significant piece of prior art. It teaches the use of multiple clock frequencies for different cores in a multi-core processor. This directly relates to the core concept of Claim 1 and Claim 21 of the '339 patent. The level of detail in this application regarding the control system for these clock domains could potentially anticipate some of the more specific claims of the '339 patent, depending on its disclosure of how communication is handled during frequency transitions.

6. US Patent Application Publication 2009/0138737 A1

• Full Citation: US 2009/0138737 A1, "Apparatus, method and program product for adaptive real-time power and performance optimization of multi-core processors"
• Publication Date: May 28, 2009
• Filing Date: November 28, 2007
• Brief Description: This application discloses a system for adaptively optimizing power and performance in a multi-core processor by adjusting operating parameters like voltage and frequency for individual cores based on real-time workload demands.
• Potential Anticipation of Claims: This reference further establishes the state of the art in dynamic voltage and frequency scaling (DVFS) for multi-core processors. It supports the environment in which the '339 invention operates. While it describes the dynamic adjustment of voltage and frequency, its focus is on the optimization algorithm rather than the specific hardware interface and communication protocol for synchronizing cores during these transitions, which is the focus of the '339 patent's claims, particularly Claim 15.

Conclusion

Based on the cited prior art, the general concept of having multiple processor cores operating in independent and dynamic voltage and frequency domains was well-established before the filing of US Patent 8,549,339. Patents such as US 7,263,457 B2 and patent application US 2009/0106576 A1 appear to disclose the fundamental architecture of separate voltage and clock domains for different sets of processor cores, which is a key element of the independent claims of the '339 patent.

The patentability of the claims in US 8,549,339 likely rests on the specific implementation of the interface block and the method for managing communications during clock frequency changes. Specifically, the novelty appears to be in the process of idling communications in response to a frequency change request and resuming them only after determining that the PLLs for the involved clock domains have acquired a lock, as detailed in claims 12, 13, and 15. The prior art references discuss the need for communication between different domains but do not appear to explicitly disclose this specific PLL-based synchronization method for managing transitions.

Therefore, while the broader independent claims may face challenges in light of the prior art, the dependent claims that recite the specific details of the communication management protocol are likely where the novelty of the invention lies.