Obviousness — US Patent 8549339

Obviousness Analysis of US Patent 8549339

I. Introduction

This analysis considers the obviousness of US Patent 8,549,339, titled "Processor core communication in multi-core processor," under 35 U.S.C. § 103. The patent, filed on February 26, 2010, describes a multi-core processor architecture where different sets of processor cores can operate with independent supply voltages and clock signals. This allows for more granular power management by tailoring the power profile of a "stripe" or region of cores to their specific computational demands. The invention also addresses the communication challenges that arise between these independently-powered and clocked regions, proposing the use of interface blocks with level shifters and synchronizers.

A person of ordinary skill in the art (POSA) at the time of the invention would have been a computer architect or electrical engineer with experience in microprocessor design, particularly in the areas of multi-core processors, power management techniques like dynamic voltage and frequency scaling (DVFS), and on-chip communication interfaces.

II. Summary of Independent Claims

The patent includes several independent claims, with Claim 1 and Claim 15 being representative of the core inventive concepts:

Claim 1 describes a multi-core processor with a first and second set of processor cores, each configured to dynamically receive an independent supply voltage and an independent clock signal (derived from a phase-locked loop or PLL). An interface block is included to facilitate communication between these two sets of cores.
Claim 15 outlines a method for managing communications in such a multi-core processor. It involves idling communications between the first and second sets of cores in response to a clock frequency change request for one set. Communications are resumed only after it's determined that the PLLs for both the requesting set of cores and the adjacent set have acquired a stable lock.

III. Analysis of Obviousness

The claims of the '339 patent are rendered obvious by a combination of prior art references that were publicly available before the February 26, 2010 priority date. The primary references for this analysis are:

US Patent 7,853,808 B2 (hereinafter '808 patent), titled "Independent processor voltage supply," filed on January 18, 2007. This patent explicitly discloses a multi-core processor where individual cores or groups of cores can be supplied with independent voltages. This allows for power savings by running cores at lower voltages when performance demands are low.
US Patent 7,263,457 B2 (hereinafter '457 patent), titled "System and method for operating components of an integrated circuit at independent frequencies and/or voltages," filed on January 3, 2006. This patent teaches a system where different functional blocks within an integrated circuit, including processor cores, can operate at independent frequencies and voltages. It also discusses the need for synchronization circuits for communication between these different clock domains.
US Patent Application Publication 2009/0106576 A1 (hereinafter '576 application), titled "Methods and systems for digitally controlled multi-frequency clocking of multi-core processors," filed on October 17, 2007. This application describes a multi-core processor where each core can have its own independently controlled clock frequency. It also discusses the use of PLLs to generate these clock signals and the need for communication protocols to handle data transfer between cores operating at different frequencies.
US Patent 6,711,447 B1 (hereinafter '447 patent), titled "Modulating CPU frequency and voltage in a multi-core CPU architecture," filed on January 22, 2003. This patent discloses a multi-core processor where the voltage and frequency of the cores can be dynamically adjusted in response to workload. It teaches that reducing voltage and frequency saves power.

IV. Motivation to Combine Prior Art

A person of ordinary skill in the art at the time of the invention would have been motivated to combine the teachings of these references for several reasons:

Power Efficiency: The overarching goal in microprocessor design at the time was to improve performance while managing power consumption. The '808 patent and the '447 patent both highlight the significant power savings that can be achieved by independently controlling the voltage supplies to different cores. The '457 patent and the '576 application extend this concept to independent frequency control. A POSA would have naturally sought to combine these techniques to create a more power-efficient multi-core processor.
Performance Optimization: The ability to independently control both voltage and frequency for different sets of cores, as suggested by the combination of the cited art, would allow for a more optimized balance between performance and power consumption. High-performance tasks could be assigned to cores running at high voltage and frequency, while less demanding tasks could be relegated to cores running in a lower power state.
Addressing Known Problems: The '457 patent and the '576 application both acknowledge the communication challenges that arise when different parts of a chip operate in different clock domains. They both propose the use of synchronization circuits and communication protocols to manage this. A POSA, when combining the teachings of independent voltage and frequency domains, would have recognized the need for such an interface and would have been motivated to implement a solution like the one described in the '339 patent. The use of level shifters to handle communication between different voltage domains was also a well-understood and standard practice in mixed-signal and multi-voltage domain chip design.

V. Mapping of Prior Art to Claims

Claim 1: The '808 patent teaches a first and second set of processor cores with independent supply voltages. The '457 patent and the '576 application teach independent clock signals for different cores, with the '576 application specifically mentioning the use of PLLs. The combination of these references directly discloses all the elements of Claim 1. The interface block for communication is a necessary and obvious component when combining these technologies, and its general function is taught by both the '457 and '576 references.
Claim 15: The '576 application discusses the need for a protocol to manage communication when clock frequencies change. The concept of idling communication during a transition period to avoid data corruption is a standard engineering practice when dealing with clock domain crossings. A POSA would have understood that before communication can be safely resumed, the new clock signal must be stable. The '576 application teaches the use of PLLs to generate the clock signals, and it was well known in the art that a PLL needs time to "lock" onto a new frequency. Therefore, the method of idling communication and waiting for the PLLs to lock, as described in Claim 15, would have been an obvious and logical implementation detail for a system combining the teachings of the prior art.

VI. Conclusion

The independent claims of US Patent 8,549,339 are rendered obvious by a combination of the '808, '457, '576, and '447 patents and patent applications. A person of ordinary skill in the art, motivated by the goals of improving power efficiency and performance in multi-core processors, would have found it obvious to combine the known techniques of independent voltage and frequency scaling for different sets of cores. The communication challenges that arise from such a combination were also well-understood, and the solutions proposed in the '339 patent—using interface blocks with level shifters and synchronizers, and a method of idling communication during frequency changes—were either explicitly taught by the prior art or would have been obvious and routine design choices for a skilled engineer. Therefore, the claims of US Patent 8,549,339 do not represent a patentable invention over the prior art.