US 8549339

An analysis of United States Patent 8,549,339 reveals a technology focused on managing power and communication in multi-core processors, which has been the subject of significant litigation.

Summary of U.S. Patent 8,549,339

• Title: Processor core communication in multi-core processor
• Assignee: The current assignee is Redstone Logics LLC. The original assignee was Empire Technology Development LLC.
• Inventors: Andrew Wolfe, Marc Elliot Levitt
• Filing Date: February 26, 2010
• Issue Date: October 1, 2013
• Abstract: The patent describes techniques for handling communication between processor cores in a multi-core processor. The processor includes a first set of cores in one region that dynamically receive a first supply voltage and clock signal, and a second set of cores in another region that dynamically receive a second supply voltage and clock signal. An interface block is coupled to both sets of cores to facilitate communication between them.

Plain-Language Overview of Independent Claims

U.S. Patent 8,549,339 has three independent claims: 1, 15, and 21.

• Claim 1: This claim describes a multi-core processor with at least two groups of processor cores. Each group of cores receives its own independent power supply voltage and its own independent clock signal that is managed by a phase lock loop (PLL). A special "interface block" connects these two groups of cores, allowing them to communicate with each other.

• Claim 15: This claim outlines a method for managing communications within a multi-core processor that has different groups of processor cores. When a request to change the clock frequency for one group of cores is made, communications between that group and another group are temporarily paused. Communications are resumed only after it's confirmed that the clock signals for both groups of cores are stable. This prevents errors that could occur from the temporary instability of a changing clock signal.

• Claim 21: This claim is very similar to claim 1, describing a multi-core processor with two sets of cores, each with its own independent supply voltage from a power control block and its own independent clock signal from a clock control block. It also specifies an "interface block" to handle communication between these two sets of cores.

Litigation Involving U.S. Patent 8,549,339

As of early 2026, U.S. Patent 8,549,339 has been actively litigated by its current owner, Redstone Logics LLC, against several major technology companies. Cases have been filed in the Western and Eastern Districts of Texas against defendants including MediaTek, NXP Semiconductors, Samsung, AMD, Apple, and NVIDIA.

The lawsuits generally allege that the companies' multi-core processors, which often use architectures like ARM big.LITTLE or DynamIQ Shared Unit, infringe on the patent's claims for managing separate power and clock domains for different sets of processor cores. Some of these legal disputes have been resolved, with court records indicating a settlement in the case against NXP Semiconductors and a notice of resolution in the case against MediaTek.

No specific dockets for US patent 8,549,339 were found in a search of the U.S. Court of Appeals for the Federal Circuit (CAFC) for 2026, suggesting that any appeals from the district court cases may not have reached that stage or were not filed under this specific patent number within that timeframe.

Redstone Logics LLC Asserts Patent 8,549,339 in Multiple Lawsuits Against Tech Giants

As of April 26, 2026, US Patent 8,549,339, titled "Processor core communication in multi-core processor," is the subject of multiple patent infringement lawsuits filed by plaintiff Redstone Logics LLC against several major technology companies. The patent, which describes a method for managing communication between processor cores with independent supply voltages and clock signals, has been asserted in various district courts and has also faced challenges at the Patent Trial and Appeal Board (PTAB).

Here is a summary of the known litigation involving US Patent 8,549,339:

District Court Litigation:

• Redstone Logics LLC v. NXP Semiconductors N.V., et al.

  • Plaintiff: Redstone Logics LLC
  • Defendants: NXP Semiconductors, N.V., NXP B.V., and NXP USA, Inc.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:24-cv-00028
  • Filing Date: January 2024
  • Outcome: The case was settled, and the plaintiff's claims were dismissed with prejudice in May 2025. NXP's counterclaims were dismissed without prejudice.

• Redstone Logics LLC v. MediaTek, Inc., et al.

  • Plaintiff: Redstone Logics LLC
  • Defendants: MediaTek, Inc. and MediaTek USA, Inc.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:24-cv-00029
  • Filing Date: January 26, 2024
  • Current Status: Active. A claim construction order was issued on February 21, 2025. The lawsuit alleges that MediaTek's products with DynamIQ Shared Unit architecture infringe the '339 patent.

• Redstone Logics LLC v. Qualcomm Inc., et al.

  • Plaintiff: Redstone Logics LLC
  • Defendants: Qualcomm Incorporated and Qualcomm Technologies, Inc.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:24-cv-00231
  • Filing Date: September 2024
  • Current Status: Active. The complaint targets Qualcomm products implementing DynamIQ Shared Unit or big.LITTLE architectures, such as the Snapdragon 8 Gen 2 and Snapdragon 835 Mobile Platform. The parties have filed a joint claim construction statement.

• Redstone Logics LLC v. Apple, Inc.

  • Plaintiff: Redstone Logics LLC
  • Defendant: Apple, Inc.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:25-cv-00183
  • Filing Date: 2025
  • Current Status: Active. On November 20, 2025, the court granted a joint motion to adopt prior claim constructions from the Redstone Logics LLC v. Qualcomm Inc. case.

• Redstone Logics LLC v. Advanced Micro Devices, Inc.

  • Plaintiff: Redstone Logics LLC
  • Defendant: Advanced Micro Devices, Inc.
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:2025cv00182
  • Filing Date: April 18, 2025
  • Current Status: Active.

Patent Trial and Appeal Board (PTAB) Proceedings:

In addition to the district court litigations, US Patent 8,549,339 has also been the subject of Inter Partes Review (IPR) petitions filed at the PTAB, seeking to invalidate the patent's claims.

• IPR2025-00085

  • Petitioner: MediaTek, Inc. and MediaTek USA, Inc.
  • Filing Date: October 22, 2024
  • Status: Pending.

• IPR2025-00485

  • Petitioners: NXP USA, Inc., Qualcomm Incorporated, Qualcomm Technologies, Inc., Freescale Semiconductor Holdings V, Inc., NXP B.V., and NXP Semiconductors N.V.
  • Filing Date: January 21, 2025
  • Status: Pending.

These proceedings indicate a concerted effort by the accused infringers to challenge the validity of the '339 patent. The outcomes of these IPRs could significantly impact the ongoing district court litigations.

Here is the analysis of AIA trial proceedings for US patent 8,549,339.

Proceedings overview

Three inter partes reviews (IPRs) have been filed against US patent 8,549,339, and the Patent Trial and Appeal Board (PTAB) has refused to institute a trial in all three instances. This means no claims have been invalidated or canceled via PTAB proceedings. For a defendant, this history significantly strengthens the patent's defensive posture, as it has survived multiple challenges, suggesting that obviousness and anticipation arguments may be difficult to advance successfully before the PTAB.

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IPR2025-01532 — [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Redstone Logics, LLC

• Type: Inter Partes Review
• Filed: 2025-09-16
• Status: Discretionary Denial — The PTAB declined to institute trial based on discretionary factors, not on the merits of the prior art arguments.
• Judge panel: Information on the judge panel is not publicly available in the denial order.
• Petition grounds: The petition challenged claims of US 8,549,339 based on prior art under 35 U.S.C. § 103 (obviousness).
• Institution decision: The Board exercised its discretion to deny institution on 2026-03-31. This was likely based on the Fintiv factors, which consider the advanced state of a parallel district court litigation involving the same patent and parties. In such cases, the Board often denies institution to avoid duplicative efforts and potentially conflicting outcomes with the district court.
• Final Written Decision: Not issued, as trial was not instituted.
• Settlement / termination: Not applicable.
• Appeal: Not applicable, as institution denial decisions are generally not appealable.
• Defensive value: This proceeding offers no direct defensive value from a prior art perspective, as the merits were not considered. It does signal that the patent owner, Redstone Logics, is actively litigating this patent in a forum that is proceeding quickly, making co-pending IPRs less likely to be instituted.

IPR2025-00485 — NXP USA, INC., et al. v. Redstone Logics, LLC

• Type: Inter Partes Review
• Filed: 2025-01-22
• Status: Not Instituted - Procedural — The PTAB denied institution for procedural reasons.
• Judge panel: Information not publicly available.
• Petition grounds: The petition asserted that certain claims of US 8,549,339 were unpatentable based on prior art. The full list of petitioners included NXP USA, INC., QUALCOMM INCORPORATED, QUALCOMM TECHNOLOGIES, INC., FREESCALE SEMICONDUCTOR HOLDINGS V, INC., NXP B.V., AND NXP SEMICONDUCTORS N.V.
• Institution decision: The trial was not instituted due to procedural deficiencies in the petition or a failure to meet statutory requirements for filing. This type of denial does not address the substance of the unpatentability arguments.
• Final Written Decision: Not issued.
• Settlement / termination: Not applicable.
• Appeal: Not applicable.
• Defensive value: This outcome provides little defensive value. It highlights the strict procedural requirements of the PTAB and does not preclude a future, properly filed petition on the same or different grounds, subject to time bars and other rules.

IPR2025-00085 — MediaTek, Inc. and MediaTek USA, Inc. v. Redstone Logics, LLC

• Type: Inter Partes Review
• Filed: 2024-10-22
• Status: Not Instituted - Merits — The PTAB denied institution because the petitioner failed to establish a reasonable likelihood of prevailing on the merits.
• Judge panel: Information not publicly available.
• Petition grounds: The petition argued that claims of US 8,549,339 were unpatentable as obvious under 35 U.S.C. § 103 over various prior art references.
• Institution decision: The Board concluded that the petitioner's arguments and evidence were not persuasive enough to meet the threshold for instituting a trial. This is a substantive decision indicating the asserted prior art combinations were not sufficient to demonstrate unpatentability.
• Final Written Decision: Not issued.
• Settlement / termination: Not applicable.
• Appeal: Not applicable.
• Defensive value: This is the most challenging outcome for a potential future defendant. The Board has already reviewed prior art arguments against the patent and found them unpersuasive. Any new petitioner would need to present substantially different and stronger arguments or prior art to have a chance at institution. This denial significantly hardens the patent against future PTAB challenges.

Strategic summary

All claims of US 8,549,339 remain valid and enforceable, as no claim has been canceled or amended through a PTAB trial. The patent has been challenged three times by sophisticated petitioners (Apple, NXP/Qualcomm, MediaTek), and each attempt to initiate a trial has failed. One petition was denied on the merits (IPR2025-00085), signaling the patent's resilience to obviousness challenges based on the art presented. The other two were denied on discretionary or procedural grounds, reflecting the patent owner's active litigation strategy.

From an estoppel perspective, because no Final Written Decisions were issued, the powerful statutory estoppel under 35 U.S.C. § 315(e)(2) does not apply to any of the petitioners. This means they are not barred from raising the same or other grounds in district court or in a future IPR. However, from a practical standpoint, any new petition would face a high bar. The Board is aware of the previous failed attempts, and the denial on the merits in IPR2025-00085 creates a significant headwind for any petitioner using similar art or arguments. The pattern of filings by major technology companies suggests the patent is being broadly asserted. The patent's original assignee was Empire Technology Development LLC, and the current assignee, Redstone Logics, LLC, appears to be an enforcement entity.

Recommended next steps

For a defendant facing an assertion of US 8,549,339, a validity challenge at the PTAB is a high-risk, uphill battle.

• Review the merits-based denial: Before considering a new IPR, a defendant must obtain and meticulously analyze the petition and the Decision Denying Institution in IPR2025-00085. This will reveal the arguments and prior art that the PTAB has already deemed insufficient. A new attack would require fundamentally different prior art that was not reasonably available during the search for the first IPR.
• Focus on District Court: Given the PTAB history, the primary focus for a defense should be in district court. The prior art from the failed IPRs can still be used, but the defendant should be prepared for the patent owner to argue that the PTAB's denial confirms the strength and validity of the patent.
• Monitor Active Proceedings: There are no active PTAB proceedings. The patent owner has successfully defended its patent at the institution phase, and future PTAB challenges appear unlikely to succeed without a novel invalidity theory. Any defense should be built around non-infringement or district court invalidity arguments.

Inventors

• Andrew Wolfe: No employer is listed on the patent.
• Marc Elliot Levitt: No employer is listed on the patent.

There are no unusual patterns immediately apparent from the inventor list alone.

Original assignee

The original assignee of US patent 8549339 is Empire Technology Development LLC. Empire Technology Development is a patent monetization firm, a subsidiary of Allied Inventors. It does not appear to have shipped any products embodying the claims of this patent. Its business model is acquiring patents and licensing them. The company is still in operation.

Assignment timeline

2010-02-11 (executed) / recorded 2010-03-02 — Reel 024009/0530

• Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
• Assignor: Andrew Wolfe; Marc Elliot Levitt
• Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
• Correspondent: Joseph M. Noto, The Marbury Law Group, PLLC, 11800 Sunrise Valley Drive 15th Floor, Reston, VA 20191
• Context: Standard assignment of invention from inventors to the acquiring company.

2018-12-28 (executed) / recorded 2019-01-29 — Reel 048373/0217

• Conveyance: SECURITY INTEREST
• Assignor: EMPIRE TECHNOLOGY DEVELOPMENT LLC
• Assignee: CRESTLINE DIRECT FINANCE, L.P.
• Correspondent: Michael T. O'Neill, Law Office of Michael T. O'Neill, PC, 5949 Sherry Lane, Suite 1030, Dallas, TX 75225
• Context: The patent was used as collateral in a securitization agreement, a common way for patent-holding companies to raise capital.

2022-12-12 (executed) / recorded 2022-12-16 — Reel 062120/0206

• Conveyance: RELEASE BY SECURED PARTY
• Assignor: CRESTLINE DIRECT FINANCE, L.P.
• Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
• Correspondent: Michael T. O'Neill, Law Office of Michael T. O'Neill, PC, 5949 Sherry Lane, Suite 1030, Dallas, TX 75225. This is the same correspondent from the prior security agreement.
• Context: The security interest was released, returning full control of the patent to Empire Technology Development LLC.

2022-12-12 (executed) / recorded 2023-08-14 — Reel 064575/0934

• Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
• Assignor: EMPIRE TECHNOLGY DEVELOPMENT, LLC
• Assignee: REDSTONE LOGICS, LLC
• Correspondent: Andrew G. Hamill, P.O. Box 630606, Houston, TX 77263
• Context: Transfer from the original patent monetization firm to a new entity, Redstone Logics, LLC, which has since initiated litigation.

Timeline diagram

timeline
    title Ownership of US 8549339
    2010 : Filed by inventors
         : Assigned to Empire Technology Development LLC
    2013 : Patent issued
    2019 : Security interest to Crestline Direct Finance
    2022 : Security interest released
         : Assigned to Redstone Logics LLC
    2023 : First infringement suit filed by Redstone Logics

NPE / troll-pattern signals

1. Shell-entity transfer — present. The final assignment is from Empire Technology Development LLC, a known monetization firm, to Redstone Logics, LLC (Reel 064575/0934). Redstone Logics, LLC was formed in Texas in December 2022, the same month as the assignment, and has no known products. Litigation records confirm it is an assertion entity.

2. Known asserter in the chain — present. Redstone Logics, LLC, the current assignee, is a known patent asserter. It began filing infringement lawsuits in October 2023. Unified Patents has identified Redstone Logics as an NPE and has filed an Inter Partes Review (IPR2025-00085) against this patent.

3. Repeat correspondent across the chain — present. Michael T. O'Neill of Dallas, TX, acted as the correspondent for both the security agreement to Crestline (Reel 048373/0217) and the release from Crestline (Reel 062120/0206), suggesting a consistent legal team managing the financial transactions for the patent-holding entity.

4. Cascading transfers — not present. The transfers are separated by several years.

5. Pre-litigation transfer — present. The assignment to Redstone Logics, LLC was executed on December 12, 2022 (recorded August 14, 2023). The first lawsuits asserting this patent were filed by Redstone Logics in October 2023, approximately 10 months after the transfer was executed. This fits the pattern of transferring a patent to a special-purpose assertion vehicle shortly before launching a litigation campaign.

6. Bankruptcy fire-sale — not present. There is no evidence of bankruptcy proceedings for any assignee in the chain.

7. Privateering — unclear. Empire Technology Development acquires patents from various sources, so it is not a classic case of an operating company spinning out patents to assert against its own competitors.

8. Defensive aggregator (anti-NPE) — not present. The patent has not been transferred to any known defensive aggregator.

Verdict

NPE — high confidence

The ownership chain shows a clear and deliberate transfer from one non-practicing entity (Empire Technology Development LLC) to a newly-formed LLC (Redstone Logics, LLC) for the explicit purpose of litigation. This is evidenced by the assignment to Redstone Logics (Reel 064575/0934) occurring less than a year before the first infringement lawsuits were filed. The current owner is a known asserter with no products, fitting the classic NPE model.

Verification of the assignment history can be performed at the USPTO Patent Assignment Search page.

To the Senior US Patent Analyst,

The following is an analysis of the prior art cited in US Patent 8,549,339, titled "Processor core communication in multi-core processor." This analysis is based on the patent's own cited references and an understanding of 35 U.S.C. § 102 regarding novelty and anticipation.

Analysis of Prior Art for US Patent 8,549,339

Subject Patent:

• Patent Number: 8,549,339
• Title: Processor core communication in multi-core processor
• Filing Date: February 26, 2010
• Issue Date: October 1, 2013
• Assignee: Empire Technology Development LLC.

Summary of the Invention:
US Patent 8,549,339 describes a multi-core processor architecture where different sets of processor cores can operate with independent and dynamically adjustable supply voltages and clock signals. The invention includes an interface block to facilitate communication between these different sets of cores. A key aspect is the management of this communication during changes in clock frequency, including idling and resuming communication based on the stability of phase-locked loops (PLLs) associated with the different clock domains.

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Cited Prior Art Analysis:

The following patents were cited as prior art during the prosecution of US Patent 8,549,339.

1. US Patent 6,711,447 B1

• Full Citation: US Patent 6,711,447 B1, "Modulating CPU frequency and voltage in a multi-core CPU architecture"
• Publication Date: March 23, 2004
• Filing Date: January 22, 2003
• Brief Description: This patent discloses a method for modulating the frequency and voltage of individual CPUs in a multi-core architecture. It describes selecting a CPU to operate at a lower frequency and voltage to reduce power consumption, while other CPUs may operate at a higher performance level.
• Potential Anticipation of Claims: This reference appears to anticipate the general concept of having different processor cores operating at different voltages and frequencies. It could potentially anticipate the broader aspects of Claim 1 and Claim 21, which describe a first set of processor cores with a first supply voltage and clock signal and a second set with a second, independent supply voltage and clock signal. However, the '447 patent may not explicitly detail the "interface block" for communication or the specific PLL-based management technique for idling and resuming communication as recited in the dependent claims of the '339 patent.

2. US Patent 7,219,245 B1

• Full Citation: US Patent 7,219,245 B1, "Adaptive CPU clock management"
• Publication Date: May 15, 2007
• Filing Date: June 3, 2004
• Brief Description: This patent describes a system for adaptively managing the clock frequency of a CPU based on workload. It includes monitoring CPU activity and adjusting the clock frequency to balance performance and power consumption.
• Potential Anticipation of Claims: The '245 patent teaches dynamic frequency scaling, which is a component of the '339 patent's invention. It could be argued to anticipate the concept of dynamically receiving a clock signal as mentioned in Claim 1 and Claim 21. However, it appears to focus on a single CPU's clock management rather than the communication and synchronization between multiple cores operating in independent clock domains, which is a central element of the '339 patent's claims.

3. US Patent 7,263,457 B2

• Full Citation: US Patent 7,263,457 B2, "System and method for operating components of an integrated circuit at independent frequencies and/or voltages"
• Publication Date: August 28, 2007
• Filing Date: January 3, 2006
• Brief Description: This patent discloses a system where different components on a single integrated circuit can operate at independent frequencies and voltages. It addresses the challenges of communication between these different "voltage and frequency islands."
• Potential Anticipation of Claims: This patent is highly relevant as it describes the core concept of independent voltage and frequency domains on a chip. It likely anticipates the foundational elements of Claim 1 and Claim 21, which describe two sets of processor cores with independent supply voltages and clock signals. The '457 patent also discusses the need for communication between these domains, potentially touching upon the function of the "interface block" in the '339 patent. The novelty of the '339 patent would likely reside in the specific implementation of the interface block and the method of managing communication during frequency changes as detailed in claims like Claim 12, Claim 13, and Claim 15.

4. US Patent 7,853,808 B2

• Full Citation: US Patent 7,853,808 B2, "Independent processor voltage supply"
• Publication Date: December 14, 2010
• Filing Date: January 18, 2007
• Brief Description: This patent describes a multi-processor system where each processor has an independent voltage supply. This allows for individual control of the voltage to each processor to optimize power and performance.
• Potential Anticipation of Claims: This reference reinforces the concept of independent voltage domains for different processors, which is central to Claim 1 and Claim 21 of the '339 patent. While it focuses on independent voltage supplies, its teachings contribute to the general state of the art that the '339 patent builds upon. The inventive step of the '339 patent would likely be argued to be the combination of independent clock domains and the specific communication management protocol.

5. US Patent Application Publication 2009/0106576 A1

• Full Citation: US 2009/0106576 A1, "Methods and systems for digitally controlled multi-frequency clocking of multi-core processors"
• Publication Date: April 23, 2009
• Filing Date: October 17, 2007
• Brief Description: This application describes a multi-core processor where individual cores or groups of cores can be clocked at different frequencies. It discloses a digital control system for managing these multiple clock domains.
• Potential Anticipation of Claims: This is a significant piece of prior art. It teaches the use of multiple clock frequencies for different cores in a multi-core processor. This directly relates to the core concept of Claim 1 and Claim 21 of the '339 patent. The level of detail in this application regarding the control system for these clock domains could potentially anticipate some of the more specific claims of the '339 patent, depending on its disclosure of how communication is handled during frequency transitions.

6. US Patent Application Publication 2009/0138737 A1

• Full Citation: US 2009/0138737 A1, "Apparatus, method and program product for adaptive real-time power and performance optimization of multi-core processors"
• Publication Date: May 28, 2009
• Filing Date: November 28, 2007
• Brief Description: This application discloses a system for adaptively optimizing power and performance in a multi-core processor by adjusting operating parameters like voltage and frequency for individual cores based on real-time workload demands.
• Potential Anticipation of Claims: This reference further establishes the state of the art in dynamic voltage and frequency scaling (DVFS) for multi-core processors. It supports the environment in which the '339 invention operates. While it describes the dynamic adjustment of voltage and frequency, its focus is on the optimization algorithm rather than the specific hardware interface and communication protocol for synchronizing cores during these transitions, which is the focus of the '339 patent's claims, particularly Claim 15.

Conclusion

Based on the cited prior art, the general concept of having multiple processor cores operating in independent and dynamic voltage and frequency domains was well-established before the filing of US Patent 8,549,339. Patents such as US 7,263,457 B2 and patent application US 2009/0106576 A1 appear to disclose the fundamental architecture of separate voltage and clock domains for different sets of processor cores, which is a key element of the independent claims of the '339 patent.

The patentability of the claims in US 8,549,339 likely rests on the specific implementation of the interface block and the method for managing communications during clock frequency changes. Specifically, the novelty appears to be in the process of idling communications in response to a frequency change request and resuming them only after determining that the PLLs for the involved clock domains have acquired a lock, as detailed in claims 12, 13, and 15. The prior art references discuss the need for communication between different domains but do not appear to explicitly disclose this specific PLL-based synchronization method for managing transitions.

Therefore, while the broader independent claims may face challenges in light of the prior art, the dependent claims that recite the specific details of the communication management protocol are likely where the novelty of the invention lies.

Obviousness Analysis of US Patent 8549339

I. Introduction

This analysis considers the obviousness of US Patent 8,549,339, titled "Processor core communication in multi-core processor," under 35 U.S.C. § 103. The patent, filed on February 26, 2010, describes a multi-core processor architecture where different sets of processor cores can operate with independent supply voltages and clock signals. This allows for more granular power management by tailoring the power profile of a "stripe" or region of cores to their specific computational demands. The invention also addresses the communication challenges that arise between these independently-powered and clocked regions, proposing the use of interface blocks with level shifters and synchronizers.

A person of ordinary skill in the art (POSA) at the time of the invention would have been a computer architect or electrical engineer with experience in microprocessor design, particularly in the areas of multi-core processors, power management techniques like dynamic voltage and frequency scaling (DVFS), and on-chip communication interfaces.

II. Summary of Independent Claims

The patent includes several independent claims, with Claim 1 and Claim 15 being representative of the core inventive concepts:

• Claim 1 describes a multi-core processor with a first and second set of processor cores, each configured to dynamically receive an independent supply voltage and an independent clock signal (derived from a phase-locked loop or PLL). An interface block is included to facilitate communication between these two sets of cores.

• Claim 15 outlines a method for managing communications in such a multi-core processor. It involves idling communications between the first and second sets of cores in response to a clock frequency change request for one set. Communications are resumed only after it's determined that the PLLs for both the requesting set of cores and the adjacent set have acquired a stable lock.

III. Analysis of Obviousness

The claims of the '339 patent are rendered obvious by a combination of prior art references that were publicly available before the February 26, 2010 priority date. The primary references for this analysis are:

• US Patent 7,853,808 B2 (hereinafter '808 patent), titled "Independent processor voltage supply," filed on January 18, 2007. This patent explicitly discloses a multi-core processor where individual cores or groups of cores can be supplied with independent voltages. This allows for power savings by running cores at lower voltages when performance demands are low.

• US Patent 7,263,457 B2 (hereinafter '457 patent), titled "System and method for operating components of an integrated circuit at independent frequencies and/or voltages," filed on January 3, 2006. This patent teaches a system where different functional blocks within an integrated circuit, including processor cores, can operate at independent frequencies and voltages. It also discusses the need for synchronization circuits for communication between these different clock domains.

• US Patent Application Publication 2009/0106576 A1 (hereinafter '576 application), titled "Methods and systems for digitally controlled multi-frequency clocking of multi-core processors," filed on October 17, 2007. This application describes a multi-core processor where each core can have its own independently controlled clock frequency. It also discusses the use of PLLs to generate these clock signals and the need for communication protocols to handle data transfer between cores operating at different frequencies.

• US Patent 6,711,447 B1 (hereinafter '447 patent), titled "Modulating CPU frequency and voltage in a multi-core CPU architecture," filed on January 22, 2003. This patent discloses a multi-core processor where the voltage and frequency of the cores can be dynamically adjusted in response to workload. It teaches that reducing voltage and frequency saves power.

IV. Motivation to Combine Prior Art

A person of ordinary skill in the art at the time of the invention would have been motivated to combine the teachings of these references for several reasons:

• Power Efficiency: The overarching goal in microprocessor design at the time was to improve performance while managing power consumption. The '808 patent and the '447 patent both highlight the significant power savings that can be achieved by independently controlling the voltage supplies to different cores. The '457 patent and the '576 application extend this concept to independent frequency control. A POSA would have naturally sought to combine these techniques to create a more power-efficient multi-core processor.

• Performance Optimization: The ability to independently control both voltage and frequency for different sets of cores, as suggested by the combination of the cited art, would allow for a more optimized balance between performance and power consumption. High-performance tasks could be assigned to cores running at high voltage and frequency, while less demanding tasks could be relegated to cores running in a lower power state.

• Addressing Known Problems: The '457 patent and the '576 application both acknowledge the communication challenges that arise when different parts of a chip operate in different clock domains. They both propose the use of synchronization circuits and communication protocols to manage this. A POSA, when combining the teachings of independent voltage and frequency domains, would have recognized the need for such an interface and would have been motivated to implement a solution like the one described in the '339 patent. The use of level shifters to handle communication between different voltage domains was also a well-understood and standard practice in mixed-signal and multi-voltage domain chip design.

V. Mapping of Prior Art to Claims

• Claim 1: The '808 patent teaches a first and second set of processor cores with independent supply voltages. The '457 patent and the '576 application teach independent clock signals for different cores, with the '576 application specifically mentioning the use of PLLs. The combination of these references directly discloses all the elements of Claim 1. The interface block for communication is a necessary and obvious component when combining these technologies, and its general function is taught by both the '457 and '576 references.

• Claim 15: The '576 application discusses the need for a protocol to manage communication when clock frequencies change. The concept of idling communication during a transition period to avoid data corruption is a standard engineering practice when dealing with clock domain crossings. A POSA would have understood that before communication can be safely resumed, the new clock signal must be stable. The '576 application teaches the use of PLLs to generate the clock signals, and it was well known in the art that a PLL needs time to "lock" onto a new frequency. Therefore, the method of idling communication and waiting for the PLLs to lock, as described in Claim 15, would have been an obvious and logical implementation detail for a system combining the teachings of the prior art.

VI. Conclusion

The independent claims of US Patent 8,549,339 are rendered obvious by a combination of the '808, '457, '576, and '447 patents and patent applications. A person of ordinary skill in the art, motivated by the goals of improving power efficiency and performance in multi-core processors, would have found it obvious to combine the known techniques of independent voltage and frequency scaling for different sets of cores. The communication challenges that arise from such a combination were also well-understood, and the solutions proposed in the '339 patent—using interface blocks with level shifters and synchronizers, and a method of idling communication during frequency changes—were either explicitly taught by the prior art or would have been obvious and routine design choices for a skilled engineer. Therefore, the claims of US Patent 8,549,339 do not represent a patentable invention over the prior art.

Patent Term and Family Details for U.S. Patent 8,549,339

Projected Expiration Date: August 4, 2031

Based on a review of the United States Patent and Trademark Office (USPTO) records, U.S. Patent No. 8,549,339 has a projected expiration date of August 4, 2031. This date includes a Patent Term Adjustment (PTA).

The patent was filed on February 26, 2010, and granted on October 1, 2013. Without any adjustments, its term would typically end 20 years from the filing date, in February 2030. However, the USPTO has granted a PTA, extending the patent's life.

Continuity and Family Data:

U.S. Patent 8,549,339, which issued from application number 12/713,220, does not have any domestic parent or child applications, such as continuations or divisionals, in the United States.

However, the patent is part of a larger international patent family. The original U.S. application serves as the priority document for several foreign counterparts. These include:

• World Intellectual Property Organization (WIPO): WO2011106172A1
• China: CN102667744B
• Japan: JP5547820B2
• South Korea: KR101426341B1
• Germany: DE112011100695T5

The legal status of these international family members varies, with several listed as expired due to non-payment of fees or having been withdrawn.

There are no recorded Patent Term Extensions (PTE) for this patent under 35 U.S.C. § 156, which are typically granted for delays in regulatory review for products such as pharmaceuticals.

Here is a comprehensive Defensive Disclosure document generating derivative works from US Patent 8,549,339 to establish prior art against future incremental inventions.

Defensive Disclosure: Derivative Architectures and Methods for Heterogeneous Multi-Core Processors

Publication Date: May 13, 2026
Reference Patent: US 8549339 B2

This document discloses novel variations, applications, and integrations of the core technologies described in US Patent 8549339. The purpose of this disclosure is to place these derivative concepts into the public domain, thereby rendering them obvious or non-novel for the purposes of future patent prosecution.

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Axis 1: Material & Component Substitution

Derivative 1.1: Silicon-Photonics Interface Block

• Enabling Description: The electrical interface block (120, 200, 300) between processor core sets is replaced with a silicon-photonics interface. Each processor stripe (e.g., 112, 114) terminates its electrical signaling at an on-chip optical modulator (e.g., a Mach-Zehnder modulator). Data is transmitted via an on-chip silicon waveguide to an optical receiver (e.g., a germanium photodetector) integrated into the adjacent stripe. This substitution completely decouples the voltage domains, making electrical level shifters (202) unnecessary. Clock domain synchronization is achieved by embedding the source clock into the transmitted optical data (e.g., using a Manchester encoding scheme) and recovering it at the receiver using a clock-data recovery (CDR) circuit, which replaces the purely digital synchronizer (302). Power for the optical components is supplied by the respective voltage domain of each stripe.

• Mermaid Diagram:

  graph TD
      subgraph Stripe_A [Stripe A @ Vdd_A, Clock_A]
          CoreA1(Core A1) --> E_O_A{Electrical-to-Optical<br>Modulator};
      end
      subgraph Stripe_B [Stripe B @ Vdd_B, Clock_B]
          O_E_B{Optical-to-Electrical<br>Photodetector/CDR} --> CoreB1(Core B1);
      end
      E_O_A -- Optical Signal in Waveguide --> O_E_B;
  
      subgraph Interface_Block [Optical Interface Block]
          E_O_A;
          O_E_B;
      end
  
      style Stripe_A fill:#f9f,stroke:#333,stroke-width:2px
      style Stripe_B fill:#ccf,stroke:#333,stroke-width:2px
  

Derivative 1.2: GaN/SiC High-Power Core Integration

• Enabling Description: The multi-core processor is fabricated on a hybrid substrate. The first set of processor cores (e.g., high-performance cores) is implemented using Gallium Nitride (GaN) High-Electron-Mobility Transistors (HEMTs) to enable operation at extremely high frequencies (>10 GHz) and higher supply voltages (e.g., 5V). The second set of processor cores (e.g., efficiency cores) is implemented in standard low-power silicon CMOS (e.g., at 0.8V). The interface block must now handle a massive voltage differential. The level shifters (202) are implemented as a cascade of diode-based clamps and Schmitt triggers robust enough to translate the 5V GaN logic levels down to the 0.8V CMOS logic levels without latch-up or damage.

• Mermaid Diagram:

  sequenceDiagram
      participant GaN_Core as GaN Core Set<br>(5V Logic)
      participant Interface as Interface Block
      participant CMOS_Core as CMOS Core Set<br>(0.8V Logic)
  
      GaN_Core->>+Interface: Transmit High-Voltage Signal (5V)
      Interface->>Interface: Cascade Level Shifter (5V -> 2.5V -> 0.8V)
      Interface->>+CMOS_Core: Deliver Low-Voltage Signal (0.8V)
      CMOS_Core-->>-Interface: Acknowledge
      Interface-->>-GaN_Core: Acknowledge
  

Derivative 1.3: MEMS Resonator Clock Source

• Enabling Description: The per-stripe Phase-Locked Loops (PLLs) are replaced by Micro-Electro-Mechanical System (MEMS) resonators. Each stripe (112, 114) has its own tunable MEMS resonator coupled with a driver circuit. A frequency change request (as in Claim 15) is serviced by applying a new DC bias voltage to the MEMS structure, which changes its resonant frequency. The "lock acquisition" step (408) is replaced by a "frequency stabilization" check, where the output frequency from the MEMS driver is compared against a reference using a digital frequency counter until the drift is below a specified tolerance (e.g., 10 ppm). This component substitution offers higher Q-factor and lower phase noise compared to traditional LC-tank PLLs.

• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Stable_FreqA
      Stable_FreqA --> Changing_Freq: Receive Freq Change Request
      Changing_Freq --> Stable_FreqB: Bias voltage applied, resonator settles
      state Changing_Freq {
          direction LR
          [*] --> Applying_Bias
          Applying_Bias --> Measuring_Drift: New DC Bias applied to MEMS
          Measuring_Drift --> Measuring_Drift: Drift > 10 ppm
          Measuring_Drift --> Freq_Stable: Drift <= 10 ppm
          Freq_Stable --> [*]
      }
      Stable_FreqB --> [*]
  

---

Axis 2: Operational Parameter Expansion

Derivative 2.1: Wafer-Scale Implementation

• Enabling Description: The technology is applied to a Wafer-Scale Engine (WSE). The "stripes" are entire silicon reticles, each containing hundreds of cores. Each reticle operates on an independently supplied voltage and is clocked by a unique, wafer-region-specific clock tree. The "interface block" is the physical boundary logic between adjacent reticles, handling communication across the scribe lines. The method of idling communication (Claim 15) is critical, as an entire reticle can be powered down or have its frequency changed for yield management (to disable a faulty reticle) or to create a specialized high-performance zone on one part of the wafer. The transition processing routine (308) is managed by a dedicated controller located at the center of the wafer.

• Mermaid Diagram:

  graph TD
      subgraph Wafer
          R1(Reticle 1<br>Vdd_A, Clock_A)
          R2(Reticle 2<br>Vdd_B, Clock_B)
          R3(Reticle 3<br>Vdd_C, Clock_C)
          R4(Reticle 4<br>Vdd_D, Clock_D)
          R1 <-->|Interface Logic| R2
          R1 <-->|Interface Logic| R3
          R2 <-->|Interface Logic| R4
          R3 <-->|Interface Logic| R4
      end
      WaferControl(Wafer-Scale Controller) -.-> R1
      WaferControl -.-> R2
      WaferControl -.-> R3
      WaferControl -.-> R4
  
      style R1 fill:#d5f,stroke:#333
      style R2 fill:#d5f,stroke:#333
      style R3 fill:#d5f,stroke:#333
      style R4 fill:#d5f,stroke:#333
  

Derivative 2.2: Cryogenic Quantum Controller Application

• Enabling Description: The processor is designed to control a qubit array in a dilution refrigerator. A first set of cores operates at the 4K stage of the cryostat, handling high-level quantum algorithm compilation and scheduling. A second set of cores operates at the 50mK stage, directly adjacent to the qubits, and is responsible for generating low-level microwave control pulses. The two sets operate at vastly different voltages and clock speeds due to the thermal and material property differences. The interface block uses superconducting single-flux quantum (SFQ) logic to transfer data with minimal heat dissipation. The method of Claim 15 is used when recalibrating the qubits, which requires changing the microwave pulse frequency, forcing the 50mK cores to change their clock, idle the SFQ interface, and re-stabilize before continuing the experiment.

• Mermaid Diagram:

  graph LR
      subgraph 4K_Stage [4K Stage]
          ControlCores(Control Core Set<br>Vdd_High, Clock_High)
      end
      subgraph 50mK_Stage [50mK Stage]
          PulseGenCores(Pulse Generation Cores<br>Vdd_Low, Clock_Low)
      end
      subgraph SFQ_Interface [Superconducting Interface]
          InterfaceLogic(SFQ Logic)
      end
      Qubits((Qubit Array))
  
      ControlCores --> InterfaceLogic
      InterfaceLogic --> PulseGenCores
      PulseGenCores --> Qubits
  

---

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Hypersonic Vehicle Flight Control

• Enabling Description: In a flight control computer for a hypersonic scramjet vehicle, the processor has two core sets. The "Atmospheric Flight" set runs at high voltage and clock frequency, processing thousands of sensor inputs per second from control surfaces. The "Guidance & Navigation" set runs at a lower voltage and frequency, handling GPS data and communication with ground control. The interface block is a radiation-hardened, fault-tolerant data bus. When the vehicle reaches a certain altitude and speed, the scramjet ignites, requiring the flight control system to enter a new operational mode. This triggers a frequency change request for the Atmospheric Flight cores. Communication with the Guidance cores is idled (Claim 15) for a few microseconds to ensure no corrupt data is passed during the transition, preventing catastrophic control failure.

• Mermaid Diagram:

  flowchart TD
      A[Start Flight] --> B{Altitude < 100k ft?};
      B -- Yes --> C[Run Atmospheric Cores @ High Power];
      C --> D{Process Sensor Data};
      D --> E[Interface with Guidance Cores];
      E --> B;
      B -- No --> F[Transition to Hypersonic Mode];
      F --> G[Request Freq Change for Atmo Cores];
      G --> H[Idle Interface to Guidance Cores];
      H --> I{Atmo Core PLL Locked?};
      I -- No --> I;
      I -- Yes --> J[Resume Interface];
      J --> K[Run Atmo Cores @ New Freq];
      K --> End;
  

Derivative 3.2: AgTech - Autonomous Vineyard Robot

• Enabling Description: An autonomous robot for monitoring grapevines uses a processor with a high-power core set for real-time stereoscopic computer vision (detecting disease, counting grapes) and motor control. A second, ultra-low-power core set handles long-range LoRaWAN communication and passive sensor monitoring (soil moisture, temperature). When the robot navigates from a sunlit row to a shaded row, the computer vision algorithm's required performance changes. The vision core set's clock frequency and voltage are reduced to save power. During this transition, the interface to the LoRaWAN core set is idled to prevent garbled telemetry data from being transmitted. The robot pauses for the milliseconds required for the PLL to re-lock before resuming its path.

• Mermaid Diagram:

  sequenceDiagram
      participant Vision as Vision Core Set (High Power)
      participant LoRa as LoRa Core Set (Low Power)
      participant Routine as Transition Routine
  
      loop Sunlight Navigation
          Vision->>Vision: Process High-Def Images
      end
      Note over Vision, LoRa: Robot enters shaded row
      Routine->>Vision: Request Clock Freq Decrease
      Routine->>Vision: IDLE communication link
      Routine->>LoRa: IDLE communication link
      par
          Vision->>Vision: Change PLL Frequency
      and
          LoRa->>LoRa: Buffer outgoing telemetry
      end
      Routine->>Vision: Wait for PLL lock signal
      Routine->>Vision: RESUME communication link
      Routine->>LoRa: RESUME communication link
      loop Shade Navigation
          Vision->>Vision: Process Low-Light Images
      end
  

---

Axis 4: Integration with Emerging Tech

Derivative 4.1: AI-Driven Predictive Power Management

• Enabling Description: The clock control block (110) and power control block (108) are managed by an on-chip Reinforcement Learning (RL) agent. The RL agent's state is defined by performance counters, thermal sensors, and instruction pipeline statistics from all core sets. Its action space is the set of possible voltage/frequency pairs for each stripe. The reward function is maximizing energy efficiency (performance per watt) while staying within a thermal design power (TDP) budget. The RL agent learns the workload patterns and predictively initiates frequency changes before they are demanded by the software. It also learns the precise settling time of each PLL, allowing it to minimize the communication idle time (Claim 15) to the physical minimum required for that specific transition.

• Mermaid Diagram:

  graph TD
      subgraph On-Chip_Fabric
          CoreSet_A(Core Set A) -- Telemetry --> RL_Agent;
          CoreSet_B(Core Set B) -- Telemetry --> RL_Agent;
          RL_Agent(RL Agent);
          PowerControl(Power Control Block)
          ClockControl(Clock Control Block)
          RL_Agent -- Action: V/F Pairs --> PowerControl;
          RL_Agent -- Action: V/F Pairs --> ClockControl;
          PowerControl -- Vdd_A/Vdd_B --> CoreSet_A & CoreSet_B;
          ClockControl -- Clock_A/Clock_B --> CoreSet_A & CoreSet_B;
      end
      style RL_Agent fill:#f96,stroke:#333
  

Derivative 4.2: IoT Sensor-Triggered Proactive Idling

• Enabling Description: The multi-core processor is integrated with a dense array of on-die IoT sensors, including voltage-droop monitors, thermal diodes, and current sensors. These sensors feed a real-time monitoring unit. If the monitor detects a voltage droop on Stripe A that exceeds a critical threshold, it preemptively triggers the "idle communication" step (404) between Stripe A and its neighbors before a clock or data error can occur. It then instructs the power control block to either increase Vdd_A or, if that fails, instructs a task scheduler to migrate the workload off Stripe A. Communication is only resumed after the sensor network confirms the supply voltage has stabilized. This turns the reactive method of Claim 15 into a proactive, fault-avoidance mechanism.

• Mermaid Diagram:

  stateDiagram-v2
      state "Normal Operation" as Normal
      [*] --> Normal
      Normal --> Proactive_Idle: Droop Sensor > Threshold
      Proactive_Idle --> Normal: Voltage Stabilized
      Proactive_Idle --> Fail_State: Voltage Fails to Stabilize
  
      state Proactive_Idle {
        description Idles interface, attempts Vdd correction
      }
  

---

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Graceful Degradation via Asynchronous Link

• Enabling Description: The interface block (300) is enhanced with a parallel, low-bandwidth, asynchronous serial link (e.g., a 2-wire I2C-like bus) in addition to the primary high-speed synchronous bus. When a clock frequency change is requested, the transition processing routine (308) does not completely "idle" communications. Instead, it disables the high-speed bus and enables the asynchronous link. This allows low-priority but critical information like heartbeats, status flags, or emergency commands to continue flowing between core sets during the PLL re-locking period. Once the new clock is stable, the asynchronous link is disabled and the high-speed bus is re-enabled, ensuring zero downtime for critical state awareness.

• Mermaid Diagram:

  sequenceDiagram
      autonumber
      participant A as Core A
      participant B as Core B
      participant IF as Interface Block
  
      A->>IF: High-speed Data
      IF->>B: High-speed Data
      Note over A,B: Freq Change Request
      IF->>IF: Disable High-Speed Bus
      IF->>IF: Enable Async Low-Speed Bus
      A-xIF: Low-speed Heartbeat
      IF-x>B: Low-speed Heartbeat
      Note over A,B: PLL Re-locks
      IF->>IF: Disable Async Low-Speed Bus
      IF->>IF: Enable High-Speed Bus
      A->>IF: High-speed Data
      IF->>B: High-speed Data
  

Derivative 5.2: Failsafe Permanent Idle Mode

• Enabling Description: A hardware watchdog timer is associated with each PLL. If a PLL fails to acquire a lock within a programmable time window after a frequency change command (as determined in step 408), the watchdog triggers a "permanent idle" state. The interface block tri-states all its outputs connected to the faulty core set's stripe. The transition routine then logs the error and signals the hypervisor or operating system to permanently de-schedule any tasks for that hardware region, effectively and safely removing the faulty stripe from the system's available resources without causing a system crash.

• Mermaid Diagram:

  flowchart TD
      Start(Freq Change Req) --> Idle(Idle Comms);
      Idle --> Change(Change PLL Freq);
      Change --> StartTimer(Start Watchdog Timer);
      StartTimer --> CheckLock{PLL Locked?};
      CheckLock -- Yes --> Resume(Resume Comms);
      Resume --> End(End);
      CheckLock -- No --> CheckTimer{Timer Expired?};
      CheckTimer -- No --> CheckLock;
      CheckTimer -- Yes --> FailSafe(Enter Permanent Idle);
      FailSafe --> Log(Log Error & Notify OS);
      Log --> End;
  

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Combination Prior Art Scenarios

1. With RISC-V TileLink: A multi-core processor based on the RISC-V ISA is architected with two distinct core clusters: a high-performance cluster of "BOOM" (Berkeley Out-of-Order Machine) cores and an efficiency cluster of "Rocket" cores. These clusters operate in separate voltage and frequency domains. They are interconnected using the open-standard TileLink cache-coherent bus. The "interface block" of Claim 1 is implemented as a TileLink-to-TileLink bridge that incorporates the necessary level-shifting and clock-domain-crossing (CDC) logic. The method of Claim 15 is executed by a dedicated management core when the operating system requests a performance state change for the BOOM cluster. The TileLink protocol's channel handshakes are used to "idle" the link by stalling new requests until a hardware signal confirms the BOOM cluster's new clock is stable.

2. With ARM AMBA AXI: The invention is applied to an ARM big.LITTLE system. The "first set of processor cores" is an ARM Cortex-A7x cluster (the "big" cores) and the "second set" is an ARM Cortex-A5x cluster (the "LITTLE" cores). These are in distinct voltage/frequency domains. The "interface block" is the AMBA AXI Coherent Hub (or a similar coherent interconnect fabric) that bridges the two clusters. This AXI fabric inherently contains the synchronizers (CDC logic) and logic to support the different power domains. A frequency change, managed by a Power Policy Unit (PPU), uses the AXI protocol's ability to "quiesce" traffic on specific channels. This quiescence corresponds to "idling communications" (Claim 15), and is maintained until the PPU receives a "PLL lock" confirmation from the target cluster's clock controller, after which it de-asserts the quiesce signal to "resume communications".

3. With OpenPOWER CAPI/OpenCAPI: The technology is embodied in a system using the Open Coherent Accelerator Processor Interface (OpenCAPI) standard. The "first set of cores" is a standard IBM POWER CPU core complex. The "second set of cores" is a field-programmable gate array (FPGA) acting as a hardware accelerator. The POWER CPU and the FPGA have completely independent power and clocking. The "interface block" is the physical layer (PHY) and link layer of the OpenCAPI interface itself, which is designed to handle communication between such disparate domains. The method of Claim 15 is used when the FPGA is partially reconfigured or its internal clock is changed to optimize for a new algorithm. The OpenCAPI link layer protocol is commanded to enter a low-power "retrain" state (the equivalent of "idling"), the FPGA PLL re-locks, and then the link is retrained and brought back to full operation ("resuming communications").