US 8076735

US Patent 8076735, titled "Semiconductor device with trench of various widths," was filed on October 2, 2009, and issued on December 13, 2011. The original assignee was United Microelectronics Corp., and the current assignee is [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) The inventor is Chun-Hsien Lin.

Abstract:
The patent describes a semiconductor device and a method for its fabrication. The method involves forming a polysilicon layer on a substrate, doping it with an N-type dopant, and then removing a portion to create dummy patterns. Each dummy pattern has a top, a bottom, and a neck between them, where the neck's width is narrower than the top's. A dielectric layer is then formed, covering the substrate between dummy patterns and exposing their tops. After removing the dummy patterns to create trenches in the dielectric layer, gate structures are formed in these trenches.

Plain-language overview of independent claims:

• Claim 1: This claim describes a semiconductor device comprising:
  • A substrate with a dielectric layer on it, where a trench is located within the dielectric layer.
  • A gate structure placed in the trench, which includes a high dielectric constant layer, a work function metal layer, and a metal layer, sequentially positioned on the substrate.
  • A source/drain region situated in the substrate on either side of the gate structure.
  • The trench itself has a specific shape: a top, a bottom, and a neck between them. The key feature is that the width of the neck is narrower than the width of the top, and the width of the neck is also narrower than or equal to the width of the bottom.

No specific CAFC 2026 dockets mentioning US patent 8076735 were found in the provided search results.

Known litigation involving US patent 8076735 is limited to a pending Inter Partes Review (IPR) case before the Patent Trial and Appeal Board (PTAB) of the U.S. Patent and Trademark Office.

Case Details:

• Case Number: IPR2026-00220
• Plaintiff(s) / Petitioner(s): Unified Patents
• Defendant(s) / Patent Owner(s): [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) (Inferred. Marlin Semiconductor Ltd. is the current assignee of US8076735, making them the likely patent owner in this IPR. However, this has not been explicitly confirmed by a litigation-specific source within the search results.)
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Filing Date: Not explicitly available in the provided search results.
• Outcome or Current Status: Pending

Proceedings overview

There is currently one active AIA trial proceeding on US Patent 8076735, an Inter Partes Review (IPR), IPR2026-00220. The proceeding is pending, meaning no claims have been invalidated or sustained yet. This gives a defendant limited immediate defensive posture based on PTAB outcomes, as the patent's claims remain currently enforceable.

IPR2026-00220 — Taiwan Semiconductor Manufacturing Company Ltd. v. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.)

• Type: Inter Partes Review
• Filed: 2026-01-16
• Status: Pending. The proceeding is ongoing and has not yet reached a final decision.
• Judge panel: Not yet publicly available.
• Petition grounds: Not yet publicly available. Details on specific claims, prior art, and statutory bases (§ 102 / § 103 / § 112) will become available after institution.
• Institution decision: Not yet issued. The deadline for the institution decision is typically six months from the filing date.
• Final Written Decision (if issued): Not applicable, as the proceeding is pending.
• Settlement / termination: Not applicable, as the proceeding is pending.
• Appeal: Not applicable, as the proceeding is pending.
• Defensive value: This proceeding is in its early stages. While it indicates a challenge to the patent's validity, no claims have been impacted yet. A defendant facing assertion of this patent should monitor this IPR closely, as a successful challenge could significantly weaken the patent owner's position.

Strategic summary

Currently, all claims of US8076735 are UNTESTED in a final PTAB decision, as the single IPR (IPR2026-00220) is still pending. No claims have been canceled or explicitly sustained by a Final Written Decision.

Regarding the estoppel landscape, if IPR2026-00220 proceeds to a Final Written Decision, § 315(e)(2) will bar the petitioner, Taiwan Semiconductor Manufacturing Company Ltd., and its privies from raising any ground that was raised or reasonably could have been raised in the IPR. For a defendant currently being asserted against, this means that if they are not in privy with the petitioner, they might still be able to use the same prior art or even different prior art in a new IPR, depending on the grounds ultimately instituted and decided upon in IPR2026-00220.

There are no apparent pattern signals of multiple IPRs filed by the same petitioner or aggressive PTAB appeals by the patent owner at this time, given that only one IPR is on file and it is still pending. The petitioner is Taiwan Semiconductor Manufacturing Company Ltd., a significant entity in the semiconductor industry.

Recommended next steps

If you are a defendant facing assertion of US8076735, your primary next step should be to closely monitor IPR2026-00220. Key upcoming milestones include the institution decision deadline (typically 6 months from the filing date of 2026-01-16, so around 2026-07-16), and, if instituted, the subsequent trial-stage milestones leading to a Final Written Decision within one year of institution. You can track its progress on the USPTO PTAB E2E system by searching for IPR2026-00220.

Inventors

The sole inventor listed for US Patent 8076735 is Chun-Hsien Lin. At the time of filing, Chun-Hsien Lin was employed by United Microelectronics Corp., as indicated by the original assignment of the patent rights from the inventor to United Microelectronics Corp. on September 18, 2009, prior to the patent's filing date [cite: Reel 023323/0944].

Original assignee

The original assignee named on the issued patent is United Microelectronics Corp. (UMC). UMC is a major global semiconductor foundry, meaning its primary line of business is manufacturing integrated circuits for fabless design companies. As a foundry, UMC ships products embodying semiconductor device claims as part of its manufacturing services. UMC is currently an operating company.

Assignment timeline

• 2009-09-18 (executed) / recorded 2009-10-02 — Reel 023323/0944
  • Conveyance: Assignment
  • Assignor: LIN, CHUN-HSIEN
  • Assignee: UNITED MICROELECTRONICS CORP.
  • Correspondent: WINSTON HSU, P.O. BOX 70, HSINCHU, TAIWAN (R.O.C.)
  • Context: Original assignment from the inventor to the initial corporate assignee.
• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292
  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED
  • Correspondent: DAVID G. RASMUSSEN, P.O. BOX 1069, SANDY, UT 84091. This correspondent has been noted on NPE assertion lists.
  • Context: Transfer of patent rights from an operating company to a new entity.

Timeline diagram

timeline
    title Ownership of US 8076735
    2009 : Inventor assigned to UMC
    2011 : Patent Issued
    2021 : UMC assigned to Marlin Semi

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from United Microelectronics Corp., a large operating semiconductor foundry, to Marlin Semiconductor Limited. Marlin Semiconductor Limited is identified by Unified Patents as a patent monetization entity. The transfer is recorded as Reel 056991/0292, executed 2021-06-18 and recorded 2021-07-26.
2. Known asserter in the chain — Present. Marlin Semiconductor Limited, the current assignee per Reel 056991/0292, is listed as a known Non-Practicing Entity (NPE) and high-frequency plaintiff by Unified Patents.
3. Repeat correspondent across the chain — Present. David G. Rasmussen, P.O. Box 1069, Sandy, UT 84091, is the correspondent for the 2021-07-26 assignment to Marlin Semiconductor Limited [cite: Reel 056991/0292]. Mr. Rasmussen's name has appeared as counsel for multiple NPEs on assertion lists, as tracked by organizations like Unified Patents.
4. Cascading transfers — Not present. There are only two assignments recorded post-issuance, and they are not in a rapid sequence between chained LLCs.
5. Pre-litigation transfer — Present. The patent was assigned to Marlin Semiconductor Limited on July 26, 2021 (recorded date) [cite: Reel 056991/0292]. Marlin Semiconductor Ltd. subsequently filed an infringement suit, Marlin Semiconductor Ltd. v. MediaTek Inc., on November 23, 2021, which is less than six months after the assignment was recorded. This timing indicates the transfer was arranged to enable assertion.
6. Bankruptcy fire-sale — Not present. United Microelectronics Corp. is an active, operating company, and there is no indication of bankruptcy proceedings leading to the sale of this patent.
7. Privateering — Unclear. There is no publicly available information in the patent record or general business news indicating that United Microelectronics Corp. transferred the patent to Marlin Semiconductor Limited with the intent for Marlin to assert it on UMC's behalf against competitors.
8. Defensive aggregator (anti-NPE) — Not present. The chain terminates with Marlin Semiconductor Limited, which is an NPE, not a defensive aggregator.

Verdict

NPE — high confidence. The assignment chain clearly shows a transfer from an operating company (United Microelectronics Corp.) to Marlin Semiconductor Limited, a known Non-Practicing Entity. This transfer was handled by a correspondent attorney (David G. Rasmussen) associated with NPE activities and occurred within six months prior to the first known infringement lawsuit filed by Marlin Semiconductor Ltd. asserting this patent [cite: Reel 056991/0292, 5].

USPTO Assignment Center search for US8076735

To find the most relevant prior art for US patent 8,076,735, I will examine the patent citations listed within the patent itself. The USPTO provides resources for searching patent databases and prior art. Prior art includes publicly known information before the effective filing date of a patent application, such as U.S. patents, foreign patents, and published applications.

Here's an analysis of the patent citations for US8076735, focusing on their potential anticipation under 35 U.S.C. § 102.

Cited Patents (Examiner Cited, unless otherwise noted):

• US5834816A (Goldstar Electron Co., Ltd.)

  • Publication Date: November 10, 1998
  • Description: This patent describes a MOSFET having a tapered gate electrode. The tapering is generally aimed at reducing short channel effects and improving device performance.
  • Potential Anticipation (35 U.S.C. § 102): May anticipate elements of Claim 1, particularly regarding the concept of a non-uniform (tapered) gate electrode or trench shape, if the specific "neck narrower than top" and "neck narrower than or equal to bottom" features of the trench in US8076735 are considered to be an ordinary tapering. However, US8076735 specifies a unique funnel-like or wide-top/narrow-bottom trench profile created by differential etching rates based on dopant concentration, which might differentiate it from a general tapered gate.

• US5840611A (Goldstar Electron Company, Ltd.)

  • Publication Date: November 24, 1998
  • Description: This patent describes a process for making a semiconductor MOS transistor. Similar to US5834816A, it likely deals with aspects of gate electrode formation and device structure.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US5834816A, it could potentially anticipate the broad concept of forming MOS transistors with shaped gate electrodes. The specific method of doping a polysilicon layer to control etching rates and create a unique trench profile, as detailed in US8076735, would be a key differentiator.

• US5685950A (Sony Corporation)

  • Publication Date: November 11, 1997
  • Description: This patent describes a dry etching method. Etching processes are crucial in semiconductor fabrication for creating desired patterns and shapes.
  • Potential Anticipation (35 U.S.C. § 102): Could potentially anticipate the general use of dry etching in semiconductor fabrication (as mentioned in the detailed description of US8076735 for forming dummy patterns using a halogen-containing reactant). However, it is unlikely to anticipate the specific method of controlling the etching rate via N-type dopant concentration in a polysilicon layer to achieve the specific dummy pattern/trench shape of US8076735.

• JPH0855863A (Nec Corp)

  • Publication Date: February 27, 1996
  • Description: This Japanese patent application describes the manufacture of a field-effect semiconductor device. Without a full English translation, specific details are hard to ascertain, but it likely covers aspects of FET fabrication.
  • Potential Anticipation (35 U.S.C. § 102): General claims about FET manufacturing might be broad enough to encompass some aspects, but the specific trench geometry and formation method of US8076735 would likely provide novelty.

• US6060375A (Lsi Logic Corporation)

  • Publication Date: May 9, 2000
  • Description: This patent describes a process for forming a re-entrant geometry for a gate electrode of an integrated circuit structure. A re-entrant geometry often implies an undercut or wider opening at the top, which is relevant to US8076735's "wide opening in the top" feature.
  • Potential Anticipation (35 U.S.C. § 102): This patent appears highly relevant to Claim 1 of US8076735, particularly the "width of the neck is narrower than a width of the top" aspect of the trench. The method of forming this re-entrant geometry would need to be compared to the N-type dopant-controlled etching of US8076735 to determine if the specific method of achieving the re-entrant shape is anticipated, or just the resulting shape itself. If the re-entrant shape is inherently similar and achieved by a known method, it could anticipate this aspect of the claim.

• US5879975A (Advanced Micro Devices, Inc.)

  • Publication Date: March 9, 1999
  • Description: This patent describes heat treating a nitrogen implanted gate electrode layer for improved gate electrode etch profile. This indicates an awareness of using implantation and heat treatment to influence etch profiles.
  • Potential Anticipation (35 U.S.C. § 102): This could potentially anticipate the general idea of using implantation to modify etching characteristics of a gate electrode layer, which is a core part of the method in US8076735. However, the specific N-type dopants (P, Sb, As) in polysilicon and their effect on etching rates to create the precise "neck narrower than top" and "neck narrower than or equal to bottom" profile would need detailed comparison.

• US6661066B2 (Mitsubishi Denki Kabushiki Kaisha)

  • Publication Date: December 9, 2003
  • Description: This patent describes a semiconductor device including an inversely tapered gate electrode and a manufacturing method thereof. An inversely tapered gate could potentially refer to a structure where the top is wider than a lower portion, aligning with the concept of a "neck narrower than top" in US8076735.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US6060375A, this patent is highly relevant to Claim 1's trench shape. The key would be whether the "inversely tapered" definition specifically matches the "neck narrower than top, and narrower than or equal to bottom" of US8076735, and if the method of fabrication is similar enough to render the specific doping and etching of US8076735 obvious or anticipated.

• US6674137B2 (Nec Corporation)

  • Publication Date: January 6, 2004
  • Description: This patent describes a semiconductor device and its manufacturing method. Without further details on the specific device or method, its relevance is broad.
  • Potential Anticipation (35 U.S.C. § 102): Generic claims for semiconductor devices and manufacturing methods are unlikely to anticipate the specific trench geometry and fabrication method of US8076735 without more detailed correspondence.

• US7208361B2 (Intel Corporation)

  • Publication Date: April 24, 2007
  • Description: This patent describes a replacement gate process for making a semiconductor device that includes a metal gate electrode. US8076735 explicitly states it uses a "gate last process to form a complementary metal oxide semiconductor (CMOS) device," which is a type of replacement gate process.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to the overall gate last (or replacement gate) process described in US8076735. While it might not anticipate the specific trench shape, it could anticipate the broader method steps related to forming dummy patterns and then replacing them with metal gates. This might impact the novelty of method claims in a broader sense, but not necessarily the specific structural claims related to the trench shape.

• US20070126067A1 (Intel Corporation)

  • Publication Date: June 7, 2007
  • Description: This publication describes angled implantation for removal of thin film layers. Angled implantation can influence etch rates and profiles.
  • Potential Anticipation (35 U.S.C. § 102): This could potentially anticipate the concept of using ion implantation to affect the removal (etching) of layers. However, US8076735 focuses on vertical blanket doping to create a depth-dependent etch rate, resulting in a specific trench profile, which may be distinct from angled implantation for general thin film removal.

• US20090189219A1 (Shinbori Atsushi)

  • Publication Date: July 30, 2009
  • Description: This publication describes a semiconductor device and a manufacturing method of the same. The priority date of US8076735 is October 2, 2009, so this publication is prior art. Specific details would be needed to assess anticipation.
  • Potential Anticipation (35 U.S.C. § 102): Without specific details from the publication, it's difficult to assess. However, given its close publication date to the filing of US8076735, it could potentially contain similar advancements in semiconductor device fabrication or gate structures.

• US20090218603A1 (Brask Justin K)

  • Publication Date: September 3, 2009
  • Description: This publication describes semiconductor device structures and methods of forming semiconductor structures. Similar to US20090189219A1, this is also prior art due to its publication date before the filing of US8076735.
  • Potential Anticipation (35 U.S.C. § 102): Like the previous publication, a detailed comparison of its disclosed structures and methods to those claimed in US8076735 would be necessary.

• US7749911B2 (Taiwan Semiconductor Manufacturing Co., Ltd.)

  • Publication Date: July 6, 2010
  • Description: This patent describes a method for forming an improved T-shaped gate structure. A T-shaped gate typically has a wider top portion.
  • Potential Anticipation (35 U.S.C. § 102): This patent is particularly relevant to Claim 1 of US8076735 due to its focus on non-rectangular gate shapes with wider top portions. While the publication date is after the filing date of US8076735, its priority date would be critical in a 35 U.S.C. § 102 analysis. If its priority date predates US8076735, and its T-shaped gate structure with a wider top is sufficiently similar to the "neck narrower than top" feature, it could be highly anticipatory. The specific dimensions and the method of achieving the T-shape would need to be compared against the N-type dopant-controlled etching for the funnel-like or wide-top/narrow-bottom shape in US8076735.

• US20110070702A1 (United Microelectronics Corp.)

  • Publication Date: March 24, 2011
  • Description: This publication describes a method for fabricating a semiconductor device. This appears to be an application by the same original assignee as US8076735. While the publication date is after US8076735's filing, its priority date might be earlier, or it could be a related or divisional application.
  • Potential Anticipation (35 U.S.C. § 102): As an application from the same assignee, it's less likely to be used for anticipation under § 102 against its own family unless it has a significantly earlier priority date for similar subject matter and is not considered a parent or divisional application. It is more likely to be considered for obviousness under 35 U.S.C. § 103, or perhaps as a related application containing overlapping subject matter.

• US7939895B2 (Sony Corporation)

  • Publication Date: May 10, 2011
  • Description: This patent describes a semiconductor device with a forwardly tapered P-type FET gate electrode and a reversely tapered N-type FET gate electrode and a method of manufacturing the same. This patent also directly addresses tapered gate electrodes in different FET types.
  • Potential Anticipation (35 U.S.C. § 102): This patent is also highly relevant to Claim 1 of US8076735, specifically regarding tapered gate electrodes and varying profiles for different transistor types. Similar to US7749911B2 and US6661066B2, a detailed comparison of the specific tapering, especially the "neck narrower than top, and narrower than or equal to bottom" aspect of the trench in US8076735, against the disclosed tapered profiles in this Sony patent would be crucial. The manufacturing method, particularly the use of differential etching based on N-type dopant concentration in polysilicon, would be a key point of distinction.

For a patent to be deemed obvious under 35 U.S.C. § 103, the differences between the claimed invention and the prior art must be such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA) to which said subject matter pertains. This assessment considers whether there was a motivation in the prior art to combine existing elements to achieve the claimed invention, with a reasonable expectation of success.

The independent claim of US Patent 8076735, Claim 1, describes a semiconductor device with a trench having a specific profile: a neck narrower than the top, and narrower than or equal to the bottom. This unique trench shape is key to the invention's benefits, such as void-free metal fill and unaffected critical dimensions. The method of achieving this shape, as detailed in the patent, involves doping a polysilicon layer with an N-type dopant to create differential etching rates.

To establish obviousness, one would need to demonstrate that a PHOSITA, at the time of the invention (October 2, 2009), would have been motivated to combine prior art references to arrive at this specific trench structure and the resulting semiconductor device, with a reasonable expectation of success.

Let's examine the cited prior art and consider potential combinations:

Prior Art References and their relevant disclosures:

• US5834816A (Goldstar Electron Co., Ltd.): Discloses a MOSFET having a tapered gate electrode. This suggests knowledge of controlling gate electrode shapes.
• US5840611A (Goldstar Electron Company, Ltd.): Describes a process for making a semiconductor MOS transistor.
• US5685950A (Sony Corporation): Pertains to a dry etching method.
• JPH0855863A (Nec Corp): Discloses the manufacture of a field-effect semiconductor device.
• US6060375A (Lsi Logic Corporation): Describes a process for forming re-entrant geometry for a gate electrode of an integrated circuit structure. "Re-entrant geometry" suggests non-uniform widths along the trench sidewalls, which is relevant to the "neck" feature of the present invention.
• US5879975A (Advanced Micro Devices, Inc.): Focuses on heat treating a nitrogen implanted gate electrode layer for an improved gate electrode etch profile. This teaches the concept of modifying polysilicon properties (via doping/implantation) to influence etching.
• US6661066B2 (Mitsubishi Denki Kabushiki Kaisha): Discloses a semiconductor device including an inversely tapered gate electrode and a manufacturing method. "Inversely tapered" could imply a wider bottom than top, or a non-uniform profile.
• US6674137B2 (Nec Corporation): Covers a semiconductor device and its manufacturing method.
• US7208361B2 (Intel Corporation): Deals with a replacement gate process for making a semiconductor device that includes a metal gate electrode. This establishes the "gate last" process context, which is the framework for US8076735.
• US20070126067A1 (Intel Corporation): Relates to angled implantation for removal of thin film layers, which is a technique for modifying etching characteristics.
• US20090218603A1 (Brask Justin K): Discusses semiconductor device structures and methods of forming semiconductor structures.
• US7749911B2 (Taiwan Semiconductor Manufacturing Co., Ltd.): Describes a method for forming an improved T-shaped gate structure. A T-shaped gate structure inherently has different widths at different vertical positions, similar to the concept of a neck.
• US20090189219A1 (Shinbori Atsushi): Pertains to a semiconductor device and a manufacturing method.
• US20110070702A1 (United Microelectronics Corp.): Describes a method for fabricating a semiconductor device. This is a related patent from the original assignee.
• US7939895B2 (Sony Corporation): Discloses a semiconductor device with a forwardly tapered P-type FET gate electrode and a reversely tapered N-type FET gate electrode and a method of manufacturing the same. This explicitly teaches varying gate electrode profiles for different transistor types.

Motivation to combine:

The primary motivation for a PHOSITA to combine these references would be to overcome the known problems in conventional gate-last processes, specifically the poor metal gap fill and void formation in trenches that are narrower at the top. The background of US8076735 explicitly states these problems, noting that "the resultant dummy patterns are usually shaped into trapezoids having a narrow top and a wide bottom, so that an included angle between the top sidewall of each the dummy pattern and the surface of the interlayer dielectric layer is about 88°-89°." This leads to "an opening with a narrower top portion" after dummy pattern removal, resulting in "poor metal gap fill effect" and "formation of voids in the metal layer." The invention aims to solve this by creating a trench with a "wider opening in a top" (i.e., an included angle greater than 90°) and a neck that is narrower than the top.

A PHOSITA would be looking for methods to improve metal gate fill and device reliability in gate-last processes.

Possible Obviousness Combinations:

1. US7208361B2 (Intel) + US5879975A (Advanced Micro Devices, Inc.) + US6060375A (Lsi Logic Corporation) / US7749911B2 (TSMC) / US7939895B2 (Sony)

   • US7208361B2 (Intel) establishes the context of a replacement gate process (gate-last process) for metal gate electrodes. This is the fundamental process flow that US8076735 seeks to improve.
   • US5879975A (Advanced Micro Devices, Inc.) teaches the concept of modifying polysilicon layers through implantation (e.g., nitrogen implantation) to achieve an improved etch profile. This directly provides the technical means for selectively altering etch rates within a polysilicon dummy gate.
   • US6060375A (Lsi Logic Corporation) discloses forming "re-entrant geometry" for gate electrodes. While not explicitly defining a "neck narrower than the top," it indicates an awareness and desire to create non-uniform gate electrode shapes. Alternatively, US7749911B2 (TSMC) describes T-shaped gate structures, which also exhibit varying widths along the vertical dimension. US7939895B2 (Sony) explicitly discusses forwardly and reversely tapered gate electrodes, demonstrating an understanding of intentionally designing gate profiles with different widths.
   • Motivation and Expectation of Success: Given the known problem of poor metal gap fill in narrow-top trenches in gate-last processes (as articulated in the background of US8076735), a PHOSITA would be motivated to create a trench with a wider top opening. By combining the replacement gate process of Intel with the knowledge of etch rate modification through doping (Advanced Micro Devices) and the general concept of forming non-uniform or re-entrant/tapered gate/trench geometries (Lsi Logic, TSMC, or Sony), a PHOSITA would have a strong motivation to use differential doping to create a dummy gate that results in a trench with a wider top and a narrower neck. The expectation of success would be reasonable because the principle of dopant-dependent etching of polysilicon was known, and the desired outcome (improved fill) directly addresses a recognized problem. The specific "funnel-like" or "wide top and narrow bottom" shapes described in US8076735 for the dummy patterns (and thus the inverse for the trenches) are a predictable result of applying a dopant with varying concentration, combined with an etching process sensitive to that dopant, as taught by Advanced Micro Devices.

2. US20070126067A1 (Intel) + H. Seidel et al., "Anisotropic Etching of Crystalline Silicon in Alkaline Solutions: II. Influence of Dopants"

   • US20070126067A1 (Intel) introduces the concept of angled implantation for removal of thin film layers, which implies an understanding of how ion implantation can be used to modify materials for subsequent removal. While not directly about gate structures, it highlights the use of implantation to alter material properties for processing.
   • H. Seidel et al. (Non-Patent Citation): This non-patent literature explicitly discusses the "Influence of Dopants" on the anisotropic etching of crystalline silicon in alkaline solutions. It clearly establishes that the etching rate of polysilicon doped with N-type dopants is higher than undoped polysilicon, and increases with dopant concentration. This is a direct teaching of the mechanism utilized in US8076735 to create the varied trench widths.
   • Motivation and Expectation of Success: A PHOSITA, aware of the issues with metal fill in narrow trenches in gate-last processes, would be motivated to find ways to create wider trench openings. Knowing from Seidel et al. that N-type dopants can significantly increase polysilicon etch rates, and understanding from Intel (or general knowledge) that implantation can selectively introduce dopants, it would be obvious to apply an N-type dopant in a controlled manner to a polysilicon dummy gate layer. By controlling the dopant concentration profile (e.g., higher concentration where a narrower neck is desired, or vice versa depending on the etch chemistry), one could engineer a dummy pattern that, upon removal, yields a trench with a wider top opening. The expectation of success is high given the explicit teachings regarding dopant-dependent etching rates in the Seidel paper.

The invention's specific claim details, such as the ratio of heights (2:1, Claim 2) or the included angle (>90°, Claim 3), might be considered optimization choices for a PHOSITA once the underlying principle of creating a wider-top trench via dopant-controlled etching of a dummy gate is established. These specific dimensions would be within the purview of a PHOSITA experimenting to achieve optimal void-free metal fill, especially given the various teachings on tapered and re-entrant gate structures in the cited prior art.