US 7906363

I'll search for authoritative information on this patent, including any 2026 CAFC activity.

Let me check for any 2026 litigation or CAFC docket activity specifically involving this patent.

Let me verify the claim set and confirm no 2026 CAFC activity.

US Patent 7,906,363 — Summary

Important caveat on scope: I searched for 2026 CAFC docket activity on this specific patent and found none. I could not locate any Federal Circuit appeal, docket entry, or 2026 litigation naming U.S. Patent No. 7,906,363. If such a docket exists, it is not surfacing in the sources I can reach; treat that as an absence of evidence, not proof of absence. Google Patents lists the patent's legal status as "Active," with an adjusted expiration of 2026-06-05, so any 2026 activity would likely concern the tail end of its term.

Bibliographic data

Source note: Justia's patent page and uspto.report both list ZyCube Co., Ltd. as the assignee (as of issue); Google Patents and Rambus's later assignment records show the current assignee is Rambus Inc. These are consistent, not contradictory — the assignment simply changed hands twice after grant.

Abstract (as given)

"A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film."

Plain-language overview of the independent claims

The patent is a method-of-manufacturing patent for 3D-stacked semiconductor devices (stacked wafers/chips with vertical "buried interconnections"). The specification organizes the invention into four "aspects," each corresponding to a distinct independent claim family. In plain terms:

Aspect 1 (Claim 1 family) — "trench-first from the front side."
Build the vertical via early: (a) etch a trench into the front (device) side of a silicon substrate; (b) line it with a first insulating film; (c) fill it with conductive material to make a conductive plug; (d) then form the transistor/circuit in the substrate; (e) cover the front with a second insulating film; (f) bond the wafer front-side-down to a support substrate or to another stacked circuit layer; (g) grind/etch away the substrate from the back until the trench's insulating liner is exposed; (h) strip that liner to reveal the conductive plug's bottom end at the back face — ready for a bump that connects to the next layer up. The point is that the via is formed before, or independent of, the later wiring structure, so you don't have to drill through complex back-end wiring.

Aspect 2 (Claim family with "second insulating film" trench liner) — "vias through the front insulating film."
The circuit is formed first, then covered with a first insulating film. A trench is etched through that film into the substrate and lined with a second insulating film. The trench is filled with conductive material, and the wafer is bonded to the support/next layer using a first electrode positioned at the plug's front end. Back-side removal then exposes the second insulating film, which is stripped to expose the plug. This variant suits cases where the trench can pass through the surface dielectric.

Aspect 3 (Claim family covering back-side trench formation) — "vias formed from the back."
Here the circuit is made, covered with a first insulating film, and the wafer is bonded first (via that film or through a wiring structure) to the support/next layer. Only then is the trench formed in the substrate and lined with a second insulating film, and the trench filled with conductive material. An added refinement: the second insulating film is given a controlled opening near the trench's end so the first electrode can make electrical contact to the conductive plug just by filling the trench. This suits situations where forming/filling the trench from the front side is impossible or impractical.

Aspect 4 (Claim family interchanging element formation and trench formation) — "sequence-swapped variant of Aspect 1."
Identical to Aspect 1 except the order of "form the element/circuit" and "form the trench" is reversed. The specification states this yields the same advantages for the same reasons.

Additional independent-style claims. The granted claim set extends at least into the 40s (I confirmed the presence of claims 40, 41, 42, and 43 in the issued patent). Claims 41–43 each recite their own "A method of fabricating a semiconductor device having a three-dimensional stacked structure formed by stacking semiconductor circuit layers on a support substrate, comprising the steps of:" preamble, indicating they are independent claims in their own right, largely tracking the first/second aspect steps but adding "third insulating film" / "planarization film" back-side-processing limitations and the requirement that those layers be selectively removed along with the trench liner when the conductive plug is exposed.

Common dependent-claim themes (from the spec and the surfaced claim text): providing a third insulating film on the wafer back, optionally with a planarization film over it; forming a second electrode (bump) on the exposed plug end; use of a single or multiple semiconductor members as the substrate; and use of microbump first electrodes for bonding. None of these dependent limitations change the core inventive concept.

Uncertainty notes

• CAFC 2026 docket: no results found for this patent number. I cannot confirm or deny any 2026 appeal.
• Full claim text: I retrieved partial claim text (claims 41–43 clearly, plus fragments of others) rather than the complete verbatim claim set. The number of independent claims and their exact numbering (beyond 40–43) is inferred from the specification's four-aspect structure; verify against the USPTO full-text record before relying on it.
• Assignee field: Justia/uspto.report reflect the original assignee (ZyCube); Google Patents reflects the current assignee (Rambus Inc.). Both are correct for their respective dates.

I'll research litigation involving US Patent 7,906,363. Let me run several searches.

Let me search more specifically on litigation databases and for the patent owner's enforcement activity.

Litigation Search Results — U.S. Patent No. 7,906,363

Conclusion

I found no record of any litigation involving U.S. Patent No. 7,906,363. Based on my searches of patent-litigation sources, this patent does not appear as an asserted patent in any known U.S. district court case, ITC investigation, or Federal Circuit appeal. No plaintiff/defendant case data can therefore be provided, because no case has been located.

Search scope and what I checked

• Patent number–specific queries ("7,906,363" / "7906363" + litigation, lawsuit, infringement case) — returned only the patent's own bibliographic page (Google Patents/aggregator mirrors) and unrelated matches (e.g., an unrelated Brazilian corporate-registry entry that happens to contain the digit string "7906363", and unrelated patents numbered 7,861,006, 7,910,xxx, etc.). Do not treat these as records for '363.
• Owner-based queries (Rambus, ZyCube, Kamiyacho IP Holdings) combined with the patent number — returned only the patent's chain of title and English-language equivalents (e.g., CN102290425B), but no enforcement action.
• Unified Patents litigation portal / general litigation aggregator queries — no '363 hit.

Patent context (for diligence purposes)

• US 7,906,363 B2, "Method of fabricating semiconductor device having three-dimensional stacked structure"; inventor Mitsumasa Koyanagi.
• Priority date 2004-08-20; filed 2005-08-19 (App. No. 11/573,976); granted 2011-03-15; adjusted expiration 2026-06-05 (i.e., the patent term has effectively now run — see caveat below).
• Chain of title: ZyCube Co., Ltd. → Kamiyacho IP Holdings (recorded 2012-04-13) → Rambus Inc. (recorded 2014-01-30). Current listed assignee: Rambus Inc.
• Status listed as Active with a stated adjusted expiration of 2026-06-05.

Notably, the well-documented Rambus campaigns I retrieved — the NVIDIA suits (N.D. Cal., 2008/2010; ITC investigations), the Hynix/Samsung/Micron DRAM cases, and the JEDEC-related antitrust and spoliation litigation — assert memory-controller/DRAM patents (Ware, Barth, Dally, Daily families, etc.), not this Koyanagi 3D-stacking fabrication patent. Nothing in those records ties '363 to any of those cases.

Important limitations (please verify before relying on this)

1. I could not retrieve live results from the Unified Patents litigation case-list or PACER directly — those queries did not return usable data within my search budget, so my negative finding rests on broad web/index searches rather than a complete Docket Navigator/PACER docket sweep. A definitive "no litigation" answer requires a direct query of PACER/Reuters Docket Navigator by patent number.
2. Given the 2026 adjusted-expiration, any enforcement would most likely predate 2026; a historical docket search (2005–2026) would be the correct scope.
3. I found no record either way of Rambus v. [party] or a declaratory-judgment action specifically naming '363. Its absence from all retrieved Rambus litigation narratives supports "no known litigation," but is not proof of nonexistence.

Recommendation: If you need a court-admissible negative, run a docketed search on Docket Navigator / PACER restricted to "7,906,363" and on the Unified Patents litigation portal, and confirm whether Kamiyacho/Rambus ever asserted it. On the evidence available to me, the correct answer is: no known litigation.

I'll start by verifying the canonical list against public sources.

Let me run additional targeted checks before concluding.

Proceedings overview

Zero AIA trial proceedings on file. The USPTO Open Data Portal "PTAB proceedings on file" block reports no AIA trial proceedings for US 7,906,363, and my independent web checks (PTAB/petition document search, Google Patents litigation/PTAB panel, CourtListener) surfaced no IPR, PGR, or CBM involving this patent as the challenged patent. Breakdown: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0 — the patent has never been through an AIA trial. Defensive posture: none of the claims have been tested at the PTAB, so you get no free invalidity judgment and no § 315(e)(2) estoppel shield from anyone else's prior petition; the upside is that no claim is estopped-blessed either, and the countervailing fact for a 2026 defendant is that the patent term appears to have run (see below).

⚠️ Flag on the structured data: the Google Patents legal-status field shows "Active, expires 2026-06-05" and an "Adjusted expiration" event dated 2026-06-05. Google's legal status is expressly an assumption, not a legal conclusion, but if that adjusted-expiration date is right, the 20-year term from the 2005-08-19 filing plus PTA lapsed roughly four months ago (today is 2026-10-01). Verify term and maintenance-fee status in USPTO Patent Center before doing anything else — it changes the entire posture (past damages under § 286 vs. ongoing exposure).

Proceedings

None to report. There are no proceeding sections to write, because no proceedings exist. I will not manufacture proceeding numbers, petitioners, panels, or decisions.

For completeness, the record facts that are confirmed:

• Patent: US 7,906,363 B2, "Method of fabricating semiconductor device having three-dimensional stacked structure"
• Inventor: Mitsumasa Koyanagi
• Original assignee: ZyCube Co., Ltd.
• Assignments: ZyCube Co., Ltd. (2008-10-28, inventor assignment) → Kamiyacho IP Holdings (2012-04-13) → Rambus Inc. (2014-01-30, current assignee)
• Priority: 2004-08-20 | Filed: 2005-08-19 (App. 11/573,976) | Granted: 2011-03-15
• Published application: US 2009/0149023 A1 (2009-06-11)
• PTAB activity: none on file (USPTO ODP), none found on web

One search artifact worth dismissing explicitly: "Koyanagi" appears in several PTAB records (e.g., FPGA/3D-stacking IPRs) as a prior-art publication cited by petitioners, not as the patent-owner of 7,906,363. Those hits are not proceedings on this patent.

Strategic summary

Claim status: entirely untested. Not one claim of 7,906,363 has been canceled, confirmed, or construed in an AIA trial. There is no FWD, no institution decision, and therefore no claim-level narrowing you can bank on. Contrast that with the family-typical pattern for 3D-stacking patents of this vintage: heavy IPR traffic. This patent drew none, which most plausibly reflects the commercial reality that ZyCube's licensing efforts (and later the Rambus-owned Kamiyacho portfolio) did not push it into sustained litigation against defendants with the budget and incentive to file. Absence of PTAB activity on a 20-year-old patent is a signal of low assertion pressure, not of a hardened patent. It also means there is no § 315(e)(2) estoppel wall — no third party has spent the money to lock in grounds.

Estoppel landscape: wide open. Because no IPR/PGR was ever instituted (or even filed), there is no § 315(e)(2) estoppel running against you or against anyone else. Your invalidity case is unconstrained by PTAB art: you may raise § 102 and § 103 on any reference, plus § 112 indefiniteness on the "buried interconnection"/"conductive plug" claim language and the method-step ordering, without any PTAB-raised-grounds carve-out. Conversely, you cannot borrow anyone else's invalidity work product — you'd be building the first real challenge to this patent.

Pattern signals: none. No repeat petitioner exists (there are no petitioners). The patent owner has never appealed a PTAB loss to the Federal Circuit (there is nothing to appeal). There is no Unified Patents or other defensive aggregator in the chain — the ownership path is inventor → ZyCube → Kamiyacho IP Holdings → Rambus, a straight commercial licensing chain, with Rambus holding the asset since 2014. The absence of any inter partes activity over ~15 years on a broad method claim covering through-silicon-via fabrication is itself the most informative fact here.

Recommended next steps

1. Confirm the term, immediately. Pull the Patent Center / Patent Term Adjustment record for 7,906,363 and confirm whether the term expired 2026-06-05 (as Google's adjusted-expiration line suggests). If it did, the patent cannot support injunctive relief or prospective royalties; your exposure is limited to past damages within the § 286 six-year lookback (i.e., acts on or after 2020-06-05 through expiry), and only for claims that were infringed on a claim-by-claim, product-by-product basis. This is the single highest-leverage check in this matter. Note that no FWD exists to cite, and there is no PTAB decision link to give you — do not let an adversary imply otherwise.

2. Verify through the official registers rather than relying on this memo. PTAB: USPTO PTAB E2E / PTACTS — search by patent number 7,906,363 and by application 11/573,976. Dockets and any appellate history: CourtListener — search "7,906,363" and "Kamiyacho IP Holdings." Patent text and status: US7906363B2 on Google Patents. If anything turns up that the ODP ingest missed, treat that as the operative record and re-run this analysis.

3. If the term has not expired and you are facing assertion, you are in a first-mover position on invalidity. Budget for a full prior-art search on the 3D-stacking/TSV literature predating the 2004-08-20 priority date — the Koyanagi/Fukushima/Tanaka Tohoku University publications and the 2003-2005 3D-integration conference record are the natural starting points, as they appear repeatedly as prior art in other parties' 3D-stacking IPRs. There is no estoppel narrowing your options, which is rare and valuable.

4. If active proceedings do appear in a re-check, the statutory clock is 1 year from institution to FWD (35 U.S.C. § 316(a)(11)) — diarize the institution deadline (3 months from the § 315(b) service bar date), the oral-hearing notice (typically ~2-3 months pre-FWD), and the FWD due date the moment a proceeding number exists. None exists today.

Bottom line for a defendant: no claims of 7,906,363 have been invalidated at the PTAB — so no "the troll's patents are dead" play exists here — but the patent also appears to be at or past the end of its term, which is a stronger defensive fact than any FWD would have given you. Confirm term status first; everything else is secondary.

I'll research the assignment and ownership record for US 7906363. Let me run several targeted searches.

Let me dig deeper into the specific assignment records and the Kamiyacho→Rambus transaction.

Ownership & Assignment Reconstruction — US Patent No. 7,906,363

Scope note / data limitation (read first): I was able to retrieve the USPTO/Google Patents legal-events list of recorded assignments (which is derived from the Assignment Center/Assignment Search database), but I was not able to pull the underlying reel/frame numbers, execution dates, or correspondent-of-record names for each conveyance from the Assignment Center via the sources available to me. Per the task constraints, I have not fabricated reel/frame or correspondent data. Where a field is unavailable, it is marked [not retrieved]. The three recorded conveyances below are corroborated by the Google Patents legal-events entries in the authoritative patent text and by the granted-patent bibliographic entry (Original Assignee: ZyCube Co Ltd; Current Assignee: Rambus Inc).

Inventors

Pattern note: This is a single-inventor university-technology case, not the classic "inventor team departs the assignee" pattern. The more notable fact is the assignor/assignee overlap: the inventor was an officer and co-founder of the assignee company, and the inventor→company assignment was not recorded until 2008-10-28, roughly three years after U.S. filing and four years after the priority date. That delay is more consistent with a startup formalizing its IP paperwork than with a distressed-portfolio signal. No evidence of inventors departing the original assignee within 12 months of filing was found.

Original assignee

ZyCube Co., Ltd. (also styled 株式会社ザイキューブ; assignment records render it "ZYCUBE CO., LTD.").

• Entity: Japanese "semi-fabless" 3D-LSI startup. Founded/established 29 March 2002 (press coverage says founded March 2002). Registered office originally Nihonbashi, Chuo-ku, Tokyo (Mitsuyoshi Bldg. 9F, 3-5-13 Nihonbashi); later listed at Yokohama. Capital ~¥34,000,000; ~6 employees per a later (2018) regional industry guide.
• Principals: Manabu Bonkohara (President/CEO), Mitsumasa Koyanagi (CTO/board director).
• Line of business / product: Developer of wafer- and chip-level 3D stacking using buried vertical vias — branded "Smart-Stack" and later "Super-Smart-Stack (SSS)". This is squarely the technology of the '363 claims (trenches formed from the front side, SiO₂-lined, filled to form conductive plugs, thinned from the back, bumps formed). ZyCube planned an 8-inch pilot line in late 2005, 2-layer volume production in 2007, and 3-layer in 2008 (per EE Times and Japanese trade coverage).
• Did they ship a product embodying the claims? Uncertain. ZyCube described itself as the layer that performs only the "stacking" steps (~30 of ~500 wafer process steps) and was targeting CSP/sensor and licensing revenue. I found no confirmation of volume shipment of a device practicing the '363 method. By a 2018 regional guide ZyCube was still listed as operating (offering "licensing of TSV core and technical know-how"), which suggests it did not simply vanish — yet it had already divested this patent in 2012.
• Current status: Appears to have remained an operating/licensing entity (not a bankruptcy case on the record I could see), but its patent portfolio was transferred away in 2012 (see timeline). [I could not confirm a dissolution date, merger, or bankruptcy filing — verify.]

Assignment timeline

All three records below are the conveyances listed in the patent's legal events. Execution dates and reel/frame are [not retrieved] — the listed dates are the recordation events surfaced by Google Patents/USPTO.

1. 2008-10-28 (recorded) — Reel [not retrieved] / Frame [not retrieved]

   • Conveyance: Assignment of Assignors' Interest
   • Assignor: Mitsumasa Koyanagi (inventor)
   • Assignee: ZYCUBE CO., LTD.
   • Correspondent: [not retrieved]
   • Context: Founder-inventor-to-company assignment (startup formalizing ownership of its founder's patent).

2. 2012-04-13 (recorded) — Reel [not retrieved] / Frame [not retrieved]

   • Conveyance: Assignment
   • Assignor: ZYCUBE CO., LTD.
   • Assignee: KAMIYACHO IP HOLDINGS
   • Correspondent: [not retrieved]
   • Context: Transfer from the operating startup to an IP-holding entity — monetization/portfolio-consolidation move. (Corroborated externally: the CN family member CN102290425B lists assignee "Kamiyacho知识产权控股公司" = Kamiyacho IP Holdings.)

3. 2014-01-30 (recorded) — Reel [not retrieved] / Frame [not retrieved]

   • Conveyance: Assignment
   • Assignor: KAMIYACHO IP HOLDINGS
   • Assignee: RAMBUS INC.
   • Correspondent: [not retrieved]
   • Context: Acquisition of the holding entity's portfolio by Rambus (licensing/monetization-oriented acquirer). This is the assignment recorded closest to Rambus's 2013–2014 licensing-expansion period.

(No later assignments appear in the record.)

Verification links:

• USPTO Assignment Center search: https://assignmentcenter.uspto.gov/
• Legacy Assignment Search (same underlying data): https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US7906363/en

Timeline diagram

timeline
    title Ownership of US 7906363
    2002 : ZyCube founded in Tokyo
    2004 : Priority date
    2005 : US application filed
    2008 : Koyanagi assigns to ZyCube
    2011 : Patent issued
    2012 : ZyCube assigns to Kamiyacho IP Holdings
    2014 : Kamiyacho assigns to Rambus Inc
    2026 : Adjusted expiration

NPE / troll-pattern signals

1. Shell-entity transfer — Present (moderate). The 2012-04-13 conveyance moves the patent from an operating startup (ZyCube) to "Kamiyacho IP Holdings," a name-suffixed (IP Holdings) non-operating holding entity. Corroborated by the foreign family member listing the same holding company as assignee. Caveat: I could not verify a registered-agent address, single-member LLC status, or absence of products for Kamiyacho — so this is grounded on the conveyance + entity type, not on the stronger "shell" tell-tags.

2. Known asserter in the chain — Present (with nuance). The current assignee (recorded 2014-01-30) is Rambus Inc., a publicly traded company that is one of the most prolific historical patent enforcers (DRAM/interface litigation against Hynix/Samsung/Micron, NVIDIA, ITC actions). Rambus does ship products (memory-interface chips, security IP), so it is not a classic non-practicing shell, but it is a licensing-first enforcer widely surfaced by RPX/Unified-type tracking as a high-frequency plaintiff. It is not on the standard Acacia/Marathon/IV/Vringo lists.

3. Repeat correspondent across the chain — Unclear / undetermined. The correspondent-of-record for each reel/frame was [not retrieved], so recurrence cannot be assessed. This is the single most important missing tell; verify directly on the Assignment Center PDFs.

4. Cascading transfers — Present. Two consecutive assignments within ~21 months (2012-04-13 → 2014-01-30) passing the patent through a holding entity en route to Rambus. Whether the two assignees shared a correspondent address/attorney is [not retrieved].

5. Pre-litigation transfer — Not present (as far as observable). The previously generated litigation section found no known litigation naming '363, so there is no suit to anchor a 6-month pre-suit transfer. If a suit does exist outside the sources checked, this should be re-evaluated.

6. Bankruptcy fire-sale — Not present / unconfirmed. No ZyCube Chapter 7/11-type proceeding was identified; ZyCube still appears in industry listings after 2012. The 2012 transfer is better characterized as a portfolio/holding-company move than an insolvency sale.

7. Privateering — Unclear. ZyCube (operating) → Kamiyacho (holding) → Rambus (licensor) resembles monetization rather than classic privateering, and I found no evidence of Rambus asserting this patent on ZyCube's behalf against ZyCube's competitors.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates at Rambus, a licensing-oriented enforcer, not at RPX, AST, LOT, Unified Patents, or OIN. No neutralizing transfer found.

Verdict

NPE — moderate confidence.

The recorded chain shows the patent leaving the operating developer ZyCube on 2012-04-13 to an IP-holding entity (Kamiyacho IP Holdings) and then, on 2014-01-30, to Rambus Inc. — a licensing-first, high-frequency patent enforcer that does not practice this particular 3D-stacking fabrication method. That is a transfer-to-monetizer pattern with a holding-entity intermediate and two transfers inside ~21 months (cascading-transfer signal), which supports a moderate NPE call; it does not rise to high confidence because (a) no assertion/litigation naming '363 was found, (b) Rambus is a real operating company rather than a pure shell, and (c) the key hard-evidence fields — reel/frame, execution dates, and correspondent-of-record — could not be retrieved, so the "repeat correspondent" and address-overlap tells remain unverified. To upgrade or downgrade this call, pull the three assignment PDFs at https://assignmentcenter.uspto.gov/ and confirm the correspondent names and reel/frame citations.

I'll research the prior art references for US Patent 7,906,363. Let me start with the patent's own citation records.

Let me retrieve the actual front-page citation list from the patent document itself.

Let me pull the front-page citation list directly from the patent's full-text sources.

Prior-Art Analysis — US 7,906,363 B2

0. Critical limitation to state up front

The task asks me to "look at each patent citation for 7906363" and map each to the claim(s) it anticipates under 35 U.S.C. § 102. I was unable to retrieve the verbatim front-page "References Cited" list (the "(56) References Cited" block) for US 7,906,363 during this session. My searches surfaced the patent's bibliographic data, its abstract, its specification, and the forward citations (patents that cite '363), but not the enumerated U.S. patent documents / foreign patent documents / other publications that the examiner listed as prior art on the face of '363 itself.

Rather than fabricate citations or attribute references to '363 that I did not actually see on its face, I am giving you only what I can ground, and flagging precisely what is missing. Do not treat the list below as the complete examiner-cited art — it is not, because I could not obtain it.

1. Patent identity confirmation (this is the correct patent)

This matches the patent analyzed in the earlier sections; no contradiction found. (Note: search snippets containing the digit string "7906363" for an unrelated BR 7906363 hydraulic-suspension application and a Chinese corporate-registry page are not this patent and I excluded them, as the previous litigation search also cautioned.)

2. Prior art identifiable from the '363 specification itself (grounded)

The '363 specification expressly identifies the following background references. These are the references the patent document itself cites/discusses, so I can ground them, though I do not have the examiner's front-page listing to confirm they were the formal "References Cited."

(a) Kurino et al., "Intelligent Image Sensor Chip with Three-Dimensional Structure," 1999 IEDM Technical Digest.

• Type: Non-patent literature (conference paper), published 1999.
• What the spec says it discloses: A four-layer stacked image sensor chip — processor array/output circuit in layer 1; data latches/masking circuits in layer 2; amplifiers/ADCs in layer 3; image sensor array in layer 4; the four layers mechanically joined with adhesive and electrically connected via buried interconnections using conductive plugs and microbump electrodes. (This is the "solid-state imaging sensor announced by Kurino et al." referenced in the spec.)
• Relevance to claims: This is the closest generic disclosure of the stacked-layer + buried-interconnection + microbump architecture that the '363 claims build on. It is most relevant to the structural/environmental context of the independent claims (stacked semiconductor circuit layers, buried interconnections along the stacking direction). However, it does not disclose the specific fabrication sequence (trench-first from the front side → plug → element → second insulating film → bond → back-side thinning → strip liner), which is the core of the '363 claim families. So it is background/§ 102(b) art of limited anticipatory force against the method claims as a whole, but relevant to the "stacking direction buried interconnection" concepts.

(b) Lee et al., image-processing chip.

• Type: Non-patent literature (paper), date not specified in the excerpt I retrieved.
• What the spec says: The Lee et al. image-processing chip "has approximately the same configuration as the solid-state imaging sensor announced by Kurino et al."
• Relevance: Cumulative with (a); same architectural context.

(c) "Non-Patent Document 2" — method of fabricating a semiconductor chip with penetrating holes.

• As described in the spec: Penetrating holes with a T-shaped (the OCR renders it "?-shaped") cross-section — larger part and smaller part joined — are formed in a semiconductor substrate; small-part ends open at the first main surface, large-part ends open at the second main surface; hole walls are covered with insulating films; the holes are filled with conductive material to form conductive plugs; thereafter a multilayer wiring structure is formed on the first main surface.
• Relevance: This is the most substantive prior-art item the spec itself flags, because it discloses the buried-conductive-plug-through-a-lined-hole concept — the same physical idea the '363 claims. It is potentially relevant under § 102 to the plug/liner/back-side-exposure features. I could not retrieve the bibliographic identity (author/patent number/date) of this "Non-Patent Document 2" — the OCR of the Google Patents HTML stripped the citation. I will not guess it.

(d) "Non-Patent Document 1" — conventional 3D device via bonding wires.

• As described: A 3D semiconductor device fabricated by stacking/unifying semiconductor chips on a support substrate, placing bonding wires around the stacked chips, and electrically interconnecting the chips with the bonding wires.
• Relevance: This is the admitted prior art the invention distinguishes itself from (the spec says the invention's buried-interconnection approach "is different from" it). Admitted prior art of this type is relevant to § 103 obviousness reasoning and to claim construction, but it uses wire bonding, not buried vias, so it does not read on the trench/plug/liner limitations.

3. Forward citations (patents citing '363) — NOT prior art

These appeared in my searches but are later-in-time documents that cite '363. They cannot anticipate '363 and are listed only to prevent misuse as prior art:

• US 10,204,893 B2 — "Stacked dies and methods for forming bonded structures"
• US 2011/0095367 A1 — "ESD/antenna diodes for through-silicon vias" (cited-by list)
• US 7,791,175 B2 — "Method for stacking serially-connected integrated circuits and multi-chip device made from same" (this patent cites '363)
• Various 2009–2011 TSV publications (e.g., US 2010/0244876, US 2010/0252934, US 2011/0001249, US 2010/0164062)

None of these have a date before the '363 2004-08-20 priority date, so all are outside the § 102 window.

4. § 102 anticipation mapping — what I can and cannot responsibly say

• I cannot produce a defensible, reference-by-reference § 102 mapping to specific claims, because I could not retrieve (i) the examiner's verbatim cited-reference list for '363, or (ii) the full text of the references, which § 102 requires me to read against each claim limitation.
• What I can say confidently: the references the patent itself identifies are strongest against the conceptual / architectural features (stacked circuit layers; buried conductive plugs; microbumps) and weakest against the claimed ordering of fabrication steps — which is the actual point of novelty across the four "aspects" (trench-first/front-side; trench-through-surface-dielectric; trench-from-the-back-after-bonding; and the sequence-swapped variant). The specification's stated object is precisely that these fabrication-sequence variants solve layout/process restrictions that the cited background art did not address.
• Recommendation: To do the § 102 job properly, pull (a) the "References Cited" front page of US 7,906,363 (Google Patents PDF at patentimages, USPTO PatentCenter full text, or the file wrapper/IFW), and (b) the PCT/JP2005/015133 international search report and the JP priority application (JP 2004-240___ , 2004-08-20) search report, which will list the art the examiner actually considered. Only then can each reference be cited with publication/filing date and mapped to claims 1, 40–43, etc.

5. Bottom line

I am deliberately not auto-generating plausible-looking patent numbers for the "(56)" list, because the instruction set requires literal fidelity and prohibits fabrication of identifiers. The absence of the examiner-cited list here is a gap in retrievable evidence, not a finding that '363 has no cited prior art.

If you can supply the patent's front page (or let me run a targeted query against the USPTO PatentCenter full-text/IFW for App. 11/573,976), I can complete the reference-by-reference § 102 table as requested.

I'll research the prior art landscape for this patent before analyzing obviousness.

Let me identify the specific prior-art references cited on the face of this patent and in its background section.

Let me pin down the specific references cited on the face of this patent.

Obviousness Analysis — U.S. Patent No. 7,906,363 under 35 U.S.C. § 103

0. Scope, sources, and caveats (read first)

What I relied on. The current task says to use "the results from the Prior Art section of this page." The Google Patents page for '363 supplies prior-art keywords (semiconductor substrate; semiconductor; insulating film; substrate; back side) but, in the full text I was given, no verbatim front-page "References Cited" list. I attempted to retrieve that list directly and could not (the targeted queries returned no usable record). Accordingly, the analysis below is grounded in:

• The prior art the '363 specification itself acknowledges (its "Non-Patent Document 1," "Non-Patent Document 2," and "Patent Document 2"), which are prior art of record in the prosecution; and
• Well-known contemporaneous art in the wafer-bonding/through-silicon-via (TSV) space that a POSITA would have consulted.

Flagged contradiction. The prior generated sections state the analysis date as 2026-10-01; this task states 2026-04-26. Neither affects the § 103 analysis (the reference prior-art date is 2004-08-20 and the relevant prior art long predates it). But it does matter to the term: Google Patents lists an adjusted expiration of 2026-06-05, so on either date the patent is at the very end of its term. That is relevant to remedial posture, not to validity.

Flagged uncertainty (material). I could not confirm the identity of the "φ-shaped penetrating-hole" reference that the '363 calls "Patent Document 2." The specification describes it as forming penetrating holes "whose relatively large parts and relatively small parts are respectively joined together," lining the walls with insulating films, filling with conductive material to form conductive plugs, and then forming a multilayer wiring structure on the first main surface. My search surfaced several plausible candidates of this general type (e.g., US 5,998,292-type two-sided via processes; JP 2000-036574; US 6,707,157; EP 1 926 136 A2), but I cannot assert with high confidence which one is the reference of record. Treat that reference's mapping as the weakest link in the combination below and verify against the prosecution file.

Flagged uncertainty (claim set). As noted in the prior sections, I confirmed the existence of claims 40–43 (each carrying its own "A method of fabricating…" preamble) but did not obtain the full verbatim claim set. Independent-claim numbering beyond 40–43 is inferred from the specification's four-"aspect" structure. Verify before relying on claim numbers.

1. Legal framework and the level of ordinary skill

Standard. Obviousness is measured under the Graham v. John Deere factors as elaborated by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007): (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) the level of ordinary skill; and (4) secondary considerations. Under KSR, a combination is obvious not only where there is an explicit teaching, suggestion, or motivation, but also where the combination is "the product of ordinary creativity," involves "a predictable variation," or is "a simple substitution of one known element for another" to obtain predictable results. KSR, 550 U.S. at 415–21.

POSITA. As of the 2004-08-20 priority date, a POSITA would have: (a) a B.S. in EE/Materials Science/Physics plus 3–5 years in semiconductor process integration or packaging, or an M.S./Ph.D. with 2–3 years; and (b) working familiarity with deep-Si trench etching (e.g., ICP/DRIE), thermal oxidation and LPCVD of doped polysilicon, CMP-based wafer thinning, microbump (e.g., In/Au) formation, and wafer-to-wafer alignment/bonding with adhesive injection. This is not a hypothetical profile: it is precisely the skill set published by the inventors' own Tohoku University group in the very references below.

Secondary considerations. I found no known litigation asserting '363 (per the prior Litigation section), so there is no record of an infringement-driven nexus argument. The chain of title (ZyCube → Kamiyacho IP Holdings → Rambus Inc.) reflects acquisition of a portfolio, not evidence of commercial success attributable to this claim set with a nexus. Absent such evidence, secondary considerations do not rebut the prima facie case.

2. The prior art of record, mapped to the common elements

All of the following were publicly available more than one year before 2004-08-20 and therefore qualify as § 102(b) art (and as § 103 art), notwithstanding that some are the inventors' own publications:

Note on "buried interconnection." The '363's Definitions section defines "buried interconnections" as interconnection lines for electrical connection along the stacking direction embedded in each semiconductor layer. Kurino 1999 and Lee 2000 use the identical term of art ("buried interconnection") for the trench-filled plug. This is significant: the disclosed structure claimed by '363 is not novel terminology; it is the same structure, formed by the same trench-oxidize-fill technique, then back-thinned to expose the plug.

3. Claim-by-claim / aspect-by-aspect obviousness

3.1 Aspect 1 (the "trench-first from the front side" family — likely claim 1)

Recited steps: (a) trench in substrate from front side, inner wall lined with first insulating film; (b) fill from front side → conductive plug; (c) then form element/circuit in/on the substrate; (d) cover surface with second insulating film; (e) fix substrate to support/another circuit layer by joining the second insulating film directly or through a wiring structure; (f) remove substrate from the back to expose the first insulating film; (g) selectively remove the first insulating film to expose the plug.

Primary combination: Kurino 1999 + Lee 2000.

• Steps (a)–(b): Expressly disclosed. Both references etch a deep Si trench, oxidize it (the "first insulating film"), and fill with doped poly-Si (the "conductive plug").
• Step (c): Expressly disclosed/obvious. Both form MOS devices in the same wafer; Lee bonds a device wafer to another device wafer.
• Steps (d)–(e): Disclosed. Kurino's device wafer is "glued to a quartz glass" support (Lee: to a device wafer); bonding to a support or to a remaining circuit layer is the stated purpose. The "second insulating film" is the surface passivation, and "through a wiring structure" is met by Lee's/TED-2006-era back-end wiring over the devices.
• Step (f): Expressly disclosed. Grinding + CMP from the back to expose the buried interconnections — which necessarily exposes the oxide that lines the trench, because the oxide surrounds the plug.
• Step (g): The only meaningful delta. Kurino/Lee reach the exposed plug principally by CMP "through" the plug, then deposit an insulation film and open the bump sites. The '363 instead etches the liner selectively to reveal the plug end.

Why (g) is obvious. Once the liner is exposed at the back face (step (f)), removing it with an etch selective to the liner relative to the poly-Si/metal plug is a textbook, predictable variation. Etch selectivity between SiO₂ and poly-Si/metal is among the most routine knobs in the art, and the benefit — a clean, contamination-free exposed plug end for bumping — is the expected result. Under KSR this is "a simple substitution of one known element for another" and "a predictable variation." There is also an affirmative design incentive: the '363's own background states the demand for a "highly reliable electrical connection along the stacking direction" and that "concrete methods of forming the buried interconnections and microbumps are not disclosed" in the known devices — i.e., the art itself frames the delta as an optimization problem, the classic KSR "finite number of identified, predictable solutions."

Secondary combination: Kurino 1999 (or Lee 2000) + "Patent Document 2" (φ-shaped hole).

• Patent Document 2 supplies the architecture (insulating-lined penetrating holes filled with conductive plugs, plus a multilayer wiring structure on the first main surface) and confirms that forming plugs before the overlying wiring structure was known.
• Kurino/Lee supply the single-etch trench-first, support-bonding, back-thinning process.
• Motivation to combine: The '363's own specification supplies it — the φ-hole method "has a disadvantage that each of the mask formation process and the etching process needs to be carried out twice." A POSITA seeking to reduce mask/etch count would be directly led to substitute the single-etch trench-first sequence of Kurino/Lee for the two-step φ-hole. KSR treats "simplification of a known process" and reduction of process steps as an ordinary design incentive.

Result. Aspect 1 is obvious as a matter of law-directed analysis. The independent claim recites a sequence of individually known process steps whose only arguable novelty is the order of trench formation relative to device formation — and the '363's own Aspect 4 (below) concedes that this order is functionally interchangeable.

3.2 Aspect 2 (vias through the front "first insulating film," plug-liner as "second insulating film")

Recited steps: form circuit → cover surface with first insulating film → etch trench through the first insulating film into the substrate → line with second insulating film → fill → bond using a first electrode at the plug's front end → back-remove to expose the second insulating film → strip it to expose the plug.

• The "first insulating film" over the devices is the ordinary interlayer dielectric; the trench through it with a lining and a fill is precisely the conventional via/interconnect process (US 5,702,982; US 6,707,157; EP 1 926 136 A2; and the generic oxide-liner/W- or Cu-plug art).
• The "first electrode" at the plug's front end for bonding is the microbump of Kurino/Lee.
• Patent Document 2 supplies the plug-and-liner-plus-overlying-wiring structure.
• Motivation: Same as §3.1; combining the known interlayer-dielectric via process with the known wafer-bonding/back-thinning flow is the aggregation of known elements with predictable results.

Result. Aspect 2 is obvious over Kurino 1999 / Lee 2000 in view of the conventional interlayer-via art and Patent Document 2.

3.3 Aspect 3 (back-side trench formation after bonding)

Recited steps: form circuit → cover with first insulating film → bond to support/another layer first → then form the trench in the substrate and line it with a second insulating film → fill → (optional refinement) give the second insulating film a controlled opening so the first electrode can contact the plug by filling alone.

• Bond-then-thin-then-form-backside-features is disclosed by Kurino/Koyanagi 2002 ("wiring and bumps formation on the back side" after thinning) and is standard in back-side-illuminated imager and TSV flows.
• The stated rationale in '363 — applicable "in a case where formation of the trench and filling of the conductive material from the surface side… is impossible" — is an express articulation of the motivation a POSITA would have had. An applicant's own statement of why one would select a known alternative is powerful evidence of obviousness.
• The "opening" refinement (allowing the electrode to contact the plug when the trench is filled) is a result-effective process optimization with a predictable outcome.

Result. Aspect 3 is obvious over Kurino 1999 / Kurino/Koyanagi 2002 in view of Patent Document 2 and conventional back-side via processing.

3.4 Aspect 4 (swap the order of "form element/circuit" and "form trench")

This is the same as Aspect 1 with the two steps reordered. Two independent grounds compel obviousness:

1. The '363 itself states the method "is the same as the method according to the first aspect… except that the order of the step of forming the element or circuit and the order of the step of forming the trench are interchanged," and that "the same advantages… are obtained… for the same reason." An applicant's admission that the reordering yields only the same expected benefits is essentially dispositive — no unexpected result, and the order is not critical. Cf. In re Kao, 639 F.3d 1057 (Fed. Cir. 2011) (obvious to optimize a known parameter); MPEP § 2144.04 (order of steps obvious where not critical).
2. The prior art (Kurino/Lee + Patent Document 2) already brackets both orders.

Result. Aspect 4 is obvious.

3.5 The "third insulating film / planarization film" independent claims (appearing as claims 40–43)

These add: (i) a third insulating film covering the wafer back after the first insulating film is exposed, and (ii) optionally a planarization film over it, with those layers selectively removed along with the trench liner when the plug is exposed.

• Depositing a passivation/insulating film on the back after thinning and before bumping is expressly disclosed by Kurino 1999/Lee 2000 ("In-Au micro bumps are formed on the back surface using the lift-off technique after the deposition of insulation film").
• Adding a planarization layer before polishing/etching is the ordinary use of spin-on dielectrics/BCB/polyimide and CMP planarization.
• Stripping the passivation together with the oxide liner in a single selective-removal step is a predictable manufacturing shortcut with expected results.

Result. These claims are obvious over Kurino 1999 / Lee 2000 in further view of the conventional backside-passivation and planarization art.

3.6 Common dependent themes

• Second electrode / bump on the exposed plug end ("used as a bump electrode"): expressly disclosed by Kurino/Lee (In-Au microbumps on the back at the buried-interconnection ends).
• Single or multiple semiconductor members as the substrate ("any one of the size of a semiconductor wafer… the size of a chip… intermediate… larger than the wafer size"): a straightforward, result-effective choice of substrate format; changing wafer→chip→wafer-size is the classic obvious design choice, and the '363 provides no teaching of criticality.
• Microbump "first electrodes" and direct/pressure bonding, or bonding via In/Au, Sn/Ag, Cu, W with an intervening bonding metal: expressly disclosed by Kurino/Lee (In-Au bumps; epoxy adhesive injection) and the conventional bonding-metal art.
• Trench shape/size/depth "optional"; isotropic/anisotropic etch or CMP for removal: routine process selections recited at the level of a specification's optional-embodiment discussion, not as claim-critical parameters.

None of these limitations changes the core concept; each is either expressly disclosed by Kurino/Lee or is an obvious, predictable process option.

4. Motivation to combine — consolidated

Substantial, evidence-based motivations exist, independently satisfying KSR:

1. Same field, same problem, same inventors. Kurino 1999, Lee 2000, and Kurino/Koyanagi 2002 are directed to the identical problem (vertical electrical interconnection between stacked semiconductor circuit layers) and use the identical term of art ("buried interconnection"). Combination is not analogous-art gymnastics; it is the natural continuation of a single research program.
2. The art's own identification of the gap. The '363 background states the known 3D-stacked devices "are not disclosed" as to "concrete methods of forming the buried interconnections and the microbump electrodes," and that a "highly reliable electrical connection along the stacking direction" is needed. Framing the delta as an unmet, known need supplies the "how and why."
3. Design incentive to simplify. The '363 criticizes the φ-hole method for requiring two mask/etch cycles. Reducing steps is a recognized design incentive under KSR.
4. Predictable results / reasonable expectation of success. Each step (trench etch, oxidation, poly-Si fill, CMP thinning to expose the plug, selective liner strip, bump formation) was previously performed, individually and in combination, by the same group. There is no unpredictable mechanism; the reference structure (oxide-lined trench filled with poly-Si, exposed at the back) is literally the '363's structure.
5. Order-swap concession (Aspect 4). The specification's own admission that the reordered method yields the same advantages "for the same reason" removes any argument that the sequence is critical.

5. Anticipated patent-owner rebuttals and how they fare

• "The references don't disclose selectively removing the first insulating film to expose the plug." This is the strongest argument, but it fails under KSR: it is a single, predictable process substitution (etch chemistry selective to liner vs. plug) with an expected benefit, in a field where etch-selectivity selection is routine.
• "Teaching away" / "different approach." Weak. The φ-hole criticism is a criticism of step count, not of operability; criticizing an alternative as less efficient does not teach away from its structure, and the '363 itself adopts that structure.
• "The inventors are the same, so this is not 'prior art.'" Legally incorrect for § 102(b)/§ 103: the inventors' own publications more than one year before the priority date are prior art, and common inventorship does not remove them. This is, if anything, a double-edged sword — the same group published the enabling process.
• Secondary considerations (commercial/acquisition success). No litigation record, no nexus evidence surfaced. The Rambus acquisition reflects portfolio value, not nexus to these claims.

6. Bottom line

On the record available to me, the claims of U.S. 7,906,363 would be vulnerable to a § 103 obviousness challenge, grounded principally on:

• Kurino 1999 (IEDM) + Lee 2000 (IEDM), which together disclose the trench-lined-and-filled conductive plug, device formation in the substrate, support/device-wafer bonding, and back-thinning that exposes the buried interconnection; and
• "Patent Document 2" of the '363 (φ-shaped penetrating-hole method) — or, alternatively, the routine interlayer-via and backside-passivation art (e.g., US 5,702,982; US 6,707,157; EP 1 926 136 A2) — for the plug-and-liner-plus-overlying-wiring structure and the backside insulating/planarization layers;

with the sole substantive delta (selectively stripping the exposed liner to expose the plug, and the associated order-of-steps variations) being a predictable variation and/or a simplification with expected results and ample express motivation in the specification itself.

Recommended next steps to make this litigation-grade.

1. Obtain the verbatim front-page "References Cited" list and the full claim set from USPTO PatentCenter/Global Dossier, and confirm the identity of "Patent Document 2." My mapping of that reference is the weakest link (flagged in §0).
2. Pull the prosecution history to see which references the examiner applied and whether any § 103 rejection was overcome by argument (which would inform the strongest obviousness theory and any estoppel).
3. If a PTAB petition is contemplated, build the motivation-to-combine record with a POSITA declaration citing the '363's own background admissions and the Kurino/Lee process details, and consider whether the 2026-06-05 adjusted expiration makes IPR timing (and any statutory disclaimer/expiration bar) moot.

Caveat reiterated: I was unable to retrieve the actual front-page reference list, and I could not confirm the identity of the φ-shaped-hole reference; the conclusion above rests on the patent's own acknowledged prior art plus general knowledge of the 2004 TSV art. Verify items (1)–(2) before relying on this analysis for any adversarial purpose.