US 7154299

I'll research this patent, including any recent litigation activity and CAFC dockets.

Let me search for any 2026 appellate activity involving this patent's owner.

Let me verify the IPR outcome and check for any 2026 appellate activity.

US Patent 7,154,299 — Analyst Summary

Source basis: Full text retrieved from Google Patents (https://patents.google.com/patent/[US7154299](/patent/US7154299)/en) plus PTAB/CAFC materials surfaced via web search. Note on scope: I was able to confirm PTAB and Federal Circuit activity touching this patent, but I found no 2026 CAFC docket for patent 7,154,299, and no CAFC 2026 docket at all in the results returned. Details and caveats below.

1. Bibliographic Data (authoritative, from the patent document)

Abstract (verbatim): "An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together."

2. Plain-Language Overview of the Independent Claims

The core idea across all independents: move the sequential element (flip-flop) out of the PLB and into the routing structure, so any PLB can borrow it, and make both its input and output simultaneously reachable through the common interconnect matrix using essentially only pass gates/switches.

• Claim 1 (architecture, "connecting means"): A PLD where a sequential circuit element lives in the routing domain associated with a PLB. A connecting means selectively links that element's input to a first signal-pass node of the common interconnect matrix — through no circuit element other than one or more switch elements — while simultaneously linking its output to a second signal-pass node of that matrix. (The "no other circuit element" negative limitation was important: per the prosecution history, it is what distinguished the prior art.)
• Claim 5 (method): Same concept framed as a method — improve resource utilization by selectively connecting a sequential element's input to a first matrix node via only pass gates, and simultaneously connecting its output to a second matrix node.
• Claim 7 (method): As in claim 5, but expressly adding bi-directional propagation of a signal between the first and second signal-pass nodes.
• Claim 8 (integrated circuit): First and second PLBs, plus routing resources adjacent to the first PLB containing a sequential element. The element's input couples to the second logic block via only pass gates, and its output simultaneously couples to either a PLB input or the second logic block.
• Claim 9 (IC with tiling): Same structure, plus a tile section holding the routing resources and its adjacent PLB, with at least one logic block coupled to the sequential element's input/output located outside that tile section.
• Claim 13 (IC, bidirectional): As in claim 8, where the routing resources permit bidirectional communication between the logic block on the input side and the logic block on the output side.
• Claim 14 (IC, bidirectional via the element): As above, but the bidirectional communication occurs through the sequential element itself.
• Claim 16 (electronic system): A system built around the claim-8-style IC (first and second PLBs + routing-resource flip-flop reachable via pass gates only).
• Claim 19 (electronic circuit — "direct/registered" switch): A circuit input; a flip-flop whose input couples to the circuit input via no circuit element other than first switches; a second switch that couples the circuit input to a distribution node; a third switch that couples the flip-flop output to that distribution node; and multiple distribution switches each coupling the distribution node to a respective output node. This is essentially the FIG. 8 circuit (selectable "direct mode" vs. "registered mode").
• Claim 21 (electronic circuit — bidirectional variant): Similar, but with a first switch from the circuit input to the distribution node, a second switch from the flip-flop output to the distribution node, plus third and fourth switches routing the circuit input to the first/second switches respectively — i.e., the FIG. 9 direction-selectable structure.
• Claim 23 (method): Route a sequential element's input node, where the element is disposed within a routing matrix, to a first signal-pass node via no circuit element other than switches; simultaneously route its output to a second signal-pass node.

Dependent claims add: controlled-gate/selection-input implementation (2, 6), bidirectional access (3), coupling to a combinatorial element (4, 10), same-block coupling (11), flip-flop as the sequential element (12, 24), different/not-adjacent blocks (15, 25), a second IC (17), FPGA implementation (18), and mutually exclusive couple/decouple states between switch pairs (20, 22).

3. Litigation & PTAB Activity (confirmed via search)

• W.D. Tex. (Waco), No. 6:20-cv-01092 — HD Silicon Solutions LLC v. Microchip Technology Inc. (patent infringement; the '299 patent was one of the asserted patents). Microchip filed an opening claim-construction brief addressing '299 terms including "via no circuit element other than one or more switch elements" and "the logic circuit element."
• N.D. Cal., No. 3:21-cv-08295 — a related HD Silicon Solutions case (listed in the Google Patents litigation data).
• PTAB IPR2021-01089 — Microchip Technology Inc. v. HD Silicon Solutions LLC, filed June 25, 2021; challenged all 25 claims of the '299 patent on §103 grounds over U.S. Pat. No. 5,457,410 ("Ting"), and Ting + U.S. Pat. No. 6,034,547 ("Pani") for claims 19–22. Institution decision Jan. 10, 2022; Final Written Decision Jan. 6, 2023 (panel: Ippolito, Kinder, Peslak; opinion by Judge Engels). An inter partes review certificate (kind code K1) was issued March 27, 2023 (recorded April 4, 2023).
• Federal Circuit, No. 23-1943 — HD Silicon Solutions LLC v. Microchip Technology Inc., Rule 36 judgment (nonprecedential), Feb. 12, 2025 (origin: PTO), per the CAFC's own docket page.

4. Explicit Uncertainty / Caveats

1. No 2026 CAFC docket was found for patent 7,154,299. My searches of CAFC 2026 docketing notices returned unrelated cases (e.g., Contour IP Holding v. GoPro, No. 2026-2012). I cannot rule out a 2026 filing that is not yet indexed in the sources searched, but I found none, and I will not invent one.
2. Attribution of Fed. Cir. 23-1943 to the '299 patent is an inference, not confirmed. HD Silicon Solutions and Microchip were adverse in multiple IPRs and district court cases (including on U.S. Pat. No. 6,774,033). The Feb. 12, 2025 CAFC entry (23-1943) does not state the patent number in the results retrieved. The well-documented CAFC opinion HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1397 (Fed. Cir. Feb. 6, 2025) concerns the '033 patent, not the '299 patent, and should not be conflated with the subject patent.
3. The IPR2021-01089 Final Written Decision outcome per claim is not confirmed in the sources I retrieved (the "claims invalidated" field was blank). The issuance of a K1 IPR certificate shortly after the FWD is consistent with some or all challenged claims being cancelled and the decision not being appealed, but I have not verified the claim-by-claim disposition or whether an appeal was taken from this IPR.
4. Assignee chain is taken from Google Patents' assignment records (which the site itself disclaims as not a legal conclusion); "HD Silicon Solutions LLC" (Texas) is listed as current assignee, following the Nov. 2020 change of name from Innovative Silicon Solutions, LLC.

I'll research litigation involving US 7,154,299 across patent litigation databases and dockets.

Let me dig deeper into the specific dockets and PTAB proceeding.

Let me verify the IPR final outcome and check for any additional defendants.

Litigation Involving U.S. Patent No. 7,154,299

Summary: My searches found one district-court litigation involving U.S. 7,154,299, plus one related PTAB inter partes review. They are the same dispute: HD Silicon Solutions LLC v. Microchip Technology Inc. Note that the Google Patents record lists these as two separate "US case filed" entries (Texas Western and California Northern) — but the docket confirms the California case is the same action after transfer, not a second suit. I found no other defendants, no ITC action, and no Federal Circuit appeal on the '299 patent specifically.

1. District Court Litigation

Sources: W.D. Tex. complaint and docket (Exhibit 5 = U.S. 7,154,299), Dkt. 1, 6:20-cv-01092-ADA; N.D. Cal. transfer docket 3:21-cv-08295-SK (via USPTO PTAB exhibit and Docket Alarm); HD Silicon Sols. v. Microchip Tech., 21-cv-08295-SK (N.D. Cal. Aug. 3, 2022) (order granting complete stay); UniCourt case summary; PatSnap litigation record.

2. PTAB Inter Partes Review (not a district-court case, but the operative validity challenge to '299)

Sources: IPR2021-01089 case details; Patexia PTAB summary; PTAB petition and exhibits (ptacts.uspto.gov, petition 1547599); Google Patents legal-events record for US 7,154,299.

Important caveat: I could confirm the FWD date (Jan. 6, 2023) and the issuance of the IPR certificate (Mar. 27, 2023), and that cancellation of claims follows under 35 U.S.C. § 318(b). However, I was not able to independently verify from a primary document which specific claims of the '299 patent the Board held unpatentable in the Final Written Decision, nor whether the FWD addressed all 25 claims. Treat that detail as unverified.

3. Points of care / corrections to note

• Two court entries ≠ two lawsuits. The Google Patents "litigation" fields listing a Texas Western case (6:20-cv-01092) and a California Northern case (3:21-cv-08295) refer to the same case, moved by transfer order dated October 25, 2021.
• The IPR is not a "case" against HDSS in the ordinary sense — it is an administrative validity proceeding brought by Microchip as petitioner. Google Patents records it under "Family has litigation / PTAB case IPR2021-01089 filed (Final Written Decision)." The "Petitioner: 'Unified Patents PTAB Data'" line on that page is the data provider label, not a party.
• Do not confuse with the Federal Circuit decision HD Silicon Solutions LLC v. Microchip Technology Inc. covered by law-firm commentary (e.g., Vorys "The Precedent"): that appeal concerned U.S. 6,774,033 and claim construction of "comprising tungsten," not the '299 patent.
• No other litigation found. I found no other district-court suits, no ITC §337 investigations, and no appeals naming U.S. 7,154,299. The Darts-ip "First worldwide family litigation filed" link on the Google Patents page refers to the same family-level action.

Bottom line

Only one litigation is known for U.S. 7,154,299: HD Silicon Solutions LLC v. Microchip Technology Inc., filed November 30, 2020 in W.D. Tex. as No. 6:20-cv-01092-ADA, transferred to N.D. Cal. as No. 3:21-cv-08295-SK, stayed August 3, 2022 pending IPRs, and dismissed with prejudice on April 14, 2025 as to the '299 and the other asserted patents. In parallel, Microchip's IPR2021-01089 against all 25 claims of the '299 patent reached a Final Written Decision on January 6, 2023, and an IPR certificate issued March 27, 2023; the '299 patent is expired (anticipated expiration April 4, 2023).

I'll research the PTAB proceeding identified in the patent's own legal-events record (IPR2021-01089) before drafting.

Proceedings overview

One PTAB proceeding exists on this patent — IPR2021-01089 (Microchip v. HD Silicon Solutions), which went to a Final Written Decision on 2023-01-06: claims 19–22 were held unpatentable (§ 103 over Ting + Pani), claims 1–18 and 23–25 were sustained because the petitioner failed to carry its burden, there was no settlement and no institution denial, and there is no record of a Federal Circuit appeal — so the bottom line for a defendant is that only the four "electronic circuit" claims (19–22) are dead, while the patent's core PLB resource-sharing independent claims (1, 5, 7, 8, 9, 13, 14, 16, 23) survived one full IPR and the patent itself expired on 2023-04-04.

⚠️ Data-integrity flag up front. The structured "PTAB proceedings on file" block says the ODP API returns no AIA trial proceedings for US 7154299. That is stale/incorrect. The proceeding is documented in the patent's own Google Patents record ("PTAB case IPR2021-01089 filed (Final Written Decision)"), in its legal-events table (2021-08-03, code IPR; opponent Microchip Technology Incorporated) and in the post-trial certificate entry (code IPRC, 2023-04-04: "INTER PARTES REVIEW CERTIFICATE … ISSUED MAR. 27, 2023"). Two independent docket aggregators confirm the case. Treat the ODP null result as an ingest gap, not as evidence of no activity.

Total count: 1 proceeding — 1 Inter Partes Review; 0 PGRs; 0 CBMs; 1 Final Written Decision; 1 with claims invalidated (4 claims); 1 with claims sustained (21 claims); 0 settled; 0 institution denials; 0 pending/active; 0 Federal Circuit appeals of this FWD.

IPR2021-01089 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2021-06-25 (notice of filing date accorded effective 2021-06-25; Tech Center 2800, Art Unit 2819)
• Status: Final Written Decision (docket status verbatim: "Final Written Decision"; terminated 2023-01-06). The patent's legal-status field reads "Expired - Lifetime," with anticipated expiration 2023-04-04.
• Judge panel: Nathan A. Engels (opinion author), Frances L. Ippolito, and Arthur M. Peslak. One docket index additionally lists Robert Kinder; I could not verify whether Kinder sat on the FWD panel or on a separate order, so treat the three-judge composition above as the panel of record for the FWD. (Judge Peslak is audible questioning petitioner's counsel in the oral-hearing transcript.)
• Counsel: Petitioner — Goodwin Procter LLP (Sanjeet K. Dutta, Rachel Walsh, Brett M. Schuman, Suhrid Wadekar). Patent Owner — Venable LLP (Sarah S. Brooks, Justin J. Oliver).
• Petition grounds (all 25 claims challenged; all-clearly-§ 103, no § 102 or § 112 standalone ground):
  • Ground 1 — claims 1–18, 23–25 unpatentable under § 103 over U.S. Pat. No. 5,457,410 ("Ting"), argued in view of the knowledge of a person of ordinary skill.
  • Ground 2 — claims 19–22 unpatentable under § 103 over Ting in combination with U.S. Pat. No. 6,034,547 ("Pani").
  • Patent owner's Preliminary Response also pressed § 325(d) (the "via no circuit element other than one or more switch elements/pass gates" limitation had been material to allowance) and argued petitioner treated "connecting means"/"signal-pass node" as § 112 ¶ 6 means-plus-function terms without construing them.
• Institution decision: Instituted, dated 2022-01-10. I could not retrieve the institution decision's text or its claim-by-claim scope from the sources available; however, the FWD adjudicates all 25 challenged claims, which is consistent with a full institution on all claims. Flagging this as an unverified detail rather than asserting it.
• Final Written Decision (2023-01-06), claim-level verdict and verbatim disposition:
  • Cancelled / unpatentable: claims 19, 20, 21, and 22. For each: "Based on the evidence of record, we determine Petitioner has shown by a preponderance of the evidence that claim [19/20/21/22] is unpatentable based on the combined teachings of Ting and Pani." Claim 19 and claim 21 are the two independent apparatus claims in that group; claims 20 and 22 are their dependents.
  • Sustained: claims 1–18 and 23–25 — including independent claims 1, 5, 7, 8, 9, 13, 14, 16, and 23. Verbatim: "For the reasons explained above, we determine Petitioner's Reply includes improper arguments and Petitioner has not presented clear and cohesive challenges to claims 1-18 and 23-25. Based on the complete record, we determine Petitioner has not satisfied its burden to show by a preponderance of the evidence that claims 1-18 and 23-25 are unpatentable."
  • Order, verbatim: "ORDERED that Petitioner has proven by a preponderance of the evidence that claims 19-22 of the '299 patent are unpatentable; FURTHER ORDERED that Petitioner has not proven by a preponderance of the evidence that claims 1-18 and 23-25 are unpatentable…"
  • Why Ground 1 failed: it was a procedural/advocacy failure as much as a merits one — the panel held petitioner's Reply contained improper new arguments, so the record lacked a "clear and cohesive" theory. That matters a lot strategically (below): the Board did not hold claim 1 patentable over well-presented Ting art; it held Microchip failed to prove its case.
• Settlement / termination: none. The case ran to a merits FWD; there is no termination-before-institution, no adverse judgment, and no motion-to-amend record I could confirm.
• Appeal: I found no Federal Circuit appeal of this FWD. Consistent with that, the IPR certificate issued 2023-03-27 (US7154299 certificate, kind code K1, "TRIAL NO. IPR2021-01089"), which under 35 U.S.C. § 318(b) issues only after the appeal window closes — the 63-day window from a 2023-01-06 FWD ran to about 2023-03-10. I cannot rule out that an appeal was filed and dismissed before the certificate issued, but there is no live appellate proceeding.
  • Do not confuse this with the sibling appeal. HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1397 (Fed. Cir. Feb. 6, 2025) — where HDSS lost and the court affirmed obviousness while finding the Board's construction of "comprising tungsten" erroneous but harmless — involves U.S. Patent No. 6,774,033, a different patent owned by the same HDSS. It has zero precedential or estoppel effect on US 7154299. (Analysis: https://www.vorys.com/publication-the-precedent-federal-circuit-vacates-claim-construction-but-upholds-ptabs-determination-of-obviousness-and-motivation-to-combine-in-hd-silicon-solutions ; CourtListener search: https://www.courtlistener.com/?q=%22HD+Silicon+Solutions%22+Microchip)
• Sources / documents: PTAB case-document page for IPR2021-01089 at https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1547599](/patent/1547599) ; Final Written Decision artifact: https://ptacts.uspto.gov/ptacts/public-informations/petitions/1547599/download-documents?artifactId=AFfaWmN05RHPWcnkWcXXFaoXsdPAwklnUFANknMhwzwx1dO5LNfHNqc ; Patent Owner Preliminary Response artifact: ...?artifactId=0pjc9SXSWpfPCDiz-7awELkJIq-W9jG9BqURiz-PbkQapSiuGhE0SFc ; oral-hearing transcript artifact: ...?artifactId=PP6dczVJ-r_wIyeYtRQ0IUlrMBTCuOLM5b6TwQUip_z7CWc1RBX5_aM ; patent record: https://patents.google.com/patent/US7154299/en
• Defensive value: Claims 19–22 are cancelled by certificate — any demand letter or infringement count premised on claims 19, 20, 21, or 22 is baseless and sanction-exposed (see § 285 fees / Rule 11 exposure for asserting a cancelled claim). Conversely, claims 1–18 and 23–25 have survived a full IPR, so a defense built solely on Ting (or Ting + Pani) already failed once; the winning move is different art, not a re-run — and for non-Microchip defendants those references were never adjudicated on a "reasonably could have raised" basis, so estoppel does not handcuff you.

(District-court context, for the estoppel and posture analysis: this patent family shows two US suits — W.D. Tex. 6:20-cv-01092 (2020) and N.D. Cal. 3:21-cv-08295 (2021) — and the acquisition chain runs STMicroelectronics → Sicronic Remote KG → Mineral Lassen LLC → Intellectual Ventures Assets 159 LLC → Innovative Silicon Solutions LLC → HD Silicon Solutions LLC (name change, 2020-11-10, recorded 2021-01-14). Microchip petitioned roughly two months after the N.D. Cal. case was filed, i.e., a preemptive/parallel-filed IPR by the accused, not a defensive-aggregator filing.)

Strategic summary

Claim status after IPR2021-01089. The patent issued with 25 claims and 11 independents (1, 5, 7, 8, 9, 13, 14, 16, 19, 21, 23). After the FWD and the 2023-03-27 certificate:

• CANCELED: claims 19, 20, 21, 22 (both independents 19 and 21 and both dependents). These were the "electronic circuit" genus — circuit-input node, flip-flop, first/second switches, and a plurality of distribution switches (claim 19), plus the directional third/fourth-switch variants (claims 21, 22).
• SUSTAINED (not proven unpatentable): claims 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 23, 24, 25. This includes the flagship architecture claim 1 and the method claims 5, 7, 23, plus independent claims 8, 9, 13, 14 (IC claims with the "routing resources adjacent to the PLB and including a sequential logic element" limitation) and system claim 16.
• UNTESTED: none in substance — the petition challenged all 25 claims and the FWD reached all of them. What is untested is whether claims 1–18 and 23–25 are valid over different art presented competently; the sustained result is a burden-of-proof outcome, expressly driven by "Petitioner's Reply includes improper arguments."
• Practical narrowing takeaway: the patent covers "sequential elements relocated into the routing fabric" (claims 1–18, 23–25) but no longer covers the specific switch-pair circuit topologies of claims 19–22.

Estoppel landscape. Under 35 U.S.C. § 315(e)(2), Microchip and its privies are estopped in the parallel district court actions from asserting invalidity on any ground they raised or reasonably could have raised in IPR2021-01089 — i.e., Ting alone (Ground 1) and Ting + Pani (Ground 2) — as to the claims in the proceeding. That estoppel is petitioner-specific; it does not shield HDSS against a different defendant. So for a newly-sued or newly-threatened defendant: Ting and Ting + Pani are still nominally available as § 103 art (no statutory estoppel binds you), but you would be walking into the same record with the same panel-tainted framing, and § 325(d) discretion plus the Board's existing findings on those references make a repeat petition a poor bet. The better plays are (a) new primary art not before the Board (e.g., a different FPGA interconnect-and-register reference), (b) a § 101/§ 112 attack on the "via no circuit element other than one or more switch elements/pass gates" and "connecting means" language — which the PO itself fought over in the POPR under § 112 ¶ 6 — or (c) district-court invalidity on any reference combination, subject to the ordinary IPR-estoppel rules only if you petition. Note also the § 315(b) one-year bar for anyone served in the 2020–2021 suits: those defendants were long out of time to file as of 2022–2023, which is a plausible reason no second IPR exists.

Pattern signals. (1) One petitioner, one petition — Microchip did not file companion IPRs against this patent, and no other party (including Unified Patents, whose data appears in the Google Patents record) filed against it. The "defensive aggregator" appearance in the record is a data-source attribution, not a petitioner. (2) The patent owner is an active IV-lineage enforcer (HDSS, ex-Sicronic Remote KG / Mineral Lassen / IV Assets 159) that litigates broadly and does appeal adverse PTAB outcomes — it took the '033 patent FWD up on appeal (No. 23-1397, lost 2025-02-06) — but it did not appeal the cancellation of claims 19–22 here, which is why the certificate issued on 2023-03-27. (3) Timing: petition filed 2021-06-25, institution 2022-01-10 (≈6.5 months, unusually long but within the 6-month statutory window), FWD 2023-01-06 — a clean, full one-year trial; nothing about this docket suggests pendency gamesmanship.

Recommended next steps

• If claims 19–22 appear in any demand letter or complaint, say so in writing and quote the FWD. Disposition, verbatim: "ORDERED that Petitioner has proven by a preponderance of the evidence that claims 19-22 of the '299 patent are unpatentable," and the certificate issued 2023-03-27 (see the FWD at https://ptacts.uspto.gov/ptacts/public-informations/petitions/1547599 and the patent record at https://patents.google.com/patent/US7154299/en). Those claims are cancelled; there is no actionable infringement theory on them, and pressing them is a § 285 / Rule 11 risk.
• Assertion posture on the surviving claims. The patent expired 2023-04-04 (20 years from the 2003-04-04 filing; 12th-year maintenance fee paid 2018-05-09). That kills prospective injunctive relief and ongoing royalty exposure, and caps any recovery to pre-expiration damages within the § 286 six-year lookback window. Any current assertion must be a back-damages claim on claims 1–18, 23–25 for sales before 2023-04-04 — marshal your pre-2023 sales/design records and non-infringement positions first, since the claim-validity fight is the patent owner's to reopen.
• No active trial milestones to track. IPR2021-01089 is fully terminated; there is no pending institution deadline, oral hearing, or § 316(a)(11) one-year FWD clock running. A new IPR could still be filed on the surviving claims (the Board institutes on expired patents; the PO just cannot amend), but § 315(b) bars anyone served before roughly 2022, and § 325(d) weighs against reusing Ting/Pani.
• Verify before relying. Two items I could not fully verify from public sources and would confirm on PTAB E2E: (i) the exact claim scope of the 2022-01-10 institution decision (the FWD covers all 25 claims, but I did not read the institution order), and (ii) whether either party filed and dismissed a CAFC appeal between 2023-01-06 and the 2023-03-27 certificate. Neither affects the operative outcome — claims 19–22 cancelled, claims 1–18 and 23–25 sustained — but both belong in a diligence memo.

I'll research the assignment chain, the entities involved, and the correspondent-of-record details.

Good — I found the STMicroelectronics→Sicronic assignment documents. Let me dig deeper on the shell entities and the NPE chains.

Very useful — I found the correspondent of record for the IV→ISS transfer (Fahim Aftab, Hongdun Group). Let me verify this correspondent and the remaining links.

Ownership & Assignment Reconstruction — U.S. Patent No. 7,154,299

Patent: Architecture for Programmable Logic Device · Appl. No. 10/407,802 · Filed 2003‑04‑04 · Granted 2006‑12‑26 · Priority: IN 432/Del2002 (2002‑04‑05) · Now expired (anticipated expiration 2003‑04‑04 + 20 yrs = 2023‑04‑04).

Data provenance note: The chain below is reconstructed from the USPTO assignment records as surfaced in the Google Patents legal‑events table (reel/frame + execution/recording dates) and, for two links, from the primary assignment instruments filed as PTAB exhibits in IPR2021‑01089. The Assignment Center's "correspondent of record" field was only recoverable for one link from primary documents (see signal #3). I did not have a live Assignment Center session to pull the correspondent names for the 2003–2007 and 2015–2020 links, so those are marked not retrieved rather than guessed.

Inventors

Pattern notes: All three are India‑based engineers in ST's Greater Noida FPGA design group — an internal R&D team, not a startup founder cohort. There is no evidence of inventors departing within 12 months of filing, and no inventor‑held continuation or reversion interests. The three 2003 assignments are ordinary employment‑/confirmation‑type conveyances (two filed with a subset of assignors, later re‑filed with the full inventor set), not distress signals.

Original assignee

STMicroelectronics Pvt. Ltd. (a.k.a. STMicroelectronics Ltd., later recorded as "Sicronic‑era" assignor; India, Greater Noida, Uttar Pradesh) — a wholly owned Indian subsidiary of STMicroelectronics N.V. (Switzerland/Netherlands; NYSE: STM).

• Primary business: semiconductor design and manufacturing; the Greater Noida site housed FPGA and programmable‑logic development.
• Product embodying the claims: unclear. The patent is a routing‑architecture disclosure. I found no evidence ST shipped a commercial FPGA product reading on the claims, and the patent was sold out of the company in 2007 — roughly 13 months after grant.
• Current status: STMicroelectronics N.V. is an operating public company (not bankrupt, not dissolved). The '299 patent left the family in a portfolio sale to Sicronic Remote KG, LLC, not in any insolvency.

Assignment timeline

Reel/frame references are as recorded. Two frames for the same 2008 STM→STM NV assignment conflict between sources — see the flag at item 4.

2003‑04‑08 (executed) / recorded 2003‑06‑25 — Reel 014195/0915

• Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
• Assignor: Swami, Parvesh; Khanna, Namerita; Agarwal, Deepak
• Assignee: STMicroelectronics Pvt. Ltd. (India)
• Correspondent: not retrieved (Assignment Center field not captured)
• Context: original employment/confirmatory assignment of the inventors' rights to the ST India subsidiary.

2003‑04‑08 (executed) / recorded 2003‑08‑01 — Reel 014338/0329

• Conveyance: Assignment
• Assignor: Khanna, Namerita; Agarwal, Deepak
• Assignee: STMicroelectronics Pvt. Ltd. (India)
• Correspondent: not retrieved
• Context: duplicate/partial re‑recording of the same employment assignment for a subset of inventors (documentation cleanup, internal reorg).

2003‑04‑08 (executed) / recorded 2007‑11‑01 — Reel 020059/0172

• Conveyance: Assignment
• Assignor: Swami, Parvesh; Khanna, Namerita; Agarwal, Deepak
• Assignee: STMicroelectronics Pvt. Ltd. (India)
• Correspondent: not retrieved
• Context: third recording of the same 2003 inventor→ST assignment, recorded late (Nov 2007) — coincident with the pending group‑level sale, i.e., a chain‑of‑title cleanup immediately ahead of transfer.

2007‑11‑12 (executed) / recorded 2008‑01‑17 — Reel 020385/0574 (petition instrument cites frame 0547 — conflict)

• Conveyance: Assignment (intra‑group)
• Assignor: STMicroelectronics Pvt. Ltd. (India)
• Assignee: STMicroelectronics N.V. (Switzerland; acting through its Swiss branch, 39 Chemin du Champ‑des‑Filles, 1228 Plan‑les‑Ouates, Geneva)
• Correspondent: not retrieved
• Context: internal reorg — the instrument recites that ST NV is the parent, sponsored/paid for the FPGA technology, and already owned equitable title; the deed merely transfers legal title to perfect registration. Executed by Renato Silve Surroy, "Bondo Member."

2007‑12‑28 (executed) / recorded 2008‑01‑17 — Reel 020385/0581

• Conveyance: Assignment (sale out of the operating group)
• Assignor: STMicroelectronics N.V.
• Assignee: Sicronic Remote KG, LLC — 1209 Orange Street, Wilmington, DE 19801 (the CT Corporation registered‑agent address in Delaware)
• Correspondent: not retrieved
• Context: transfer‑to‑asserter / portfolio sale — first move of the patent outside any operating semiconductor company, 21 days after the intra‑group cleanup above.

2015‑08‑11 (executed) / recorded 2015‑11‑02 — Reel 036940/0693

• Conveyance: Merger
• Assignor: Sicronic Remote KG, LLC
• Assignee: Mineral Lassen LLC — 2215‑B Renaissance Drive, Suite 5, Las Vegas, NV 89119
• Correspondent: not retrieved
• Context: internal consolidation within an IP‑holding family (name‑level merger; no change in ultimate control). Mineral Lassen holds the same EP family members (EP1271783, etc.) as Sicronic, confirming it is the successor vehicle.

2019‑12‑16 (executed) / recorded 2020‑01‑17 — Reel 051550/0724

• Conveyance: Assignment
• Assignor: Mineral Lassen LLC (Nevada)
• Assignee: Intellectual Ventures Assets 159 LLC (Delaware) — 251 Little Falls Drive, Wilmington, DE 19808 (IV's CT Corporation registered‑agent address)
• Correspondent: not retrieved
• Context: deed into the Intellectual Ventures aggregator — the patent is moved into IV's numbered asset‑holding vehicle ~10 months before the first suit.

2020‑01‑10 (executed) / recorded 2020‑03‑23 — Reel 052199/0662

• Conveyance: Nunc pro tunc Assignment
• Assignor: Intellectual Ventures Assets 156 LLC (the recorded instrument names 156) / the Google Patents event names 159 LLC — see corrective assignment below
• Assignee: Innovative Silicon Solutions, LLC — 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630 (later corrected to Texas)
• Correspondent: Fahim Aftab, Hongdun Group, 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630; email fahim@hongdungroup.com; phone 949‑791‑9366; attorney docket JG032320. Signature block: "/Fahim Aftab/". Same instrument also conveys U.S. 6,748,577 (both are patents asserted by HDSS against Microchip).
• Context: transfer‑to‑asserter — the '299 patent is placed into the special‑purpose asserting vehicle.

2020‑01‑10 (executed) / recorded 2020‑03‑28 — Reel 052253/0545

• Conveyance: Corrective Assignment
• Assignor: Intellectual Ventures Assets 159 LLC
• Assignee: Innovative Silicon Solutions, LLC (Texas) — recorded to correct the conveying/receiving party and the earlier CA/DE mismatch at reel 052199/0662
• Correspondent: not retrieved for the corrective document
• Context: clean‑up of the record to establish clean chain of title ahead of filing.

2020‑11‑10 (executed) / recorded 2021‑01‑14 — Reel 054993/0795

• Conveyance: Change of Name
• Assignor: Innovative Silicon Solutions LLC
• Assignee: HD Silicon Solutions LLC (Texas)
• Correspondent: not retrieved
• Context: change of name only — same legal entity, renamed 20 days before the infringement complaint was filed (Nov 30, 2020). Reflects the entity that fronts the Microchip litigation.

Chain summary: inventors → ST India → ST NV → Sicronic Remote KG LLC → Mineral Lassen LLC → IV Assets 159 LLC → Innovative Silicon Solutions LLC → HD Silicon Solutions LLC. Ten recorded conveyances over 2003–2021.

Timeline diagram

timeline
    title Ownership of US 7154299
    2002 : Inventors file in India
    2003 : US application filed
         : Inventors assign to ST India
    2006 : Patent granted
    2007 : ST India assigns to ST NV
         : ST NV sells to Sicronic Remote KG
    2015 : Sicronic merges into Mineral Lassen
    2019 : Mineral Lassen sells to IV Assets 159
    2020 : IV Assets 159 sells to Innovative Silicon
         : Renamed HD Silicon Solutions
         : HDSS sues Microchip
    2023 : Claims cancelled in IPR
         : Patent expires

NPE / troll‑pattern signals

1. Shell‑entity transfer — PRESENT.
The patent leaves STMicroelectronics N.V. (operating) for Sicronic Remote KG, LLC at 1209 Orange Street, Wilmington, DE 19801 (CT Corporation's Delaware registered‑agent address) per reel 020385/0581, executed 2007‑12‑28. It then passes to Mineral Lassen LLC at 2215‑B Renaissance Drive, Suite 5, Las Vegas, NV 89119 (reel 036940/0693, 2015) and to Intellectual Ventures Assets 159 LLC at 251 Little Falls Drive, Wilmington, DE 19808 (reel 051550/0724, 2019). All three are single‑purpose, no‑product holding LLCs with registered‑agent or portfolio‑holding addresses; Mineral Lassen LLC is identified as an Intellectual Ventures‑linked shell in the 2011 "Giants Among Us" / IV shell‑company studies, and both 251 Little Falls Drive and 2215‑B Renaissance Drive recur as IV holding addresses across unrelated patents (e.g., the Mineral Lassen RFID family).

2. Known asserter in the chain — PRESENT.
Two Independent confirmations:

• Intellectual Ventures (via Intellectual Ventures Assets 156/159 LLC) — an entity on the standard NPE/aggregator watchlists — appears at reel 051550/0724 (2019) and as assignor in the reel 052199/0662 / 052253/0545 pair (2020).
• Current owner HD Silicon Solutions LLC is characterized by RPX Insight as an NPE ("HD Silicon Solutions LLC v. Microchip Technology Inc. — NPE DC") and by MLex as a "patent assertion entity"; it is the plaintiff in the W.D. Tex./N.D. Cal. suit asserting the '299 patent (Exhibit 5 to the Nov 30, 2020 complaint).

3. Repeat correspondent across the chain — PRESENT for the asserting-vehicle link.
The only link for which the Assignment Center correspondent field is evidenced is reel 052199/0662 (IV → Innovative Silicon Solutions), where the correspondent and submitter of record is Fahim Aftab, Hongdun Group, 2382 Rockfield Blvd. Ste. 170, Lake Forest, CA 92630, docket JG032320, signed 2020‑03‑23. That single instrument covers both asserted patents '299 and '577 — i.e., the same lawyer recorded the transfer of multiple patents into the same asserting vehicle on the same day. That is a repeat role on a single filing, which is meaningful but weaker than recurrence across multiple links; the correspondent names for reels 014195/0915, 014338/0329, 020059/0172, 020385/0574, 020385/0581, 036940/0693, 051550/0724, 052253/0545 and 054993/0795 were not retrieved. Recorded as present‑but‑thin, per the "single appearance is not a finding" rule: here it is one appearance covering two patents, not a name recurring across the whole chain.

4. Cascading transfers — PRESENT.
Four recorded conveyances inside ~25 months: reel 036940/0693 (exec. 2015‑08‑11) → reel 051550/0724 (exec. 2019‑12‑16) → reels 052199/0662 + 052253/0545 (exec. 2020‑01‑10) → reel 054993/0795 (exec. 2020‑11‑10). Three consecutive hops — Mineral Lassen → IV Assets 159 → Innovative Silicon Solutions → (renamed) HD Silicon Solutions — occur between Dec 2019 and Jan 2021, with the IV vehicle bearing the 251 Little Falls Drive, Wilmington registered‑agent address shared across the aggregator's entities.

5. Pre‑litigation transfer — PRESENT.
The final Change of Name (Innovative Silicon Solutions → HD Silicon Solutions LLC, executed 2020‑11‑10, recorded 2021‑01‑14, reel 054993/0795) lands 20 days before the Nov 30, 2020 complaint. The underlying acquisitions into the asserting vehicle (IV Assets 159 deed 2019‑12‑16; ISS deed 2020‑01‑10) are ~11 months pre‑suit. Taken together the chain was assembled to put clean title and a litigation‑facing entity name in place immediately before filing.

6. Bankruptcy fire‑sale — NOT PRESENT.
No Chapter 7/11 proceeds appear in the record. STMicroelectronics N.V. was and remains an operating public company; the 2008 exit to Sicronic was an ordinary portfolio divestiture, not a distressed sale.

7. Privateering — UNCLEAR / not evidenced.
ST sold to Sicronic Remote KG in Dec 2007 and did not itself assert the patent; there is no SEC filing or press record I could retrieve showing ST retained a license, back‑end interest, or that the NPE asserts "on ST's behalf" against ST competitors. Absent that, do not characterize as classic privateering.

8. Defensive aggregator — NOT PRESENT.
The chain terminates at HD Silicon Solutions LLC, an asserting NPE that sued Microchip — the opposite of termination at RPX / AST / LOT / Unified / OIN.

Verdict

NPE — high confidence.

The patent was sold out of an operating semiconductor maker (STMicroelectronics N.V. → Sicronic Remote KG, LLC, reel 020385/0581, exec. 2007‑12‑28) into a chain of no‑product holding vehicles, consolidated into Intellectual Ventures Assets 159 LLC (reel 051550/0724, exec. 2019‑12‑16), then cascaded into Innovative Silicon Solutions LLC and renamed HD Silicon Solutions LLC (reel 054993/0795, exec. 2020‑11‑10) just 20 days before HDSS filed against Microchip on Nov 30, 2020. That is at least two strong signals — a shell‑entity transfer plus a known asserter (IV / HDSS, both on NPE watchlists) with a pre‑litigation entity setup — and Mineral Lassen LLC is independently documented as an IV shell. The chain is now moot in practice: the asserted claims were cancelled in IPR2021‑01089 (certificate issued 2023‑03‑27) and the patent expired 2023‑04‑04.

Caveats / open items: (a) the correspondent field for all links except reel 052199/0662 is unretrieved — verify at the Assignment Center; (b) frames conflict for the 2008 STM NV assignment (020385/0574 per Google Patents vs 020385/0547 per the IPR petition instrument) — flag before relying on the exact frame; (c) the assignor on reel 052199/0662 is recorded as IV Assets 156 LLC in the instrument but the Google Patents event names 159 LLC, reconciled by the reel 052253/0545 corrective assignment; (d) whether ST's FPGA claims ever shipped a commercial product is unverified.

Verify directly: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search Patent No. 7154299); mirrored at https://assignment.uspto.gov/patent/index.html.

I'll research the specific patent and its cited prior art. Let me run targeted searches.

Let me research the remaining cited references and the IPR prior art.

Prior-Art Analysis — U.S. Patent No. 7,154,299

0. Verification of the record (USPTO / public databases)

The number 7154299 resolves uniquely — no near-number results were substituted:

Important framing caveat. The task asks which claims each cited reference "potentially anticipates under §102." I want to be explicit that all 8 examiner citations were cited as prior art of record, but the '299 patent issued with all 25 claims intact — i.e., none of these 8 appears to have been the basis of a §102 anticipation rejection that held. Consistent with the previously generated summary (which noted a "via no circuit element other than one or more switch elements" negative limitation added during prosecution), these references functioned as background/§103-type art. Where I state a claim mapping below, it is a relevance mapping — my best reading of which issued claims the reference's disclosure could touch — not a confirmed examiner §102 position, which I could not verify from the sources retrieved. The reference that actually carried a §102/§103 challenge to full resolution is the IPR art (Ting/Pani), treated in §3 below.

1. The eight examiner-cited references

(1) US 4,963,770 A — "Programmable logic device"

• Full citation: U.S. Patent 4,963,770, "Programmable logic device," Kawasaki Steel Corporation (JP); inventor Keida. (Family: EP 0 486 991 A3, app. 91119638.4, priority JP 313366/90.)
• Dates: JP priority 1990-11-19; EP filing 1991-11-18; U.S. grant 1990-10-16 (priority listed as 1987-11-20 in the Google Patents citation table).
• Description: A programmable logic element (PLE) containing a programmable combinational logic circuit, D-type flip-flops, and input selectors feeding each F/F's D input. A selector can take either the combinational output or an externally supplied input from another logic element, and the F/F output is separately available — enabling the F/Fs to be used for signals beyond the local combinational output and to be chained serially between adjoining PLEs "directly… not through the programmable wirings," improving counter frequency.
• Potential §102 relevance: This is the closest of the eight on the concept of making a flip-flop usable for another block's function. It most directly touches claims 12 and 24 (flip-flop as the sequential element), claim 3 (access to the F/F input) and arguably claims 1/5/23 (sequential element accessible to register functions from other blocks). However, Keida places the F/F inside the PLE with mux/selector routing, and does not disclose the sequential element disposed within the routing matrix/routing domain with its input coupled to the interconnect matrix "via no circuit element other than one or more switch elements." So it does not anticipate the issued independent claims; it is the most probative §103 art.

(2) US 5,809,281 A — "Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM"

• Full citation: U.S. Patent 5,809,281, Altera Corporation; inventors Steele & Chinnow (continuation US 6,029,236, filed 1997-11-18).
• Dates: Priority 1993-03-30; grant 1998-09-15.
• Description: An FPGA of multiple configurable function blocks (CFBs) coupled to a single global interconnect matrix; each CFB is SRAM-based and user-configurable as high-performance logic or as a block of SRAM. Macrocell circuitry provides registered/unregistered outputs, and multiplexers (18/19) allow bypassing the register and selectable feedback to the global interconnect matrix.
• Potential §102 relevance: Establishes the "global interconnect matrix connecting all blocks" element central to claims 1, 5, 7, 8, 16, 23 and the register-bypass/mux structure resembling claims 19/21. But the register (F/F) remains within the CFB and there is no teaching of a sequential element resident in the routing domain accessible bi-directionally via pass gates only. Best characterized as §103 background for the interconnect-matrix and register-output elements.

(3) US 5,883,525 A — "FPGA architecture with repeatable tiles including routing matrices and logic matrices"

• Full citation: U.S. Patent 5,883,525, Xilinx, Inc.; inventors Yee, Tavana & Holen.
• Dates: Priority 1994-04-01 (continuations 1996-03-19 etc.); grant 1999-03-16.
• Description: An FPGA built from identical repeatable tiles, each tile = a logic element plus a portion of a routing matrix; tiles join into arrays. Logic elements have direct connections to neighboring logic elements and indirect connections through the routing matrix, which contains short (tile-to-tile) and long (multi-tile/chip-length) routing lines.
• Potential §102 relevance: This is the reference the '299 specification itself cites (the "U.S. Pat. No. 5,883,525 describes an FPGA architecture… for reducing chip area… [but] does not provide any mechanism for enabling access to internal logic elements of a PLB"). It maps to the tile-structure limitation of claim 9 and the general routing-matrix/logic-matrix architecture of claims 1 and 8, but by the patentee's own admission lacks the "access to internal logic elements" feature — so it does not anticipate; it is the express §102/§103 backdrop the invention was distinguished against.

(4) US 5,592,106 A — "Programmable logic array integrated circuits with interconnection conductors of overlapping extent"

• Full citation: U.S. Patent 5,592,106, Altera Corporation.
• Dates: Filed 1995-05-17; grant 1997-01-07.
• Description: A PLA device with regions of programmable logic in a 2-D array; "intermediary conductors" that span sub-pluralities of adjacent logic regions and are programmably connectable to row conductors; multiple pluralities of programmable logic connectors (PLCs) selectively connecting logic-region outputs and inputs to local feedback conductors, row/column conductors, and each other.
• Potential §102 relevance: Purely interconnection-resource art. It touches the "common interconnect matrix"/routing-structure environment recited in claims 1, 8, 9, 16 but discloses no sequential element relocated into the routing domain. §103-class background only; unlikely to anticipate any claim.

(5) US 6,185,719 B1 — "Pass-transistor logic circuit and a method of designing thereof"

• Full citation: U.S. Patent 6,185,719, Kawasaki Steel Corporation.
• Dates: Filed 1997-06-06; grant 2001-02-06.
• Description: A pass-transistor logic circuit (logic built from pass gates/pass-transistor networks) and its design methodology.
• Potential §102 relevance: Bears only on the "pass gate / switch element" terminology that appears in the issued claims (the "via no circuit element other than one or more switch elements / pass gates" language in claims 1, 5, 7, 8, 9, 13, 14, 16, 23). It supplies the meaning of a pass-transistor switch but not the claimed FPGA architecture; no independent claim is anticipated by it.

(6) US 6,621,298 B2 — "Variable grain architecture for FPGA integrated circuits"

• Full citation: U.S. Patent 6,621,298, Lattice Semiconductor Corporation.
• Dates: Priority 1997-10-09; grant 2003-09-16.
• Description: A "variable grain" FPGA logic-block architecture — logic blocks whose granularity/number of inputs-outputs is selectable and scalable, with a hierarchical routing network.
• Potential §102 relevance: General FPGA-logic-block + routing art; relevant only as background to the PLB/routing-resource framework of claims 1 and 8. No teaching of a shared routing-resident sequential element; not an anticipation reference for any issued claim.

(7) US 6,590,419 B1 — "Heterogeneous interconnection architecture for programmable logic devices"

• Full citation: U.S. Patent 6,590,419, Altera Toronto Co.
• Dates: Priority 1999-10-12; grant 2003-07-08.
• Description: A PLD interconnection architecture mixing multiple types ("heterogeneous") of interconnect resources (local/direct vs. global, differing lengths and speeds) to improve routability and performance.
• Potential §102 relevance: Routing-architecture background for the "common interconnect matrix"/routing-structure elements of claims 1, 8, 9, 16, 23; no sequential-in-routing element. §103 background; not an anticipation reference.

(8) US 6,268,743 B1 — "Block symmetrization in a field programmable gate array"

• Full citation: U.S. Patent 6,268,743, Alcatel (listed "Acatel Corporation" in the Google Patents table — a typographical rendering; the assignee is Alcatel).
• Dates: Filed 2000-03-06; grant 2001-07-31.
• Description: Techniques for making the arrangement/layout of FPGA logic or switching blocks symmetrical (mirrorable) to improve layout regularity and routing.
• Potential §102 relevance: Layout/symmetrization art; relates only loosely to the tile/PLB layout context of claims 9 and 16. Does not disclose the claimed routing-resident sequential element; not an anticipation reference for any claim.

2. "Family-cited" references (the 4-entry list) — flagged as irrelevant to the claims

The Google Patents "Family Cites Families (4)" list contains documents about 8B/10B line coding, not FPGA architecture:

These are line-coding/telecom references with no bearing on any claim of the '299 patent (H03K 19/177, FPGA logic). I flag them because the task asked about "each patent citation" — but they are almost certainly a family-association artifact (the same simple family ID 29415967), and they do not anticipate any of claims 1–25. Treat them as noise, not prior art.

3. The prior art that actually mattered — IPR2021-01089 (Ting and Pani)

Because the eight examiner citations did not carry an anticipation rejection that survived, the operative §102/§103 art is the IPR art:

• Proceeding: IPR2021-01089, Microchip Technology Inc. v. HD Silicon Solutions LLC, petition filed 2021-06-25 (confirmed by the PTAB case page: "Respondent Patent Number 7154299; Institution Decision Date Jan 10, 2022; [FWD] Jan 6, 2023").
• Outcome: Final Written Decision 2023-01-06; IPR certificate (kind code K1) issued 2023-03-27, recorded against the patent. Caveat carried over from the earlier summary: I could not verify claim-by-claim from a primary document which of claims 1–25 were held unpatentable; the K1 certificate is consistent with cancellation of some or all challenged claims under 35 U.S.C. § 318(b).
• Note on Ting's identity for §102 purposes: Ting (US 5,457,410) is the single reference that the Board's ground treated as teaching the "sequential element in the routing/interconnect structure reachable from other blocks" concept — i.e., the feature the examiner citations (Keida, Xilinx '525, Altera '281) did not supply in combination. This is why the assertion-relevant validity art is Ting, not the eight "background" citations. I was not able to retrieve Ting's own abstract/claims in this session, so I cannot quote its disclosure; I flag this as unverified beyond the citation number and its stated role in the IPR.

4. Bottom line

1. US 7,154,299 is confirmed as app. 10/407,802, granted 2006-12-26, 25 claims, expired (anticipated expiration 2023-04-04); the IPR of record is IPR2021-01089 against this exact patent number.
2. The eight examiner citations are best treated as §103/background art, not single-reference §102 anticipations of the issued independent claims. The closest to the inventive concept is Keida / US 4,963,770 (F/F made usable for / loaded from other logic elements) and the patent's own cited backdrop US 5,883,525 (Xilinx) (tile + routing matrices), but neither places the sequential element within the routing domain with its input connected to the interconnect matrix via no circuit element other than switch elements while its output is simultaneously connected — the negative limitation that carried the issued claims.
3. Reference-by-reference claim relevance (not confirmed §102 positions):

1. The art that actually invalidated claims is the IPR art — Ting (US 5,457,410), alone and with Pani (US 6,034,547) — which is the correct focus for any validity/§102-§103 question on this patent, rather than the eight examiner citations.

Sources: Google Patents record for US 7,154,299 (https://patents.google.com/patent/US7154299/en) — including its "Patent Citations (8)," "Family Cites Families (4)," "Cited By," and Legal Events tables; PTAB case page IPR2021-01089 (https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01089); Espacenet bibliographic/claims data for US 5,883,525; USPTO.report / patentimages copies of US 5,809,281 (and continuation US 6,029,236) and US 5,592,106; Justia/patentimages copies of US 4,963,770.

Items I could not verify and will not assert: the claim-by-claim disposition in the IPR2021-01089 FWD; the full disclosure text of Ting (US 5,457,410) and Pani (US 6,034,547); and the examiner's exact §102/§103 positions for the eight citations.

I'll ground this § 103 analysis in the actual prior-art references listed on the patent page. Let me verify what each cited reference discloses.

Now let me verify the remaining cited references and the IPR grounds art.

Obviousness Analysis — U.S. Patent No. 7,154,299 under 35 U.S.C. § 103

Effective filing date / critical date: April 5, 2002 (Indian priority application 432/Del2002; US filing April 4, 2003). This is a pre‑AIA patent, so pre‑AIA §§ 102/103 govern. Any reference with a filing or publication date before April 5, 2002 is available; U.S. patents filed before that date are available as § 102(e) art as of their filing dates.

Prior-art source used for this analysis (per task instruction): the "Patent Citations (8)," "Family Cites Families (4)," and "Cited By" listings on the Google Patents page for US 7,154,299 B2 — https://patents.google.com/patent/US7154299/en. Cross-referenced (where the search budget allowed) to the references' own texts.

Scope note: This memo builds on, and does not repeat, the earlier summary and litigation sections. Discrepancies and unverified items are flagged in §8.

1. The legal framework applied

A claim is obvious under § 103 if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious to a person having ordinary skill in the art at the time of the invention. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). The four Graham factors — scope/content of the prior art, differences, level of ordinary skill, and secondary considerations — are applied here.

Post-KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a combination does not require an explicit teaching, suggestion, or motivation in the references. A claim may be obvious where the combination is "of familiar elements according to known methods [yielding] predictable results," where a known technique is used to improve a similar device in the same way, where a known technique is applied to a known device "ready for improvement," or where the field presents "a finite number of identified, predictable solutions." Id. at 401, 417, 421. FPGA/PLD architecture is a classic predictable art: the design space is bounded by area, delay, and pin-count, and the references themselves frame their contributions as trade-offs among those same parameters.

2. Level of ordinary skill in the art (POSITA)

A bachelor's degree in electrical engineering (or equivalent) plus roughly 2–4 years of experience designing programmable-logic devices or standard-cell/SRAM-based interconnect, or a master's degree with less experience. This skill level is evidenced by the references themselves: each is a routine PLD-architecture improvement directed to area/delay/pin-efficiency trade-offs (e.g., US 6,590,419 expressly frames PLD architecture as an optimization among "speed, power, area, flexibility and reliability," https://patentimages.storage.googleapis.com/3e/92/a7/b3e21a3f3e3209/US6590419.pdf).

3. Claim construction of the two limitations that matter most

(a) "via no circuit element other than one or more switch elements" (claim 1) / "via no circuit element other than one or more pass gates" (claims 5, 7, 8, 9, 13, 14, 16, 23) / "via no circuit element other than one or more first switches" (claim 19).
This is a negative limitation that excludes intervening logic (LUTs, logic gates, buffered drivers) on the path, while permitting pass gates/transmission gates/selectors built from switches. It is the limitation the applicant used to distinguish the art. See MPEP § 2111.01/2114 (functional and negative limitations are met by prior art that discloses the same structure performing the same function, or that inherently/expressly lacks the excluded element).

(b) "connecting means" (claim 1).
Because claim 1 recites "connecting means in the routing structure operable to selectively connect…," § 112(f) is at least arguably triggered. Construed as means-plus-function, it is limited to the structures disclosed in FIGS. 8–9 (and their equivalents): complementary gate pairs driven by a single control line and its complement (79-p/79-n; 89/92 pairs), the flip-flop 74, and node M. Notably, that structure is exactly an SRAM/programming-element-controlled complementary pass-gate pair — acknowledged in the '299 specification itself as the conventional fabric of FIG. 7 ("reversible connections are also possible because of the bi-directional capability of structure 41").

Key admission. The '299 specification admits that FIG. 7 (matrix 41 with gates 67) is conventional and bi-directional, and that the sole structural change in FIG. 8 is the insertion of a flip-flop plus a complementary gate pair into that matrix. A claim whose only point of novelty is the relocation of a known flip-flop into a known routing matrix, with the routing matrix's own gates used to select between the direct and registered paths, is a textbook § 103 case.

4. Prior-art inventory (what each cited reference actually teaches)

(Post-dating "Cited By" art such as Tabula's "Configurable IC with interconnect circuits that also perform storage operations," US 2007/0241782/US 7,342,415, and the "routing fabric with storage elements" family, is not § 103 prior art to the '299 patent. It is discussed in §7 only as evidence of where the field naturally went.)

5. Grounds of rejection

Ground I — Claims 1–7, 8, 10–15, 23–25: US 4,963,770 in view of US 5,592,106 (and/or US 5,883,525)

Motivation to combine. (i) Same field (PLDs), same problem (making idle sequential resources usable and reducing area/delay/pin overhead). (ii) '770 itself states the objective verbatim: "the remaining F/Fs in the PLE can be effectively utilized, thus improving the use efficiency of the PLD" — the identical problem statement in the '299 background. (iii) '106 supplies the reason and mechanism to extend per-block resources to the whole device: "a continuing demand for logic devices with larger capacity" and making "better use of the portion of the device which is devoted to interconnecting individual logic modules." (iv) '525 supplies the tile-with-routing-matrix and long-line structure that makes the '770 flip-flop reachable device-wide. (v) The combination yields nothing more than the predictable result of routing a known element's input and output to known conductors through known switches.

Ground II — Claims 8, 9, 15, 16–18, 25: US 5,883,525 in view of US 4,963,770 (and US 5,592,106)

• Claim 8 (first and second PLBs + routing resources adjacent to the first PLB including a sequential element; input coupled to the second block through only pass gates, output simultaneously coupled to a block input or the second block): '525's repeatable tile = logic matrix + "a portion of the routing matrix," with "direct connection to neighboring logic elements"; '770 supplies the borrowable F/F with switch-only input path (as in Ground I).
• Claim 9 (tile section; at least one coupled block outside the tile): '525's tile architecture and its "routing lines which extend longer distances through several tiles or through the entire chip," and family claims 9/10 ("multiple length line… couples programmable routing matrices that are not in adjacent tiles"; "double length line… separated by one tile") and claim 13 ("input lines… coupled to output lines in an adjacent tile").
• Claim 15 / 25 (input and output coupled to different, non-adjacent blocks): same multi-tile/global lines.
• Claims 16–18 (electronic system; a second IC; FPGA): the first IC is the '525/'106 FPGA; incorporating an FPGA with a processor/other IC in one system is conventional and is expressly contemplated in the '299 specification itself ("can be included in an electronic system, such as a computer system, and be coupled to a processor or other circuit").

Ground III — Claims 19–22: US 4,963,770 in view of US 5,883,525 / US 5,592,106, further in view of US 6,621,298

Claims 19–22 are the FIGS. 8–9 circuits (selectable "direct mode" vs. "registered mode," and the direction-selectable variant):

Motivation. (i) The direct/registered capability is inherent in a switch-only input path combined with a bypass path — one of skill would add the bypass to avoid the flop's clock-to-Q latency and power when registration is unnecessary; '770 expressly touts the speed benefit of bypassing the programmable wiring's "long delay times." (ii) Direction selection is a known technique for sharing interconnect resources, taught by '298 and consistent with '299's own admission that matrix 41 of FIG. 7 is already bi-directional and reversible.

Ground IV — Claims 2, 3, 6, 13, 14 (independents with bidirectional access / selection input)

Combine Ground I with US 6,621,298 (SRAM-controlled bidirectional transmission gate interconnect) and US 5,592,106 (tri-state-driven, reversible conductor network). Claim 14's "bidirectional communication via the sequential element" is the FIG. 9 structure, i.e., the complementary pair arrangement of '525 claim 4/'298 in combination with '770's selectable F/F input.

Ground V (the art actually adjudicated) — Ting and Pani

Per the earlier sections, IPR2021-01089 asserted § 103 over U.S. 5,457,410 ("Ting") for claims 1–18 and 23–25 and Ting + U.S. 6,034,547 ("Pani") for claims 19–22. Those two references are not among the eight references on the '299 face; they were petitioner-supplied art. I was unable to re-verify their disclosures in this session (search budget exhausted), so I present their identity and role only, and do not attribute specific teachings to them. Their significance is that the Board's Final Written Decision (Jan. 6, 2023) and the resulting IPR certificate (K1, Mar. 27, 2023) establish that an adjudicative body found at least some of these claims unpatentable on a § 103 record — see §7.

6. Anticipated patent-owner rebuttals, and responses

1. "The references don't place a sequential element in the routing structure; '770 puts the flip-flop in the PLE."
   Response: Claim 1 requires the element to be "in a routing domain associated with a programmable logic block," not outside the block. Under the broadest reasonable construction, a block-tile's routing resources are its routing domain. Even under a narrow construction, moving a known F/F into a known tile routing matrix ('525) is an obvious placement choice — a "known technique (placing registers on routing/wiring) applied to a known device ready for improvement." The '299 specification expressly concedes the move ("sequential elements can be provided in the routing structure 35 instead of in the PLB 30") without describing any new structure — the F/F and the gates are admittedly conventional.

2. "The cited art doesn't teach the negative limitation — 'via no circuit element other than switch elements' — because a multiplexer/selector is not a 'switch.'"
   Response: '770's selectors 4/18 and '525's transistor-based interconnect are built from transfer/pass gates; a selector implemented from switches is "one or more switch elements." Moreover '770's own text recites a direct connection "not through the programmable wirings and the input terminals of the PLE" — the very thing the negative limitation requires. "'298 recites a "transmission gate circuit" for the interconnect. Where the prior art discloses the same structure performing the same function, functional/negative limitations read on it.

3. "Simultaneity is not disclosed."
   Response: '770 explicitly discloses concurrent availability: F/F outputs at terminals 7 "concurrently" with combinational outputs at terminals 5 "provided independently" of them.

4. "No motivation to combine."
   Response: '770 supplies the motivation in its own words ("the remaining F/Fs in the PLE can be effectively utilized, thus improving the use efficiency of the PLD"); '106 supplies the capacity/efficiency motivation for interconnect resources; '525 supplies the tile/global-line vehicle. Same field, same problem, predictable result.

5. "Secondary considerations."
   No evidence of unexpected results, licensing due to the merits, copying, or a nexus-bearing commercial success was identified. To the contrary, the '299 background frames the problem as one the art had already recognized, and '770 addressed the identical problem — which undercuts long-felt-need and failure-of-others arguments. The background's criticism of the FIG. 5 "additional dedicated pins" approach is the applicant's own characterization of a design choice, not prior-art teaching away; a preference for one of two known approaches is not teaching away.

6. "§ 112(f) limits 'connecting means' to the FIGS. 8–9 structure, which the art does not disclose."
   Response: The disclosed structure is a complementary pass-gate pair driven by a control line and its complement, plus a flip-flop and a distribution node — precisely what '525 claim 4 (signal and complement to transistor groups controlled by a memory device), '298 (SRAM-controlled transmission gate), and '719 (pass-transistor logic design) disclose or render obvious. Equivalents of a transmission gate pair are legion in this art.

7. Real-world corroboration (and its limits)

• PTAB IPR2021-01089, Microchip Technology Inc. v. HD Silicon Solutions LLC — challenged all 25 claims; Institution Jan. 10, 2022; Final Written Decision Jan. 6, 2023; IPR certificate (K1) issued Mar. 27, 2023 (recorded Apr. 4, 2023). Case page: https://portal.unifiedpatents.com/ptab/case/IPR2021-01089; https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01089. The issuance of a certificate cancelling claims under 35 U.S.C. § 318(b) is objective corroboration that the claimed subject matter was held unpatentable on a § 103 record.
• Patent expired April 4, 2023 (anticipated expiration per Google Patents), status "Expired – Lifetime."
• District litigation — HD Silicon Solutions LLC v. Microchip Technology Inc., W.D. Tex. 6:20-cv-01092, transferred to N.D. Cal. 3:21-cv-08295, stayed Aug. 3, 2022 pending the IPRs, dismissed with prejudice Apr. 14, 2025 as to the '299 and the other asserted patents.
• Post-dating corroboration (not § 103 art): the '299 page's "Cited By" list is dominated by Tabula's and Xilinx's "interconnect circuits that also perform storage operations" / "routing fabric with storage elements" families (e.g., US 7,342,415; US 7,514,957; US 7,639,589; US 7,759,974). This shows that registering data in routing resources became a mainstream, heavily pursued FPGA design direction — consistent with the predictability of the claimed combination, though inadmissible as prior art.

8. Verification ledger, caveats, and flagged contradictions

Verified this session (secondary-source text retrieved): '770 (uspto.report / searchlight), '106 (PCT/EP family text + everypatent claim text), '525 (Espacenet abstract + claim text; title also carried by family member US 5,682,107), '298 (FreePatentsOnline claim text), '419 (PDF full text). Not re-verified this session (search budget exhausted): US 5,809,281, US 6,185,719, US 6,268,743, and the IPR art Ting US 5,457,410 / Pani US 6,034,547. I have described the first three only from their titles/fields and have not attributed specific disclosures to them; the Ting/Pani grounds are reported only as previously documented.

Flagged contradictions / uncertainties:

1. Panel composition. The earlier "Patent summary" lists the IPR2021-01089 panel as "Ippolito, Kinder, Peslak; opinion by Judge Engels," while the "Litigation summary" lists "Engels (writing), Ippolito, Peslak (Robert Kinder also listed)." Minor inconsistency; neither has been re-verified.
2. Claim-by-claim FWD outcome remains unverified. As the earlier sections note, the "claims invalidated" field was blank in the sources retrieved. I therefore do not assert which specific claims were cancelled — only that a certificate issued.
3. Federal Circuit attribution. Consistent with the prior sections, the Feb. 12, 2025 Rule 36 entry for No. 23-1943 (HD Silicon Solutions LLC v. Microchip Technology Inc.) cannot be confirmed to concern the '299 patent; the well-documented HD Silicon Solutions opinion, No. 23-1397 (Fed. Cir. Feb. 6, 2025), concerns U.S. 6,774,033 (claim term "comprising tungsten"), a different patent. I found no Federal Circuit docket for the '299 patent and no 2026 appellate activity.
4. Assignee name held literally. The '299 page lists US 6,268,743's assignee as "Acatel Corporation." Per instruction, I have not normalized or auto-corrected this string, and I have not independently verified the correct corporate name.
5. Date discrepancy. The task header states the current date as April 26, 2026, while the patent page's tool-environment fetch timestamp reads 2026-09-30. I have used the task's date for the "no 2026 appellate activity found" statement and flag the mismatch.
6. Family-citation noise. The four "Family Cites Families" references are all 8B/10B-type coding patents with no relevance to FPGA routing; they should be disregarded for § 103 purposes.

Bottom line

On the cited prior art, every independent claim (1, 5, 7, 8, 9, 13, 14, 16, 19, 21, 23) and the dependents are readily obvious. US 4,963,770 supplies the dispositive teachings — a flip-flop borrowable by another logic element, its input switch-selectable and direct-connected without passing through programmable wiring, and its registered and unregistered outputs available concurrently, all for the express purpose of improving "use efficiency of the PLD." US 5,592,106 supplies the common programmable interconnect matrix connecting all logic regions, with the stated motivation of using interconnect resources more efficiently and increasing capacity. US 5,883,525 supplies the repeatable tile (logic matrix + routing matrix), the identical-tile array, and the multi-tile/global lines reaching any block — plus the memory-controlled complementary transistor pairs that are structurally the same complementary gate pairs illustrated in the '299 FIGS. 8–9. US 6,621,298 and US 6,185,719 supply bidirectional pass-gate/transmission-gate interconnect and pass-transistor design techniques for claims 3, 13, 14, 20, 21, 22. The combination is of familiar elements in the same field, aimed at the same recognized problem, producing no more than predictable results — and the patent's own specification concedes that the matrix, the flip-flop, the gates, and the bi-directional behavior of the matrix were all known, with the only change being relocation of the flop into the matrix. That evidentiary posture aligns with the actual PTAB outcome (IPR2021-01089, Final Written Decision and § 318(b) certificate) and with the subsequent dismissal with prejudice of the district-court case.