US 7091904

I'll search for authoritative information on US patent 7091904, including any CAFC 2026 docket activity.

Let me check for litigation and any Federal Circuit activity specifically tied to this patent.

I have enough to answer. One more check on any current 2026-level docket activity.

Summary of US Patent 7,091,904 B2

Important caveat on one part of your request: I searched for CAFC (Federal Circuit) 2026 docket activity tied to this patent and found no evidence of any 2026 Federal Circuit appeal involving 7,091,904. I do not have direct access to the CAFC docket database (PACER/CM-ECF) or the USPTO Patent Center as a live query tool, so this is a "no results found" statement, not proof of non-existence. The historical litigation I did find is the 2007–2008 ITC investigation, described below.

Bibliographic data

Source: https://patents.google.com/patent/[US7091904](/patent/US7091904)/en

Abstract (as published)

"A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications."

Plain-language overview of the independent claims

The three independent claims share the same skeleton — a single-chip GPS baseband "tracker" architecture built around a bus with a CPU core, cache, RAM, ROM, and a GPS/WAAS engine — and they differ mainly in what they add on top of that skeleton.

Claim 1 — the multi-protocol interface claim (the core claim).
A GPS architecture for tracking at least one GPS satellite, comprising:

• a bus structure;
• a CPU core containing a microprocessor, coupled to the bus;
• a cache memory (for storing software code) coupled to the bus;
• a RAM (for storing data) coupled to the bus;
• a ROM (for storing a boot program) coupled to the bus; and
• a GPS engine that includes a receiving, tracking, and demodulating engine for both GPS and WAAS signals;
• wherein the architecture can couple to at least two different protocol interfaces via a multiple-protocol interface to the bus structure, and that multiple-protocol interface is compatible with those at least two different protocol interfaces.

In plain terms: one integrated GPS baseband chip that can talk to the outside world over more than one serial/peripheral protocol, rather than being hard-wired to a single host bus.

Claim 11 — the autonomous-code claim.
Same architecture, but the RAM stores not only data but also "autonomous code used for tracking at least one GPS satellite"; the claim adds "a multiple-protocol interface to the bus structure" and the GPS/WAAS engine; and it requires that the GPS engine can selectively use the stored autonomous code to track a satellite. In plain terms: the chip can, at its option, run self-contained (autonomous) tracking code out of RAM — an on-chip self-sufficiency feature, consistent with the spec's discussion of an "autonomous mode … to acquire, and track the GPS signal without any external intervention by the user."

Claim 21 — the auto-detect claim.
Same architecture again (bus, CPU core, cache, RAM, ROM, GPS/WAAS engine), wherein the architecture can couple, via a multiple-protocol interface to the bus structure, to at least two different protocol interfaces, and wherein the protocol interface is selected by the GPS architecture automatically. In plain terms: the chip senses/detects the environment and self-selects which protocol it is speaking, rather than being told in advance. This maps directly onto the spec's statement that "the architecture 100 can be auto-detecting in nature, where the architecture senses the presence or absence of certain signals … determines which protocol the architecture 100 is connected to."

Selected dependent claims worth noting:

• Claim 8 (and its mirror claim 12) defines the protocol-interface group as "I2C, CAN, PWM, SPI, J1850, USB, GPIO, MOST, parallel, and an address/data bus interface." (In the OCR text of claim 12 the group is rendered with OCR artifacts — "SIN" for SPI and "goup" for group.)
• Claim 9 / 19: protocol interface selected a priori; claim 10 / 20: selected by sensing a signal on the interface.
• Claim 2 / 13: cache memory usable as a local RAM. Claim 3 / 14: CPU can run non-GPS applications. Claim 4 / 15: GPS engine further comprises a beacon processor. Claim 5 / 16: GPS engine runs on a separate bus structure. Claim 6 / 17: GPS engine receives inputs from an external real time clock. Claim 7 / 18: further comprises a bus interface unit (BIU).

Litigation history I could confirm

• ITC Investigation No. 337-TA-596, Certain GPS Chips, Associated Software and Systems, and Products Containing Same. Instituted March 13, 2007 (72 Fed. Reg. 11378) on a complaint filed Feb. 8, 2007 by SiRF Technology, Inc. The '904 patent was one of four patents asserted: 6,304,216; 7,043,363; 7,091,904; and 7,132,980. Respondent: Global Locate, Inc. (San Jose, CA); Broadcom, Inc. was later added. The complaint/notice was amended to add claim 2 of the '904 patent (Order No. 19, July 24, 2007; Commission declined review, notice issued Aug. 15, 2007). The investigation was subsequently terminated with respect to the '904 patent (along with the '980 patent and certain claims of the '216 and '363 patents). The ALJ's final initial determination of June 13, 2008 found no violation of section 337, and the Commission extended its review deadline to Aug. 14, 2008.
  Sources: https://www.federalregister.gov/api/v1/documents/E7-4555 ; https://www.usitc.gov/secretary/fed_reg_notices/337/337-ta-596.1214421750_0.pdf ; https://www.govinfo.gov/content/pkg/FR-2007-08-21/pdf/07-4066.pdf
• Google Patents also flags "First worldwide family litigation filed" via Darts-ip (family 23186101) and the ITC case linkage to 337-TA-596.

What I could not confirm

• No CAFC 2026 docket entry for 7,091,904 was found. The June 2026 Federal Circuit scheduled-cases list I retrieved shows unrelated matters (e.g., a ParkerVision v. Qualcomm appeal, 26-1033). If you need a definitive answer, that must be checked against the CAFC docket (CM/ECF) and/or PACER directly.
• The "Prior art date 2001-07-18" on Google Patents is stated as an assumption; the statutory filing date on the face of the record is July 18, 2002, with the July 18, 2001 provisional as priority. Note also that Google's family listing shows some inconsistent priority metadata (e.g., a "2000-05-18" date appearing in family rows), which I am reporting literally rather than reconciling.
• The precise expiry/adjustment basis (Google lists "Adjusted expiration 2023-02-24") is drawn from the Google Patents legal-status field, which that site explicitly labels an assumption and not a legal conclusion.

I'll research litigation involving US 7,091,904 across patent litigation databases.

Good leads so far. Let me dig deeper into the specific cases.

Let me pin down case numbers and final dispositions for the district court actions.

Litigation involving U.S. Patent No. 7,091,904 ("Tracker architecture for GPS systems")

I ran targeted queries on patent-litigation sources (Unified Patents litigation portal reference, USITC/Federal Register records, SEC filings from the patent owner, Federal Register notices, Patexia case docket data, and news reports). I hit the search-step limit before I could verify every docket-level detail, so I flag confidence levels below. Please treat anything marked "unverified" as needing PACER confirmation.

Caveat on the search noise

Most search hits for "904" referred to different patents (e.g., Salix v. Amneal (D.N.J.) pharma '904; Lamps Plus design patent '904; Mendenhall v. Cedarapids '904; Enpath Medical '904). None of those involve US 7,091,904. All entries below were confirmed by matching the patent number 7,091,904 specifically, and they all trace to the SiRF–Global Locate/Broadcom GPS chip dispute.

Case 1 — SiRF Technology, Inc. v. Global Locate, Inc.

• Plaintiff: SiRF Technology, Inc. (San Jose, CA) — original assignee of the '904 patent
• Defendants: Global Locate, Inc. and its distributor (news reports name Innovation Sales Southern California / SBCG, Inc.; one report describes suit against "Global Locate and its United States distributor, SBCG, Inc.")
• Jurisdiction: U.S. District Court for the Central District of California
• Patents asserted: U.S. 7,091,904; 7,043,363; 6,850,557; 6,636,178
• Filing date: Complaint filed December 15, 2006 (SiRF's Form 10-K states "On December 15, 2006, SiRF's subsidiary, SiRF Technology, filed a patent infringement complaint against Global Locate, Inc."; publicly reported December 21, 2006)
• Relief sought: Injunction and monetary damages
• Counterclaims: On January 8, 2007, Global Locate filed its answer and a counterclaim in the same court asserting U.S. Patents 6,542,820; 6,560,534; 6,704,651; and 6,606,346
• Case number: Not verified in the sources I retrieved. I did not find a docket number for this C.D. Cal. action and will not guess one.
• Outcome/status: Not verified. The two companies' GPS patent disputes (SiRF, Global Locate, and Broadcom) ran in parallel through 2007–2010 across the C.D. Cal. and the ITC. I could not confirm from the retrieved sources whether this particular action was settled, dismissed, or resolved by judgment; note that Broadcom acquired Global Locate, and CSR acquired SiRF, and SiRF's '904 patent later expired. Recommend PACER/Docket Alarm verification.

Case 2 — In the Matter of Certain GPS Chips, Associated Software and Systems, and Products Containing Same

• Complainant: SiRF Technology, Inc. (San Jose, CA)
• Respondents: Global Locate, Inc. (San Jose, CA); later amended to add Broadcom Corporation (Irvine, CA) as a respondent
• Jurisdiction: U.S. International Trade Commission (Section 337)
• Investigation number: 337-TA-596 (this is the litigation link shown on the Google Patents page for US 7,091,904, and confirmed in Federal Register notices)
• Filing/institution dates: Complaint filed February 8, 2007 (supplemented February 22, 2007); Commission instituted the investigation March 13, 2007 (72 FR 11378). Presiding ALJ: Hon. Robert L. Barton, Jr.
• Patents asserted: U.S. 6,304,216; 7,043,363; 7,091,904; 7,132,980
• Relief sought: Permanent exclusion order and permanent cease and desist order
• Outcome/status (well documented):
  • The Commission later terminated the investigation with respect to the '904 patent, as well as the '980 patent and certain claims of the '216 and '363 patents (per USITC notice published at 73 FR, August 20, 2008; the complaint and notice of investigation were also amended to add Broadcom as respondent).
  • The ALJ's final initial determination issued June 13, 2008 found no violation of Section 337 by Global Locate and Broadcom (the merits findings in the ID related to the '216 and '363 patents, not to '904).
  • On August 20, 2008, the Commission issued notice that it determined not to review the final ID finding no violation — effectively ending the investigation.
  • Net effect for the '904 patent: it was dropped/terminated from the investigation before a merits decision, so no ITC liability finding on '904.

Related proceeding (does NOT involve the '904 patent — included for context only)

• In the Matter of Certain GPS Devices and Products Containing Same, Inv. No. 337-TA-602 — a separate ITC investigation brought by Global Locate against SiRF Technology, which addressed Global Locate's patents (e.g., 6,417,801; 6,606,346; 6,651,000; 6,704,651; 6,937,187; 7,158,080). Final determination January 15, 2009 issued limited exclusion and cease-and-desist orders against SiRF. This is the reverse-side dispute and did not assert 7,091,904.
• Likewise, Broadcom v. SiRF Technology (C.D. Cal., complaint May 14, 2008, four Broadcom patents; Judge James V. Selna) is a related GPS-chip case but, per the retrieved records, did not assert the '904 patent.

Bottom line

• The only confirmed litigation naming U.S. 7,091,904 is:
  1. SiRF Technology v. Global Locate (C.D. Cal., filed Dec. 15, 2006) — case number and disposition unverified; and
  2. ITC Inv. No. 337-TA-596 (filed Feb. 8, 2007; instituted Mar. 13, 2007) — where the '904 patent was terminated from the investigation and the Commission ultimately found no Section 337 violation (final ID June 13, 2008; Commission decision not to review, Aug. 20, 2008).
• I found no IPR/PGR/CBM proceedings at the PTAB against 7,091,904, and no currently pending litigation. The patent is recorded on Google Patents as "Expired – Lifetime," with an adjusted expiration of February 24, 2023 (priority July 18, 2001; filed July 18, 2002; granted Aug. 15, 2006), which is consistent with there being no live enforcement today. Current assignee is listed as Qualcomm Incorporated (assignment from CSR Technology Inc., effective Oct. 4, 2024), so Qualcomm would hold any remaining enforcement interest.

Confidence notes: The ITC 337-TA-596 details are high-confidence (Federal Register and USITC publication records). The C.D. Cal. filing date and parties are high-confidence (SEC 10-K and contemporaneous press). The C.D. Cal. case number and final disposition are unverified — I recommend confirming via PACER (C.D. Cal.), Docket Alarm, or Unified Patents' litigation portal: https://portal.unifiedpatents.com/litigation/caselist (the Google Patents record links to https://portal.unifiedpatents.com/litigation/International%20Trade%20Commission/case/337-TA-596). I was unable to run the final verification searches before reaching the tool-call limit, so I am flagging rather than filling those gaps.

Proceedings overview

Total AIA trial proceedings on U.S. Patent No. 7,091,904: 0 — zero IPRs, zero PGRs, zero CBM reviews; no claims invalidated, no claims sustained, no settlements, no institution denials, and no Federal Circuit appeals from any PTAB decision, because there is no PTAB decision to appeal. The bottom-line defensive posture is therefore unusual and should be stated precisely: this patent was never tested at the PTAB at all, but it is also expired (status "Expired – Lifetime," adjusted expiration 2023-02-24 per the Google Patents legal-status field, which that site labels an assumption), so the practical exposure today is past damages, not an injunction — and there is no PTAB record whatsoever to lean on in either direction.

Proceedings on file

None — the structured PTAB proceedings list is empty

• Type: N/A
• Filed: N/A
• Status: The canonical block supplied for this analysis states verbatim: "The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest."
• Judge panel: None assigned.
• Petition grounds: None. No § 102, § 103, or § 112 ground has ever been pleaded against 7,091,904 at the Board.
• Institution decision: None.
• Final Written Decision: None. No claim of 7,091,904 has ever been canceled, confirmed, or even construed by the PTAB. There is no FWD to link to, and I will not manufacture one.
• Settlement / termination: N/A.
• Appeal: N/A — no FWD, therefore no CAFC docket number.
• Defensive value: Because there is no § 315(e)(2) estoppel and no Board claim construction on the books, an accused infringer starts from a clean slate: nothing is foreclosed, but nothing is handed to you either. There is no "claim 1 is already dead" argument available.

Verification and its limits. I corroborated the empty structured list with independent web searches and found no IPR, PGR, or CBM petition, institution decision, or final written decision naming U.S. Patent No. 7,091,904. I could not run a direct query against PTAB E2E / USPTO Patent Center as a live tool, so treat this as a strong "no results found" rather than a certified negative. Practitioners needing a belt-and-suspenders confirmation should search the patent number directly in PTAB E2E (https://ptacts.uspto.gov/ptabweb/) and in CourtListener's PTAB docket (https://www.courtlistener.com/).

⚠️ False-positive hits to rule out — do NOT cite these as this patent

Searching for "'904 patent" plus "PTAB" surfaces a large volume of Nokia/Alcatel-family material (e.g., IPR2019-01442 and companion proceedings) referring to a different '904 patent whose claims run into the 50s (claims 28–34, 40, 50, 56–59) and whose grounds turn on Gilhousen501/761/865 cellular handoff art. 7,091,904 has only 21 claims and is a GPS baseband architecture patent. Any brief that cites those Gilhousen-based FWDs as invalidating "the '904 patent" is citing the wrong patent. Flagging this explicitly because it is the single most likely source of a fabricated invalidity narrative against this patent.

Adjacent invalidity activity (not AIA trials, but part of the real history)

None of the following is a PTAB proceeding, and none of it canceled a claim of 7,091,904 — but a defendant will encounter it in the file and should not mistake it for IPR art:

1. ITC Inv. No. 337-TA-596, Certain GPS Chips, Associated Software and Systems, and Products Containing Same. Instituted 2007-03-13 on SiRF's 2007-02-08 complaint asserting 6,304,216; 7,043,363; 7,091,904; and 7,132,980 against Global Locate (Broadcom added later). Per the previously generated ITC section, the complaint/notice was amended to add claim 2 of the '904 patent (Order No. 19, 2007-07-24), and the investigation was terminated as to the '904 patent. The ALJ's final ID of 2008-06-13 found no violation of § 337. Source: https://www.federalregister.gov/api/v1/documents/E7-4555. Reading: only claim 2 was ever in play on this patent, and it exited the case before any merits ruling — so not even the ITC has construed a claim of 7,091,904 on the record.
2. ITC Inv. No. 337-TA-602, the mirror-image case Global Locate/Broadcom brought against SiRF, asserted a different patent set (6,417,801; 6,606,346; 6,651,000; 6,704,651; 6,937,187; 7,158,080) — 7,091,904 was not asserted there. Affirmed in relevant part at SiRF Tech., Inc. v. U.S. Int'l Trade Comm'n, 601 F.3d 1319 (Fed. Cir. 2010) (CAFC docket 2009-1262; opinion at http://cafc.uscourts.gov/opinions-orders/09-1262.pdf). Do not import that appeal's result onto this patent.
3. Ex parte reexaminations were filed by SiRF in the parallel Broadcom district-court fight, but the reports I found describe SiRF reexam requests directed at Broadcom's four asserted patents — not at 7,091,904. I found no reexamination certificate (C1/C2) for 7,091,904, and I could not confirm any request for reexamination of it. If you need certainty here, check the '904 file wrapper directly; I am not asserting a negative I did not verify.

Strategic summary

Claim status: CANCELED — none. SUSTAINED — none. UNTESTED — all 21 claims. Independent claims 1 (multiple-protocol interface), 11 (RAM-stored autonomous tracking code), and 21 (automatic protocol selection) plus all 18 dependent claims stand exactly as issued on 2006-08-15. No claim has been narrowed, disclaimed by certificate, or canceled. The only public narrowing-relevant event in the record is the ITC's termination of the investigation as to this patent in 337-TA-596, which involved claim 2 only and produced no merits holding.

Estoppel landscape — § 315(e)(2) is a non-issue, which cuts both ways. No IPR was ever instituted, so no petitioner and no privy is estopped from anything, and no ground was "raised or reasonably could have been raised." That means a defendant's full § 102/§ 103 arsenal remains available in litigation (and, theoretically, in a fresh IPR). But the usual IPR-driven shortcuts are unavailable: there is no Board institution decision to point to for a stay motion, and no FWD to hand a district court. Note also two timing realities: (a) the patent is expired, so an IPR would be fought under Phillips claim construction and offers no prospective relief; and (b) § 315(b)'s one-year bar runs from service of a complaint, so if your client has been served, that clock is already running and IPR remains legally available even for an expired patent.

Pattern signals. There is no multipetitioner stack, no repeat petitioner, and no defensive aggregator (e.g., Unified Patents) appears anywhere in the chain for 7,091,904 — Google Patents flags only the 337-TA-596 ITC case and a Darts-ip "first worldwide family litigation" entry, both from 2007–2008. The patent owner never had to defend claims at the Board, so there is no history of aggressive PTAB appeals by the owner either. Ownership has since passed SiRF → CSR Technology (name change, 2010-11-19) → Qualcomm Incorporated (assignment effective 2024-10-04, recorded 2024-10-14), which matters for who you would actually be negotiating with and whether the portfolio is being monetized now.

The one genuinely useful signal: a patent asserted in a major ITC campaign (2007) and then, apparently, in no publicly reported PTAB challenge over 13 years of AIA availability is the opposite of the usual "well-asserted patents eventually attract IPRs" pattern. Given the expiration on 2023-02-24, the most likely explanation is not that the claims were bulletproof but that the patent stopped being worth the filing fee. If a demand letter cites 7,091,904 today, ask the sender which claims, which products, and when the infringement occurred — under 35 U.S.C. § 286 the damages window is limited to six years before suit, i.e., roughly 2020 onward, all of it post-issuance, and the ITC-side history suggests claim 2 was the claim the owner reached for.

Recommended next steps

1. Treat the PTAB record as blank, and say so in filings. There is no FWD to link to and no claim-level disposition to quote. Any statement that a claim of 7,091,904 was canceled or confirmed at the Board would be a fabrication.
2. Independently confirm the null with two primary sources: PTAB E2E (https://ptacts.uspto.gov/ptabweb/) and the '904 file wrapper / reexamination tab in Patent Center (https://patentcenter.uspto.gov/). Also check CourtListener (https://www.courtlistener.com/) for any appeal or PTAB docket referencing 7,091,904.
3. Do not inherit the Gilhousen-based '904 FWDs. Those belong to a different patent with claims numbered into the 50s. Verify the patent number and the claim numbers before relying on any "'904" authority.
4. Reframe the defense around expiration and § 286, not invalidity. With the patent expired (adjusted expiration per Google Patents: 2023-02-24) and no PTAB stay available, the productive work is (a) pinning the asserted claims, (b) mapping the damages window, and (c) testing invalidity in court under the full prior-art record — including the ITC record, where third-party discovery in 337-TA-596 and 337-TA-602 may already be a rich source of prior art and admissions.
5. Check who is asserting it. Qualcomm Incorporated holds the patent as of 2024-10-14. Confirm the current real party in interest and whether the '904 patent travel with any other SiRF/CSR assets in the same demand, since the family sibling US 7,970,412 (CIP, filed 2005-07-20) and related SiRF location patents share overlapping subject matter and could affect estoppel/privity analysis across a campaign.
6. One caveat I cannot close: I have no visibility into unpublished or very recent (2026) filings, so if you have a demand letter or a served complaint, run the patent number through the Board's own search before finalizing a position.

I'll dig into the USPTO Assignment Center / Google Patents legal-events record and cross-check the SiRF→CSR→Qualcomm chain.

Let me try to pull the USPTO Assignment Center records directly and check for any additional links (security interests, the CSR/SiRF merger, etc.).

Let me try to retrieve the actual Assignment Center records, including any security interests and the correspondent of record on each link.

I hit the tool-call limit mid-research, so I'll report what I verified and be explicit about the one field I could not retrieve (correspondent of record).

Source note / data gap up front: I could not open the Assignment Center API or scrape the reel/frame detail pages in this session. The three assignment records below come from the legal-events transcription of the USPTO assignment record that is mirrored on the authoritative patent text at https://patents.google.com/patent/[US7091904](/patent/US7091904)/en (each entry carries its reel/frame and free-format conveyance text). That transcription does not expose the correspondent field. So every "Correspondent" line below is marked as not retrieved, and I am not going to guess at it. The reel/frame images themselves are now downloadable as PDFs from Assignment Center (USPTO consolidated its two legacy assignment search tools into Assignment Center in late 2025), and those PDFs are the only reliable place to read the correspondent and the full assignor/assignee arrays.

Inventors

Unusual patterns — none found.

• All three inventors assigned to the same assignee on the same date under a single omnibus instrument (Reel 014900/0022). No inventor carved out a separate ownership interest, no co-ownership, no unassigned inventor.
• No evidence of near-simultaneous inventor departure. I found no record of any of the three leaving SiRF within 12 months of the 2002-07-18 filing. I did not run LinkedIn/employment-history checks, so this is "no signal found," not a verified negative.
• One date quirk worth recording literally rather than reconciling: the recorded assignment's effective/execution date is 2001-07-18, which coincides with the provisional (60/306,620) filing date and precedes the non-provisional filing date of 2002-07-18 by exactly one year. That is the normal pattern for a provisional-stage inventor assignment, not a red flag. Note that the earlier section of this analysis already flagged Google's inconsistent family-row priority metadata ("2000-05-18"); I confirm that inconsistency exists in the same source and I am not reconciling it.

Original assignee

SiRF Technology, Inc. (San Jose, CA) — named on the face of the patent and the assignee in Reel 014900/0022.

• Primary line of business: fabless semiconductor — GPS baseband chip sets and embedded/premium location software. SiRF's own 10-K describes revenue being 96–98% chip sets, sold to OEMs as chip sets, modules, IP cores and premium software.
• Did it ship a product embodying the claims? Yes, in my assessment. The architecture described is the SiRF baseband referred to in Appendix B as the "GSP2t" device — ARM7TDMI core, 0.18 µm CMOS, 4K×32 SRAM / 16K×32 boot ROM, GPS/WAAS correlator, and the I2C/SPI/CAN/USB/J1850/MOST/parallel pin-multiplexing interface block that claim 1 and claim 8 read on. SiRF's SiRFstarII/IIe-generation chip sets are the commercial embodiment of this baseband generation, and SiRF shipped them in volume into TomTom, Garmin, Palm and similar consumer devices.
• Current status: not operating under that name. SiRF Technology Holdings, Inc. (NASDAQ: SIRF), the publicly traded parent, was merged into Shannon Acquisition Sub, Inc., a wholly-owned subsidiary of CSR plc, effective 2009-06-26 (8-K dated 2009-06-26; stock-for-stock, 0.741 CSR ordinary share per SiRF share; SiRF became a direct wholly-owned CSR subsidiary and was delisted). The operating entity SiRF Technology, Inc. then changed its name to CSR Technology Inc., effective 2010-11-19 per the recorded change of name. CSR plc was acquired by Qualcomm Incorporated (announced Oct 2014, closed Aug 2015; CSR became Qualcomm Technologies International Ltd.). There was no Chapter 7 or Chapter 11 filing — SiRF had a 2008–2009 securities class action and derivative suits, but the exit was a merger, not a bankruptcy.

Nuance to flag: the record names SiRF Technology, Inc., while the SEC merger was with SiRF Technology Holdings, Inc. I found no Holdings-level assignment recorded against this patent, which is consistent with the operating subsidiary holding title and simply being renamed after the merger — but if you need clean standing you should confirm the Holdings→subsidiary title structure from the 2009 merger documents rather than infer it from the assignment record.

Assignment timeline

Three recorded events, spanning ~23 years. Correspondent of record could not be retrieved for any of them (see source note) — this is the single most important gap in this analysis, since it defeats the repeat-correspondent signal.

2001-07-18 (executed / effective) / recorded 2004-01-20 — Reel 014900/0022

• Conveyance: Assignment of assignors' interest (inventor→company)
• Assignor: Vantalon, Nicolas; Peng, Leon Kuo-Liang; Turetzky, Gregory
• Assignee: SiRF Technology, Inc. (California)
• Correspondent: NOT RETRIEVED — not exposed in the transcription. Cannot assess recurrence.
• Context: initial inventor-to-employer assignment, filed against application 10/199,253 pre-issuance (pre-grant pub. 2004/0252049 A1 issued 2004-12-16). Recorded ~2.5 years after execution — a normal recordation lag for a provisional-stage assignment, not a fire-sale tell.

2010-11-19 (effective) / recorded 2011-12-22 — Reel 027437/0324

• Conveyance: Change of Name
• Assignor: SiRF Technology, Inc.
• Assignee: CSR Technology Inc. (California)
• Correspondent: NOT RETRIEVED
• Context: change of name only — SiRF Technology, Inc. renamed CSR Technology Inc. following CSR plc's 2009-06-26 acquisition of SiRF Holdings. No change of beneficial ownership. Note this is the only record reflecting the CSR takeover on this patent: the 2009 merger itself was not recorded as a separate Merger-conveyance for this patent, which is internally consistent (title stayed in the surviving subsidiary, which was then renamed) but means there is no "Merger" reel/frame to cite for the 2009 event.

2024-10-04 (effective) / recorded 2024-10-14 — Reel 069221/0001

• Conveyance: Assignment of assignor's interest
• Assignor: CSR Technology Inc.
• Assignee: Qualcomm Incorporated (California)
• Correspondent: NOT RETRIEVED
• Context: intra-group portfolio consolidation / confirmatory transfer. Qualcomm acquired CSR plc in 2015, roughly nine years before this recordation; the 2024 record is best characterized as late-stage housekeeping moving the legacy CSR/SiRF portfolio entity-of-record into Qualcomm Incorporated itself. I cannot confirm the business rationale from the record — the timing (Oct 2024) could equally reflect a portfolio clean-up triggered by the patent's Feb 2023 expiry. Either way it is not a sale to a third party.

Recorded but non-assignment events on the same legal-events feed (listed so they are not mistaken for transfers): 2009-12-02 entity status changed to large entity plus a refund; 2010-01-14, 2014-02-17 and 2018-01-17 maintenance-fee payments; 2023-02-24 adjusted expiration. The 2005-07-20 link to US 11/185,533 (which issued as US 7,970,412) is a continuation-in-part family relationship, not an assignment.

If the timeline above is the complete record, note the negative finding: there is no Shell-entity link, no security agreement, no license, no release, and no correction recorded against this patent. I could not query Assignment Center by reel/frame to confirm that three records is the total; verify by searching patent number 7091904 at https://assignmentcenter.uspto.gov/ (legacy URL https://assignment.uspto.gov/patent/index.html now redirects there).

Timeline diagram

timeline
    title Ownership of US 7091904
    2001 : Inventors assign rights to SiRF
    2002 : Non-provisional application filed
    2004 : Inventor assignment recorded
    2006 : Patent issued to SiRF Technology
    2007 : SiRF files ITC complaint
    2009 : CSR plc acquires SiRF
    2010 : SiRF renamed CSR Technology
    2011 : Name change recorded at USPTO
    2013 : Patent term adjusted to expire
    2023 : Patent expires
    2024 : CSR assigns to Qualcomm

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. No LLC appears anywhere in the chain. Reel 014900/0022 goes inventors→SiRF Technology, Inc.; Reel 027437/0324 is a pure name change; Reel 069221/0001 goes CSR Technology Inc.→Qualcomm Incorporated. No "IP / Patents / Licensing / Holdings / Ventures" suffix, no registered-agent service address, no single-member LLC.

2. Known asserter in the chain — NOT PRESENT. The three holders are SiRF (fabless GPS chip vendor), CSR (fabless connectivity/GPS chip vendor) and Qualcomm (chip vendor with a large licensing program). None of the named entities — SiRF, CSR Technology, Qualcomm Incorporated — appears on the standard NPE lists cited in the task (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg entities). Qualcomm's licensing arm is a genuine operating-company SEP program, not an NPE; I do not have a Unified/RPX listing putting Qualcomm on a high-frequency-plaintiff NPE list, and I will not assert one without it.

3. Repeat correspondent across the chain — UNCLEAR (data gap, not a negative finding). I could not retrieve the correspondent field for Reel 014900/0022, 027437/0324 or 069221/0001. This is the exact field the task asks me to weight most heavily, and it is the one field I could not obtain. Action item: open the three reel/frame PDFs in Assignment Center and record the correspondent for each. If one firm recurs across 014900/0022 → 027437/0324 → 069221/0001, that is interesting for a different reason here (a single firm shepherding a 23-year corporate succession), not an NPE tell — three records over 23 years through three operating companies is far too sparse to satisfy the recurrence threshold anyway.

4. Cascading transfers — NOT PRESENT. The gaps between recorded links are 2004→2011 (≈7 years) and 2011→2024 (≈13 years). Nothing remotely like chained LLC hops inside 24 months. No shared correspondent address or common principal can even be evaluated because the transfers are a decade apart.

5. Pre-litigation transfer — NOT PRESENT. The one documented assertion on this patent is ITC Inv. No. 337-TA-596, instituted 2007-03-13 on a complaint filed 2007-02-08 by SiRF Technology, Inc. as complainant (asserting US 6,304,216; 7,043,363; 7,091,904; 7,132,980 against Global Locate, later joined by Broadcom; claim 2 of '904 was added by Order No. 19 in July 2007; the investigation was terminated as to '904). The assignment nearest that suit in time is Reel 014900/0022, recorded 2004-01-20 — about three years before the complaint, well outside the 6-month window. No transfer was arranged to enable the assertion.

6. Bankruptcy fire-sale — NOT PRESENT. No Chapter 7/11. SiRF's exit was a negotiated stock-for-stock merger with CSR plc that closed 2009-06-26 with SiRF stockholders receiving 0.741 CSR shares (≈27% of the combined company). The 2009–2009 shareholder litigation (Diaz v. Banatao; Reich v. SiRF) was fiduciary-duty class/derivative litigation over the merger price, not an insolvency.

7. Privateering — NOT PRESENT. There is no transfer to an NPE asserting on the operating company's behalf. The 2007 ITC action was brought by SiRF itself, as complainant, against a direct chip competitor — the classic operating-company posture. Nothing in the chain shows an operating company handing the patent to an assertion vehicle to attack competitors.

8. Defensive aggregator — NOT PRESENT. The chain terminates at Qualcomm Incorporated (Reel 069221/0001), an operating semiconductor company. It does not terminate at RPX, AST, LOT Network, Unified Patents or OIN. The patent is therefore not neutralized by defensive aggregation.

Verdict

Operating-company assertion.

The chain is a clean, 23-year corporate succession through three operating semiconductor companies — inventors → SiRF Technology, Inc. (Reel 014900/0022, recorded 2004-01-20) → CSR Technology Inc. by pure change of name (Reel 027437/0324, recorded 2011-12-22) → Qualcomm Incorporated (Reel 069221/0001, effective 2024-10-04) — with zero NPE hallmark signals: no shell entity, no security agreement, no chained LLC transfers, no pre-litigation transfer, no bankruptcy, no privateering, no defensive aggregator. The one documented assertion of this patent, ITC Inv. No. 337-TA-596 (SiRF v. Global Locate, complaint filed 2007-02-08), was an operating chip vendor suing a direct competitor over chips it shipped — which is precisely why this does not read as an NPE chain.

Two caveats that keep this from being a clean call. First, "operating-company assertion" as literally defined requires the current assignee to be asserting; Qualcomm is the current assignee but the patent expired 2023-02-24, so there is no live assertion and the chain is today non-asserting by attrition rather than by defensive aggregation. Second, my verdict is built on the reel/frame and conveyance-type fields only — the correspondent data, the single field most likely to surface a hidden pattern, was not retrievable in this session.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 7091904), and pull the three reel/frame PDFs — 014900/0022, 027437/0324, 069221/0001 — to fill in the correspondent column and confirm that no fourth recordation (e.g., an unrecorded or later-corrected security interest) exists.

I'll research US 7,091,904 against the USPTO records and confirm each cited reference. Let me run targeted searches.

Now let me research the remaining cited references.

Prior-Art Analysis — US 7,091,904 B2

0. USPTO record confirmation

The number you specified resolves to a single, unambiguous record, and I did not return anything for similar numbers:

Source: https://patents.google.com/patent/US7091904/en

1. Framing note on §102 (read this before the tables)

Two things must be stated up front, or the analysis below will be misread.

(a) These are "references of record," not adjudicated anticipations. Every reference below appears in the patent's own front-page citation list — i.e., the examiner/applicant cited them, and the patent nonetheless issued with all 21 claims. Under the strict §102 test, a reference anticipates only if it discloses every element of a claim, arranged as in the claim. So for each reference I identify which claims it is most relevant to and why full §102 anticipation fails or is arguable — not that it anticipated.

(b) The independent claims were narrowed during prosecution. The pre-grant publication US 2004/0252049 A1 prints claim 1 as ending simply "…can couple to at least two different protocol interfaces via the bus structure," and claim 21 without any "automatically" limitation. The granted claims add the "multiple-protocol interface … compatible with the at least two different protocol interfaces" element (claim 1) and "selected by the GPS architecture automatically" (claim 21). That amendment is the single most important fact for this prior-art analysis: it was almost certainly aimed at the multi-interface references below (#1, #2, #3). Source (published claims): https://patents.justia.com/patent/20040252049

Statutory-date note: the 1996–1999 references are pre-AIA §102(b) art (published more than one year before the July 18, 2002 filing). US 6,593,878 is a §102(e) reference (US application filed June 25, 2001, before the '904 invention date, though it issued in 2003).

2. The six patent citations

Reference #1 — US 5,519,403 A

• Title / assignee: "Global positioning system communications multi-interface" — Motorola, Inc.
• Dates: filed Nov. 29, 1993; granted May 21, 1996
• What it discloses: A GPS receiver (12), a processor (14), and a "communications multi-interface" (16) all tied to a processor-level bus (30). The multi-interface contains a "common controller and distributor 17, status/configuration determiner 47, and serial digital port 48, two-tone (modem) port 49, multi-tone (DTMF) port 50, and parallel bus 51," described as configurable "for nearly any possible communications protocol now or future."
• Claims potentially implicated: Claim 1 and claim 21. This is the closest art on the "at least two different protocol interfaces" and "protocol interface selected … automatically / by sensing" limitations — the status/configuration determiner 47 is a strong teaching of protocol selection. It is also plausibly the art that drove the multiple-protocol interface amendment noted above.
• Why full anticipation fails: It is a multi-protocol communications interface (modem/DTMF/serial/parallel), not the claimed recitation of a bus structure with cache memory for software code, ROM for storing a boot program, and a GPS/WAAS receiving, tracking and demodulating engine. It is also a system of discrete parts, not the integrated single-chip GPS architecture of claim 1. No WAAS.
• Source: https://patents.google.com/patent/[US5519403A](/patent/US5519403A)/en

Reference #2 — US 5,504,684 A

• Title / assignee: "Single-chip GPS receiver digital signal processing and microcomputer" — Trimble Navigation Limited
• Dates: filed Dec. 10, 1993; granted Apr. 2, 1996
• What it discloses: Combines on a single IC: an eight-channel GPS receiver, a 68330-type microprocessor, an 68681-type DUART serial controller, an A/D converter, a real-time clock, a RAM, and a boot ROM, with a "system integration module and inter-module bus" and tri-state control for emulation.
• Claims potentially implicated: Claim 1 (the architectural skeleton: bus + microprocessor + RAM + boot ROM + GPS engine), and derivatively claims 7/18 (bus interface unit), claims 6/17 (external RTC), both of which are expressly disclosed here (RTC, bus interface). This is the most structurally relevant reference to the independent claims' "core" architecture.
• Why full anticipation fails: It discloses a DUART, i.e. a single serial interface type, not "at least two different protocol interfaces via a multiple-protocol interface"; and its receiver is a GPS engine, not a GPS and WAAS engine. It therefore does not reach the added element of granted claim 1 (nor the autonomous-code element of claim 11, nor the auto-select element of claim 21).
• Source: https://patentimages.storage.googleapis.com/80/c4/3b/2b6a2b55c061e1/US5504684.pdf

Reference #3 — US 5,761,456 A

• Title / assignee: "Processor device having automatic bus sizing" — Trimble Navigation Limited
• Dates: filed Apr. 3, 1996; granted June 2, 1998
• What it discloses: A processor device (20, on a single silicon chip) with a microprocessor (22), a configurable bus interface (24), and a first (boot) memory 26; at power-up the boot memory controls the microprocessor to automatically configure the bus interface to a selected bus width. The exemplary apparatus is a GPS receiver whose "application specific circuits 34 … include the circuits for downconverting and correlating the GPS satellite signal."
• Claims potentially implicated: Claim 21 (automatic configuration/detection) and its dependents claims 10/20 ("selected … through sensing a signal"). The self-configuring bus interface is the closest art to the "automatically selected" limitation.
• Why full anticipation fails: Its automatic behavior is bus-width sizing, not protocol-interface selection; and it discloses neither a multi-protocol interface nor a GPS+WAAS engine. It is a §102/§103 reference against the automatic concept, but does not meet the claim as a whole.
• Source: https://www.freepatentsonline.com/[5761456](/patent/5761456).html

Reference #4 — US 5,877,725 A

• Title / assignee: "Wide augmentation system retrofit receiver" — Trimble Navigation Limited (inventor Rudolph M. Kalafus)
• Dates: filed Mar. 6, 1997; granted Mar. 2, 1999
• What it discloses: A GPS WAAS retrofit receiver that receives WAAS messages and translates them into RTCM SC-104 messages for transmission to an external GPS receiver over "one of many well known interface standards in use in the electronics field (e.g., RS-232, ARINC 429, ARINC 629, Milstd 1553 …)."
• Claims potentially implicated: Claims 1 / 11 / 21 only as to the WAAS limitation ("receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals"). It is the best of-record evidence that WAAS demodulation predates the '904.
• Why full anticipation fails: It is a standalone retrofit box, expressly aimed at users who do not modify their existing GPS receiver. It teaches none of the bus/CPU/cache/RAM/ROM integration and no multiple-protocol interface. It is at most §103 fodder for the WAAS element.
• Source: https://patents.google.com/patent/US5877725

Reference #5 — US 5,920,283 A

• Title / assignee: "Receiver engine for global positioning system" — Conexant Systems, Inc.
• Dates: filed May 9, 1997; granted July 6, 1999
• What it discloses: A GPS receiver-engine architecture (the title and assignee are confirmed on the '904 face; I did not retrieve the full text — see caveat in §6).
• Claims potentially implicated: Claims 1 / 11 / 21 as to the "GPS engine … receiving, tracking, and demodulating" element, i.e. the receiver-engine core. Given the "engine" framing, this is likely the reference most relevant to claim 5/16 ("GPS engine runs on a separate bus structure") and to the engine/bus sub-architecture generally.
• Why full anticipation fails: A "receiver engine" reference of this era would not disclose the multi-protocol interface, the autonomous-code RAM (claim 11), or automatic protocol selection (claim 21).
• Source (face citation confirmed): https://patents.google.com/patent/US7091904/en

Reference #6 — US 6,593,878 B2

• Title / assignee: "Integrated network interface card and global positioning system receiver" — Intel Corporation
• Dates: filed June 25, 2001; granted July 15, 2003
• What it discloses: Integration of a network interface controller with a GPS receiver — i.e., combining a GPS function with a host/network interface on one device.
• Claims potentially implicated: Claims 1 / 8 / 12 as to the notion of a GPS device that couples to a network/peripheral interface; possibly §102(e) art on the "couple to at least two different protocol interfaces" concept in the network-interface context.
• Why full anticipation fails / status notes: The patent issues after the '904 filing, so it is only §102(e) art (its application predates the invention). Its subject matter is network-interface + GPS integration, not I2C/CAN/SPI/USB/J1850/GPIO/MOST/parallel/address-data multi-protocol selection, and it lacks the cache/ROM/WAAS-engine combination of claim 1.
• Source (face citation confirmed): https://patents.google.com/patent/US7091904/en

3. The three non-patent citations

4. Ranking — "most relevant" prior art to US 7,091,904

1. US 5,504,684 (Trimble, single-chip GPS receiver DSP + microcomputer) — closest to the integrated architecture of claim 1 (bus, microprocessor, RAM, boot ROM, RTC, ADC, serial controller, on one chip). Its single defect against the granted claim is that it shows one serial interface, not a multi-protocol interface, and GPS-only (no WAAS).
2. US 5,519,403 (Motorola, GPS communications multi-interface) — closest to the multi-interface / protocol-selection elements of claims 1 and 21 (status/configuration determiner; several communication ports). Likely the art behind the prosecution amendment adding "multiple-protocol interface."
3. US 5,761,456 (Trimble, automatic bus sizing) — closest to the automatic selection element of claim 21.
4. US 5,877,725 (Trimble, WAAS retrofit receiver) and NPL-2 (Mattos, WAAS/EGNOS-ready 2-chip chipset) — the WAAS-element art.
5. US 5,920,283 (Conexant, receiver engine) — GPS-engine-core art.
6. US 6,593,878 (Intel, integrated NIC + GPS) — network-interface + GPS integration; §102(e) only.
7. NPL-1 (Kibe, TMS320C30) and NPL-3 (Zarlink GP2021) — general GPS-architecture/correlator art.

Bottom line on §102: on the record as it stands, no single one of these references anticipates claims 1, 11, or 21, principally because (i) none discloses the multiple-protocol interface element added to granted claim 1, (ii) none discloses both the autonomous code stored in RAM element of claim 11 and the multi-protocol/AI-selection elements, and (iii) the multi-interface and integration teachings are split across different references (which is a §103, not a §102, posture). The strongest §102 candidates on individual limitations are #2 against claim 1's core and #1 against claim 21's multi-interface element.

5. Cross-check against the earlier-generated section

The earlier summary's plain-language claim mapping is consistent with this analysis. One point I am flagging explicitly because it materially affects the prior-art picture: the earlier section quoted the granted claim 1 (with the "multiple-protocol interface … compatible with the at least two different protocol interfaces" clause) and the granted claim 21 (with "selected by the GPS architecture automatically"). The pre-grant publication's claim 1 and claim 21 lack those clauses (source: https://patents.justia.com/patent/20040252049). That is not a contradiction in the earlier summary — it quoted the issued text, which is correct for an infringement/validity analysis — but the difference is the key prosecution-history fact driving which references matter, and it should be carried forward.

6. What I could not confirm (stated rather than inferred)

• I ran out of search budget and could not retrieve full text for US 5,920,283 and US 6,593,878, nor the three NPL items. My characterizations of #5, #6, and NPL-1/NPL-2/NPL-3 above are based on the '904 front-page citation list (authoritative) plus title/assignee/date data; the technical descriptions of #5 and #6 are lower-confidence than those of #1–#4, which I verified from full text.
• I did not query the USPTO Patent Center / Patent Public Search API directly (no live docket tool available to me); the bibliographic data is from the Google Patents record of the same document, which mirrors the USPTO face data.
• The §102 statutory-date characterization assumes a July 18, 2001 invention date (provisional). If an earlier invention date is provable, US 6,593,878's §102(e) status could change; if the provisional is not entitled to priority for these claims, the effective date shifts to July 18, 2002.

Primary URLs used: https://patents.google.com/patent/US7091904/en ; https://patents.justia.com/patent/20040252049 ; https://patents.google.com/patent/US5519403A/en ; https://patentimages.storage.googleapis.com/80/c4/3b/2b6a2b55c061e1/US5504684.pdf ; https://www.freepatentsonline.com/5761456.html ; https://patents.google.com/patent/US5877725 ; https://patents.justia.com/patent/[7091904](/patent/7091904)

I'll ground the prior-art disclosures before analyzing. Let me pull the key cited references.

Obviousness Analysis — U.S. Patent No. 7,091,904 B2 under 35 U.S.C. § 103

Scope note. This analysis is built exclusively from the prior art listed in the "Prior Art" section of the Google Patents record for US 7,091,904 — i.e., the six Patent Citations, three Non-Patent Citations, and three Family Cites Families entries — plus the two documents the '904 specification itself incorporates by reference. I have not reviewed the file wrapper (examiner's reasons for allowance, any § 132 declarations, or the IDS). This is a technical obviousness assessment, not a legal opinion. Where a limitation has no express disclosure in the cited set, I say so rather than manufacture a citation.

I. Governing framework and the person of ordinary skill

Priority/effective filing date: July 18, 2001 (provisional 60/306,620); non-provisional filed July 18, 2002. Every reference below predates the July 18, 2001 priority date on its face, so all qualify as prior art.

PHOSITA: a person with a B.S. in electrical engineering or computer engineering and 3–5 years' experience designing GPS receiver baseband/ASIC architectures and embedded systems, familiar with the GPS ICD-200 signal structure, WAAS augmentation, the common serial/peripheral bus standards (UART, I²C, SPI, USB, CAN, J1850), and with single-chip microprocessor-plus-cache-plus-peripheral integration practice.

Legal standard applied: Graham v. John Deere, 383 U.S. 1 (1966) (scope/content of prior art; differences; PHOSITA level; secondary considerations), and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). Under KSR, a combination is obvious where the elements are "known," the combination "does no more than yield predictable results," and there exists "a design incentive to combine" or "a finite number of identified, predictable solutions." KSR also permits reliance on "common sense" and known design practice for a limitation that is a notorious staple of the art. The four MPEP 2144 rationales most relevant here are: (A) combination of known elements by known methods yielding predictable results; (B) simple substitution of known elements; (C) use of a known technique to improve similar devices in the same way; and (F) design incentives/market forces.

II. Claim construction of the key terms (construed broadly, as the spec supports)

III. Prior-art inventory (the page's "Prior Art" section)

Incorporated by reference in the '904 spec (also prior art): US 5,901,171 (Kohli et al., "Triple multiplexing spread spectrum receiver") and US 6,278,403 (Peng et al., "Autonomous hardwired tracking loop coprocessor for GPS and WAAS receiver"). US 6,278,403 is directly on point for the claim 11 autonomous-tracking limitation and for GPS+WAAS tracking.

IV. Element-by-element mapping (independent claim 1)

Observation: Claim 1 is essentially R1's single-chip GPS baseband (bus + CPU + RAM + boot ROM + GPS DSP engine) with R2's multi-protocol interface folded in, plus WAAS (R4/N2) and an on-chip cache.

V. Combination analyses

Combination A — Claim 1: R1 + R2 (+ R4 or N2), optionally + R5

• Where each element comes from: R1 supplies the single-chip GPS baseband (bus, CPU, RAM, boot ROM, tracking/DSP engine, DUART, RTC, PWM, GPIO, ADC). R2 supplies the "multiple-protocol interface" that "can couple to at least two different protocol interfaces," including its single common-controller interface block. R4/N2 supply the WAAS receive/track/demodulate capability.
• Motivation to combine (rationale (A),(C),(F)):
  1. Same field, same problem. R1 and R2 both address GPS receivers and the integration of GPS into host systems. R1's stated objects are to "reduce the size, cost and complexity of a GPS receiver," achieve "a much lower part count," and "lower system power consumption." R2's stated object is "to provide a flexible, adaptable interface between the GPS and a variety of communications systems." A PHOSITA seeking a single GPS chip usable in multiple host environments would be motivated to combine them precisely because R1 has already put the GPS baseband on one die and R2 has already taught a single interface block that reaches many protocols.
  2. Market/design incentive (KSR factor (F)). The '904 specification itself concedes the commercial driver: the architecture is meant to "support all GPS market segments: Cellular Phone, Car Navigation, GPS Hand-helds, Consumer Electronics, PC accessory and others." A chip that must serve cellular, automotive, and PC markets faces cellular (J1850/CAN/UART), PC (USB/parallel), and peripheral (I²C/SPI) interfaces — i.e., exactly the multi-protocol requirement of claim 1. The motivation is not hindsight; it is the stated market requirement.
  3. WAAS. R4 is titled a WAAS retrofit receiver and N2 is a "WAAS/EGNOS-Ready" chipset — both expressly motivate adding WAAS reception to the GPS engine, and the '904's own U.S. 6,278,403 reference (incorporated) is a "coprocessor for GPS and WAAS receiver."
• Predictable result. Combining a GPS baseband ASIC with a multi-protocol serial/parallel interface block, both known, produces the predictable result of a chip that can talk to several hosts — nothing more than an aggregation of known elements performing their known functions.

Conclusion on claim 1: Obvious under § 103 over R1 + R2 + R4 (or N2) but with one residual gap — the "cache memory" limitation, addressed in §VII.

Combination B — Claim 11: R1 + R2 + R5 (+ US 6,278,403)

Claim 11 differs from claim 1 only in that the RAM must also store "autonomous code used for tracking" and the GPS engine must selectively use it.

• Where it comes from: R5 discloses a GPS object-code library whose measurement engine runs acquisition, tracking, and data demodulation "in an autonomous or commanded mode," with the GPS software and local application co-resident in one memory system on the GPS manufacturer's microcontroller. The incorporated US 6,278,403 ("Autonomous hardwired tracking loop coprocessor") is an even closer teaching of autonomous on-chip tracking. R8 (user-controlled GPS receiver) corroborates user-selectable modes.
• Motivation (rationale (A),(C)): Both R5 and '403 are directed to the same problem — letting a GPS receiver function without a host ("autonomous") while retaining a "commanded" mode. Adding a mode bit/software switch that lets the engine "selectively" use the autonomous code is a simple substitution/design choice (rationale (B)) once the autonomous code is resident. R5's local-API/modular design makes the mode selection a routine implementation detail.
• Predictable result: Selecting between an autonomous tracking routine and a commanded one is the conventional use of stored program code.

Conclusion on claim 11: Obvious over R1 + R2 + R5 (+ US 6,278,403).

Combination C — Claim 21: R1 + R2 + R3

Claim 21 requires that the protocol interface be "selected by the GPS architecture automatically."

• Where it comes from: R3 is the key reference. It discloses a processor that, at boot-up, automatically reads initial data indicative of the selected bus width and configures its bus interface accordingly — i.e., the device self-configures its interface without user action. R3 expressly frames this as enabling "a single design of a processor device to control a programmable apparatus having a signal bus having a selected bus width" — the identical design motivation (one chip, many host configurations) that drives the '904's auto-detect feature. R2 separately teaches a status/configuration determiner that reports the correct settings and an interface that "can be dynamically reconfigured" — the sensing/detection hardware.
• Motivation (rationale (C)/(F)): The express purpose of both R3 (auto-configure to bus width) and the '904's auto-detect is one-part-serves-many-platforms. A PHOSITA seeking to sell one GPS baseband into cellular, automotive, and PC sockets would recognize that auto-detection of the attached interface is the natural extension of R3's auto-configuration teaching.
• Predictable result: Auto-sensing a connected interface and configuring to it was a well-established technique (autosensing bus width, plug-and-play, auto-baud), and applying it to the multi-protocol interface of R2 is a use of a known technique to improve a similar device in the same way.

Conclusion on claim 21: Obvious over R1 + R2 + R3.

Dependent claims

VI. Consolidated motivation-to-combine statement (for the record)

A PHOSITA at the July 2001 priority date, given (1) Trimble's single-chip GPS baseband (R1), (2) Motorola's single multi-interface block that already connects a GPS receiver and processor over a bus to a wide variety of protocols (R2), (3) Trimble's automatic bus-width self-configuration in a GPS processor (R3), and (4) WAAS-capability references (R4, N2), would have been motivated to combine them because:

1. All references are in the same field of endeavor (GPS receivers and their host interfaces) — KSR; MPEP 2144.01.
2. The references' own stated objects point at each other. R1 wants lower part count/size/cost; R2 wants interface flexibility across "nearly any possible communications protocol"; R3 wants a single processor design usable across differently-configured apparatuses. Combining a single-chip GPS baseband with a self-configuring multi-protocol interface is the direct fulfillment of all three objectives.
3. Market forces supply an explicit incentive (the '904 spec's own admission that the architecture must serve cellular phone, car navigation, GPS handheld, consumer electronics, and PC accessory segments), which by definition requires multiple host protocols on one chip.
4. Nothing teaches away. No reference disparages combining a multi-protocol interface with an integrated GPS baseband; R2 in fact anticipates and endorses future-proofing the interface.
5. The result is a predictable aggregation of known elements performing their known functions — the classic KSR "combination of familiar elements according to known methods." The claims appear directed to the architecture-level aggregation, not to any unexpected interaction between the elements.

VII. Where the obviousness case is weakest (candid flags)

1. The "cache memory" limitation (claims 1, 11, 21). None of the six cited patents or three NPL items expressly discloses an on-chip cache for the GPS/CPU architecture. This is the single most vulnerable element under a Graham "differences" analysis. The counter is that an on-chip instruction/data cache for a 32-bit embedded microprocessor was notorious common knowledge by 2001 (KSR "common sense"; MPEP 2144.01(C)); the '904's own cache is a 9 KB two-way set-associative cache, i.e., entirely conventional. But if a challenger cannot find a cache-showing secondary reference, this element carries the most weight for non-obviousness.
2. The "beacon processor" (claims 4, 15). No cited reference discloses a GPS-engine-integrated beacon demodulator (frequency-discriminator, 10-bit A/D, 50 Hz output, 3-pole Butterworth). A challenger would need additional art from the marine radiobeacon/RBDS field. These dependent claims are the strongest non-obviousness positions.
3. The recitation of a specific protocol list (claims 8, 12). The list (I²C, CAN, PWM, SPI, J1850, USB, GPIO, MOST, parallel, address/data bus) is arguably a mere aggregation of known interfaces. However, no single cited reference shows all of them in one GPS architecture (R2 covers a different set — serial digital, two-tone, multi-tone, parallel; R1 covers PWM/DUART/GPIO). Obviousness here would rest on the "enumerating known alternatives" rationale and the '904 spec's own admission that these are standard, "commonly used" interfaces — which is an admission against interest helpful to a challenger.
4. Preprogrammed vs. single-interface-block structure. Claim 1's "multiple-protocol interface … compatible with the at least two different protocol interfaces" is met by R2's common-controller interface block, but if the claims were construed to require a single physical pin-set multiplexed across protocols (as in the '904's multiplexed GPIO/interface 166), R2's separate ports might not literally read on it — though it would still render it obvious to multiplex.

VIII. Bottom line

Confidence and caveats. High confidence in the content of R1, R2, R3, R5, R6, R4 and the two NPL items, as quoted above from primary/patent-office sources. I could not retrieve the full text of US 5,877,725 (R4), US 5,864,315 (R7), US 6,078,290 (R8), or JP 3656144 B2 (R9) in this session (the search tool limit was reached), so their treatment above is based on their titles and assignees as listed on the '904 page — treat those specific references as candidate art requiring full-text verification. I also note, per the prior sections of this analysis, that no validity ruling was ever reached on the '904 claims: the ITC terminated the '904 from Inv. No. 337-TA-596 before a merits decision, so there is no adjudicated obviousness finding to rely on either way. Any actual § 103 challenge would also need the examiner's reasons for allowance and any Rule 132 evidence in the file wrapper, which I have not reviewed.