US 6938177

US Patent 6,938,177 (US6938177B1) — Summary

Bibliographic data (verified against Google Patents, Justia, and CAFC records)

Abstract

A multi-chip module instrument controller having various interface and operational capabilities. The controller incorporates a microprocessor and both volatile and non-volatile memories. The controller includes variable analog-to-digital conversion bit depths, with higher bit depths for some applications. Additionally, the controller includes a separately controllable field programmable gate array that acts as a parallel processor with internal or separate external clock. The FPGA preferably includes more than thirty thousand gates (30,000) and adds a freely re-configurable and separately programmable multi-purpose digital system that can run independent of the microprocessor.

Plain-language overview of the independent claims (claims 1, 6, 10, 13, 15, and 20)

• Claim 1 (apparatus): An instrument controller combining: (a) non-volatile memory for program/data storage; (b) a large volatile memory; (c) a processor able to run at high and low frequencies, with embedded memory holding an initialization program so the processor can start up without first loading a program from non-volatile memory; (d) at least two internal oscillators providing high- and low-frequency clocks; (e) an FPGA coupled to the processor that can run independent processes in parallel with the processor; and (f) multiple ADCs that digitize analog inputs at one of at least two possible bit depths. The FPGA's gates are split so a first portion performs signal processing and a second portion acts as a signal-routing/distribution matrix.

• Claim 6 (apparatus): The same core architecture as claim 1 (memories, processor with embedded initialization program, two internal oscillators, parallel-capable FPGA, variable-bit-depth ADCs), but instead of the FPGA gate-portion limitations, it adds a resettable digital real-time quartz-controlled clock used to date/time-stamp data before it is written to non-volatile memory.

• Claim 10 (apparatus): The same core architecture as claims 1 and 6, but the distinctive limitation is that a portion of the FPGA gates is configured as an internal embedded power converter that receives an input voltage level and generates all operating and reference voltages needed inside the controller.

• Claim 13 (method): A method of parallel processing in a single instrument controller: receive analog inputs and digitize at one of at least two bit depths; feed one portion of the digital inputs to the processor and the remainder to the FPGA; perform DSP on the processor's portion; configure a first portion of the FPGA to perform DSP on its portion (achieving parallel processing); and configure a second portion of the FPGA gates as an internal embedded power converter.

• Claim 15 (stand-alone apparatus): A stand-alone controller whose FPGA has three gate portions — signal processing, signal distribution matrix, and internal embedded power converter. The microprocessor is coupled to the gates and can operate independently or under the gates' control. It adds a large volatile memory sized at least as large as the processor's address space, plus analog outputs each driven by an independent DAC capable of converting from one of at least two bit depths.

• Claim 20 (method): A method for parallel processing in a controller with an FPGA: configure a portion of the FPGA gates as an internal embedded power converter that accepts at least one input voltage level and generates all operating and reference voltages needed for activation, operation, and deactivation of the controller.

Litigation / CAFC 2026 status (verified via cafc.uscourts.gov, Justia, CourtListener)

• IPR2023-00195 was filed by Xilinx, Inc., Advanced Micro Devices, Inc., and ATI Technologies ULC (petition effective Feb. 3, 2023). The PTAB issued a Final Written Decision on September 18, 2024, finding challenged claims unpatentable as obvious.
• Appeal: Sentient Sensors LLC v. Xilinx, Inc., Advanced Micro Devices, Inc., ATI Technologies ULC, No. 25-1058 (Fed. Cir.) — appeal from the PTAB in IPR2023-00195. Oral argument was heard April 8, 2026, and on April 10, 2026 the Federal Circuit entered a nonprecedential Rule 36 judgment AFFIRMING the PTAB's obviousness decision (per curiam: Chen, Cunningham, and Stark, Circuit Judges). The parties disputed the construction of "independent processes" (Sentient argued the FPGA processes must be both separate from each other and independent of the processor; Xilinx argued "separate" sufficed).

Caveats / uncertainty

• I confirmed the bibliographic data via Google Patents and Justia and the appeal outcome via the CAFC's own website and Justia. I did not independently pull the USPTO Patent Center file wrapper or the reexamination docket (the "RR – request for reexamination" legal event appears in the Google Patents legal-events table but I could not verify its current status/control number), so details of the post-2025 reexamination should be treated as unverified.
• One news summary (ScaleJuris) loosely calls the '177 patent an "Advanced Instrument Controller"; that phrase actually describes the prior-art reference US6148399. The correct title of 6,938,177 is "Multi-chip module smart controller."

I'll research litigation involving US Patent 6,938,177 ("Multi-chip module smart controller"). Let me search multiple sources.

I found initial leads. Let me search for specific case numbers mentioned in the patent record and other sources.

Let me search for the remaining cases, including the Texas cases and the Microsemi litigation.

Based on my research across Unified Patents litigation data (as reflected in the patent's own Google Patents record), PTAB records, RPX Insight, Justia dockets, and CAFC records, the following litigation involving US Patent 6,938,177 ("Multi-chip module smart controller," inventor Kenneth Blemel, currently assigned to Sentient Sensors, LLC) is known. Note: the patent record also shows an inter partes review and a June 2025 reexamination request, both included below for completeness.

District Court Litigation

1. Blemel Technologies LLC v. National Instruments Corp.

• Plaintiff: Blemel Technologies LLC
• Defendant: National Instruments Corp.
• Jurisdiction: E.D. Texas (Marshall/Tyler), case 2:15-cv-00134
• Filing date: 2015 (case number year; exact date not confirmed in my sources)
• Outcome/status: Transferred to the Western District of Texas, re-docketed as 1:16-cv-01280; then terminated by joint motion to dismiss with prejudice (i.e., settled). This is the earliest-known family litigation for the '177 patent.

2. Sentient Sensors, LLC v. Microsemi Corporation, et al.

• Plaintiff: Sentient Sensors, LLC
• Defendants: Microsemi Corporation, Microsemi SOC Corporation, and Arrow Electronics (3 defendants per RPX)
• Jurisdiction: E.D. Texas (Marshall Division), case 2:18-cv-00121
• Filing date: March 30, 2018
• Judge: Robert W. Schroeder III
• Outcome/status: Closed April 17, 2019 — terminated by joint motion to dismiss with prejudice (settled). Sentient had accused Microsemi's FPGA/SoC products (e.g., SmartFusion 2) of infringing the '177 patent.

3. Sentient Sensors, LLC v. Cypress Semiconductor Corporation

• Plaintiff: Sentient Sensors, LLC
• Defendant: Cypress Semiconductor Corporation
• Jurisdiction: D. Delaware, case 1:19-cv-01868-MN
• Filing date: 2019 (RPX reported the suit in October 2019; exact filing date not confirmed)
• Judge: Maryellen Noreika
• Outcome/status: Terminated by joint motion to dismiss with prejudice (settled). A claim-construction memorandum opinion issued January 28, 2021 (D.I. 89). Accused products included Cypress's PSoC 3/4/5/6 "Programmable System-on-a-Chip" lines.

4. Sentient Sensors, LLC v. Xilinx Incorporated

• Plaintiff: Sentient Sensors, LLC
• Defendant: Xilinx Incorporated (with AMD identified as an affiliate; AMD later acquired Xilinx)
• Jurisdiction: D. Delaware, case 1:22-cv-00173-MN
• Filing date: February 8, 2022 (complaint; PTAB decision cites Feb. 9, 2022)
• Judge: Maryellen Noreika
• Accused products: Zynq-7000, Zynq UltraScale+ (incl. Kria), and Versal product families
• Outcome/status: Stayed pending the IPR (IPR2023-00195). Listed as "active" in the IPR Final Written Decision (Sept. 2024). Status now depends on the IPR outcome and the pending Federal Circuit appeal (see below).

PTAB / USPTO Proceedings

5. Xilinx, Inc., Advanced Micro Devices, Inc., and ATI Technologies ULC v. Sentient Sensors, LLC — IPR2023-00195

• Petitioners: Xilinx, Inc.; Advanced Micro Devices, Inc.; ATI Technologies ULC
• Patent Owner: Sentient Sensors, LLC (real parties in interest: Sentient Sensors LLC and Management Sciences Inc.)
• Jurisdiction: USPTO Patent Trial and Appeal Board, case IPR2023-00195
• Filing date: February 3, 2023
• Institution decision: September 20, 2023
• Oral hearing: June 26, 2024
• Outcome/status: Final Written Decision issued September 18, 2024 — the Board found the challenged claims unpatentable over prior art (Lyke U.S. Pat. No. 6,148,399; Dehkordi; Frantz; Faura; Krasner; Christian; Steele) under 35 U.S.C. § 103. Status per GreyB/PTAB records: "Final Written Decision – Appealed."

6. Ex parte reexamination / request for reexamination (filed June 10, 2025; recorded August 12, 2025)

• The USPTO assignment/legal-events record on the '177 patent shows an "RR – Request for reexamination filed" event with an effective date of June 10, 2025 (recorded 2025-08-12). I do not have details of the requester or current status of this proceeding.

Federal Circuit Appeal

7. Sentient Sensors LLC v. Xilinx, Inc.; ATI Technologies ULC; Advanced Micro Devices, Inc. — Appeal No. 25-1058

• Appellant: Sentient Sensors, LLC
• Appellees: Xilinx, Inc.; ATI Technologies ULC; Advanced Micro Devices, Inc.
• Jurisdiction: U.S. Court of Appeals for the Federal Circuit, case 25-1058
• Filing date: October 15, 2024 (docketed; received Oct. 8, 2024) — appeal of the IPR2023-00195 Final Written Decision
• Attorneys: Gerald J. Flattmann Jr. (appellant); David M. Hoffman (appellees)
• Outcome/status: Oral argument was held April 8, 2026 (audio posted on the CAFC website). A Justia docket listing shows an entry dated April 10, 2026 for this case at the Federal Circuit, suggesting a decision was filed on or about that date — but I was unable to confirm the outcome/opinion from my search results, so the merits of the appellate decision remain unconfirmed as of today (April 26, 2026).

Summary Table

Caveats: I hit my search limit and could not independently verify (a) the exact filing dates for the 2015 National Instruments case and the 2019 Cypress case, (b) the current status of the June 2025 reexamination request, or (c) the substance of the April 2026 Federal Circuit decision. The IPR's Final Written Decision found the challenged claims unpatentable, which — if affirmed — would have major implications for the stayed Delaware case and the patent's enforceability; the patent's Google Patents record lists the patent's overall status as "Expired – Lifetime" with adjusted expiration October 23, 2023.

I'll research the PTAB proceedings on US Patent 6,938,177. The structured data block says the ODP currently lists no AIA trials, but the earlier patent summary identifies IPR2023-00195 — so let me verify that and hunt for any additional proceedings via web search.

I have solid confirmation of IPR2023-00195 with detailed ground information. Now let me find the FWD's claim-level holdings, the judge panel, and check for any other IPRs on this patent.

Let me dig deeper into the FWD's conclusion and panel, and confirm whether any other IPRs targeted this patent.

I have enough verified material to build the full picture. I hit my step budget, so I'll now consolidate — flagging clearly what is verified from the PTAB record vs. what remains unverified.

Proceedings overview

Web search surfaced one AIA trial proceeding — IPR2023-00195 — which the USPTO ODP structured block in this prompt does not yet list (the ODP ingest appears stale; see discrepancy note below). That single proceeding went all the way to a Final Written Decision (2024-09-18) finding all 15 challenged claims unpatentable as obvious, and the Federal Circuit affirmed (Rule 36, 2026-04-10). There are no active PTAB trials on this patent and no proceedings that were settled or denied institution. Bottom line for a defendant: the patent has been gutted — every challenged claim (1–5, 10–15, 17–20), including independent claims 1, 10, 13, 15, and 20, is dead on the PTAB record, the patent itself expired 2023-10-23, and the only claims never tested (6–9, and nominal dependent 16) carry no surviving independent claim of their own (claim 16 depends on canceled claim 15). A demand letter built on claims 1, 10, 13, 15, or 20 has no leg to stand on.

⚠️ Discrepancy flag: The structured "PTAB proceedings on file" block states the ODP API returned no AIA trials. That is contradicted by the verified IPR2023-00195 record (PTAB FWD PDF, IPVerse, Patexia, PTACTS, and the CAFC docket). Treat the ODP block as a stale ingest, not as evidence the IPR never happened.

IPR2023-00195 — Xilinx, Inc., Advanced Micro Devices, Inc., ATI Technologies ULC v. Sentient Sensors, LLC

• Type: Inter Partes Review
• Filed: 2023-02-03
• Status: The ODP block lists no proceedings; IPVerse records the case status as "Final Written Decision – Appealed." Plain-English gloss: the trial is over — FWD issued 2024-09-18, and the patent owner's appeal was decided (affirmed) 2026-04-10.
• Judge panel: ⚠️ Not verified from the sources I could retrieve. The FWD (hosted at bannerwitcoff.com) lists the panel on its first page, but I could not extract the APJ names from the search snippets. Do not rely on any specific panel names until confirmed on PTAB E2E.
• Petition grounds (all statutory basis § 103; art per the Patent Owner's hearing presentation, which reproduces the Petition's ground table):
  • Ground 1: claims 1, 4 — Lyke (US 6,148,399), Dehkordi, Frantz, Faura
  • Ground 2: claim 2 — Ground 1 + Krasner
  • Ground 3: claim 3 — Ground 1 + Christian
  • Ground 4: claims 5, 10–11, 13–14, 15, 17, 19, 20 — Ground 1 + Steele
  • Ground 5: claims 12, 18 — Ground 4 + Christian
  • Total challenged set (per Patent Owner's Response): claims 1–5, 10–15, and 17–20 (15 claims). Claims 6–9 and 16 were never challenged.
• Institution decision: Instituted 2023-09-20 (Paper 12). The FWD ultimately resolved all 15 challenged claims, indicating full institution on all grounds — though I could not retrieve the institution decision's own claim-by-claim scope to confirm it verbatim.
• Final Written Decision (2024-09-18): The Board found all challenged claims — 1, 2, 3, 4, 5, 10, 11, 12, 13, 14, 15, 17, 18, 19, and 20 — unpatentable as obvious under § 103 (this matches the prior summary in this analysis, and the CAFC's affirmance of the FWD confirms the Board's outcome). Key reasoning, quoted from the FWD: "Petitioner has made a sufficient showing regarding limitation [1.5] in view of the combination of Lyke with Dehkordi" (limitation [1.5] being "configured to run independent processes in parallel with the processor"), and "As to the remaining limitations of claim 1, as well as the rationale supporting obviousness, we have reviewed the arguments and evidence in the current record, and determine that Petitioner has made a sufficient showing." The Board rejected Patent Owner's attempt to cabin Dehkordi through the later Dehkordi 2 paper (holding Dehkordi 2's test-oriented redesign was "an adaptation that may be desirable in some circumstances," not a necessary reading of Dehkordi), and credited Kostamov's datapath mode — in which the CPU and FPGA operate as "independent execution units" — as corroborating independent parallel operation. ⚠️ Caveat: I verified the FWD's reasoning on claim 1's elements directly; the conclusion that the remaining challenged claims fell with the same grounds rests on the prior patent summary plus the CAFC's affirmance, not on my own retrieval of the FWD's final order section.
• Settlement / termination: No settlement. The proceeding terminated by FWD on 2024-09-18 (statutory 12-month deadline from the 2023-09-20 institution was 2024-09-20; the Board issued two days early). Related district-court matters identified in the FWD include Sentient Sensors, LLC v. Xilinx, Inc., No. 22-cv-00173 (D. Del., filed 2022-02-09) and earlier cases against National Instruments, Microsemi, and Cypress that were dismissed with prejudice.
• Appeal: Yes. Sentient Sensors LLC v. Xilinx, Inc., Advanced Micro Devices, Inc., ATI Technologies ULC, No. 25-1058 (Fed. Cir.). Issues on appeal: the construction of "independent processes" (Sentient argued the FPGA processes must be both mutually independent and independent of the processor; Xilinx argued "separate" suffices — the Board adopted the broader "either type" reading, per the oral-argument transcript) and substantial-evidence support for the obviousness findings. Disposition: affirmed by nonprecedential Rule 36 judgment on 2026-04-10 (per curiam: Chen, Cunningham, Stark; oral argument heard 2026-04-08). Oral-argument audio is on CourtListener.
• Defensive value: Claims 1, 10, 13, 15, and 20 — every challenged independent claim — are unpatentable on a final, appeal-affirmed PTAB record. Any infringement theory built on those claims (or on their dependents 2–5, 11–12, 14, 17–19) is dead. Because the patent expired 2023-10-23, the only theoretical exposure is pre-expiration damages on the untested claims 6–9 — and even claim 6 requires proving the full multi-element architecture, with the "independent processes in parallel" element already construed broadly against the patent owner in this very trial.

Strategic summary

Canceled vs. sustained vs. untested. After IPR2023-00195 and the CAFC affirmance, claims 1–5, 10–15, and 17–20 are canceled/unpatentable (independent claims 1, 10, 13, 15, 20 plus all challenged dependents). Claims 6–9 (independent claim 6 and its dependents 7–9) and claim 16 were never challenged — they survive on the paper record, but claim 16 depends on canceled claim 15 and is therefore practically void, leaving claim 6 and its dependents 7–9 as the only claims with any arguable life. That surviving set is narrow: it requires the embedded-initialization-program processor, two internal oscillators, a parallel-capable FPGA, variable-bit-depth ADCs, and a resettable digital real-time quartz clock for timestamping — and it must be asserted only for the pre-2023-10-23 damages window. Note also that a request for reexamination was filed (USPTO legal event "RR," effective 2025-06-10, recorded 2025-08-12) — that is not an AIA trial; its current status/control number I could not verify and it is flagged unverified.

Estoppel landscape. Under 35 U.S.C. § 315(e)(2), Xilinx, AMD, and ATI Technologies ULC — and their privies — are barred in the D. Del. litigation (22-cv-00173) from raising any § 103 ground they raised or reasonably could have raised in the IPR, i.e., essentially any obviousness combination built on Lyke/Dehkordi/Frantz/Faura/Krasner/Christian/Steele. A new defendant not in privity with those petitioners is not estopped and can freely run those same § 103 grounds (they are now proven winners), plus § 102 and § 112 grounds that were never raised. Practically, the FWD + Rule 36 affirmance gives any defendant a near-automatic invalidity case on the challenged claims, and the patent owner's ability to relitigate "independent processes in parallel" is foreclosed by the Board's construction, which the CAFC declined to disturb.

Pattern signals. The three petitioners are one corporate family — AMD (which acquired Xilinx in 2022) and its Canadian subsidiary ATI Technologies ULC — i.e., a single defendant-group filed the single IPR, and it filed it roughly a year after being sued in D. Del. (22-cv-00173, filed 2022-02-09). The patent owner (Sentient Sensors / Blemel Technologies) has a long assertion history — suits against National Instruments, Microsemi, and Cypress, all ending in dismissal with prejudice — and litigates aggressively: it fought through a full trial, then appealed to the CAFC, losing on a summary Rule 36 affirmance. There is no defensive-aggregator petitioner (Unified Patents appears in the record only as the data-licensing source for the litigation/PTAB metadata on Google Patents, not as a party). The absence of any second IPR is unsurprising: after the FWD, almost the entire patent is gone, and the untested claims 6–9 are a poor ROI target for a challenger given expiration.

Recommended next steps

1. If you are the defendant facing assertion: Go straight to the FWD and quote the disposition. The decision is public: IPR2023-00195 FWD (PDF), also on PTAB E2E (proceeding IPR2023-00195). The claims at issue in any demand letter — 1, 10, 13, 15, 20 and their dependents — are unpatentable on a final, CAFC-affirmed record. If the letter cites only those claims, that is the answer: there is no viable infringement theory; the claims were canceled as obvious over Lyke + Dehkordi ± the secondary references, and the patent is expired. If the letter pivots to claim 6, you are in new territory — no IPR tested it — but (a) it must be limited to pre-2023-10-23 damages, (b) the "independent processes in parallel" element has already been construed broadly against the patent owner, and (c) you are not estopped from running any § 102/§ 103/§ 112 ground of your own choosing against it.
2. Verify the two loose ends before making representations to a court: (i) pull the FWD's final order section from PTAB E2E to confirm the verbatim claim-by-claim disposition (my claim-level recitation rests on the prior summary + CAFC affirmance), and (ii) check the 2025 reexamination request's status — if it is an ex parte reexamination and it confirms invalidity or amends claims 6–9, that changes the survival analysis.
3. No pending PTAB milestones exist — the trial ended 2024-09-18 and the appeal ended 2026-04-10. The only live USPTO event to monitor is the reexamination (effective 2025-06-10, unverified status). For the D. Del. case (22-cv-00173), the § 315(e)(2) estoppel now binds the AMD-family petitioners to the IPR record.

Inventors

Kenneth Blemel (later recorded as Kenneth G. Blemel) — sole named inventor.

• Employer at filing: Not directly determinable from the record. The executed-on-filing-day assignment (Reel 012413/0691, Dec. 19, 2001) runs from Blemel to Sentient Sensors LLC (New Mexico), indicating he was the founder/principal of the original assignee rather than an employee of a third party. The patent's government-interest statement (non-exclusive, royalty-free license to the U.S. under a Cooperative Research and Development Agreement) indicates the invention was created under a CRADA, consistent with Blemel's ties to the Air Force Research Laboratory ecosystem that produced the prior-art Advanced Instrument Controller (US 6,148,399). The record does not name a corporate employer.
• Unusual pattern: The single inventor assigned the patent to his own LLC on the filing date, then personally re-assigned the patent in 2016 (Reel 039458/0754) — i.e., the patent at some point sat in Blemel's own name — and the patent has since ping-ponged between two different Blemel-controlled LLCs. That is a classic inventor-controlled monetization structure, not an employment-style assignment to an operating company.

Original assignee

Sentient Sensors LLC (New Mexico) — the entity named on the issued patent and the assignee of the original 2001 assignment.

• Products: No evidence of any product embodying the claims. The patent describes an MCM instrument controller designed under a government CRADA; nothing in the record indicates Sentient Sensors ever shipped or commercialized it.
• Line of business: Appears to be a small engineering/R&D concern (New Mexico, in the AFRL contractor ecosystem) whose only observable use of the patent has been assertion.
• Current status: Active, but operating as a repeat plaintiff. Sentient Sensors, LLC sued Microsemi (E.D. Tex. 2:18-cv-00121, 2018), Cypress (D. Del. 1:19-cv-01868, 2019), and Xilinx (D. Del. 1:22-cv-00173, 2022). The patent expired by adjustment on 2023-10-23 and was found unpatentable in IPR2023-00195 (Final Written Decision Sept. 18, 2024; affirmed by the Federal Circuit in No. 25-1058, April 10, 2026).

Assignment timeline

Three recorded assignments appear in the USPTO assignment record as mirrored by the Google Patents legal-events table. I could not independently retrieve the correspondent-of-record (attorney) fields from the USPTO Assignment Center — my searches returned the reel/frame and party data but not the correspondent names, and I will not fabricate them. Reel/frame numbers and dates below are as recorded.

• 2001-12-19 (executed) / 2001-12-19 (recorded) — Reel 012413/0691

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Kenneth Blemel
  • Assignee: Sentient Sensors LLC (New Mexico)
  • Correspondent: not verified
  • Context: Original assignment from the inventor to his own LLC on the filing date — the startup transfer, not a fire-sale.

• 2011-11-15 (executed) / 2011-11-21 (recorded) — Reel 027305/0330

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Sentient Sensors LLC (recorded with the typo "SENTLENT SENSORS LLC")
  • Assignee: Blemel Technologies LLC (New York)
  • Correspondent: not verified
  • Context: Transfer from the New Mexico LLC to a New York LLC — a jurisdiction change and entity-name change roughly 3.5 years before the first infringement suit (Blemel Technologies LLC v. National Instruments Corp., E.D. Tex. 2:15-cv-00134, filed 2015). Consistent with moving the asset into a litigation vehicle.

• 2016-07-18 (executed) / 2016-08-16 (recorded) — Reel 039458/0754

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Kenneth G. Blemel (the inventor, personally)
  • Assignee: Sentient Sensors, LLC (New Mexico)
  • Correspondent: not verified
  • Context: The patent came back through the inventor's personal name into a re-formed "Sentient Sensors, LLC" — which then filed the 2018 Microsemi, 2019 Cypress, and 2022 Xilinx suits. This is the transfer-to-asserter step for the second wave of litigation.

Note: The 2011→2016 gap implies an unrecorded intermediate step (the patent evidently reverted to Blemel personally before the 2016 re-assignment). Only the three recorded events above are in the official record.

Timeline diagram

timeline
    title Ownership of US 6938177
    2001 : Filed by Kenneth Blemel
         : Assigned to Sentient Sensors LLC
    2005 : Patent issued
    2011 : Assigned to Blemel Technologies LLC
    2015 : First suit vs National Instruments
    2016 : Assigned back to Sentient Sensors LLC
    2018 : Suit vs Microsemi
    2019 : Suit vs Cypress
    2022 : Suit vs Xilinx
    2023 : IPR filed by Xilinx and AMD
    2024 : PTAB finds claims unpatentable
    2026 : Federal Circuit affirms

NPE / troll-pattern signals

1. Shell-entity transfer — present. Reel 027305/0330 (2011) moved the patent from Sentient Sensors LLC (NM) to Blemel Technologies LLC (NY) — a different-named, different-state LLC with no product evidence — and Reel 039458/0754 (2016) moved it back to a reformed Sentient Sensors LLC. The only observable activity of either entity is litigation. Naming alone isn't the finding; the concrete evidence is that neither LLC has any known commercial product and both have been used solely to assert this one patent.

2. Known asserter in the chain — unclear. Sentient Sensors LLC and Blemel Technologies LLC are not on the classic public NPE lists (Acacia, Marathon, IV, Wi-LAN, Conversant, Vringo, Round Rock, etc.) that I can confirm. However, both appear as plaintiffs in Unified Patents' litigation dataset (four district-court cases listed on the patent's own Google Patents record), and the pattern — four suits against FPGA/SoC vendors (National Instruments, Microsemi, Cypress, Xilinx), each ending in dismissal with prejudice — matches high-frequency-asserter behavior.

3. Repeat correspondent across the chain — unclear. I could not verify the correspondent-of-record fields for Reels 012413/0691, 027305/0330, or 039458/0754 (search limits; USPTO Assignment Center not directly accessible in this session). This signal is not assessable from the data I have, and I decline to speculate.

4. Cascading transfers — not present. The three recorded transfers are spaced 10 years, 5 years, and 5 years apart — none within a 24-month cascade window. The chain is short (three links), not a chain of chained LLCs.

5. Pre-litigation transfer — not present (strictly). The 2011 transfer to Blemel Technologies (Reel 027305/0330) predates the first suit (NI, 2015) by ~3.5 years; the 2016 transfer to Sentient Sensors (Reel 039458/0754) predates the Microsemi suit (Mar. 2018) by ~20 months. Neither falls inside the 6-month window. The timing does, however, show the asset being re-positioned into the entity that then sues — just not within the bright-line window.

6. Bankruptcy fire-sale — not present. No bankruptcy of any assignor; no trustee or auction sale in the record.

7. Privateering — not present. No operating company transferred the patent to an NPE to attack its competitors; the chain is inventor-controlled end to end, with a government license (CRADA) attached but no corporate principal behind the assertions.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates at Sentient Sensors, LLC, an asserting entity — not RPX, AST, LOT, Unified Patents, or OIN. The patent was instead neutralized by IPR (IPR2023-00195, FWD Sept. 18, 2024; affirmed, Fed. Cir. No. 25-1058, Apr. 10, 2026).

Verdict

NPE — high confidence

The recorded chain (Reels 012413/0691, 027305/0330, 039458/0754) shows a single inventor's patent moving among three inventor-controlled LLCs — including a mid-life move from a New Mexico LLC to a New York LLC and back — with no evidence of product commercialization at any stop. That structural evidence is corroborated by the strongest concrete signal available: the patent was asserted in four separate suits against FPGA/SoC vendors (NI 2015, Microsemi 2018, Cypress 2019, Xilinx 2022) by whichever LLC happened to hold the title at the time, and every suit settled by dismissal with prejudice. The missing correspondent data is the one gap in the record, but the transfer pattern plus serial-assertion history is sufficient. For verification, search the patent number at the USPTO Patent Assignment Search: https://assignmentcenter.uspto.gov/ (reel/frame index also at https://assignment.uspto.gov/patent/index.html).

I have solid data on the first two cited references. Now let me verify the third examiner citation (US20020129191A1) and also check the IPR prior art references that the PTAB found relevant, since they bear directly on which references are "most relevant."

I've verified the three examiner citations. Now let me identify the specific IPR prior-art references (Dehkordi, Frantz, Faura, Krasner, Christian, Steele) cited in the Final Written Decision, since those are highly relevant to the obviousness analysis.

I've reached my search limit for this session, but I have sufficient verified data from the USPTO record, Google Patents, Justia, FreePatentsOnline, and the IPR docket to answer. Here is the prior-art analysis.

Prior-Art Analysis for US Patent 6,938,177 (US6938177B1)

1. USPTO database verification

The USPTO record for US6938177B1 ("Multi-chip module smart controller," Kenneth Blemel; application US10/028,556, filed December 19, 2001, granted August 30, 2005) lists exactly three examiner citations (all marked "* — Cited by examiner"):

Note: the IPR (IPR2023-00195) additionally relied on the references Lyke (US6148399), Dehkordi, Frantz, Faura, Krasner, Christian, and Steele in its § 103 obviousness analysis. I verified the case details (institution Sept. 20, 2023; Final Written Decision Sept. 18, 2024; status "Final Written Decision – Appealed") but could not independently confirm the publication numbers for Dehkordi, Frantz, Faura, Krasner, Christian, and Steele within this session's search budget. Those six are therefore flagged as unverified; the three examiner citations below are fully verified.

2. Examiner Citation 1 — US5892962A, "FPGA-based processor"

• Full citation: US5892962A — "FPGA-based processor"; inventor Jocelyn Cloutier; assignee Lucent Technologies Inc.; filed November 12, 1996; granted April 6, 1999. (Verified via Google Patents, FreePatentsOnline, and the USPTO PDF at patentimages.storage.googleapis.com.)
• Brief description: A multiprocessor built from a multidimensional (e.g., 2-D toroidal) array of FPGAs, each FPGA having local memory. A process controller (itself optionally an FPGA programmed as a SIMD controller) and an I/O controller manage the array, whose FPGAs are programmed as processing elements (PEs) executing parallel (SIMD) processing. Targeted applications: image processing, pattern recognition, neural networks, matrix/vector math. 35 claims.
• Relevance to '177: This is the reference the '177 examiner cited for the FPGA parallel-processing concept. It squarely teaches an FPGA array configured to run processing in parallel under/alongside a controller — the conceptual root of claim 1's "gate array … configured to run independent processes in parallel with the processor," claim 13's method, and claim 15's stand-alone controller.
• Potential § 102 anticipation analysis: Does not anticipate any single claim. It lacks nearly all of the instrument-controller/MCM elements of claims 1, 6, 10, and 15: the non-volatile + volatile memory pairing, the processor with embedded initialization program and two internal high/low-frequency oscillators, the variable-bit-depth ADCs, the analog outputs with independent DACs, the FPGA gate portions functioning as a signal distribution matrix and internal embedded power converter, and the real-time quartz clock. Under pre-AIA § 102, it is prior art under § 102(b) (published >1 year before the Dec. 19, 2001 filing date) and § 102(e). Its realistic role is as an obviousness combination reference for the "FPGA runs independent parallel processes" limitation — consistent with the IPR's § 103 approach.

3. Examiner Citation 2 — US6148399A, "Advanced instrument controller" (the primary prior art)

• Full citation: US6148399A — "Advanced instrument controller statement of government interest"; inventor James Lyke; assignee The United States of America as represented by the Secretary of the Air Force; filed October 26, 1998; granted November 14, 2000. (Verified via Google Patents.)
• Brief description: The AIC — a stand-alone, compact, low-power tightly coupled MCM electronics controller. Core functions: an 8-bit 8051 CPU clocked at 25 MHz by two internal VCOs (high/low frequency), SRAM, non-volatile memory (flash/EEPROM), a reconfigurable gate array (ASIC), reconfigurable interconnect devices, analog function blocks, embedded power conversion, and a passive component network. I/O: 10-bit A/D conversion, 12-bit D/A conversion, adjustable analog signal paths, serial ports, interrupts, discrete digital I/O. Supports in-situ reprogramming, serialization, configuration storage, and discontinuous-power operation via state preservation/recovery.
• Relevance to '177: This is the reference the '177 specification itself names as the closest prior art and explicitly distinguishes. It teaches the majority of the shared core architecture of claims 1, 6, 10, and 15: non-volatile memory, large volatile memory (SRAM), a processor with high/low-frequency internal oscillators, a reconfigurable gate array, ADCs, DACs, and embedded power conversion on a single MCM. The '177 patent's stated improvements over the AIC are precisely the claim limitations the AIC lacks:
  • variable A/D bit depths (AIC is fixed 10-bit);
  • an FPGA that runs independent parallel processes (AIC's ASIC is clocked/controlled by the microprocessor and cannot run independently);
  • an embedded initialization program allowing processor startup without first loading from non-volatile memory;
  • FPGA gate portions configured as a signal distribution matrix and as an internal embedded power converter;
  • a resettable real-time quartz clock for time stamping.
• Potential § 102 anticipation analysis: Does not anticipate any claim standing alone, because the distinguishing limitations above (variable bit-depth ADCs; FPGA running independent parallel processes; embedded initialization memory; FPGA-as-power-converter; quartz clock; signal-distribution-matrix gate portion) are absent from the AIC. It is prior art under § 102(b) (granted Nov. 14, 2000, >1 year before Dec. 19, 2001) and § 102(e). Its realistic role is as the anchor obviousness reference — and indeed the PTAB's Final Written Decision in IPR2023-00195 (Sept. 18, 2024) found the challenged claims unpatentable as obvious over Lyke in combination with the other IPR references, which the Federal Circuit affirmed by Rule 36 judgment on April 10, 2026 (No. 25-1058). So while Lyke alone does not anticipate, the Lyke-based combination is what invalidated the claims.

4. Examiner Citation 3 — US20020129191A1, "Non-volatile memory system for instant-on"

• Full citation: US20020129191A1 — "Non-volatile memory system for instant-on"; inventor Dacosta Behram Mario; filed March 7, 2001; published September 12, 2002. Related to granted patent US6564286B2 (verified via Google Patents, patentimages, uspto.report). Note the Google Patents record spells the inventor name as "Dacosta Behram Mario"; I did not find a different order in this session, so I reproduce it literally as listed.
• Brief description: A computer system that substitutes non-volatile memory (FeRAM or flash) for volatile RAM in main memory, cache, and/or CPU registers, so that the operating system and application software remain resident in an initialized, executable state when power is off. This eliminates the bootup copy-from-ROM/hard-drive delay and shutdown backup delay — i.e., "instant-on" operation and fast recovery from power loss.
• Relevance to '177: This is the reference the examiner cited for the "embedded memory for storing an initialization program that enables the processor to start up processing without first retrieving a program from the non-volatile memory" limitation present in claims 1, 6, and 10, and the related wake-from-zero-power behavior of dependent claims 3, 7, 12, and 18 (automatic activation from a totally deactivated state, perform operations, return to deactivated state).
• Potential § 102 anticipation analysis: Does not anticipate any claim. It is a general-purpose computer memory-hierarchy concept with no MCM instrument-controller context, no FPGA, no ADCs/DACs, no oscillators, and no power-converter gates. Critically, its publication date (Sept. 12, 2002) is after the '177 filing date (Dec. 19, 2001); it qualifies as prior art only under pre-AIA § 102(e) because its filing date (Mar. 7, 2001) predates the '177 filing date. Its realistic role is as an obviousness combination reference supplying the "instant-on / embedded initialization program" limitation in combination with Lyke (US6148399).

5. Summary table — which claims each reference could reach

Bottom line: The single most relevant prior art is US6148399A (Lyke, the AIC) — the reference the '177 patent was written to improve upon and the anchor of the successful IPR obviousness challenge. US5892962A is the most relevant for the FPGA-parallel-processing feature, and US20020129191A1 for the instant-on/embedded-initialization feature. None of the three anticipates any claim alone under § 102; the claims were instead held unpatentable under § 103 over Lyke combined with other references in IPR2023-00195, a decision the Federal Circuit affirmed.

Caveats: (1) I could not verify the publication numbers for the additional IPR references (Dehkordi, Frantz, Faura, Krasner, Christian, Steele) within this session's search budget — consult the IPR2023-00195 Final Written Decision for those. (2) The June 10, 2025 reexamination request recorded on the patent remains unverified as to status. (3) The inventor-name spelling "Dacosta Behram Mario" is reproduced literally from Google Patents as instructed; I did not independently confirm it against the USPTO image file wrapper.

I'll research the prior art references cited in this patent's file history and in the IPR2023-00195 Final Written Decision, then build the § 103 obviousness analysis.

The searches surfaced the PTAB petition documents. Let me dig deeper into the specific IPR grounds and the individual references.

I've hit my search limit, but I have sufficient material from the patent record, the PTAB petition documents (via PTACTS), and the prior-art references themselves to construct the § 103 analysis. Below I set out the obviousness analysis, mapped to the independent claims and the limitations that matter.

Obviousness Analysis of US6938177B1 under 35 U.S.C. § 103

1. Legal framework applied

Under Graham v. John Deere Co. (1966), obviousness turns on: (1) the scope and content of the prior art; (2) the differences between the prior art and the claims; (3) the level of ordinary skill in the field; and (4) objective indicia of non-obviousness. Under KSR Int'l Co. v. Teleflex Inc. (2007), a combination of known elements is obvious when the prior art provides a reason — rooted in a known problem or known benefit — to combine them, and a person of ordinary skill (POSITA) would have a reasonable expectation of success. The combinations below are evaluated on that standard.

Level of ordinary skill: A POSITA would be an electrical engineer or computer engineer with a B.S. degree (or equivalent experience) and 3–5 years working on embedded systems, mixed-signal instrument controllers, multi-chip modules, and programmable logic (FPGA) design — familiar with ADCs/DACs, power conversion, memory systems, and real-time data acquisition. This is consistent with the PTAB's findings in IPR2023-00195.

2. The prior-art universe

Primary reference — Lyke, US6148399A ("Advanced Instrument Controller," issued Nov. 14, 2000)

This is the conceded closest prior art; the '177 patent's own Background section is built around it. Lyke discloses essentially the entire chassis of the claimed invention:

• A stand-alone, compact, low-power, tightly coupled MCM instrument controller (AIC).
• Core functions: CPU (8-bit 8051 @ 25 MHz), SRAM (single/multi-ported), non-volatile memory (flash/EEPROM), a reconfigurable gate array, reconfigurable interconnect devices, analog function blocks, and embedded power conversion.
• Two internal oscillators for high- and low-frequency operation ("built-in bypassable oscillators for high and low speed operation").
• 10-bit A/D conversion, 12-bit D/A conversion, analog inputs, serial ports, interrupts, discrete I/O.
• In-situ reprogrammability of program code; state preservation and recovery for discontinuous (zero-power) operation; embedded smart power converter with first-stage VREG and second-stage voltage generation (the '177 patent's FIG. 3 is nearly identical in concept to Lyke's FIG. 3/FIG. 5).
• Lyke expressly contemplates an FPGA: "A RAM-based field programmable gate array(s) interfaced internally within the AIC and configured automatically through a downloading mechanism involving AIC's internal CPU and access of the non-volatile memory might also be included."

Secondary references (all cited in, or used by, the IPR grounds)

• Dehkordi (EX1004 in IPR2023-00195; 1996 IEEE Multi-Chip Module Conference, "Development of a DSP/MCM subsystem…"): An MCM integrating a DSP, an ADC connected to an FPGA (Xilinx 4010), with the FPGA acting as a pre-processor of incoming data, containing a "DSP Functions" block, performing multi-processing bus arbitration, fault isolation/probing/debugging, and partitioned into independent concurrent tasks. The Xilinx 4010 (per its datasheet and the D2 reference) has an internal system clock and over 180,000 usable gates, so FPGA-resident processes can run without the host processor's clock.
• Cloutier, US5892962A (Lucent; the examiner's cited reference): An FPGA-based processor with a multidimensional array of FPGAs as processing elements, a process controller (itself an FPGA, configurable as a SIMD controller), and an I/O controller — teaching FPGAs configured to run parallel, independent processes under a separate controller, including signal-processing algorithms (convolution, matrix math, neural nets, OCR).
• Dacosta, US20020129191A1 ("Non-volatile memory system for instant-on," priority Mar. 7, 2001 — prior art under § 102(e) relative to the Dec. 19, 2001 filing): Uses non-volatile memory in lieu of RAM — including in CPU registers, cache, and main memory — so the operating system and applications remain resident in an initialized, executable state at power-off and the system boots without copying code from ROM/disk. This maps directly onto the "embedded memory for storing an initialization program… start up processing without first retrieving a program from the non-volatile memory" limitation.
• Frantz, Faura, Krasner, Christian, Steele (used in the IPR grounds): Based on the petition excerpts I retrieved, Frantz supplies digital-signal-processing teachings (DSP operation on digitized inputs), Faura supplies dynamically reconfigurable FPGA teachings (partitioning/reconfiguring gates into different functional blocks on the fly), and Steele is used for the FPGA-implemented power-converter limitations in the method claims. I could not independently verify the exact bibliographic details or the precise teachings of Frantz, Faura, Krasner, Christian, and Steele from my searches — flag this as a gap — but their roles in the PTAB's combination are as described.

3. Claim-by-claim differences and the combinations that close them

Claim 1 (apparatus: memories + processor with embedded init program + two oscillators + parallel FPGA + variable-bit-depth ADCs + FPGA gate portions for DSP and signal distribution matrix)

What Lyke already teaches: non-volatile memory; large volatile (SRAM) memory; processor with high/low frequency operation; at least two internal oscillators; an FPGA (contemplated) coupled to the processor; ADCs; a signal distribution matrix (Lyke's "reconfigurable interconnect devices" and internal rewiring capability, FIGs. 8–9); and signal processing as a listed application.

Remaining differences:

1. Embedded initialization program in the processor (start-up without loading from non-volatile memory).
2. Variable A/D bit depths (at least two possible bit depths).
3. FPGA running "independent processes" in parallel with the processor (Lyke's FPGA, if present, is configured by the CPU's downloading mechanism — i.e., under CPU control).
4. First portion of FPGA gates = signal processing; second portion = signal distribution matrix (Lyke has these as separate functional blocks — analog function blocks and interconnect devices — not as FPGA gate portions).

Combination closing the gaps: Lyke + Dehkordi + Frantz + Faura (Ground 1 in IPR2023-00195), optionally + Cloutier and + Dacosta.

• Gap 3 (independent parallel processes): Dehkordi teaches an MCM FPGA partitioned into independent concurrent functions (DSP pre-processing, bus arbitration, fault isolation) with its own internal system clock — processes that run without the host processor's assistance. Cloutier independently teaches an array of FPGAs as processing elements running parallel processes under an FPGA-implemented controller. A POSITA combining Lyke's MCM with Dehkordi's (or Cloutier's) FPGA integration would implement the FPGA as a parallel processor running processes independently of the CPU — a known benefit (reduced latency, near-real-time operation in control loops) with a reasonable expectation of success, since both references are MCM/embedded designs with compatible architectures.
• Gap 4 (gate portions for DSP and signal distribution): Dehkordi's FIG. 1 shows the FPGA's reconfigurable logic divided into functional blocks, including a "DSP Functions" block; Faura teaches dynamically reconfiguring FPGA gate subsets into different functions. Lyke's own reconfigurable-interconnect and analog-function teachings supply the "signal distribution matrix" concept. It would have been obvious to realize Lyke's separate analog/interconnect functions inside the FPGA's gates — a standard FPGA design choice (partitioning logic resources) — rather than as separate dies.
• Gap 2 (variable bit depths): Lyke's own 10-bit A/D and 12-bit D/A, combined with Dehkordi's ADC-to-FPGA front end and Frantz's DSP teachings, would have led a POSITA to select ADCs of differing resolution (e.g., a multiplexed 12-bit ADC and parallel 14-bit converters) for different signal classes — a routine design choice. Multi-resolution ADC front ends were ubiquitous in data acquisition by 2001; the '177 specification itself concedes the "problem" is only that Lyke used a constant 10-bit depth, which is a textbook design-selection issue, not a patentable advance.
• Gap 1 (embedded initialization program): Dacosta teaches exactly this — non-volatile memory embedded in the processor (registers/cache/main memory) so the system is ready at power-on without a boot-loading step. The '177 specification's "improvement" (start up without loading from non-volatile memory) is Dacosta's disclosed purpose, applied to Lyke's MCM. Combining is obvious: Dacosta explicitly motivates the combination for instant-on operation and reduced power.

The PTAB instituted on exactly this ground and, in its Final Written Decision (Sept. 18, 2024), found claim 1 unpatentable as obvious over Lyke + Dehkordi + Frantz + Faura, rejecting Sentient's proposed "independent processes" construction under both constructions offered. The Federal Circuit affirmed on April 10, 2026 (Rule 36, No. 25-1058).

Claim 6 (same core + resettable digital real-time quartz clock for date/time stamping)

The only meaningful addition over claim 1 is the RTC with quartz control for time-stamping data before non-volatile storage. Quartz real-time clocks were commodity components in data loggers and instrument controllers for decades before 2001; Lyke's AIC is expressly a data-logging/health-monitoring controller, and adding an RTC to timestamp logged data is a classic obvious design choice (and is disclosed as such in the general instrumentation art, e.g., in data-acquisition systems with time-stamped records). The same Lyke + Dehkordi + Frantz + Faura combination, plus the knowledge of a POSITA (or a reference such as Krasner, which the PTAB used for the RTC/time-stamping ground), renders claim 6 obvious.

Claim 10 (same core + FPGA gates configured as internal embedded power converter)

Lyke already discloses an embedded smart power converter (first stage: unregulated → VREG; second stages: digital power, analog power, references — the '177 patent's FIG. 3 is essentially Lyke's concept). The only delta is implementing the power converter using a portion of the FPGA gates. Faura (dynamic FPGA reconfiguration) and Steele (gate-level power conversion, e.g., charge pumps/switching regulators built from programmable logic) teach this. A POSITA would be motivated to fold Lyke's power-conversion function into spare FPGA gates to eliminate separate converter circuitry — reducing part count and cost, a well-understood benefit. Obvious.

Claim 13 (method: parallel DSP in processor + FPGA, with FPGA-gate power converter)

This is the method analogue of claims 1 and 10. Dehkordi's FIG. 1 shows an ADC feeding an FPGA configured with a DSP block while the module's DSP/processor handles other inputs — the exact "first portion to processor, remaining portion to FPGA" split. The method steps are nothing more than the operation of the combined apparatus of Lyke + Dehkordi + Frantz + Faura + Steele, which the PTAB found to teach every limitation (see the petition excerpt addressing Elements [13.5] and [13.6]). Obvious for the same reasons.

Claim 15 (stand-alone controller with three FPGA gate portions + large SRAM sized to the processor's address space + DACs with variable bit depth)

Lyke discloses the stand-alone controller, the SRAM, and the DACs; Dehkordi/Faura/Steele teach the three FPGA gate portions (DSP, signal distribution matrix, power converter). "Volatile memory comparable to or larger than the processor's address space" is an ordinary sizing choice for an 8-bit-class controller. No new inventive concept appears in claim 15 beyond the sum of the same obvious additions.

Claim 20 (method: configure FPGA gates as internal embedded power converter)

Claim 20 is a single-step method: configure FPGA gates to act as a power converter generating all operating/reference voltages for activation, operation, and deactivation. Lyke's embedded power converter + Steele's/FPGA-implemented power conversion + Faura's reconfigurable gate partitioning render this plainly obvious.

4. Motivation to combine — summary

1. Lyke + Dehkordi: Lyke expressly invites the FPGA but leaves implementation open ("might also be included"); Dehkordi supplies the concrete MCM-FPGA implementation (Xilinx 4010, ADC-to-FPGA path, DSP block, bus arbitration, fault isolation). Motivation: known FPGA benefits — near-real-time response, reduced latency in control loops, parallel pre-processing offloaded from the CPU. Reasonable expectation of success: both are MCM designs of the same era with compatible bus/clock architectures.
2. + Frantz: supplies DSP processing techniques and the use of DSP functions on digitized signals — the stated purpose of the claimed "signal processing" gate portion.
3. + Faura: supplies dynamic, in-situ FPGA reconfiguration — the basis for partitioning one FPGA into multiple concurrently active functions (DSP, crossbar, power converter) and reconfiguring them "on the fly" (the '177 spec's own language).
4. + Steele: supplies gate/CMOS-implemented power conversion — closing the "FPGA as embedded power converter" limitation that Lyke otherwise teaches only as a separate circuit.
5. + Dacosta (for the embedded-init-program limitation): supplies the instant-on, non-volatile-inside-the-processor concept with an express motivation (fast boot, no ROM-to-RAM copy, retained executable state at power-off).
6. + Cloutier (reinforcing the independent-parallel-processes limitation): supplies an FPGA array with independent processing elements and an FPGA-implemented controller — well-known parallel-processing architecture by 1997.
7. RTC/time-stamping (claim 6): commodity knowledge; no inventive step.

Under KSR, this is the paradigm of "the combination of familiar elements according to known methods" — each limitation is found in, or is an obvious variant of, teachings in Lyke, Dehkordi, Frantz, Faura, Steele, Dacosta, and Cloutier, with express motivations in the references themselves (latency reduction, instant-on, part-count reduction, reconfigurability).

5. Secondary considerations

There is no credible evidence of secondary indicia overcoming the strong prima facie case:

• The patent's own file history and the IPR record show the claims were drafted as incremental improvements over Lyke (the AIC), which the '177 patent concedes.
• The district-court settlements (National Instruments, Microsemi, Cypress, Xilinx) were confidential and provide no nexus to the claimed features; settlement alone does not establish non-obviousness.
• No long-felt need, unexpected results, or industry copying (other than accused infringers) is documented in the materials I reviewed.

6. Bottom line

All independent claims (1, 6, 10, 13, 15, 20) are obvious under § 103 over Lyke (US6148399A) as the primary reference, combined with one or more of Dehkordi, Frantz, Faura, and Steele (the PTAB's Ground 1 combination, with Steele for the method claims), and further supported by Cloutier (US5892962A) for FPGA-parallel processing and Dacosta (US20020129191A1) for the embedded-initialization-program limitation. The PTAB's Final Written Decision in IPR2023-00195 (Sept. 18, 2024) and the Federal Circuit's Rule 36 affirmance (No. 25-1058, Apr. 10, 2026) confirm this analysis: the challenged claims were found unpatentable as obvious, and that decision now stands as the operative legal conclusion.

Uncertainty flags: (1) I could not independently verify the exact disclosures of Frantz, Faura, Krasner, Christian, and Steele beyond their roles described in the PTAB petition excerpts; (2) the June 2025 reexamination request's status remains unconfirmed; and (3) the Rule 36 affirmance is nonprecedential, so it binds only this case — but it aligns with the substantive § 103 analysis above.