US 6888400

I'll verify the patent details against live sources and check for any litigation/docket appearances.

Let me check specifically for any litigation or post-grant proceedings involving this patent.

US Patent 6,888,400 — Verified Summary

Sourcing note: My verification used Google Patents (full text), Justia, FreePatentsOnline, and general web search. I did not have direct authenticated access to USPTO Patent Center, PACER, or the CAFC docket. Where I could not confirm something, I say so below rather than filling the gap.

Bibliographic data (confirmed against the patent text)

Uncertainty flagged — status conflict: The Google Patents page header also carries an "Adjusted expiration 2022-11-27" entry, which is inconsistent with the 2009 non-payment lapse in the legal-events log. I cannot reconcile these two records from the sources available; both are reported above as found.

Abstract (verbatim)

"A charge pump circuit has input and output nodes, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. A drain of the first transistor and a drain of the second transistor are connected to the input node. A source of the second transistor and a drain of the third transistor are connected to the output node. The first capacitor is connected to a gate of the second transistor. The third transistor is connected to a substrate and a source of the second transistor. When the first transistor is turned on, a voltage at the input node will charge the first capacitor. When the second transistor is turned on, the third transistor is turned on simultaneously so that the substrate and the source of the second transistor will reach the same voltage level. Then, voltage at the input node will charge the second capacitor."

Plain-language overview of the claims

Claim 1 — the sole independent claim

A charge pump built from multiple driving stages wired in a cascade (series). Each stage contains an input port, an output port, two internal nodes ("first node," "second node"), two capacitors, and four transistors:

• First capacitor tied to the first node; second capacitor tied to the output port (these are the clock-driven pump capacitors).
• First transistor — substrate → second node; gate → output port; drain → input port; source → first node. (Pre-charges the first capacitor; its gate is driven by the stage's output.)
• Second transistor — substrate → second node; gate → first node; drain → input port; source → output port. (The main charge-transfer pass device.)
• Third transistor — substrate → a first predetermined voltage; source → second node; drain → output port. (This is the body-bias/back-gate device: when it turns on, it pulls the second node—and therefore the substrates of the first and second transistors—to the output voltage level, collapsing the source-to-substrate voltage difference and suppressing the body effect.)
• Fourth transistor — substrate → a second predetermined voltage; source → second node; drain → input port. Its gate is connected to the gate of the third transistor in the previous adjacent stage. (This is the added anti-PN-junction/"initial pump" device that equalizes node voltages during the first clock cycles so the internal parasitic junctions don't forward-bias.)

Practical read of claim 1: It reads most directly onto the fifth and sixth charge pump circuits of FIGS. 11 and 13 in the specification (the variants that add transistor 152/162 and tie the body-bias transistor's substrate to a fixed rail). Note that the "Summary of Invention" and Abstract describe a three-transistor stage with the third transistor's substrate tied to the second node — the granted claim 1 instead requires four transistors with the third transistor's substrate tied to a fixed "first predetermined voltage." That is a meaningful gap between the summary narrative and the claims as issued.

Claims 2–4 — dependent on claim 1

• Claim 2: all four transistors are PMOS.
• Claim 3: all four transistors are NMOS.
• Claim 4: each of the four transistors has a triple-well structure.

Claim 5 — dependent on claim 1 (adds the front-end "input unit")

Adds an input unit whose output port feeds the input port of the first driving stage. That input unit mirrors the stage architecture but with a first transistor whose substrate goes to a third predetermined voltage, a second transistor whose substrate goes to the stage's second node, and a third transistor whose substrate goes to a fourth predetermined voltage — and whose gate is tied to the gate of the fourth transistor of the first (beginning) driving stage. This is the boundary stage that supplies the initial clock-driven voltage.

Claim 6 — dependent on claim 1 (adds the back-end "output unit")

Adds an output unit whose input port is connected to the output port of the last driving stage. It contains a first capacitor tied to that input port, a second capacitor tied to the output port, a first transistor (substrate → first node; gate → input port; drain → input port; source → output port) and a second transistor (substrate → a fifth predetermined voltage; gate tied to the gate of the third transistor of the last driving stage; source → substrate of the first transistor; drain → input port). This is the output/buffer stage.

Summary: there is only one independent claim — claim 1. Claims 2–6 all depend on claim 1. There are therefore no multiple independent claims to compare; the useful distinction is that claims 5 and 6 add the boundary input/output stages to the cascaded core.

Litigation / CAFC check

No CAFC 2026 docket (or any district-court, ITC, IPR, or reexam proceeding) involving US 6,888,400 turned up in my searches. Its citation record shows only patent-to-patent activity: five cited references (US 6,130,574; US 5,982,223; US 6,175,264; US 6,457,438 "Triple well no body effect negative charge pump"; US 6,677,806) and 13 citing documents, several from eMemory itself (e.g., US 7,576,593 and US 10,333,396).

Caveat: absence of results in a web search is not proof that no proceeding exists. I could not query PACER or the Federal Circuit's docket system directly, so I cannot state affirmatively that no 2026 CAFC appeal exists — only that I found no evidence of one.

Identifier-confusion warning (per the no-auto-correction rule): A separate, unrelated patent — Japanese Patent No. 6888400 (特許第6888400号), a "golf club set" filed 2017-04-28 by a different applicant — appeared in results. It is a distinct national right and has no relationship to US 6,888,400. Similarly, current 2026 news about Chinese litigation by "埃姆梯尔存储技术(深圳)有限公司" (a memory-patent assertion vehicle associated with Memory Technologies LLC / Longsys) involves eMMC-related patents from a Nokia portfolio and does not involve US 6,888,400.

I'll search litigation databases and related sources for US patent 6888400.

The initial results reference unrelated "'840 patents." Let me search more specifically for this patent and its owner.

Let me try more targeted searches, including the Google Patents litigation tab and possible NPE/assertion activity.

Summary finding

Based on my searches, I found no litigation involving U.S. Patent No. 6,888,400. The patent does not appear to have ever been asserted in any district court, at the ITC, or in any post-grant proceeding that I could locate.

I want to be explicit about the limits of this answer: I was able to run several web searches (including patent-litigation-oriented sources such as Unified Patents–related filings, PACER/recap-style documents surfaced via CourtListener, PTAB/PTACTS petitions, and Google Patents) but I was not able to complete a direct, exhaustive query of PACER, the CAFC docket, or the Unified Patents litigation case list before reaching my search limit. So treat this as "no litigation found" rather than an absolute negative. I did not fabricate any case to fill the gap.

Important caution — false positives you should not rely on

Several search hits referenced an "'840 Patent," but these are different patents and must not be attributed to US 6,888,400:

• Oplus v. Vizio / Sears — the "'840 Patent" claim 56 there concerns pixel entropy / inter-local neighborhood values (image processing), i.e., a completely different patent. Source: Finnegan PDF of the Oplus v. Sears order.
• ABC Products v. BonWeiry (N.D. Ill., No. 22-cv-556, a drink-caddy/home-goods design dispute) — a different "'840 Patent."
• Unified Patents IPR petitions referencing "'991," "'508," "'562," "'006," etc. — unrelated to US 6,888,400.

None of these is US 6,888,400, which is a charge pump circuit patent. I flag them only so they aren't mistaken for the patent at issue.

Patent 6,888,400 — relevant context (why litigation is unlikely)

• Title: Charge pump circuit without body effects
• Patent no.: US 6,888,400 B2, granted 2005-05-03
• Application: 10/604,405, filed 2003-07-17
• Priority: 2002-08-09 (divisional of App. 10/064,714, which issued as US 6,642,773 B2)
• Assignee: eMemory Technology Inc. (Hsinchu, Taiwan); inventors Hong-Chin Lin, Nai-Hsien Chen, Jain-Hao Lu, Chien-Hung Ho
• Legal status: Expired – Fee Related. Maintenance-fee reminder mailed 2008-11-10; lapse for failure to pay maintenance fees 2009-05-03; patent expired due to nonpayment of maintenance fees under 37 CFR 1.362 (effective 2009-05-03). (Google Patents lists an "Adjusted expiration" of 2022-11-27, but the patent actually went abandoned/expired in 2009.)
• Owner profile: eMemory is a technology/IP-licensing company (embedded non-volatile memory IP). Its model is licensing (upfront fees + royalties) rather than offensive litigation; its public reports emphasize licensing and state it was not party to certain competitive lawsuits.

Two practical reasons no litigation is likely on this patent: (1) it lapsed in 2009, leaving only a ~4-year enforceable window (2005–2009); and (2) the patent family was commercialized through eMemory's IP-licensing business rather than enforcement suits. There is also no litigation listed on the Google Patents "Litigation" record for US 6,888,400, and the "Cited By" entries are all subsequent patents (e.g., eMemory's own two-phase/four-phase charge pump patents such as US 7,576,593 and US 10,333,396), not court cases.

Requested table

Caveats

• Absence of evidence in my searches is not proof of non-assertion. If you need a definitive clearance, the authoritative checks are: PACER (all district courts), the Federal Circuit docket, USPTO Patent Trial and Appeal Board (IPR/PGR/CBM) and PatentCenter reexamination records, the ITC EDIS system, and Unified Patents' litigation case list (https://portal.unifiedpatents.com/litigation/caselist). Those resources should be queried directly for "6,888,400."
• I deliberately did not auto-correct any number. If you intended a different patent (for example the closely related sibling US 6,642,773, or a similarly numbered unrelated "'840 Patent" from the Oplus/Vizio or ABC Products matters), please confirm and I can re-run the search against that specific identifier.

I'll verify the structured block with targeted searches before concluding.

Let me run a couple more targeted checks before finalizing.

One more check on the assignee's PTAB track record for the pattern-signals section.

Proceedings overview

Total AIA trial proceedings on US 6,888,400: 0 (0 active, 0 claims invalidated, 0 claims sustained, 0 settled, 0 institution denials). The USPTO Open Data Portal structured block for this patent returns no IPR, PGR, or CBM records, and independent web verification surfaced no older or recently-filed AIA trial on this number or on its parent, US 6,642,773 — so the defensive posture is not "hardened by surviving IPRs," it is "the patent lapsed for non-payment of maintenance fees on 2009-05-03 and no challenger ever needed the PTAB."

Because there are no proceedings to enumerate, the usual per-proceeding subsections are omitted deliberately rather than left blank — I found nothing to populate them with, and I will not invent docket numbers.

Verification trail (what I checked, and what came back)

Conflation warnings — my searches repeatedly surfaced look-alike "840" patents that are not this patent. Do not let any of these enter a brief or an IPR chart:

• US 10,958,840 — the subject of IPR2024-01164 (video stabilization). Different number, different field.
• Oplus's '840 patent (pixel entropy / inter-local neighborhood parameters, litigated against Vizio) — different patent entirely.
• US 7,777,557 / US 7,920,018 (Panasonic booster circuits with multi-well body-bias) — same technical neighborhood, different patents, and the 2025 petitions there cite Meng and Park, not this disclosure.

Strategic summary

Claim status on US 6,888,400: no claim is canceled, no claim is sustained, and no claim has ever been tested. All six granted claims remain on paper exactly as issued on 2005-05-03: claim 1 (the sole independent claim, reciting first/second/third transistors plus a fourth transistor whose gate is tied to the gate of the third transistor of the previous adjacent driving unit), claims 2–4 (transistor conductivity type, triple-well structure), and claims 5–6 (the input unit and output unit appended to claim 1). There is no Final Written Decision to cite, no claim-level disposition, no Federal Circuit appeal, and no settlement. Note the substantive asymmetry with the parent, US 6,642,773: the divisional claim 1 here adds the fourth transistor and the "first/second predetermined voltage" substrate limitations, so any analysis of the parent's claims does not carry over.

Estoppel: none. Because no IPR/PGR was ever instituted, 35 U.S.C. § 315(e)(2) estoppel is a null set — no petitioner is barred from anything, and no defendant inherits a narrowed ground set. Every invalidity theory is available in district court: § 102/§ 103 on pre-2002-02-22 art, § 112 written-description/enablement attacks, and prior public use or on-sale activity. The one thing a defendant cannot do is point to an existing PTAB record as a shortcut; the validity fight, if any, starts from scratch.

The dominant fact is not a PTAB fact — it is the fee lapse. The legal events record shows the maintenance-fee reminder mailed 2008-11-10, lapse for failure to pay 2009-05-03, and docketing of discontinuation on 2009-06-23 ("PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362"). The patent therefore was unenforceable from 2009-05-03, roughly three years before IPR practice even began (2012-09-16). That explains the empty PTAB docket better than any theory of patent strength: there was never a live royalty to attack. Google Patents separately displays a computed "Adjusted expiration 2022-11-27" field, which is a term-calculation artifact and does not override the recorded lapse; treat the register's non-payment entry as controlling, and confirm with the USPTO Patent Center Maintenance Fee Events tab before taking any position. As of 2026-09-29, the § 286 six-year damages lookback reaches back only to 2020-09-29 — a period during which this patent had already been dead for eleven years — so monetary exposure is effectively zero even if the patent were somehow revived, and revival under 37 C.F.R. § 1.378 would collide with seventeen years of intervening rights and laches. There is no defensive aggregator (Unified Patents, RPX, etc.) anywhere in this chain, and eMemory Technology Inc. has not been an active PTAB appellant on this family.

Pattern signal: the absence of PTAB activity here is not a "hardened patent" signal. IPRs cluster around patents being asserted for money; this one expired by fee lapse three years before the AIA trial regime launched and was never asserted in any proceeding my searches could locate. Treat it as an abandoned asset, not a battle-tested one.

Recommended next steps

• If a demand letter cites US 6,888,400, lead with expiration, not invalidity. Pull the Maintenance Fee Events and "Expired - Fee Related" status from USPTO Patent Center and the recorded lapse (2009-05-03; discontinuation docketed 2009-06-23) from the patent's Google Patents legal events. A 2009 lapse plus the § 286 six-year bar means there is no compensable infringement window; this is a Rule 11 / fee-shifting posture question, not an invalidity question.
• Do not file an IPR. IPR remains technically available against an expired patent (the Board can institute to cancel claims notwithstanding expiration), but there is no litigation to stay, no royalties at stake, and filing would burn § 315(b) positioning and fees for zero defensive gain. Reallocate that budget to a motion or a thickness-of-the-record letter.
• If the owner asserts reinstatement, check the Patent Center for any petition decision under 37 C.F.R. § 1.378 and the fee paid, then build the intervening-rights and laches record from the 2009–2026 gap of non-use.
• If real litigation nevertheless appears, the untested § 112 angle is worth a look: the specification carries forward from application 10/064,714 "without any amendment," and the divisional claim 1's fourth-transistor limitation rests on scattered support (the FIG. 11 transistor 152 configuration and the passage that "the substrate of the transistor 98 in each driving unit 82 can be electrically connected to a predetermined voltage (Vdd for example)"). That is a support question, not a decided one — flag it as untested, because no tribunal has ever construed these claims.
• Confirm the empty docket yourself before relying on it: search the patent number in PTAB E2E / the USPTO PTAB public search and run the number through CourtListener RECAP for any district court or CAFC docket. My searches covered the ODP block, PTAB petitions, and family members, but only the USPTO registers are authoritative for a negative.

Bottom line for a defendant: the patent has no PTAB history because it has no history — it died of a missed maintenance fee on 2009-05-03, before IPRs existed and before anyone had a reason to file one. No FWD exists to link, no claim is canceled, and no claim is sustained. Your defense is expiration and the § 286 bar, not an IPR record.

I'll verify the assignment record and check for litigation/NPE signals before building the report.

Let me check for any litigation or reassignment activity involving this patent or its assignee.

I have the authoritative patent record and corroborating sources. Note: the eMMC/Nokia→Memory Technologies LLC litigation results surfaced by search are a different patent family and are not connected to US 6888400 — I exclude them. Report below.

Inventors

All four are the joint assignors on the sole recorded assignment (Reel 014745/0798, effective 2003-07-15), which conveys "ASSIGNMENT OF ASSIGNORS INTEREST" to eMemory Technology Inc. — i.e., they were eMemory personnel and assigned to their employer as a matter of course. eMemory was founded in 2000, so the 2002–2003 filing window places these inventors inside the founding engineering team of the company (see eMemory company profile: founded 2000, HQ Zhubei/Hsinchu, Taiwan — https://www.tpex.org.tw/en-us/mainboard/listed/company-detail.html?code=3529).

Unusual-pattern check: No evidence of inventor departure, no inventor-name assignment activity post-filing, and no inventor-initiated filings. Nothing to flag.

Original assignee

eMemory Technology Inc. (Taiwan) — named on the face of US 6,888,400 B2.

• Business: Pure-play developer/licensor of logic non-volatile memory (NVM) silicon IP — NeoBit, NeoFuse, NeoMTP, NeoEE, NeoFlash, NeoPUF. It licenses to foundries, IDMs, and fabless houses; it does not sell a packaged chip embodying the charge-pump claims. It is a non-manufacturing IP licensor, but it is not a litigation entity.
• Products embodying the claims: No direct product. The claims cover a charge-pump architecture used inside eMemory's licensed NVM IP macros; the charge pump is an internal building block of the licensed IP, monetized through license fees and wafer royalties.
• Status: Operating. Founded 2000; listed on the Taipei Exchange (ticker 3529) since 2011; ~330–360 employees, ~62% of opex on R&D; reported NT$3.6B revenue and NT$24.57 EPS in 2024, with record 2025 results (source: eMemory IR — https://www.ememory.com.tw/en-US/Investor/Overview; TPEx company profile above). Not acquired, not dissolved, not in bankruptcy.

Assignment timeline

Only one assignment is recorded against US 6,888,400. There is no post-issuance ownership chain.

• 2003-07-15 (executed) / recorded 2003-12-01 — Reel 014745/0798
  • Conveyance: Assignment (assignment of assignors' interest)
  • Assignor: Lin, Hong-Chin; Chen, Nai-Hsien; Lu, Jain-Hao; Ho, Chien-Hung (all four, jointly)
  • Assignee: eMemory Technology Inc., Taiwan
  • Correspondent: Not surfaced in the available record. The Google Patents legal-event entry carries only the U.S. assignment free-format text ("ASSIGNMENT OF ASSIGNORS INTEREST; ASSIGNORS:LIN, HONG-CHIN; CHEN, NAI-HSIEN; LU, JAIN-HAO; AND OTHERS; REEL/FRAME:014745/0798") and no correspondent/attorney field. The Assignment Center reel image would be required to capture the recording correspondent; I will not guess a name. No recurrence to flag.
  • Context: Founder/inventor-to-employer assignment of rights, executed two days before the divisional application was filed (US 10/604,405 filed 2003-07-17). Routine pre-filing title cleanup, not a monetization transfer.

Related title event (parent, for context only): US 6,888,400 is a divisional of application Ser. No. 10/064,714, filed 2002-08-09, which issued as US 6,642,773 B2 ("Charge pump circuit without body effects"). Per the specification's Cross Reference section, the divisional was filed with the specification and drawings carried forward "without any amendment." Google Patents lists the 10/064,714 application with a 2002-02-22 priority claim — i.e., there is an earlier priority link upstream of the 2002-08-09 date.

Post-issuance: nothing happened. No security agreements, no mergers, no change-of-name, no licenses recorded, no transfers to any LLC, aggregator, or asserter. The only post-issuance legal events are maintenance-fee events:

• 2008-11-10 — Maintenance fee reminder mailed
• 2009-05-03 — Lapse for failure to pay maintenance fees
• 2009-06-01 — Status: patent discontinuation
• 2009-06-23 — Expired due to failure to pay maintenance fee (37 CFR 1.362)

Note on the two conflicting expiry figures. The Google Patents header carries the flags "Expired - Fee Related" and "Adjusted expiration 2022-11-27," while the recorded legal events show the patent lapsing in mid-2009 for nonpayment. The 2022-11-27 figure is a computed statutory-term date (20 years from priority plus adjustments); the recorded events show the patent was abandoned ~13 years before that. No reinstatement, revival, or petition event appears in the record. I report both and flag the discrepancy rather than resolve it.

Because there is exactly one recorded assignment and it is the original inventor-to-employer grant, there is no post-issuance chain to reconstruct.

Timeline diagram

timeline
    title Ownership of US 6888400
    2002 : Parent application filed 9 Aug
    2003 : Inventors assign to eMemory 15 Jul
         : Assignment recorded 1 Dec
         : Divisional filed 17 Jul
    2005 : Patent issued 3 May
    2008 : Maintenance fee reminder mailed
    2009 : Lapsed for unpaid maintenance fees

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only assignment runs to the operating parent eMemory Technology Inc. (Reel 014745/0798). No "IP / Holdings / Licensing / Ventures" successor, no registered-agent address, no single-purpose LLC. The patent died in eMemory's name in 2009.

2. Known asserter in the chain — Not present. eMemory appears on no NPE/PAE list I can identify. It is a genuine R&D and IP-licensing operating company (TSMC Best IP Partner 15 consecutive years; 1,150+ patents; ~2,300–2,600 customers). The search hits naming "Memory Technologies LLC / MTL" as a PAE involve entirely separate Nokia eMMC patents — not this patent and not this owner; I explicitly do not import them.

3. Repeat correspondent across the chain — Unclear / not applicable. With a single recorded assignment, there is no chain across which a correspondent could recur, and the correspondent field is not exposed in the sources I have (the recording attorney on Reel 014745/0798 would need to be read off the reel image). No finding either way.

4. Cascading transfers — Not present. Zero transfers after the 2003 grant; no chained LLCs, no shared correspondent addresses, no common principals. (The only internal relationship is the divisional link to US 6,642,773, which is a prosecution event, not an ownership transfer.)

5. Pre-litigation transfer — Not present. No U.S. infringement litigation naming US 6,888,400 was found; the assignment predates issuance by ~22 months and predates any conceivable suit by years. There is no assertion to be "pre-" to.

6. Bankruptcy fire-sale — Not present. eMemory has never been in Chapter 7/11; it IPO'd in 2011 and is currently profitable. No Kodak/Nortel-style disposition.

7. Privateering — Not present. No operating company → NPE transfer; eMemory retained and then abandoned the patent itself.

8. Defensive aggregator (anti-NPE) — Not present as a recorded transfer, but note the functional equivalent: the patent was never asserted and was allowed to lapse for nonpayment of maintenance fees in 2009, which neutralizes it by abandonment rather than by acquisition into RPX / AST / LOT / Unified / OIN. The chain does not terminate at a defensive aggregator; it terminates at the original owner's fee lapse.

Verdict

Insufficient data — with an affirmative non-NPE reading.

The rubric's "Insufficient data" bucket is defined as "no records, or only the original assignment," and US 6,888,400 has exactly one recorded assignment: the four-inventor grant to eMemory Technology Inc. at Reel 014745/0798, executed 2003-07-15 and recorded 2003-12-01. There is no post-issuance chain, so no NPE signal can be scored "present," and the patent was abandoned for unpaid maintenance fees in 2009 — it has never been asserted. I deliberately do not score this as "Operating-company assertion," because that verdict requires the current assignee to both ship products embodying the claims and sue competitors, and here there is no litigation and no shipped charge-pump product.

Verification links: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ · legacy search — https://assignment.uspto.gov/patent/index.html · Google Patents legal events for US 6,888,400 — https://patents.google.com/patent/US6888400/en (see Legal Events table) · parent US 6,642,773 — https://patents.google.com/patent/[US6642773B2](/patent/US6642773B2)/en.

Confidence caveat: the correspondent of record on Reel 014745/0798 is not exposed by the sources I could reach, so link 3 cannot be fully evaluated. If you can pull the reel image from Assignment Center, that field is the one remaining gap.

I'll search for the specific patent number and its citations.

Let me get more detail on each cited reference.

Prior‑Art Analysis: US 6,888,400 B2 — "Charge Pump Circuit Without Body Effects"

1. Confirming the target patent (interpreted literally)

Important scope note for §102 purposes: Claim 1 is the only independent claim. Claims 2–6 all depend from claim 1, so a reference can only anticipate a dependent claim if it also discloses every element of claim 1. Claim 1 recites a driving unit with first, second, third and fourth transistors, specific source/gate/drain/substrate connections, and the cross‑stage limitation that "the gate of the fourth transistor within one driving unit is electrically connected to the gate of the third transistor within previous adjacent driving unit." (This four‑transistor topology corresponds to the FIG. 11 / FIG. 13 embodiments, i.e., the auxiliary transistor 152/162.)

2. The patent citations recorded for US6888400B2

The Google Patents record for US6888400B2 lists five "Patent Citations." Note on status marking: in the fetched record these five entries do not carry the "†/* Cited by examiner/Cited by third party" asterisk flag, so I can confirm only that they are the five references listed on the face of the patent — not the examiner/applicant attribution. I flag this rather than assume.

2.1 US6130574A — "Circuit configuration for producing negative voltages, charge pump having at least two circuit configurations and method of operating a charge pump"

• Full citation: US 6,130,574 A; Siemens Aktiengesellschaft; priority 1997‑01‑24; published 2000‑10‑10.
• Prior‑art date basis: Granted more than one year before the earliest priority (2002‑02‑22) → §102(b) art.
• Brief description: A circuit/charge‑pump arrangement for generating negative voltages, employing at least two circuit configurations (pump stages) and a method of operating them. Directed to the general problem of producing negative pump voltages from a low supply.
• §102 assessment: Relevant to the preamble of claim 1 (a charge pump made of plural stages/units) and to the negative‑voltage context of the specification. It does not appear to disclose the claim‑1 combination of first/second/third/fourth transistors with (a) both the first and second transistor substrates tied to the second node, (b) the third transistor substrate at a first predetermined voltage, (c) the fourth transistor substrate at a second predetermined voltage, and (d) the cross‑stage gate connection. Not a §102 anticipation of claim 1 or any dependent claim; at most §103 background/combination art.
• Confidence caveat: I did not retrieve the full text of US6130574A; the description rests on its title/abstract and general knowledge of negative‑pump architecture. Treat the element‑level mapping as provisional.

2.2 US5982223A — "Charge pump system with improved programming current distribution"

• Full citation: US 5,982,223 A; Integrated Silicon Solution, Inc.; priority 1997‑06‑20; published 1999‑11‑09.
• Prior‑art date basis: Granted well before the priority date → §102(b) art.
• Brief description: A charge‑pump system for non‑volatile memory programming that improves the distribution of programming current among pump elements/stages. Its focus is output‑current delivery/efficiency, not threshold/body‑effect correction.
• §102 assessment: Bears on the claim‑1 preamble (a charge pump comprising plural cascaded elements) and on the memory‑programming context. It does not disclose the four‑transistor driving‑unit topology, the substrate‑to‑node / substrate‑to‑predetermined‑voltage connections, or the cross‑stage gate link. Not a §102 anticipation; background/§103 art only.

2.3 US6175264B1 — "Charge pump for generating negative voltage without change of threshold due to undesirable back‑gate biasing effect"

• Full citation: US 6,175,264 B1; inventor Toshikatsu Jinbo; NEC Corporation; US filing 1999‑03‑12; foreign priority JP 10‑065817 (1998‑03‑16); granted 2001‑01‑16. (Appl. no. 09/267,158; class 327/536, 327/534.)
• Prior‑art date basis: Granted > 1 year before the earliest priority → §102(b) art.
• Brief description: A negative‑voltage charge pump whose boosting stage has a boosting capacitor on a boosted node and an n‑channel FET fabricated on a p‑type well connected to a node (the well serves as the back gate), so the well/back‑gate potential restricts the back‑gate (body) biasing effect. Claim 1 discloses a diode circuit plus cascaded boosting stages, each with a second FET whose second back gate is connected to a node and a first capacitor boosting the node; claim 10 adds a second capacitor on the FET's gate electrode and a third FET connected between that gate electrode and a node, whose back gate is connected to the node; the wells are described as being formed with opposite conductivity type to the channel (wells as back gates — an isolation structure akin to claim 4's triple well).
• §102 assessment — this is the most conceptually on‑point of the five references because it is expressly directed to eliminating back‑gate/body effect. Element correspondence to claim 1: the NEC "second FET" + first capacitor + back‑gate‑to‑node arrangement corresponds loosely to the claimed second transistor (substrate to the second node; gate to the first node) and the first capacitor; the NEC "third FET" (back gate to a node, connecting a gate electrode to that node) has some structural kinship to the claimed third transistor (source to the second node, drain to the output port). However, NEC does not disclose: the claimed first transistor (drain→input port, source→first node, gate→output port, substrate→second node); the claimed third transistor's substrate being tied to a first predetermined voltage; the claimed fourth transistor (substrate to a second predetermined voltage, source→second node, drain→input port); or the cross‑stage gate connection of claim 1. Therefore US6175264B1 does not anticipate claim 1 (or any claim depending from it). It is strong §103 art, and is best cited against the body‑effect‑reduction principle rather than the claimed topology.

2.4 US6677806B2 — "Charge pump for generating high voltages for semiconductor circuits"

• Full citation: US 6,677,806 B2; Infineon Technologies AG; priority 1999‑11‑09; granted 2004‑01‑13. (Corresponding disclosure: DE19953882C2 / WO00/38303A1.)
• Prior‑art date basis: Granted after the 2002‑08‑09 filing, but on an application with a 1999 priority → pre‑AIA §102(e) art; its DE/WO counterparts also published 2000–2001.
• Brief description: A charge pump of cascaded pump stages, each with a power transistor whose bulk (well) terminal is freely switchable and held at a predetermined potential via a well charge path substantially separate from the power path. In a preferred form, first and second well charging transistors (M4x, M5x) are connected in series, their junction connected to the bulk terminal of the power transistor (M1x), with the outer terminals of the series pair in parallel with the power transistor's outputs; control transistors (M2x, M3x) and boost capacitors (Cb1x, Cb2x) drive the stage; the power transistor may be an NMOS triple‑well device (n‑well with an inner p‑well) or a PMOS device. The stated object is to avoid the body effect (and forward‑biased well pn junctions) that otherwise limits output voltage.
• §102 assessment: This reference discloses the concept on which claim 1's third and fourth transistors (the two substrate‑biasing devices per unit, each with a terminal at the second/substrate node and a substrate at a predetermined voltage) and claim 4 (triple‑well structure) read most closely: the paired well‑charging transistors M4x/M5x feeding the bulk of the charge‑transfer transistor, plus triple‑well devices. Nevertheless it does not disclose the exact claim‑1 topology (source→second node / drain→output port for the third device; source→second node / drain→input port for the fourth device with separate predetermined voltages) nor the cross‑stage gate connection (gate of the fourth transistor = gate of the previous stage's third transistor). Not a §102 anticipation of claim 1; very strong §103 art against claims 1, 3/4.

2.5 US6452438B1 — "Triple well no body effect negative charge pump"

• Full citation: US 6,452,438 B1; Intel Corporation; priority 2000‑12‑28; granted 2002‑09‑17.
• Prior‑art date basis: Filed 2000‑12‑28 (before the earliest priority) and granted 2002‑09‑17 → pre‑AIA §102(e) art.
• Brief description: An N‑type (NMOS) negative charge pump built from triple‑well devices, eliminating body effect. Each pump stage has an N‑type switching (charge‑transfer) device, a boot capacitor on its control terminal, an N‑type pull‑up device, an N‑type control device, an N‑type pull‑down device, a storage capacitor, and a pair of N‑type well‑biasing devices coupled to the substrate (P‑well) terminals of the switching/pull‑up/control/pull‑down devices. Per claim 5, the first well‑bias device has its source at the switching device's source and its gate at the switching device's gate; the second has its source at the switching device's drain, its gate at the switching device's source, and its drain at the first device's drain (a cross‑coupled well‑bias pair that shorts the P‑well to the lower node). The stated effect is body‑effect elimination and prevention of well‑to‑diffusion junction turn‑on / latch‑up; claim 6 requires all devices in a triple well.
• §102 assessment: This reference reads on the substrate/well‑biasing‑transistor concept and on the triple‑well feature (claim 4), and it uses NMOS charge‑transfer devices (cf. claim 3). Mapping to claim 1: Intel's well‑bias pair at least arguably corresponds to a pair of substrate‑connected devices, and its storage/boot capacitors to the claimed first/second capacitors. But Intel does not disclose the claimed four‑transistor unit topology, the first/second‑node labeling and substrate connections, the third‑transistor substrate at a first predetermined voltage with the fourth‑transistor substrate at a second predetermined voltage, or the cross‑stage gate connection. Not a §102 anticipation of claim 1 or its dependent claims; substantial §103 art especially against claims 1, 3 and 4.

3. Bottom line

1. Most relevant prior art: The three body‑effect‑focused references — US6175264B1 (NEC), US6677806B2 (Infineon) and US6452438B1 (Intel) — are the ones that read on the invention's core purpose (substrate/well biasing to suppress the body effect) and on the "triple well" dependent claim. US6130574A (Siemens) and US5982223A (ISSI) are more peripheral (negative‑voltage generation and programming‑current distribution, respectively).

2. No clean §102 anticipation: On the record available, none of the five citations discloses every element of claim 1 — in particular the fourth transistor with its substrate at a second predetermined voltage and, critically, the limitation that "the gate of the fourth transistor within one driving unit is electrically connected to the gate of the third transistor within previous adjacent driving unit." Consequently none anticipates claim 1, and because claims 2–6 depend from claim 1, none anticipates them either. The five references therefore function as §103 obviousness art (individually or in combination), not as §102 anticipatory art.

3. Caveats / confidence: I could not retrieve the full specifications of US6130574A and US5982223A, so those two element‑level assessments are lower‑confidence and rest on titles/abstracts. The §102(e) characterization of US6677806B2 and US6452438B1 assumes a pre‑2003 effective filing date (consistent with the recorded priorities) and the pre‑AIAs statutory framework applicable to a 2002/2003 priority. I have not independently verified the examiner‑vs‑applicant attribution of the five citations (the fetched record shows no asterisk flags for them), and I have taken the dates as recorded by Google Patents rather than from the USPTO PatentCenter/Global Dossier.

Source: https://patents.google.com/patent/US6888400/en (patent text, claim set, and citation lists).

I'll ground this analysis by pulling details on the cited prior-art references.

Now let me pull the remaining three cited references.

Let me verify two precise details: the gate connection of the Siemens "fourth transistor," and the Infineon well-charging transistor circuit.

Obviousness Analysis — U.S. Patent No. 6,888,400 under 35 U.S.C. § 103

Patent under analysis: US 6,888,400 B2, "Charge pump circuit without body effects" (eMemory Technology Inc.; inventors Lin, Chen, Lu, Ho)
Application: 10/604,405, filed 2003-07-17; publication US 2004/0222841 A1 (2004-11-11); granted 2005-05-03
Effective filing date: 2002-08-09 (filing date of parent 10/064,714, which is itself a continuation-in-part‑filing claiming 2002-02-22); the present patent is a division of 10/064,714 (now US 6,642,773 B2), with the specification and drawings "carried forward … without any amendment."
Governing law: Pre‑AIA § 103 (application filed 2003). Graham v. John Deere Co., 383 U.S. 1 (1966); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Status: Expired — fee related (lapsed 2009-05-03 / 2009-06-23 per the legal events table).

Note on sources: I relied on the Google Patents record for US 6,888,400 and on the full text/abstract/claims of the five references listed in its Patent Citations section. Where a reference's disclosure is only partially reproduced in the material available to me (notably one gate connection in US 6,130,574), I say so explicitly rather than assume.

1. The claims at issue

The patent has six claims; claim 1 is the only independent claim.

Two drafting observations that materially affect the § 103 analysis:

1. The third transistor's gate connection is not recited in claim 1. The specification itself offers two alternatives for exactly that gate — node X (FIG. 5, first circuit 80) or node W (FIG. 9, third circuit 130) — and both are said to work identically. Claim 1 therefore reads on either.
2. The claim is drawn to the four‑transistor stage (the added transistor 152/162) with cross‑stage gating. That is the only structural difference between claim 1 and the three‑transistor stage claimed in the parent US 6,642,773 B2, which the same disclosure says is driven by the same timing diagrams (FIGS. 6, 8, 12, 14 are all described as interchangeable).

2. Person having ordinary skill in the art (PHOSITA)

A circuit designer holding a B.S. in electrical engineering (or equivalent) with roughly 2–4 years of experience designing on‑chip high‑voltage generators for non‑volatile memory (EEPROM/flash), familiar with Dickson/Schenkel charge pumps, four‑phase non‑overlapping clocking, MOS body effect, and triple‑well layout. The patent's own background touts a 1.8 V supply and ±10 V needs — the standard flash‑memory context of 2002, and precisely the context of all five cited references.

3. The prior art of record (all § 102(b) art)

All five are analogous art: same field of endeavor (on‑chip charge pumps for non‑volatile memory), same problem (generating and transferring large ± voltages without threshold/body‑effect losses), and each is cited on the face of the patent — a strong evidentiary anchor for "reasonably pertinent to the particular problem."

4. Element‑by‑element comparison of claim 1 to the references

Claim 1's four‑transistor stage is, in substance, the Siemens well‑biasing pair grafted onto the Siemens/NEC/Infineon pump stage. The mapping below uses the patent's own node labels (W = input port, Z = output port/second capacitor node, X = first node/boot node, Y = second node/well).

Net: every element of claim 1 except the express cross‑stage gate tie (last row) is disclosed, largely singly, by Siemens — and all of it is disclosed collectively by Siemens in view of NEC and Intel. The cross‑stage gate tie is the classic "design choice" element: it changes nothing but the phase at which a well‑bias transistor conducts, and it is the express teaching of the patent's own specification that the purpose is merely "avoiding PN junction conduction … at an initial operation of each cascaded stage."

5. Grounds of rejection

Ground A — Siemens in view of Intel (claims 1–4)

Claim 1. Siemens discloses the cascaded multi‑stage negative charge pump with a bootstrapped pass transistor in a dynamically biased well, plus the third/fourth well‑biasing transistor pair (well‑to‑source and well‑to‑drain). Intel teaches that in a triple‑well charge pump, per‑stage well‑biasing devices can have their drains tied together with the substrate terminals and be switched between the stage's source and drain potentials to "eliminate body effect" while being grounded/fixed at the deep n‑well. Intel's express quantification of the benefit (0.6 V vs. 2.2 V threshold degradation at −12 V out) supplies both the reason and the expected result. Claim 1 requires the third and fourth transistor substrates to be at "first/second predetermined voltages" — Intel's grounded deep n‑well and per‑stage well biasing devices, and Infineon's statement that bulk terminals "must be kept at zero volts or be per se at zero volts," teach exactly fixed‑rail well biasing as an alternative to the fully floating well of Siemens.

Claim 2/3. Siemens itself notes the configuration "can also be realized with p‑MOS transistors on an n‑substrate"; the patent concedes the NMOS version is "equivalent to the first charge pump circuit having n‑channel … transistors instead of PMOS." Polarity swap is a simple substitution of a known element for another with predictable results (KSR).

Claim 4. Siemens' FIG. 2 is a triple‑well cross‑section (p‑well in a deep insulating n‑well in a p‑substrate, both grounded). Intel and NEC likewise expressly claim triple‑well isolation. Claim 4 is squarely obvious.

Ground B — Siemens in view of NEC (claims 1, 3, 4)

NEC is the most explicit teaching of the claimed function: bias the well/back gate to a node potential so the threshold does not shift with the back‑gate bias. NEC claim 1 recites a back gate "connected to the positive power supply line via a diode" and to a node and "supplied with a potential for restricting a back‑gate biasing effect" — i.e., both the dynamic‑tracking and the fixed‑rail options; NEC claims 10/12 supply the third and fourth transistors around the second gate electrode; NEC claims 2/8 supply isolated wells in a third well with reverse‑biased junctions (the § 4 triple‑well limitation and the mechanism for keeping junctions from forward‑biasing, which is the '400's stated reason for the fixed substrate voltages). A PHOSITA seeking to reduce the "serious" body effect that the '400 background attributes to the prior art (substrates "commonly connected to a ground voltage (0 volts)") would adopt NEC's well‑node biasing.

Ground C — Infineon as primary (alternative), in view of Siemens/Intel/NEC

Infineon discloses the four‑phase, two‑transistor‑plus‑two‑capacitor pump stage (power transistor M1x, control transistor M2x, pump capacitor Cpx, boost capacitor Cbx) in an N+1 series cascade, which is a better structural match to the claimed four‑device stage than Siemens alone, and it expressly articulates the problem the '400 solves: fixed bulk biasing causes a "rising substrate control factor," and "the output voltage is limited by the last transistor in the chain." Infineon even discloses well charging transistors in series whose junction point is connected to the bulk of the power transistor — the equivalent of the '400's Y‑node biasing pair. Combined with Siemens' cascaded well‑biasing third/fourth transistor pair and NEC's back‑gate‑biasing‑restriction teaching, Infineon renders claim 1 obvious as well.

Ground D — any of the above in view of ISSI (claims 1, 5, 6)

Claim 1 does not recite clocking, but the specification's distinguishing operational feature is that "driving units are driven sequentially… when one driving unit is operating, other adjacent driving units will not operate to affect the driving unit that is working," implemented with four non‑overlapping clocks (FIGS. 6, 8). ISSI discloses a phase/clock generator producing "non‑overlapping different phase pulse trains that drive the positive and negative pump circuits" and sequential operation of groups of pump circuits for flash/EEPROM programming, and Siemens discloses the four‑clock, half‑period‑shifted cascade with a duty ratio > 0.5 "so that the second and fourth clock signals overlap… the first transistors are precharged." The sequencing architecture is therefore fully supplied.

Dependent claims 5 and 6 (boundary stages)

Claim 5 (input unit). Siemens' first circuit configuration is expressly described with "the input connection … connected to ground potential," i.e., a head/input stage; the claimed input unit differs from a driving unit only in that its first/third transistor substrates go to third/fourth predetermined voltages and in that the third transistor's gate is tied to the gate of the fourth transistor of the first driving unit. The former is the same fixed‑rail well bias already supplied by Intel/NEC/Infineon; the latter is the same cross‑stage gate tie discussed above (itself a design choice). Claim 5 adds nothing patentable over the Ground A–C combinations.

Claim 6 (output unit). The claimed output unit is the tail stage of the same cascade, with the same well‑node substrate tie and the same cross‑stage gate tie to the last driving unit. A PHOSITA terminating a charge‑pump cascade with a stage whose well bias follows the preceding stage's control signal is doing no more than applying the same well‑biasing scheme to the terminal stage — the very thing Intel does for each of its pump cells and Infineon does with its well‑charging transistor pairs.

6. Articulated motivation to combine (the KSR / In re Kahn "reasoned rationale")

A rejection must supply a reason; the record here is unusually strong because the references supply it themselves:

1. The references state the problem the '400 claims to solve. Intel: well biasing "eliminate[s] body effect," with a measured threshold penalty avoided. Infineon: fixed bulk bias "implies a rising substrate control factor … the output voltage is limited by the last transistor in the chain." NEC's title is the solution statement ("without change of threshold due to undesirable back‑gate biasing effect"). Siemens frames the failure mode as the parasitic well‑substrate bipolar turning on. A PHOSITA reading the '400's own background (substrates grounded → "the body effect is serious enough to greatly reduce the output voltage") would immediately be led to these documents.
2. Same field, same device, same purpose. All five address on‑chip charge pumps generating ±10 V/−12 V from 2.5–3.3 V supplies for EEPROM/flash program/erase. Combining them is a combination of known elements performing known functions to yield a predictable result — the touchstone of KSR.
3. The improvement is a "known technique to improve similar devices in the same way." Intel's triple‑well no‑body‑effect technique is applied to Siemens' stage, exactly as it was applied to Intel's own cells. Infineon's well‑charging transistor pair is applied to the same power transistor it was designed for.
4. Finite, predictable design space. Where to tie the substrate (source node, drain node, or a fixed supply rail) is a small set of predictable alternatives, each with a known trade‑off: dynamic tracking minimizes Vsb during transfer; a fixed rail is simpler and guarantees junction reverse‑bias at start‑up (the '400's own stated reason for using Vdd/ground for the 98/152 substrates). Select‑the‑known‑option is obvious to try where results are predictable.
5. Ordinary engineering of the cross‑stage gate tie. "When one driving unit is operating, other adjacent driving units will not operate" is a timing constraint that any four‑phase pump designer must satisfy; the simplest implementation is to drive the auxiliary device from the adjacent stage's existing control node (which is what the '400's FIG. 11 literally does with transistor 152's gate). The patent nowhere asserts any unexpected result from that connection; it says only that it prevents junction conduction "at an initial operation."

7. Where a validity defense could be mounted (and why it likely fails)

8. Bottom line

• Claim 1 is, on this record, obvious under § 103 over US 6,130,574 (Siemens) in view of US 6,452,438 (Intel) and/or US 6,175,264 (NEC), and alternatively over US 6,677,806 (Infineon) in view of the same. Siemens supplies the cascaded stage, bootstrapped pass transistor, first/second capacitors, the dynamically biased common well, and a well‑to‑source / well‑to‑drain transistor pair (the claimed third and fourth transistors) in a triple well. Intel and NEC supply the triple‑well isolation, the substrate‑tie and fixed‑rail well‑bias options ("predetermined voltages"), the reverse‑biased‑junction rationale, and the express motivation (quantified body‑effect elimination). The only element not tracked verbatim — the fourth transistor's gate being tied to the previous stage's third‑transistor gate — is a predictable timing/design choice that the specification itself justifies only as a start‑up junction‑conduction safeguard.
• Claims 2 and 3 (PMOS/NMOS) are obvious by simple substitution; Siemens itself notes the PMOS‑on‑n‑substrate alternative, and the '400 concedes equivalence.
• Claim 4 (triple well) is disclosed by Siemens (FIG. 2), Intel, and NEC.
• Claims 5 and 6 (input and output units) add only boundary stages using the same well‑bias and cross‑stage gating scheme, and are obvious over the same combinations, with US 5,982,223 (ISSI) supplying the non‑overlapping multi‑phase clocking/sequential‑stage architecture for the ordering aspect.
• The strongest (still thin) non‑obviousness foothold is the cross‑stage gate connection of the fourth transistor, unsupported by any evidenced unexpected result.

Confidence: High on the mapping of Siemens/NEC/Intel/Infineon to the claimed well‑biasing, capacitor, cascade, and triple‑well elements. Lower on the precise gate connection of Siemens' "fourth transistor" and on the exact node couplings inside the '400's input/output units — those would need the full FIG. 1/3/5 drawings and the complete claim set of US 6,130,574 and US 6,677,806 to confirm, and I have flagged them above rather than assumed them.