US 6816491

I'll search for current information on this patent, then summarize.

US Patent 6,816,491 B1 — Summary

Ground truth note: I verified this against the authoritative full text you provided (Google Patents, fetched 2026-09-28) and corroborating sources. I found no 2026 CAFC docket that specifically names patent 6,816,491; see the litigation/uncertainty note at the end.

Bibliographic data

Ownership chain (per recorded assignments): Hitachi, Ltd. / Hitachi Video & Information System → Hitachi Consumer Electronics Co., Ltd. (2013) → Hitachi Maxell, Ltd. (2014) → MAXELL, LTD. (2018) → Maxell Holdings, Ltd. (2021 merger) → MAXELL, LTD. (2021 change of name).

Family: Two continuations claim priority to the 1998-11-04 priority date — US 7,447,241 B2 (appl. 10/945,905, filed 2004-09-22) and US 8,098,695 B2 (appl. 12/235,942, filed 2008-09-23). Both list the same four inventors.

Abstract (verbatim)

"A multiplexed audio data decoder apparatus is provided in which integration of an audio decoder is easy, and has a high flexibility when the number of the formats to be processed is increased or when the specification is changed. In an external ROM 60 there are accumulated a plurality of decoding program codes corresponding to respective plural methods for compressing and encoding. A controller means 50 transfers the decoding program code corresponding to the method for compressing and encoding after changing thereof, from the external ROM 60 to an internal RAM 25. A DSP 22 starts decoding processing by using the decoding program code which is transmitted into the internal RAM 25."

Plain-language overview of the independent claims

Claim 1 — Core decoder architecture. A decoder for multiplexed, compressed audio (e.g., an MPEG transport stream carrying multiple programs). It has:

• a demultiplexer that picks out the user-selected audio stream using per-packet property/attribute info (PID-style filtering), and reads the compression/encoding method from the audio stream's header information;
• a first memory holding decoding program codes with decoding algorithms for that encoding method;
• a DSP that decodes the compressed audio in sequence using those codes;
• a read-only memory (ROM) holding multiple decoding program codes, one per supported compression/encoding method; and
• controller means that detects a change in the compression/encoding method, and transfers the matching decoding program code from the ROM into the first memory.

The DSP begins decoding using the code transferred into the first memory. Plainly: rather than hard-wiring all decoders in on-chip ROM, you keep a library of decoder programs in an external ROM and load only the needed one into fast local RAM at format-change time. This was new over the incorporated-by-reference-style prior art (Lsi Logic's fixed MPEG-2/AC-3 audio core, U.S. 5,845,249 and 6,430,533) and Hitachi's own earlier EP 0 935 385 A3.

Claim 2 — Audio + video decoder with shared work memory. Same as claim 1 plus a video decoder, and a second memory used as a work area by both the DSP and the video decoder (e.g., the A/V decode memory 80 in Fig. 6). The controller transfers the multiple decoding program codes from the ROM into that second memory in advance, and on detecting a format change also moves the relevant code into the first memory. Plainly: piggyback the audio decoder-code store onto the large A/V decode memory already present for video, so code transfer is fast and adding formats is cheap.

Claim 3 — Transfer-error check. Depends on claim 1. After the applicable decoding program code is transferred from the ROM to the first (or second) memory, the DSP performs a process for deciding whether transfer errors occurred (the spec describes CRC and/or decoding known test data and comparing with an expected value). Drafting note: claim 3 (depending on claim 1) references "said first memory or said second memory," although claim 1 has no second memory — an internal inconsistency in the claim set.

Claim 4 — Same error check, applied to claim 2. Identical subject matter to claim 3 but depends on claim 2.

Claim 5 — Error check by decoding test audio. Depends on claim 1. Adds that in the transfer-error decision process, a specific audio data sequence is decoded using the decoding program code and compared with a corresponding expected value.

Claim 6 — Same test-decode error check, applied to claim 2. Identical subject matter to claim 5 but depends on claim 2.

Claim 7 — Apparatus defined by function, no ROM/controller recited. A decoder comprising: a demultiplexer that inputs one compressed audio stream selected from a multiplex and extracts its compression/encoding method; a first memory that obtains and accumulates from an outside source a decoding program code (with decoding algorithm) corresponding to that method when the method changes; and a DSP that decodes the stream in sequence per that code. Plainly: the broad, "load decoder code from outside on format change" claim, without requiring the external ROM or controller elements.

Claim 8 — Decoder with ROM-stored multiple decoding programs. A demultiplexer selecting a user-designated compressed audio stream; a read-only memory that accumulates plural kinds of decoding program codes (each with decoding algorithms) corresponding to the respective compression/encoding methods of the multiplexed streams; and a DSP that decodes the selected stream in sequence using that code when the compression/encoding method changes.

Claim 9 — Receiver apparatus. The only apparatus-level receiver claim: receiving means for receiving the multiplexed compressed audio streams; a demultiplexer selecting the user-designated stream; a ROM accumulating plural decoding program codes with algorithms for each compression/encoding method; and a DSP decoding the selected stream per that code when the method changes. Plainly: a broadcast receiver (e.g., the set-top/tuner boxes of Figs. 10–13) built around the same loadable-decoder principle.

Notable cited prior art (of record)

U.S. 4,817,146 (GE, 1989); U.S. 5,914,955; U.S. 6,026,088 (both LSI Logic, network-on-a-chip family); U.S. 5,845,249 and U.S. 6,430,533 (LSI Logic — MPEG-2/AC-3 audio decoder core architecture and algorithm partitioning, the most on-point references); U.S. 6,288,748 (Hitachi, digital-broadcast-compatible display); U.S. 6,378,101 (Agere, multiple-program decoding for DAB); U.S. 6,449,596 (Matsushita). Foreign family citations include JP 3221763 B2 (Hitachi, "Audio codec"), JP 3651699 B2, KR 0183328 B1, and EP 0 935 385 A3 (Hitachi). Non-patent citation: "Design and Implementation of AC-3 Codes," Vol. 41, No. 3, Aug. 1995 — the AC-3 DSP decoder paper referenced in the specification's background.

Litigation / PTAB status — and an explicit uncertainty flag

• PTAB: IPR2018-00239 was filed against this patent (petitioner ZTE Corporation / ZTE (USA) Inc., filed 2017-11-22). Per the record, it was not instituted on the merits ("Not Instituted - Merits"). The '491 patent also appears in the related ZTE IPR series (IPR2018-00235, -00236, -00238, -00239, -00240) noted in petitioner counsel's pro hac vice declaration.
• District court: Asserted in Maxell, Ltd. v. ZTE Corp. (E.D. Tex. 5:16-cv-00179), which produced a reported $43.3 million verdict across seven Maxell patents (including U.S. 6,816,491) that the asserted patents survived IPR; also referenced in later filings for 5:18-cv-00136 (E.D. Tex.) and 6:21-cv-00158 (W.D. Tex.).
• CAFC 2026: I did not locate any Federal Circuit docket currently identifying U.S. 6,816,491 as an asserted/appealed patent. The Maxell Federal Circuit activity I did find in the 2025–2026 window involves other Maxell patents — e.g., Maxell v. Samsung, Nos. 26-1111, 26-1320, 26-1330 (and PTO appeals 26-1623/26-1625), plus a Maxell v. Vizio appeal that was dismissed. I cannot confirm, and therefore do not assert, that the '491 patent is part of any of those appeals. Anyone needing that answer should check PACER/CAFC dockets directly, since a patent that expired 2019-11-03 would normally only appear on appeal for pre-expiration damages, and I have no authoritative evidence of such a 2026 appeal.

All claim text, inventorship, dates, and assignee data above are taken directly from the patent document you supplied; litigation/PTAB items are grounded in the search results cited (Google Patents, Unified Patents PTAB/litigation portal, and the Docket Alarm IPR2018-00235 exhibit listing the '491 patent among those asserted in 5:16-cv-00179).

I'll research litigation involving US patent 6816491 using both the patent record data provided and targeted searches on litigation databases.

I have the patent's own litigation record. Let me now drill into each specific case to confirm details.

Litigation Involving US Patent 6,816,491

Patent: US 6,816,491 B1 — "Multiplexed audio data decoding apparatus and receiver apparatus"
Priority: 1998-11-04 · Filed: 1999-11-03 · Granted: 2004-11-09 · Anticipated expiration: 2019-11-03 (Expired – Lifetime)
Original assignee: Hitachi, Ltd. / Hitachi Video and Information System, Inc. · Current assignee: Maxell, Ltd.

Below is every matter I could confirm that implicates the '491 patent, drawn from the patent's own litigation record on Google Patents, the Unified Patents litigation/PTAB portals, Docket Alarm, RPX Insight, and contemporaneous Law360 reporting. I flag the one case I could not fully verify.

1. Maxell, Ltd. v. ZTE Corporation and ZTE USA Inc. (District Court action — the principal case)

Details. Maxell asserted eight patents originally, including the '491 patent, against ZTE USA. The '491 and '695 patents ("two audio decoding patents" per Law360) were among the patents tried. Maxell's post-trial briefing confirms the jury verdict included '491 claim 8 and claim 1, which Maxell defended against ZTE's Rule 50/Rule 59 motions. The case was preceded almost a year earlier by licensing negotiations (from June 2013). A related action against ZTE Corp. was bifurcated into Maxell Ltd. v. ZTE Corp., 5:18-cv-00080 (E.D. Tex.), which was settled on the same terms.

Case No. 5:16-cv-00179 is consolidated for pretrial purposes with 5:16-cv-00178 (Maxell v. [Huawei Device USA Inc.](/litigations/by-defendant/Huawei%20Device%20USA%20Inc.) et al.) — the '491 patent was asserted only against ZTE USA, not against Huawei.

• Sources: https://www.docketalarm.com/cases/Texas_Eastern_District_Court/5--16-cv-00179/ · https://portal.unifiedpatents.com/litigation/Texas%20Eastern%20District%20Court/case/5:16-cv-00179 · https://www.mayerbrown.com/-/media/files/news/2019/02/maxell-zte-reach-settlement-after-43m-patent-verdi.pdf

2. PTAB Inter Partes Review — IPR2018-00239

Details. ZTE's IPR petition was denied institution, so the '491 patent survived the challenge. Contemporaneous counsel correspondence (from Maxell's litigation counsel in the ZTE case) states that "each of these asserted patents also survived IPR petitions filed by ZTE," consistent with a denial.

• Sources: https://portal.unifiedpatents.com/ptab/case/IPR2018-00239 · Google Patents litigation record for US 6,816,491

3. Maxell, Ltd. v. ASUSTeK Computer Inc. (E.D. Tex.)

Caveat. The '491 patent's own litigation record (Google Patents / Unified Patents Darts-IP mapping) lists this case as a '491 matter. However, a separate Docket Alarm query tagged this same case number (5:18-cv-00136) to a different patent (US 7,995,897), and RPX lists the case as involving five patents-in-suit. I could not independently confirm from the retrieved records that the '491 patent specifically was asserted against ASUSTeK. Treat the '491 link here as "reported by the patent's litigation data, not independently verified."

• Sources: https://www.docketalarm.com/cases/Texas_Eastern_District_Court/5--18-cv-00136/Maxell_Ltd._v._ASUSTEK_COMPUTER_INC/ · https://insight.rpxcorp.com/litigation/txedce-[185754](/patent/185754)-maxell-v-asustek-computer

4. Maxell, Ltd. v. [defendant not confirmed] — W.D. Tex. Case 6:21-cv-00158

Note / limitation. The '491 patent's litigation record lists a case in the Texas Western District Court, case number 6:21-cv-00158, as part of this patent's litigation history. My targeted searches did not return the docket, the named defendant, the filing date, or the outcome. Maxell ran a multi-defendant W.D. Tex. campaign in that period (e.g., the 6:22-cv-00334 action against Lenovo entities), but I will not assume a defendant identity for 6:21-cv-00158 without verification — this should be confirmed directly via PACER or the Unified Patents case list before being relied upon.

• Source reference: Google Patents litigation record for US 6,816,491 (Darts-IP family 33307830)

Items checked but NOT found

• No Federal Circuit (CAFC) appeal involving the '491 patent was found in the sources retrieved. The ZTE district-court case ended in a confidential settlement after post-trial briefing, and the IPR was denied institution — so no apparent appellate ruling on the '491 patent.
• No litigation currently active. The '491 patent expired (anticipated) on 2019-11-03 ("Expired – Lifetime"), so it cannot be asserted in new infringement suits. No post-expiration damages-phase matters were found.
• No ITC Section 337 action naming the '491 patent was found (Maxell's later Section 337 matters, e.g., Inv. No. 337-TA-1432 against Samsung, involve different patents).

Summary table

Bottom line: The only litigation in which the '491 patent's assertion and outcome are well documented is the ZTE matter (E.D. Tex. 5:16-cv-00179), which produced a willful-infringement verdict and was settled, plus the related IPR2018-00239 that ZTE lost at the institution stage. The ASUSTeK case is reported in the patent's litigation data but its '491-specific linkage is unverified, and the W.D. Tex. 6:21-cv-00158 case is listed in the patent record but its defendant, filing date, and outcome could not be confirmed and should be verified in PACER/Unified Patents before use.

I'll research this. Let me start with the proceeding that the patent record itself surfaces, plus check for any others.

The patent's own record shows an IPR2018-00239 by ZTE (not instituted). Let me dig into that and check for other IPRs on this patent or its sibling.

Strong lead: IPR2018-00239 was part of a ZTE wave (‑00235/‑00236/‑00238/‑00239/‑00240). Let me confirm which patents each targeted and check for later petitions against the '491/'695 family.

PTAB Proceedings — US 6,816,491 ("Multiplexed audio data decoding apparatus and receiver apparatus")

Important sourcing caveat up front. The structured "PTAB proceedings on file" block says the USPTO ODP API returns no AIA trial proceedings for this patent. That is not the whole story: the patent record itself — and contemporaneous reporting — show at least one IPR filed against the '491 patent that ODP has not surfaced. I flag it below. I could not independently confirm a second '491-specific petition, so I treat IPR2018-00239 as the only one; if ODP is simply lagging on an older, non-instituted case, that is the likely explanation.

Proceedings overview

One AIA trial proceeding on US 6,816,491: IPR2018-00239 (ZTE Corp. / ZTE (USA) Inc. v. Maxell, Ltd.) — institution DENIED on the merits; zero claims canceled, zero claims adjudicated. Breakdown: 0 active, 0 claims invalidated, 0 claims sustained-in-FWD, 0 settled, 1 institution denied (non-instituted). Bottom line for a defendant: the '491 patent has never been invalidated at the PTAB and all nine claims are technically intact — but no tribunal has ever reached the merits, so "hardened" would be the wrong word. The claims are untested, not affirmed, and the patent expired on 2019-11-03, so the practical exposure today is historical (pre-expiration) damages only.

IPR2018-00239 — ZTE Corporation and ZTE (USA) Inc. v. Maxell, Ltd.

• Type: Inter Partes Review
• Filed: 2017-11-22 (the "Effective date" recorded against this PTAB case on the patent record; the case number was assigned in the 2018 IPR series). Confidence: moderate — I could not open the petition itself.
• Status: "Not Instituted – Merits" (verbatim from the record). Plain English: the Board denied institution on the merits — it never got to a trial, so there is no Final Written Decision.
• Judge panel: Not confirmed for IPR2018-00239 in the sources available. (By way of context for the same ZTE wave, the parallel non-institution decision in IPR2018-00236 on the '493 patent, Paper 9, was issued 2018-06-01 by APJs McMillan, Chung, and Hudalla.)
• Petition grounds: Not confirmed. I will not guess at the § 102/§ 103 references. Two data points that bound it: (i) ZTE filed this in a coordinated wave alongside IPR2018-00235, -00236, -00238, and -00240 — five petitions in the same Maxell v. ZTE campaign (per Maxell's lead counsel's pro hac vice declaration, 2018-03-05); and (ii) in the co-pending district case the parties narrowed '491/'695 invalidity theories, dropping Japanese App. Pub. Hei 6-295195 ("Hirose") and U.S. Pat. No. 5,765,136 ("Fukuchi") (meet-and-confer emails, 2018-06-11/12). Neither confirms what was in the IPR.
• Institution decision: Denied. The exact Paper/date for -00239 is not confirmed in my sources, but the ZTE Maxell IPR wave concluded with the Board denying ZTE's final challenge on/around 2018-07-02, per contemporaneous reporting ("PTAB驳回了中兴针对该案其中一件涉案专利提起的专利无效质疑，这也是PTAB对中兴提出相关7起无效质疑的最后一起"). Maxell then asked the district court to take judicial notice of "the USPTO's Decisions Denying Institution of Inter Partes Review of U.S. Patent Nos. 6,748,317, 6,816,491, 8,736,729, 8,098,695, and 8,339,493" — i.e., the '491 denial is part of a documented set of five.
• Final Written Decision: None. With institution denied, no FWD issued, so no claim of the '491 patent has been canceled, and none has been held patentable on the merits. Do not represent otherwise in any brief or demand response.
• Settlement / termination: N/A at the PTAB (denied pre-institution). The underlying district court case did settle: the jury returned a willful-infringement verdict of $43.3M on 2018-06-29 (E.D. Tex. No. 5:16-cv-00179; the verdict covered '491 claims 1 and 8), and the parties filed a confidential settlement on 2019-02-04.
• Appeal: None — and none is available. Under 35 U.S.C. § 314(d) a decision not to institute an IPR is final and non-appealable. (For the flavor of that rule being litigated in this very portfolio: Apple later tried to appeal the Board's Fintiv non-institution of IPR2020-00407 on Maxell's '317 patent; the Federal Circuit dismissed for lack of jurisdiction, Nos. 20-2132, -2211, -2212, -2213, 2021-1033. That is a different patent — the '317, not the '491.)
• Defensive value: The Board's denial means there is no § 315(e)(2) IPR estoppel running against ZTE (estoppel attaches only after an FWD), and, by extension, no estoppel benefit Maxell can point to against other defendants. Equally, the denial gives you no invalidating artifact to cite — if a demand letter leans on the '491 patent, you cannot say "claims 1–9 are canceled." Your leverage is different: the patent expired 2019-11-03, and the only merits rulings on '491 terms came from a district court Markman, not the PTAB.

Strategic summary

Claim status. All nine claims (1–9; claims 1, 2, and 7 independent) are UNTESTED and intact. Nothing is CANCELED; nothing was SUSTAINED by a PTAB panel. The only merits record on the '491 claims is the E.D. Tex. case, where the jury found infringement of claims 1 and 8, and the court construed the key limitations — e.g., "demultiplexer for extracting…" given its plain and ordinary meaning; "controller" disputed as a § 112 ¶ 6 term; the claims 1/2 preambles held limiting; and claim 9's "receiving means" construed as an antenna + equivalents. Those constructions live in Maxell Ltd. v. Huawei Device U.S. Inc., 297 F. Supp. 3d 668 (E.D. Tex. 2018) — a district court opinion, not a PTAB outcome. Note also the family: US 7,447,241 and US 8,098,695 are continuations of the '491, share substantially the same specification, and the '695 likewise survived a ZTE IPR denial. Any '491 assertion has two sibling patents behind it.

Estoppel landscape. Because IPR2018-00239 was denied institution, there is no IPR estoppel on either side — no FWD, no § 315(e)(2) bar. For a defendant today, every prior-art ground remains available: § 102, § 103, § 112, on any reference, in the district court. There is no "reasonably could have raised" trapdoor here. (Contrast the situation where partial institution produces Shaw-style carve-outs; that doctrine never engaged because there was no institution at all.) The counterpoint: you also get no free win from the PTAB record, and the window in which an IPR would have been most valuable has closed with expiry.

Pattern signals. The ZTE campaign was multi-petition — ZTE filed a coordinated wave against five Maxell patents (IPR2018-00235/‑00236/‑00238/‑00239/‑00240), not a single '491 petition, and every one was denied institution. A separate follow-on petitioner then filed IPR2018-00904/‑00905/‑00906/‑00907/‑00911 against the '493 patent — on a patent it "never been sued" on — which Maxell beat back with § 314(a)/General Plastic serial-petition arguments. Maxell is a serial, well-resourced enforcer (Mayer Brown, Banner & Witcoff, Finnegan) that has litigated this portfolio against ZTE, Huawei, Apple, Samsung, Motorola, VIZIO, TCL, BlackBerry, and Lenovo, and has both won IPR institution fights and appealed losses (the Fed. Cir. rehearing petition on its '251 battery patent). I found no defensive aggregator (Unified Patents, RPX) driving the '491 proceeding — IPR2018-00239 was ZTE's own litigation-driven petition. Note the ODP block being empty is almost certainly an indexing gap for a denied 2018 case, not evidence of no activity.

Recommended next steps

• Do not cite a "cancelled claim" narrative. There is no FWD and no cancellation. If you are responding to a demand letter on the '491 patent, the accurate, defensible framing is: "The only IPR ever filed against this patent (IPR2018-00239, ZTE) was denied institution; no claim has been invalidated. The patent expired on 2019-11-03; any claim is limited to pre-expiration damages and carries no injunctive leverage."
• Verify the primary source before you rely on it in a filing. Pull the IPR2018-00239 non-institution decision from USPTO PTAB E2E (Case IPR2018-00239) or the PTAB public-information portal to lock down the exact paper number, date, and panel, and confirm the asserted grounds. My filing date (2017-11-22) and the ~2018-06/07 denial date are the weakest-sourced facts here.
• Get the district court constructions. For any invalidity or non-infringement theory on '491, anchor to the '491 claim constructions in Maxell Ltd. v. Huawei Device U.S. Inc., 297 F. Supp. 3d 668 (E.D. Tex. 2018) — available on CourtListener: https://www.courtlistener.com/opinion/[7329083](/patent/7329083)/maxell-ltd-v-huawei-device-us-inc/ — and the E.D. Tex. record in No. 5:16-cv-00179.
• No live PTAB milestones to track. There is no pending trial-stage clock on the '491 patent — no institution deadline, no oral hearing, no FWD due date. If ODP later surfaces an additional '491 case (e.g., a '695-adjacent or later-filed petition I could not confirm), treat it as new and re-run the analysis; don't assume completeness from the empty ODP block alone.
• Family check. Before finalizing any defense, confirm whether the assertion also implicates US 7,447,241 and/or US 8,098,695 (same specification, separate patent numbers, separate expiry math). The '695 also saw a ZTE petition denied institution, but it is a different patent — do not import '491 conclusions onto it.

I'll research the cross-referenceable public records before assembling the report. Note in advance: the Google Patents legal-events feed I was given contains reel/frame strings but does not contain correspondent (attorney) names, so I will not invent any — I'll flag that gap explicitly.

Good — I have litigation and one correspondent data point. Let me pin down the assignment correspondents and any NPE-directory characterization.

US 6816491 — Ownership Chain and NPE-Pattern Analysis

Patent: US 6,816,491 B1 — Multiplexed audio data decoding apparatus and receiver apparatus
Appl. 09/433,049 · filed 1999-11-03 · priority JP 10-313254 (1998-11-04) · granted 2004-11-09 · anticipated expiration 2019-11-03 (Expired – Lifetime)
Family continuations: US 7,447,241 B2 (from 10/945,905) and US 8,098,695 B2 (from 12/235,942)

Data-quality note up front: the authoritative text I was given (the Google Patents record) publishes reel/frame strings and recording dates but not the correspondent (attorney) field. I retrieved exactly one correspondent for this chain from an independent USPTO filing (a 37 CFR 3.73(c) statement citing Reel 045142/0208). For the other eight recordings I could not retrieve correspondent data, and I have not fabricated any names or reel numbers. Everything below is either from the patent record itself or from the cited third-party sources.

Inventors

All four are named in the recorded assignment Reel 013637/0462 ("ASSIGNORS: FUJII, YUKIO; OBATA, SHINICHI; SHIRANE, HIROAKI; AND OTHERS"), conveying to the two co-assignees named on the issued patent.

Unusual patterns: none of the classic "inventor exodus" tells. The inventors never appear again in the chain; the patent was held inside Hitachi-affiliated entities continuously for ~18 years before moving to the Maxell name. The one mildly notable item is administrative rather than suspicious: the inventors executed the assignment 1999-11-10, but it was not recorded until 2003-01-07 — a ~3-year recordation lag (Reel 013637/0462). That pattern recurs in this chain (see the 2009 and 2014 mergers recorded in 2016) and is characteristic of a large Japanese conglomerate doing periodic bulk assignment clean-ups, not of a deliberate pre-litigation chain arrangement.

Original assignee

Hitachi Video and Information System, Inc. (recorded spelling in Reel 013637/0462: "HITACHI VIDEO AND IMFORMATION SYSTEMS, INC." — a typo in the record itself) and Hitachi, Ltd., both of Japan, as co-assignees.

• Primary line of business: Hitachi, Ltd. is a diversified Japanese industrial/consumer conglomerate; Hitachi Video and Information System, Inc. was its video/consumer-electronics and information-systems subsidiary. The patent's own field (multiplexed MPEG/AC-3 audio decoding for digital broadcast receivers) is squarely a consumer-A/V design of the late 1990s.
• Product embodiment: Plausible but not documented. Hitachi was an active manufacturer of digital broadcast receivers and MPEG/AC-3 audio decoding silicon in this era (the specification cites the AC-3 decoder literature and describes a broadcast receiver embodiment), so the claims were presumably practiced in Hitachi's own digital TV/STB line. I have no specific product evidence for this patent and will not assert one.
• Current status: Hitachi, Ltd. remains an operating public company. Hitachi Video and Information System, Inc. no longer exists as a separate entity — per recorded Reel 037859/0049 it merged into Hitachi Advanced Digital, Inc. effective 2009-04-03, which in turn merged into Hitachi Industry & Control Solutions, Ltd. per Reel 037776/0708 (executed 2014-04-01). No bankruptcy, no Chapter 7/11, no fire-sale anywhere in the chain.
• Current assignee of record: Maxell, Ltd. (1 Koizumi, Oyamazaki, Oyamazaki-cho, Otokuni-gun, Kyoto, Japan) — a real operating manufacturer (batteries, storage media, projectors, lenses, wireless charging) with 50+ years of history, per its own pleadings.

Assignment timeline

Nine recorded assignments. Reel/frame values below are taken verbatim from the patent's legal-events record.

1. 1999-11-10 (executed) / recorded 2003-01-07 — Reel 013637/0462

• Conveyance: Assignment of assignors' interest
• Assignor: Yukio Fujii; Shinichi Obata; Hiroaki Shirane; Eiji Yamamoto (inventors)
• Assignee: Hitachi Video and Information System, Inc.; Hitachi, Ltd. (co-assignees)
• Correspondent: not published in the source record (not fabricated)
• Context: Initial inventor-to-employer assignment; routine, but recorded ~3 years late.

2. 2013-06-07 (executed) / recorded 2013-06-12 — Reel 030668/0719

• Conveyance: Assignment of assignor's interest
• Assignor: Hitachi, Ltd.
• Assignee: Hitachi Consumer Electronics Co., Ltd.
• Correspondent: not published in the source record
• Context: Internal corporate reorganization — Hitachi, Ltd. pushed its consumer-product-facing IP into its consumer-electronics division (Hitachi's own description of the 2009–2013 IP alignment appears in Maxell, Ltd. v. Apple Inc., W.D. Tex. 6:21-cv-00158, Compl. ¶ 4).

3. 2014-08-26 (executed) / recorded 2014-09-08 — Reel 033694/0745

• Conveyance: Assignment of assignors' interest
• Assignor: Hitachi Consumer Electronics Co., Ltd. (listed twice in the record, "CO., LTD." and "CO, LTD." — duplicate-line artifact, not two assignors)
• Assignee: Hitachi Maxell, Ltd.
• Correspondent: not published in the source record
• Context: Internal reorganization/divestiture — consumer-electronics IP aligned with Hitachi Maxell ahead of the Maxell licensing program.

4. 2009-04-03 (executed) / recorded 2016-02-19 — Reel 037859/0049

• Conveyance: Merger
• Assignor: Hitachi Video & Information System, Inc.
• Assignee: Hitachi Advanced Digital, Inc.
• Correspondent: not published in the source record
• Context: Internal corporate merger — the original assignee absorbed. Executed 2009 but not recorded until 2016 (7-year lag).

5. 2014-04-01 (executed) / recorded 2016-02-19 — Reel 037776/0708

• Conveyance: Merger
• Assignor: Hitachi Advanced Digital, Inc.
• Assignee: Hitachi Industry & Control Solutions, Ltd.
• Correspondent: not published in the source record
• Context: Internal corporate merger, second hop of the same 2009-era absorption.

6. 2016-01-29 (executed) / recorded 2016-02-19 — Reel 037776/0765

• Conveyance: Assignment of assignor's interest
• Assignor: Hitachi Industry & Control Solutions, Ltd.
• Assignee: Hitachi Maxell, Ltd.
• Correspondent: not published in the source record
• Context: Internal reorganization — consolidates the orphaned Video/Advanced Digital line back into Hitachi Maxell alongside the 2014 transfer.

7. 2017-10-01 (executed) / recorded 2018-01-25 — Reel 045142/0208

• Conveyance: Assignment of assignor's interest (141 pages — a bulk, multi-patent portfolio assignment)
• Assignor: HITACHI MAXELL, LTD.
• Assignee: MAXELL, LTD. (Maxell's registered address: 1 Koizumi, Oyamazaki, Oyamazaki-cho, Otokuni-gun, Kyoto, Japan)
• Correspondent: NADEEN NSOULI, 71 South Wacker Drive, Chicago, IL 60606 — confirmed as the correspondent of record for this reel/frame from a USPTO 37 CFR 3.73(c) statement reproduced in IPR exhibits (e.g., the file-history exhibits for US 10,129,590 and 10,176,848). This is a single appearance in the chain; I found no second Nsouli-signed recording for this patent, so I cannot call it a repeat-player correspondent. (The same reel also shows attorney signatures "/John R." and "/Robert L." on downstream §3.73(c) statements for other Maxell patents — those are prosecution signatories, not assignment correspondents.)
• Context: Change-of-name/holding-company reorganization executed as an assignment; aligns the patent with the Maxell licensing vehicle.

8. 2021-10-01 (executed) / recorded 2021-11-29 — Reel 058255/0579

• Conveyance: Merger
• Assignor: MAXELL, LTD.
• Assignee: MAXELL HOLDINGS, LTD.
• Correspondent: not published in the source record
• Context: Pure holding-company reorganization; no change in ultimate control.

9. 2021-10-01 (executed) / recorded 2021-12-03 — Reel 058666/0407

• Conveyance: Change of Name
• Assignor: MAXELL HOLDINGS, LTD.
• Assignee: MAXELL, LTD.
• Correspondent: not published in the source record
• Context: Change of name only — the operating name "Maxell, Ltd." is restored after the holding-company merger. Chain terminates here; patent already expired (2019-11-03).

Litigation overlay (needed for the signal analysis):

• 2016-11 — Maxell, Ltd. v. ZTE Corp., E.D. Tex. 5:16-cv-00179 (patent asserted). Jury verdict 2018-06-29: $43.3M across seven patents including the '491 patent. Google Patents also records an E.D. Tex. case 5:18-cv-00136, and the '491 claims were construed in Maxell Ltd. v. Huawei Device U.S. Inc., 297 F. Supp. 3d 668 (E.D. Tex. 2018).
• 2018 — IPR2018-00239, petitioner ZTE Corporation and ZTE (USA) Inc. (Unified Patents portal entry); not instituted.
• 2021-02-19 — Maxell, Ltd. v. Apple Inc., W.D. Tex. 6:21-cv-00158; dismissed with prejudice 2021-04-01 (short-lived, likely a refiling/venue maneuver).

Timeline diagram

timeline
    title Ownership of US 6816491
    1998 : JP priority application filed
    1999 : US application filed
    1999 : Inventors assign to Hitachi units
    2003 : Inventor assignment recorded
    2004 : US patent issued
    2009 : Video unit merges into Hitachi Advanced Digital
    2013 : Hitachi Ltd assigns to Hitachi Consumer Electronics
    2014 : Assigned to Hitachi Maxell Ltd
    2016 : Three merger and assignment links recorded
         : First suit filed against ZTE in East Texas
    2017 : Hitachi Maxell assigns to Maxell Ltd
    2018 : ZTE verdict of 43.3 million dollars
    2021 : Merger into Maxell Holdings Ltd
         : Renamed back to Maxell Ltd

NPE / troll-pattern signals

Verdict

Operating-company assertion.

The chain is a single, continuous, 22-year internal ownership line — inventing engineers → Hitachi Video and Information System / Hitachi, Ltd. (Reel 013637/0462) → Hitachi Consumer Electronics (Reel 030668/0719) → Hitachi Maxell (Reels 033694/0745, 037776/0765) → Maxell, Ltd. (Reel 045142/0208) → Maxell Holdings → Maxell, Ltd. by change of name (Reels 058255/0579, 058666/0407) — with no shell LLC, no security interest, no bankruptcy, and no defensive-aggregator terminus. The end owner, Maxell, Ltd., is a genuine Japanese manufacturer (batteries, storage media, projectors) that asserted this patent itself and won a $43.3M jury verdict against ZTE on 2018-06-29 in E.D. Tex. 5:16-cv-00179, so this is an operating-company enforcing its own portfolio rather than an NPE chain.

Two honest caveats: (a) the "ships products embodying the claims" prong is only partially satisfied — the '491 claims cover a multiplexed broadcast-audio decoder, a product line Maxell no longer manufactures, so functionally this patent behaves as a monetization asset; and (b) W.D. Tex. 6:21-cv-00158 was filed 2021-02-19 in Judge Albright's court and dismissed with prejudice six weeks later (2021-04-01), a pattern consistent with venue positioning. The weakest link in this analysis is signal 3 (correspondent) — only one correspondent (Nadeen Nsouli, Reel 045142/0208) was retrievable, and the remaining eight correspondent fields must be verified directly.

Verify at: https://assignmentcenter.uspto.gov/ and https://assignment.uspto.gov/patent/index.html — search patent number 6816491 (reels to pull: 013637/0462, 030668/0719, 033694/0745, 037776/0708, 037776/0765, 037859/0049, 045142/0208, 058255/0579, 058666/0407).

I'll search for the patent and its prior-art citations to ground this analysis.

Let me confirm details on the most on-point cited references.

Prior-Art Analysis — US 6,816,491 B1

Scope note. I searched for the exact identifier 6816491 and did not substitute any similar number. The searches returned US 6,816,491 B1 ("Multiplexed audio data decoding apparatus and receiver apparatus," Hitachi) and no conflicting record. All citation lists below are read from the authoritative full text you supplied (Google Patents, fetched 2026-09-28), which enumerates 8 examiner-cited patent references, 1 non-patent citation, and 18 "family-cited" references (art cited in the related family members / foreign counterparts). I have not conflated the two lists.

1. Critical-date framework (needed before any §102 statement)

Because this application was filed 1999-11-03 (pre-AIPA), §102(e) prior art is dated from a reference's US filing date, not its foreign priority date. This matters materially below.

Effect on two cited references:

• US 6,378,101 (filed 1999-01-27) post-dates the 1998-11-04 priority date and has no earlier effective date. It is therefore not §102 prior art against any claim of the '491 patent — it can only be relevant, if at all, to the separate continuations (US 7,447,241 / US 8,098,695) if those have later critical dates. This is a correction/refinement worth flagging.
• US 6,026,088 (published 2000-02-15, but filed 1993-10-20) and US 5,914,955 (filed 1993-10-20) are §102(e) prior art as of their 1993-10-20 US filing date.

2. Examiner-cited patent references (the "of record" list)

Non-patent citation (of record):

• "Design and Implementation of AC-3 Coders" (spec. cites "AC-3 Codes"), IEEE Trans. Consumer Electronics, Vol. 41, No. 3, Aug. 1995. Describes a DSP-based AC-3 decoder — the very background the specification concedes. §102(b) printed publication. It supports claims 1 and 8 only as to the DSP decoding compressed audio using program code, and says nothing about a ROM-resident multi-format library or format-change-triggered code transfer. §103/background, not §102.

3. Family-cited references (art cited in related family members / foreign counterparts)

These are not on the examiner's "citations" list for '491 itself; they surfaced in the family's prosecution. The notable ones, with §102 potential:

4. Bottom line on §102 anticipation, claim by claim

Strict §102 requires one reference to disclose every element. On the record as cited, no reference anticipates any independent claim:

• Claims 1 and 2 — require a demultiplexer + a first memory of decoding program codes + a DSP + a ROM of plural decoding program codes + controller means transferring the format-matched code on change. The LSI Logic pair (US 5,845,249 / US 6,430,533) get closest on ROM/RAM/DSP and multi-format support, but teach fixed hardware/firmware partitioning and note the expense of large code ROMs — they do not disclose the load-on-change mechanism. No §102; §103 candidate in combination.
• Claims 3–6 — the transfer-error-check / test-decode-and-compare limitations appear to have no counterpart in any cited reference; strongest on validity, weakest as an anticipation target.
• Claim 7 — broadest. US 6,167,521 (code download) and JP H05-313908 (program download) touch the "obtain from outside" element; none combines it with the format-change-triggered loading for an audio decoder. §103, not §102.
• Claim 8 — US 5,845,249 / US 6,430,533 are the only §102(a)/(e) references with a ROM holding plural compression-method logic; the "program code" (vs. hardware state machine) limitation is the distinguishing feature. §103.
• Claim 9 — receiver claim; US 6,288,748 (receiving/display) is the nearest §102(e) art but does not disclose the ROM/format-change decoder structure. §103.

Most dangerous art, ranked: (1) EP 0 935 385 A3 (Hitachi's own; could not verify text) → (2) US 6,430,533 → (3) US 5,845,249 → (4) KR 0183328 / JP 3221763 (unverified) → (5) US 6,256,487. The first three are also the references a petitioner would most likely combine; consistent with the record that IPR2018-00239 (ZTE) was not instituted on the merits and that the asserted claims survived the related Maxell v. ZTE IPRs.

5. Explicit confidence flags and one reconciliation

• High confidence: all bibliographic dates, the 8-item examiner citation list, and the NPL citation (taken verbatim from the authoritative text).
• Lower confidence: the substance of the JP/KR/EP references (JP 3221763, KR 0183328, EP 0 935 385). My search budget was exhausted before I could retrieve their full texts, so my "potentially anticipates" characterizations for those are based on title/abstract only and should be verified against the original documents before any validity opinion is relied upon.
• Reconciliation with the earlier summary (no contradiction, one refinement): the earlier section called US 5,845,249 and US 6,430,533 "the most on-point references." That is correct for the US art of record, and I build on it — but I refine it in two ways: (a) both are properly §103 material rather than §102 anticipations, because each omits the load-decoding-program-code-on-format-change element; and (b) EP 0 935 385 A3, which the earlier section listed only as a family citation, may be at least as close substantively (Hitachi's own earlier "decoder device and receiver") — it deserves a §102(e) date check for any US counterpart.
• Reminder: the '491 patent expired 2019-11-03, so this §102 analysis is validity-historical (relevant to the IPR and to pre-expiration damages) rather than to any live infringement claim.

I'll research the key prior-art references before building the § 103 analysis.

Now let me research the Hitachi family references and other cited art.

Let me examine the ZTE IPR petition (IPR2018-00239) to see the actual obviousness theory advanced, and check other references.

Obviousness Analysis — U.S. Patent 6,816,491 B1 under 35 U.S.C. § 103(a)

Note on framework: The '491 patent was filed 1999-11-03 with a 1998-11-04 priority date, so pre-AIA § 103(a) governs. The critical date for prior art is 1998-11-04 (or 1999-11-03 for art that is only § 102(a)/102(e) art, though nothing here turns on that distinction). I use the references of record listed in the patent page's Prior Art / Citations and Family-Citations sections, as instructed. I do not repeat the claim or litigation summaries already generated; I build on them.

I flag up front the central tension this analysis must acknowledge — and I return to it in § 6: the real-world PTAB outcome (IPR2018-00239 not instituted on the merits) is not a merits finding of non-obviousness. Non-institution means the panel did not find a reasonable likelihood of prevailing on the particular petition as filed. A § 103 analysis performed independently can therefore reach the opposite provisional conclusion, and mine does. That dissonance is a feature of the record, not an error, and the reader should not treat the earlier non-institution as an invalidity shield.

1. Person of Ordinary Skill in the Art (PHOSITA)

For the 1998-11-04 critical date, the PHOSITA is a person with a bachelor's in electrical engineering or computer engineering (or equivalent) and at least 3–5 years of experience designing digital audio/video decoders for consumer electronics, including DSP-based audio decoders and MPEG transport-stream demultiplexing. This person would be intimately familiar with:

• MPEG-1/MPEG-2 Audio and Dolby AC-3 (both referenced in the patent's own background and in the LSI Logic references) as separate, conflicting compression formats that a broadcast receiver must handle;
• MPEG-2 Transport Stream syntax (PID filtering, PMT, PCR/PTS/STC), as shown in the patent's FIGS. 2(a)–(e);
• The economics of DSP program memory — specifically the tradeoff the patent itself admits: decoders with plural formats need all the format program codes residing somewhere, and "the built-in ROM cannot be easily changed," producing integration/cost problems; and
• The long-established practice of overlaying / paging program code from a slow external memory into fast internal program RAM — a standard technique in DSP design since at least the early 1990s.

This skill level matters because the entire inventive contribution of the '491 patent is an architectural partitioning decision (put the format library outside the chip; page one code in on format change), not a new algorithm.

2. Scope and Content of the Prior Art (the references of record)

2.1 JP 3221763 B2 — Hitachi, "Audio codec" (pub. JPH06295195A, 1994-10-21; granted 2001-10-22)

This is the single most on-point reference, and it is a family citation of the '491 patent itself, i.e., Hitachi's own earlier work. Per the IPR petition excerpt describing its disclosure (PTAB petition document, https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1502556](/patent/1502556)/download-documents), JP 3221763 teaches:

• Integrating "the plurality of encoding and decoding features … on one chip, to be implemented on the DSP";
• Storing "a fixed, first boot program, all types of algorithm programs and a second boot program in a read-only memory (ROM) that is a portion of a memory space in a DSP program";
• "To implement the plurality of different encoding and decoding algorithms, one targeted encoding and decoding algorithm program is selected from the DSP external data memory, and booted up by loading to the DSP internal program memory"; and
• The stated rationale — "there is a storage limit in the internal memory in DSP, so it is impossible to store in the internal DSP memory all types of encoding and decoding algorithm programs … Therefore, the present invention disposes an external large-volume (low-speed) memory and stores all the individual plurality of programs therein. One desired program is selected and booted up."

That is, in substance: a library of alternative codec programs in external ROM, selected and loaded into internal DSP program memory under host control. The differences from the '491 claims are the trigger (the '491 uses a format change detected from the incoming stream) and the multiplexing/demux context (the '491 claims recite a demultiplexer). Both of those are supplied by well-known MPEG-system art, below.

2.2 U.S. 5,845,249 — LSI Logic, "Microarchitecture of audio core for an MPEG-2 and AC-3 decoder" (filed 1996-05-03; issued 1998-12-01)

Ground truth confirmed by direct retrieval (https://patents.google.com/patent/[US5845249](/patent/US5845249)). Teaches:

• A reusable "core" that handles both MPEG and AC-3 decoding — i.e., a single decoder architecture serving plural compression formats;
• A ROM and ROM-addressing logic within the audio core, with input RAM and output RAM located outside the core (the external-work-memory architecture relevant to claim 2);
• Explicit description of the commercially available HDMS211M chip, which "includes an MPEG-2 video decoder, an audio decoder, a system stream demultiplexer (this block separates the video and audio streams), a DRAM controller" — a direct teaching of a demultiplexer feeding audio/video decoders sharing external DRAM; and
• The motivation: the expensive "each time an MPEG-2 or AC-3 decoder is to be designed for a new application, a designer will generate a new integrated circuit layout," and the desire to avoid redesign.

2.3 U.S. 6,430,533 — LSI Logic/Kolluru et al., "Audio decoder core MPEG-1/MPEG-2/AC-3 functional algorithm partitioning and implementation" (priority 1996-05-03; issued 2002-08-06)

Confirms the same family and gives the crucial cost/ROM-size teaching: "fully software/firmware-based audio decoders require large sized Code ROMs to achieve the decoding functionality, and are expensive," while "a complete hardware implementation … comes at the expense of large number of transistor device gates that consume a large chip area." It partitions decoding between firmware and a hardware core, with the input RAM "located outside of the audio core." This is directly probative of the problem the '491 patent purports to solve (chip-integration / ROM-size pressure) and of the standard solution space (move bulk storage off-chip; partition hardware/firmware).

2.4 EP 0 935 385 A3 — Hitachi, "Decoder device and receiver using the same" (priority JP 2291698, 1998-02-04; published 1999-08-11)

A Hitachi family reference describing a decoder device/receiver handling motion-picture data used in both analog and digital broadcasts with a plurality of picture format converting means … in a common memory. Relevant as (a) prior art showing a Hitachi multi-format, common-memory decoder architecture, and (b) § 102(e)/§ 103 support for the shared-memory concepts of claim 2 (https://patents.google.com/patent/EP0935385A3/en).

2.5 U.S. 6,378,101 — Agere/Lucent, "Multiple program decoding for digital audio broadcasting and other applications" (priority 1999-01-27; issued 2002-04-23)

Cited of record. Its title and subject matter — decoding multiple programs from a digital audio broadcast — supply further evidence that demand-decoding of a user-selected program from a multiplexed stream, across formats, was a recognized objective at the critical date. (Note: with a 1999-01-27 priority this is § 102(e) art relative to the '491's 1999-11-03 filing, but post-dates the 1998-11-04 priority; I therefore treat it as corroborative of the state of the art rather than as the primary § 103 anchor.)

2.6 Other of-record references

• U.S. 6,288,748 (Hitachi, display device compatible with digital broadcasts) — context of a digital-broadcast receiver with multiple format handling.
• U.S. 5,914,955 / U.S. 6,026,088 (LSI Logic, "Switched network hub on a chip" / "Network architecture") — general programmability/modularity of decoder-chip architectures; weak but supportive.
• JPH05313908A (Fujitsu, "Program guarantee method for program download type encoder," 1993-11-26) — cited in the '491 family-citation list; on its face directed to guaranteeing/validating a downloaded program in a program-download-type codec. This is the natural secondary reference for the transfer-error-checking limitations of claims 3–6.
• "Design and Implementation of AC-3 Coders," IEEE Trans. Consumer Electronics, Vol. 41, No. 3, Aug. 1995 (the sole NPL citation, referenced in the '491 specification itself) — describes a DSP-based AC-3 decoder with decoding processes stored as program codes in ROM. This is the applicant's own admitted background.

3. Claim-by-claim § 103 analysis

I use the claim construction the E.D. Tex. court adopted in the parallel Maxell litigation, which controls the operative meanings: "demultiplexer" gets its plain and ordinary meaning (Maxell Ltd. v. Huawei Device U.S. Inc., 297 F. Supp. 3d 668 (E.D. Tex. 2018), https://www.courtlistener.com/opinion/[7329083](/patent/7329083)/maxell-ltd-v-huawei-device-us-inc/); and "controller" connotes structure rather than a pure means-plus-function term (same opinion, addressing the '695 counterpart). No limitation was construed narrowly enough to avoid the art below.

Claim 1 — Core decoder (demux + first memory + DSP + ROM of plural codes + controller transferring on format change)

Primary combination: JP 3221763 B2 in view of U.S. 5,845,249 (and/or EP 0 935 385).

• Demultiplexer element: U.S. 5,845,249 explicitly locates a "system stream demultiplexer (this block separates the video and audio streams)" alongside audio and video decoders in the HDMS211M — and the '491's own FIG. 2 hierarchy (PID → PES → audio access unit with a stream-ID/format field) is the standard MPEG-2 TS art. PID-based selection of a user-designated program and extraction of the format identifier from the stream header is exactly the ordinary skill in MPEG system design.
• ROM holding plural decoding program codes: JP 3221763 expressly discloses this ("all types of algorithm programs … in a read-only memory," in an "external large-volume (low-speed) memory").
• First memory + DSP + controller transferring the matching code on change: JP 3221763 discloses loading "one targeted … algorithm program … to the DSP internal program memory" on host instruction.
• The only arguable delta is the automatic trigger — detecting a change in compression/encoding method (from the stream) and fetching the corresponding program. That is a routine design choice: the '491 specification itself concedes that "steps for the decoding processes are memorized in the built-in ROM as the program codes" was the prior-art norm. Once JP 3221763 supplies user/host-selected loading of one of plural codec programs, causing the selection to follow the detected stream format is the mere automation of a known selection step — a predictable, result-effective variable, not an inventive leap.

Motivation to combine: The LSI Logic references (U.S. 5,845,249; U.S. 6,430,533) frame the very problem JP 3221763 solves — plural formats (MPEG-2 vs. AC-3) must coexist, and monolithic on-chip ROM makes each new format a chip redesign ("a designer will generate a new integrated circuit layout"; "large sized Code ROMs … are expensive"). JP 3221763 supplies the off-chip-library/paging solution. A PHOSITA facing a broadcast receiver that must decode whichever format a tuned program carries would be motivated to (i) keep all format program codes in an external ROM and (ii) load the one needed on tune/format-change, precisely to preserve chip integration and add formats cheaply. Reasonable expectation of success is high, because code-overlay from external memory into internal program RAM was a conventional, well-understood technique.

Claim 2 — Claim 1 + video decoder + shared second (work) memory, codes pre-loaded into that memory

Combination: JP 3221763 + U.S. 5,845,249 + EP 0 935 385 A3.

• Video decoder: U.S. 5,845,249's HDMS211M expressly includes "an MPEG-2 video decoder … an audio decoder … a DRAM controller."
• Second memory used as a work area by both DSP and video decoder: U.S. 5,845,249 teaches audio core input/output RAMs external to the core, and EP 0 935 385 teaches plural format-conversion/decoding means sharing "a common memory." A PHOSITA would naturally site the audio decode-code store in the already-present, large A/V decode DRAM rather than add a separate ROM — this is the very cost-saving rationale the patent states ("since the A/V decode memory can be made large enough, there is no chance to bring about the increase in the cost").
• Pre-loading all codes into that second memory: a direct, predictable application of JP 3221763's "store all programs in external large-volume memory" teaching to the A/V DRAM.

Motivation: architectural economy — reuse the DM bandwidth and capacity already provisioned for video, avoiding a dedicated code ROM. This is the classic "combine known elements with no change in their respective functions" situation (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007)). Expectation of success: high; the '491 specification itself notes the A/V memory "has a transmission band width [able] to put up with the video decoding process," i.e., the benefit is inherent in the known hardware.

Claims 3 and 4 — Transfer-error check after moving the code

Combination: as in claim 1/2 + JPH05313908A (Fujitsu) / admitted knowledge of CRC and self-test.

• The '491 specification admits CRC is the technique used ("a CRC (Cyclic Redundancy Check) code or a test data is decoded actually, so as to be compared with an expected value"). CRC-protected transfers of program/firmware data were ubiquitous in 1998 DSP/firmware design.
• JPH05313908A ("Program guarantee method for program download type encoder," Fujitsu, 1993) is of record and on its face addresses guaranteeing a program downloaded into a codec — i.e., verifying the integrity of a loaded program, the exact function recited.

Motivation: when you page executable code from a slow, potentially error-prone external memory into internal RAM, you must ensure the code arrived intact before executing it — an obvious reliability requirement with a known solution. Expectation of success: high; CRC and test-vector comparison are deterministic.

Drafting note carried forward: claims 3 and 4 both recite "said first memory or said second memory" although claim 1 lacks any second memory; this internal inconsistency affects the scope of claim 3 but does not aid validity — it merely raises a § 112 ¶ 2 question that is separate from § 103.

Claims 5 and 6 — Error check by decoding a specific audio sequence and comparing to an expected value

Combination: as in claims 3/4 + the admitted self-test teaching.

The '491 specification admits "a test data is decoded actually, so as to be compared with an expected value thereof." Using a known input with a known output as a functional self-test of a freshly loaded decoder program is a textbook technique (a "known-good-vector" test), and it is strictly more reliable than CRC because it also validates that the loaded code actually executes correctly on this hardware. Motivation: a CRC check confirms the bits; a test decode confirms the function — a PHOSITA would add the functional test to the transfer-integrity test as a matter of routine prudence. Expectation of success: high and predictable.

Claim 7 — Broad apparatus: demux + first memory that "obtain[s] … from an outside [source]" the code when the method changes + DSP (no ROM or controller recited)

Combination: JP 3221763 + ordinary MPEG demultiplexer art (U.S. 5,845,249).

Claim 7 is the broadest claim and drops both the external ROM element and the controller element. Its distinguishing feature is "obtain … from an outside [source] … when the method … is changed" — i.e., on-demand external loading of the decoder program. JP 3221763 discloses exactly this (external large-volume memory → internal DSP program memory, host-selected). Adding a demultiplexer that selects the user-designated stream and extracts the format is conventional MPEG system knowledge (U.S. 5,845,249's HDMS211M demultiplexer; the patent's own FIG. 2). Result: claim 7 is obvious over JP 3221763 in view of U.S. 5,845,249. Claim 7's breadth (no controller, no ROM) actually weakens it — and note the court in Maxell v. Huawei had to grapple with ZTE's indefiniteness attack on the claim 7 demultiplexer language (construed to plain meaning), showing how functionally broad the claim is.

Claim 8 — Demux + ROM of plural decoding programs + DSP decoding when the method changes

Combination: JP 3221763 + U.S. 5,845,249. This is essentially claim 7 with the ROM element added — and JP 3221763 expressly recites a ROM holding "all types of algorithm programs." Adding the MPEG demultiplexer gives claim 8. Strongly obvious.

Claim 9 — Receiver apparatus (receiving means + demux + ROM of plural codes + DSP)

Combination: JP 3221763 + U.S. 5,845,249 + U.S. 6,288,748 (Hitachi)/EP 0 935 385 (Hitachi receiver).

A receiver (tuner/FEC front end) feeding a demultiplexer is the standard digital-broadcast receiver topology — exactly what the patent's own FIGS. 10–13 depict and what Hitachi's U.S. 6,288,748 and EP 0 935 385 describe. Claim 9 adds nothing patentably distinct over the decoder claims once the receiver context is supplied by these references. Obvious.

4. Motivation to combine — synthesis

Across all claims the same three motivations align and satisfy KSR:

1. Format proliferation / interoperability pressure. The patent's own background states the receiver "must correspond to those plural formats," depending on satellite/terrestrial/cable service. U.S. 5,845,249 and U.S. 6,430,533 confirm MPEG-2 and AC-3 were the two dominant, mutually incompatible formats a single receiver had to support. Combining a multi-format library (JP 3221763) with a multiplexed-stream demultiplexer (U.S. 5,845,249) is a combination of references "designed to address the same problem."
2. Cost and integration pressure. U.S. 6,430,533 states on-chip code ROMs are "expensive" and large; U.S. 5,845,249 laments chip redesign per application; EP 0 935 385 shows reuse of a common memory. These are explicit teachings that push a PHOSITA toward off-chip code storage and shared memory — the '491 architecture.
3. The predictability of code-overlay. JP 3221763 makes paging codec programs from external memory into internal DSP program memory an express, working technique. Overlaying is a predictable mechanism with known benefits; nothing in the '491 patent asserts an unexpected result from it.

Under KSR, where "a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." JP 3221763's external-codec-library/paging technique applied to an MPEG multi-format broadcast receiver is precisely such a same-way improvement.

5. Secondary considerations

The record discloses no objective indicia that would rebut the prima facie case:

• No nexus — the patent is directed to an architectural partitioning; the record shows no evidence of unexpected results attributable to the claims as opposed to the general approach.
• No long-felt need demonstrated; to the contrary, the cited LSI Logic and JP 3221763 art shows the industry was already addressing multi-format decoding and off-chip code storage before the priority date.
• Commercial success of the Maxell/Hitachi receivers, if any, is not linked in the record to the '491 claims with the required nexus.
• The PTAB non-institution and the ZTE verdict are litigation facts, not objective evidence of non-obviousness; a verdict of infringement presupposes validity only if validity was actually litigated and decided on the merits against the specific combinations above. The record provided does not show that the JP 3221763 + LSI Logic combinations were squarely presented and rejected on the merits.

6. Caveats, uncertainties, and contrary evidence (explicit)

1. The IPR was not instituted on the merits (IPR2018-00239, petitioner ZTE). This is the most important counterweight. Non-institution reflects that the Board was not persuaded of a reasonable likelihood on the petition as filed. It is not a holding that the claims are non-obvious. My analysis is an independent reconstruction and can differ; anyone relying on it should treat the non-institution as evidence to be distinguished (e.g., different primary reference, different claim construction, or failure to articulate the JP 3221763 trigger), not as a bar.

2. I have not personally read the full JP 3221763 B2 specification in Japanese. My characterization of its disclosures is drawn from the English-language petition excerpt quoted in the search results (the PTAB petition document at ptacts.uspto.gov describing the "conventional technology" of the audio codec). The mapping of its features to the '491 claim elements should be verified against the JP specification and a certified translation before being relied upon in any filing.

3. U.S. 6,378,101's exact priority/§ 102 status relative to the 1998-11-04 priority date is not confirmed here (its listed priority is 1999-01-27, which post-dates the '491 priority but pre-dates its filing). I therefore treated it as corroborative, not as a § 103 anchor. Treating it as § 102(e) art against the '491 filing date would require that the '491's earlier foreign priority not be perfected — a fact I cannot verify from the supplied record.

4. Claim 3's internal inconsistency ("said first memory or said second memory" in a claim depending from claim 1, which has no second memory) is a § 112 issue, not a § 103 issue; I note it only so it is not mistaken for a validity-saving distinction.

5. No CAFC 2026 docket naming the '491 patent was found (consistent with the earlier summary); the patent expired 2019-11-03, so any live appellate posture would be unusual. This does not affect the merits of the § 103 analysis.

7. Conclusion

On this record, all nine claims of U.S. 6,816,491 B1 are, in my assessment, likely invalid under pre-AIA 35 U.S.C. § 103(a):

The single most probative reference is Hitachi's own JP 3221763 B2, which teaches the essential architecture the '491 patent claims as novel. The LSI Logic references supply the multi-format (MPEG-2/AC-3) decoder context, the demultiplexer, and the express cost/integration motivations. A PHOSITA at the 1998 critical date would have had both the motivation and the reasonable expectation of success to combine them.

Confidence: Moderate-to-high on claims 7, 8, and 9 (the architecture is squarely taught by JP 3221763 plus conventional MPEG demux art). Moderate on claims 1 and 2 (the "detect change and automatically transfer" trigger is the main point of attack and requires the JP reference text to be confirmed). Lower on claims 5 and 6 (the test-decode-with-expected-value limitation is the most concrete and least squarely disclosed, though still strongly suggested by the admission in the specification and by routine self-test practice).

Recommended next step before any use: obtain and read the full JP 3221763 B2 specification and JPH05313908A in translation, and confirm U.S. 6,378,101's priority status, to firm up the § 103 mappings — and reconcile the result with ZTE's non-instituted petition to determine why the Board declined institution despite this apparently strong art.